Display driving integrated circuit and display device including the same

Abstract

A display driving integrated circuit and a display device including the same are provided. The display driving integrated circuit includes a timing controller, a first source driver including a first inverting input, a first non-inverting input, and a first output, a second source driver including a second inverting input, a second non-inverting input, and a second output, and a switching circuit connected with a display panel through first and second pads. Under the control of the timing controller, the switching circuit performs one of a first switching operation connecting the first inverting input and the first output with the first pad, the second inverting input and the second output with the second pad, and the first and second decoding voltages to the first and second non-inverting inputs, respectively, and a second switching operation applying a sensing reference voltage to the first and second non-inverting inputs, connecting the first and second outputs with an output node, and connecting the first and second inverting inputs with one pad.

Description

[0001] Cross-reference to related applications

[0002] Korean Patent Application No. 10-2020-0023403, entitled "Display Driver Integrated Circuit and Display Device Including the Therein," filed on February 26, 2020, with the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments relate to a display driver integrated circuit and a display device including the thereof. Background Technology

[0004] Organic light-emitting diodes (OLEDs) have been developed as one of the light-emitting elements. Because OLEDs have self-emissive properties, OLED display devices do not require additional components for light emission, such as backlight units. Therefore, display devices using OLEDs are being researched and developed. A display panel including OLEDs may include pixels arranged in rows and columns, with each pixel including one OLED and one transistor. The brightness of the OLED can be adjusted by regulating the amount of current flowing through it. Summary of the Invention

[0005] The embodiment relates to a display driver integrated circuit for a display panel, the display driver integrated circuit comprising: a timing controller; a first source driver including a first inverting input terminal, a first non-inverting input terminal, and a first output terminal; a second source driver including a second inverting input terminal, a second non-inverting input terminal, and a second output terminal; and a switching circuit connected to the display panel via a first pad and a second pad, the switching circuit including a plurality of switches connected between the first pad and the second pad and the first source driver and the second source driver. Under the control of the timing controller, the switching circuit can be configured to perform one of the following operations: a first switching operation: controlling a plurality of switches such that a first inverting input and a first output are connected to a first pad, a first decoding voltage is applied to a first non-inverting input, a second inverting input and a second output are connected to a second pad, and a second decoding voltage is applied to a second non-inverting input; and a second switching operation: controlling the plurality of switches such that a sensing reference voltage is applied to the first non-inverting input and the second non-inverting input, a first output and a second output are connected to an output node, and the first inverting input and the second inverting input are connected to one of the first and second pads.

[0006] The embodiments also relate to a display driver integrated circuit for a display panel, the display driver integrated circuit comprising: a timing controller; a column control block including a plurality of source drivers and configured to, under the control of the timing controller, use the plurality of source drivers to control the voltage of a plurality of pixel lines connected to the display panel, and use the plurality of source drivers to receive pixel information through the plurality of pixel lines; an analog-to-digital converter configured to convert the pixel information received by the column control block into sensing data; and a memory configured to store the sensing data.

[0007] The embodiment also relates to a display device, the display device comprising: a display panel including a plurality of pixels; and a display driver integrated circuit configured to control the plurality of pixels, the display driver integrated circuit including a plurality of source drivers connected to the plurality of pixels via a plurality of pixel lines. In the display operation of the plurality of pixels, the plurality of source drivers can output a plurality of decoding voltages to the plurality of pixel lines respectively, and in the sensing operation of at least one of the plurality of pixels, the plurality of source drivers can be configured to receive pixel information via a pixel line connected to the at least one pixel among the plurality of pixel lines.

[0008] The embodiments also relate to a method of operating a display driver integrated circuit, the display driver integrated circuit including a plurality of source drivers configured to control a plurality of pixels included in a display panel, the method comprising: in the display operation of the plurality of pixels, outputting corresponding voltages to the plurality of pixels via the plurality of source drivers; and in the sensing operation of at least one pixel, sensing pixel information from at least one of the plurality of pixels via the plurality of source drivers. The pixel information may include information regarding the degree of degradation of the at least one pixel.

[0009] The embodiments also relate to a method of operating a display driver integrated circuit, the display driver integrated circuit including a plurality of source drivers configured to control a plurality of pixels included in a display panel, the method comprising: during a first period of a vertical synchronization signal and a first period of a horizontal synchronization signal, controlling a first pixel located in a first row of the plurality of pixels using the plurality of source drivers, and sensing first pixel information from at least one pixel of the first pixels using the plurality of source drivers; and during a second period of the first period of the vertical synchronization signal and the second period of the horizontal synchronization signal, controlling a second pixel located in a second row of the plurality of pixels using the plurality of source drivers, and sensing second pixel information from at least one pixel of the second pixels using the plurality of source drivers. The first pixel information may include information about the degree of degradation of the at least one pixel in the first pixel, and the second pixel information includes information about the degree of degradation of the at least one pixel in the second pixel.

[0010] The embodiments also relate to a method of operating a display driver integrated circuit, the display driver integrated circuit including a plurality of source drivers configured to control a plurality of pixels included in a display panel, the method comprising: controlling the plurality of pixels using the plurality of source drivers based on a horizontal synchronization signal; and sensing pixel information from at least one pixel of the plurality of pixels using the plurality of source drivers during a vertical blanking period. The pixel information may include information about the degree of degradation of the at least one pixel. Attached Figure Description

[0011] Features will become apparent to those skilled in the art from a detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram illustrating a display device according to an example embodiment;

[0013] Figures 2A to 2C It is shown Figure 1 A circuit diagram of an example pixel structure;

[0014] Figure 3 This is a block diagram showing a general configuration of the source driver block and sensing block of a display driver integrated circuit;

[0015] Figure 4 It is shown Figure 1 A flowchart of the operation of the display device;

[0016] Figure 5 It is shown Figure 1 A diagram of the column control blocks;

[0017] Figures 6 to 9 It is used to describe Figure 5 A diagram illustrating the display and sensing operations of the column control block;

[0018] Figure 10 This is a circuit diagram showing a first source driver among a plurality of source drivers included in a column control block according to an example embodiment;

[0019] Figure 11A and Figure 11B This is a diagram used to illustrate how a low-noise amplifier is implemented by connecting or combining multiple source drivers in parallel;

[0020] Figure 12A and Figure 12B It is shown Figure 11A and Figure 11B A diagram illustrating the equivalent circuit of a parallel-connected source driver;

[0021] Figure 13 It is shown in detail Figure 5 The circuit diagram of the column control block;

[0022] Figure 14 It is used to describe Figure 13 The timing diagram of the column control block operations;

[0023] Figures 15A to 15C It shows the basis Figure 14 A diagram showing the configuration of column control blocks in a timing diagram;

[0024] Figure 16 It is used to describe Figure 1 Timing diagram of the operation of the display driver integrated circuit;

[0025] Figure 17A and Figure 17B It is used to describe according to Figure 16 The timing diagram shows the operation and the sensing operation.

[0026] Figure 18 It is used to describe Figure 1 Timing diagram of the operation of the display driver integrated circuit;

[0027] Figure 19 It is used to describe Figure 1 Timing diagram of the operation of the display driver integrated circuit;

[0028] Figure 20 It is used to describe Figure 1 Timing diagram of the operation of the display driver integrated circuit;

[0029] Figure 21 It is shown Figure 1 A block diagram of the method for generating compensation data for the control block;

[0030] Figure 22 This is a block diagram illustrating a display device according to an example embodiment; and

[0031] Figure 23 This is a block diagram illustrating an electronic device according to an example embodiment. Detailed Implementation

[0032] Figure 1 This is a block diagram illustrating a display device according to an example embodiment. (Refer to...) Figure 1 The display device 10 may include a display panel 11, a gate driver block 12, a control block 13, a memory 14, an analog-to-digital converter 15 (ADC), and a column control block 100. In an example embodiment, the display driver integrated circuit DDI may include at least a portion of the gate driver block 12, the control block 13, the memory 14, the analog-to-digital converter 15, and the column control block 100.

[0033] Display panel 11 may include a plurality of pixels PX. The plurality of pixels PX may be arranged in rows and columns. The plurality of pixels PX may be connected to scan lines SCa to SCm and pixel lines PL1 to PLn. In an example embodiment, display panel 11 may be implemented with various display panels, such as liquid crystal display panels, organic light-emitting display panels, electrophoretic display panels, electrowetting display panels, or other display panels. In an example embodiment, display device 10 including a liquid crystal display panel may also include a polarizer (not shown), a backlight unit (not shown), etc. Hereinafter, for ease of description, it is assumed that display panel 11 is an organic light-emitting display panel including pixels based on organic light-emitting diodes (OLEDs).

[0034] Gate driver block 12 can be connected to multiple pixels PX via scan lines SCa to SCm. Gate driver block 12 can control the voltage of scan lines SCa to SCm under the control of control block 13.

[0035] Control block 13 can receive display data DD from an external host device (e.g., a host device such as an application processor (AP) or a graphics processing unit (GPU). Control block 13 can control gate driver block 12, causing gate driver block 12 to sequentially or non-sequentially activate or select multiple pixels PX in row units.

[0036] In an example embodiment, control block 13 may perform external compensation operations on display panel 11 or a plurality of pixels PX. For example, memory 14 may include pixel information about each of the plurality of pixels PX of display panel 11. Control block 13 may perform external compensation on display data DD received from an external device based on the pixel information stored in memory 14, and may output externally compensated display data DD_C (hereinafter referred to as "compensated data"). The compensated data DD_C may be provided to column control block 100. In an example embodiment, control block 13 may be or may include a timing controller configured to control the operating timing of display device 10.

[0037] Column control block 100 can be connected to multiple pixels PX via multiple pixel lines PL1 to PLn. In an example embodiment, the multiple pixel lines PL1 to PLn may include data lines DL1 to DLn and sensing lines SL1 to SLn. Data lines DL1 to DLn may be signal lines that provide a signal based on compensation data DD_C from column control block 100 to pixel PX, and sensing lines SL1 to SLn may be signal lines that provide pixel information PI from pixel PX to column control block 100. In an example embodiment, depending on the implementation of pixel PX or display panel 11, the data lines and sensing lines connected to a pixel may be separate from each other or may be the same line, as described more fully below with reference to the accompanying drawings.

[0038] Column control block 100 can control pixel lines PL1 to PLn under the control of control block 13 (e.g., in response to mode signal MS). Column control block 100 may include multiple source drivers respectively connected to pixel lines PL1 to PLn. The multiple source drivers can receive compensation data DD_C from control block 13 and can control pixel lines PL1 to PLn based on the received compensation data DD_C.

[0039] In an example embodiment, column control block 100 can sense pixel information PI for each of a plurality of pixels PX under the control of control block 13 (e.g., in response to mode signal MS). For example, as described above, column control block 100 may include a plurality of source drivers respectively connected to pixel lines PL1 to PLn. Pixel information PI can be sensed from a plurality of pixels PX by the plurality of source drivers. Therefore, the display device 10 according to the example embodiment can use a plurality of source drivers configured to control pixels PX to sense pixel information PI without the need for a separate low-noise amplifier for sensing pixel information PI. The configuration and operation of column control block 100 will now be described more fully with reference to the accompanying drawings.

[0040] The analog-to-digital converter 15 can convert the pixel information PI into a digital signal to output sensing data DS. The sensing data DS corresponding to the digital signal can be stored in the memory 14. In an example embodiment, the pixel information PI may be information about the current or voltage sensed from each of the plurality of pixels PX. The pixel information PI may refer to information about the degree of degradation of each of the plurality of pixels PX. For example, the pixel information PI may include information about the degree of degradation of the organic light-emitting diode (OLED) or transistor included in each of the plurality of pixels PX.

[0041] As described above, the display device 10 according to the example embodiment can use multiple source drivers configured to control pixel lines PL1 to PLn (e.g., data lines DL1 to DLn) connected to pixel PX to sense pixel information PI from pixel PX without the need for a separate amplifier (e.g., a low-noise amplifier) ​​for sensing pixel information PI. Therefore, the size of the display driver integrated circuit DDI can be reduced by up to the size of the low-noise amplifier, and the cost of implementing the display driver integrated circuit can be reduced.

[0042] The terms "pixel display operation" and "pixel sensing operation" are used below. Pixel display operation refers to the operation that allows a pixel to display brightness corresponding to display data or compensation data, and pixel sensing operation refers to the operation of sensing pixel information (PI) from a pixel.

[0043] Figures 2A to 2C It is shown Figure 1 A circuit diagram of an example pixel structure. Refer to... Figures 2A to 2C This describes a portion of the example pixel structure, but multiple pixels PX can have the same characteristics. Figures 2A to 2C The pixels PXa, PXb, and PXc shown have different structures.

[0044] Reference Figure 1 and Figure 2A Pixel PXa may include a first selection transistor SEL1, a second selection transistor SEL2, a driving transistor DRV, a capacitor CS, and an organic light-emitting diode OLED.

[0045] The first selection transistor SEL1 can be connected between the reference voltage VREF and the second node n2, and can operate in response to the signal of the first scan line SC1. The second selection transistor SEL2 can be connected between the data line DL / sensing line SL and the first node n1, and can operate in response to the signal of the second scan line SC2. The driving transistor DRV can be connected between the first power supply voltage ELVDD and the first node n1, and can operate in response to the voltage of the second node n2. The capacitor CS can be connected between the first node n1 and the second node n2. The organic light-emitting diode OLED can be connected between the first node n1 and the second power supply voltage ELVSS.

[0046] In the example embodiment, when performing a display operation on pixel PXa, the source driver corresponding to pixel PX (e.g., Figure 1The source driver included in the column control block 100 provides a voltage corresponding to the compensation data DD_C to the data line DL / sensing line SL. In this case, the data line DL / sensing line SL is used as a data line. When the turn-on voltage is provided to the first scan line SC1 and the second scan line SC2, the first selection transistor SEL1 and the second selection transistor SEL2 can be turned on by the turn-on voltage. Thus, the second node n2 can be set to the reference voltage VREF, and the first node n1 can be set to the voltage corresponding to the compensation data DD_C. The amount of current flowing through the driving transistor DRV can be determined by the voltage difference between the second node n2 and the first node n1, and the brightness of the organic light-emitting diode OLED can be adjusted according to the amount of current flowing through the driving transistor DRV.

[0047] In an example embodiment, when performing a sensing operation on pixel PXa, the second selection transistor SEL2 can be turned on by the turn-on voltage of the second scan line SC2. In this case, pixel information PI (or current or voltage information) can be provided to the column control block 100 via the first node n1 and the data line DL / sensing line SL. For example, in the display operation of pixel PXa, even if a signal corresponding to display data with a specific value is provided to the first node n1, the voltage of the first node n1 or the amount of current flowing through the driving transistor DRV may be non-uniform due to degradation of the driving transistor DRV, degradation of the organic light-emitting diode OLED, or degradation of the first selection transistor SEL1 and the second selection transistor SEL2. In this case, the brightness of the light emitted from the organic light-emitting diode OLED may change relative to the target. Therefore, the pixel information PI, which indicates the characteristics or degradation of the individual elements included in pixel PXa, can be sensed through the sensing operation of pixel PXa. As described above, the pixel information PI may refer to the voltage or current of the first node n1 and can be provided to the column control block 100 via the data line DL / sensing line SL. In the example embodiment, the node through which it outputs pixel information PI can be changed according to the pixel structure.

[0048] Reference Figure 1 and Figure 2B The pixel PXb may include a first selection transistor SEL1, a second selection transistor SEL2, a driving transistor DRV, a capacitor CS, an organic light-emitting diode OLED, and a light-emitting control transistor EMT.

[0049] Reference Figure 2AThe description of pixel PXa includes a first selection transistor SEL1, a second selection transistor SEL2, a driving transistor DRV, a capacitor CS, and an organic light-emitting diode (OLED). Therefore, additional descriptions will be omitted to avoid redundancy. The light-emitting control transistor EMT can be connected between the first power supply voltage ELVDD and the driving transistor DRV, and can operate in response to the light-emitting control signal EM. Except for the light-emitting control transistor EMT, the driving operation and structure of pixel PXb are similar to those of pixel PXa; therefore, additional descriptions will be omitted to avoid redundancy.

[0050] Reference Figure 2C The pixel PXc may include a first selection transistor SEL1, a second selection transistor SEL2, a driving transistor DRV, a capacitor CS, and an organic light-emitting diode (OLED). (See reference...) Figure 2A The pixel PXa describes the connection relationship between the first selection transistor SEL1, the second selection transistor SEL2, the driving transistor DRV, the capacitor CS, and the organic light-emitting diode OLED. Therefore, additional descriptions will be omitted to avoid redundancy.

[0051] Apart from the separation of the data line DL and the sensing line SL, Figure 2C The operation and structure of the pixel PXc can be compared with Figure 2A The operation and structure of pixel PXa are similar. For example, when performing the display operation of pixel PXc, a signal corresponding to the display data DD or compensation data DD_C can be provided through the data line DL. Therefore, the first node n1 can be set to the voltage corresponding to the display data DD or compensation data DD_C. The amount of current flowing through the driving transistor DRV can be determined by the voltage of the second node n2, thus controlling the brightness of the organic light-emitting diode OLED.

[0052] In the example embodiment, it can be referenced Figure 1 The description of the multiple scan lines SCa to SCm includes references Figures 2A to 2C The description includes the first scan line SC1, the second scan line SC2, and the light emission control signal EM. Therefore, depending on the implementation of the pixel, one or more scan lines can be connected to a pixel.

[0053] As described above, the structure of the plurality of pixels PX included in the display panel 11 can vary depending on the implementation. (Refer to...) Figures 2A to 2C The described pixel structure is an example. In the example embodiment, depending on the structure of pixel PX, pixel PX can be connected to a line through which data signals are received and a line through which pixel information PI is output, or it can be connected to a line through which data signals are received or pixel information PI is output.

[0054] Figure 3 This is a block diagram illustrating a general configuration of the source driver block and sensor block of a display driver integrated circuit. Figure 3 In the general configuration shown, the multiplexer MUX can be connected to the display panel via data line DL / sensor line SL. The source driver block can be connected to the multiplexer MUX via data line DL. The source driver block can receive compensation data and control the data line DL based on the received compensation data. Therefore, the source driver block can be configured to control the display operation of the pixels included in the display panel. The sensor block can be connected to the multiplexer MUX via sensing line SL. The sensor block can sense pixel information PI provided from the pixels of the display panel via sensing line SL. The sensor block can be implemented using a low-noise amplifier. In a general display driver integrated circuit, components can be provided separately for the source driver block (configured to control the display operation of pixels) and the sensor block (configured to perform the sensing operation of pixels). The sensor block can be implemented using a low-noise amplifier. Because the low-noise amplifier occupies a relatively large area, the size of the general display driver integrated circuit may be relatively large.

[0055] Figure 4 It is shown Figure 1 A flowchart illustrating the operation of the display device. (Refer to...) Figure 1 and Figure 4 In operation S110, in display mode, display device 10 can control pixels using source drivers. For example, in display mode, display device 10 can use multiple source drivers included in column control block 100 to provide signals corresponding to display data DD or compensation data DD_C to the pixels. Pixels can emit light in response to signals provided from the multiple source drivers.

[0056] In operation S120, in sensing mode, display device 10 can sense pixel information from pixels using source drivers. For example, in sensing mode, display device 10 can sense pixel information PI from each pixel using a plurality of source drivers included in column control block 100. According to an example embodiment, the plurality of source drivers can be used as a low-noise amplifier by being connected in combination or in parallel.

[0057] As described above, the display device 10 according to the example embodiment can sense pixel information from pixels by a source driver configured to control the data line of the pixel without the need for a dedicated separate amplifier.

[0058] Figure 5 It is shown Figure 1The diagram below illustrates the column control block. It is assumed that a pixel is connected to a pixel line PL, and that the pixel line PL is used as a data line DL or a sensing line SL depending on the driving scheme (i.e., display operation or sensing operation). Therefore, in the following description, a pixel line connected to a pixel may not be classified as a data line DL or a sensing line SL, and the use of the pixel line may be determined according to the driving scheme. However, for example, data lines and sensing lines may be connected to a pixel depending on the implementation of the pixel.

[0059] For ease of description, the example embodiment will now be described based on three pixels, PX1, PX2, and PX3. However, the number of pixels can be varied.

[0060] Reference Figure 1 and Figure 5 The column control block 100 may include first pads PD1 to third pads PD3, switch circuit 110, first source driver SD1 to third source driver SD3, first selection circuit MUX1 to third selection circuit MUX3, and first decoder DEC1 to third decoder DEC3.

[0061] The first pad PD1 to the third pad PD3 can be connected to the first pixel line PL1 to the third pixel line PL3, respectively. For example, the first pad PD1 can be connected to the first pixel line PL1 corresponding to the first pixel PX1 of the display panel 11, the second pad PD2 can be connected to the second pixel line PL2 corresponding to the second pixel PX2 of the display panel 11, and the third pad PD3 can be connected to the third pixel line PL3 corresponding to the third pixel PX3 of the display panel 11.

[0062] The switching circuit 110 can be connected to the first pad PD1 to the third pad PD3, and can be connected to the output terminal and the inverting input terminal of the first source driver SD1 to the third source driver SD3.

[0063] The first decoder DEC1 can decode the first compensation data DD_C1 from the control block 13 to output the first decoded voltage VDEC1. The first selection circuit MUX1 can select and output one of the first decoded voltage VDEC1 and the sensed reference voltage VP. The output of the first selection circuit MUX1 can be provided to the non-inverting input of the first source driver SD1.

[0064] The second decoder DEC2 can decode the second compensation data DD_C2 from control block 13 to output the second decoded voltage VDEC2. The second selection circuit MUX2 can select and output one of the second decoded voltage VDEC2 and the sensed reference voltage VP. The output of the second selection circuit MUX2 can be provided to the non-inverting input of the second source driver SD2.

[0065] The third decoder DEC3 can decode the third compensation data DD_C3 from control block 13 to output the third decoded voltage VDEC3. The third selection circuit MUX3 can select and output one of the third decoded voltage VDEC3 and the sensed reference voltage VP. The output of the third selection circuit MUX3 can be provided to the non-inverting input of the third source driver SD3.

[0066] Switching circuit 110 can receive mode signal MS from control block 13 and can perform switching operation between the above signal lines in response to the received mode signal MS. For example, when mode signal MS indicates a pixel display operation, switching circuit 110 can perform a switching operation such that the output of the first source driver SD1 is connected to the first pixel line PL1 of the first pad PD1, the output of the second source driver SD2 is connected to the second pixel line PL2 of the second pad PD2, and the output of the third source driver SD3 is connected to the third pixel line PL3 of the third pad PD3.

[0067] When the mode signal MS indicates a sensing operation, the switching circuit 110 can perform a switching operation, causing the inverting inputs and outputs of the first source driver SD1 to the third source driver SD3 to be connected in parallel. Depending on the switching operation of the switching circuit 110, pixel information PI can be output from the outputs of the first source driver SD1 to the third source driver SD3 (or from the switching circuit 110 itself). The structure and operation of the switching circuit 110 will be described more fully below with reference to the accompanying drawings.

[0068] In the example embodiment, the first selection circuit MUX1 to the third selection circuit MUX3 can operate in response to the mode signal MS. For example, when the mode signal MS indicates a pixel display operation, the first selection circuit MUX1 to the third selection circuit MUX3 can select and output the first decoding voltage VDEC1 to the third decoding voltage VDEC3. Therefore, the first compensation data DD_C1 to the third compensation data DD_C3 can be values ​​corresponding to the brightness represented by the first pixel PX1 to the third pixel PX3, respectively; during the pixel display operation, the first decoding voltage VDEC1 to the third decoding voltage VDEC3, respectively corresponding to the first compensation data DD_C1 to the third compensation data DD_C3, can be provided to the first pixel PX1 to the third pixel PX3. When the mode signal MS indicates a pixel sensing operation, the first selection circuit MUX1 to the third selection circuit MUX3 can select and output the sensing reference voltage VP.

[0069] Figures 6 to 9 It is used to describe Figure 5 A diagram illustrating the display and sensing operations of the column control block. For brevity and ease of description, unnecessary components describing the display and sensing operations may be omitted. In the example embodiment, reference will be made to... Figure 6 This describes the operation of column control block 100 associated with pixel display operations, and will refer to... Figures 7 to 9 Describes the operation of column control block 100 associated with the sensing operation of pixels.

[0070] Reference Figure 1 and Figures 5 to 9 According to the switching operation of the switching circuit 110, the column control block 100 can use source drivers SD1 to SD3 as data driving circuits configured to control the pixels of the display panel 11, or it can use source drivers SD1 to SD3 as amplifiers or integrators configured to receive pixel information PI from the pixels of the display panel 11.

[0071] For example, in pixel display operations, such as Figure 6As shown, the outputs of the first source driver SD1 to the third source driver SD3 of the column control block 100 can be connected to the first pad PD1 to the third pad PD3 respectively, and the outputs of the first source driver SD1 to the third source driver SD3 can provide feedback to the inverting inputs of the first source driver SD1 to the third source driver SD3. The first selection circuit MUX1 to the third selection circuit MUX3 can perform a selection operation, such that the first decoding voltage VDEC1 to the third decoding voltage VDEC3 are applied to the non-inverting inputs of the first source driver SD1 to the third source driver SD3. In the example embodiment, this can be implemented through the switching operation of the switching circuit 110. Figure 6 The diagram shows the connection relationships between the first source driver SD1 to the third source driver SD3 and the first pad PD1 to the third pad PD3.

[0072] exist Figure 6 In the display operation shown, the first source driver SD1 amplifies the first decoding voltage VDEC1 and outputs the amplified voltage to the first pixel line PL1. The second source driver SD2 amplifies the second decoding voltage VDEC2 and outputs the amplified voltage to the second pixel line PL2. The third source driver SD3 amplifies the third decoding voltage VDEC3 and outputs the amplified voltage to the third pixel line PL3. Therefore, in the display operation, the first source drivers SD1 to the third source drivers SD3 can be used as a data driving circuit, configured to amplify the first decoding voltage VDEC1 to the third decoding voltage VDEC3 and output the amplified voltage through the first pixel line PL1 to the third pixel line PL3.

[0073] Then, in the pixel sensing operation, column control block 100 can follow... Figures 7 to 9 The circuit configuration shown is as follows. For example, in the sensing operation of a pixel connected to the first pixel line PL1 of the first pad PD1, such as... Figure 7As shown, the inverting inputs of the first source driver SD1 to the third source driver SD3 can be connected to the first pad PD1, and the outputs of the first source driver SD1 to the third source driver SD3 can be connected to the node from which the first pixel information PI1 is output. A sensing reference voltage VP can be applied to the non-inverting inputs of the first source driver SD1 to the third source driver SD3. A capacitor CC and a reset switch RST can be connected in parallel between the inverting inputs and outputs of the first source driver SD1 to the third source driver SD3. Therefore, in the sensing operation of pixel PX1 connected to the first pixel line PL1, when the first source drivers SD1 to the third source driver SD3 are connected in parallel or combined, an equivalent of a low-noise amplifier AMP can be used; the first pixel information PI1 can be sensed from pixel PX1 connected to the first pixel line PL1 using the first source drivers SD1 to the third source driver SD3.

[0074] Similarly, in the sensing operation of pixel PX2 connected to the second pixel line PL2, such as Figure 8 As shown, the inverting inputs of the first source driver SD1 to the third source driver SD3 can be connected to the second pad PD2, and the outputs of the first source driver SD1 to the third source driver SD3 can be connected to the node from which the second pixel information PI2 is output. A sensing reference voltage VP can be applied to the non-inverting inputs of the first source driver SD1 to the third source driver SD3. The capacitor CC and the reset switch RST can be connected in parallel between the inverting inputs and outputs of the first source driver SD1 to the third source driver SD3. Therefore, in the sensing operation of pixel PX2 connected to the second pixel line PL2, when the first source drivers SD1 to the third source driver SD3 are connected in parallel or combined, an equivalent of a low-noise amplifier AMP can be used; the second pixel information PI2 can be sensed from pixel PX2 connected to the second pixel line PL2 using the first source drivers SD1 to the third source driver SD3.

[0075] Similarly, in the sensing operation of pixel PX3 connected to the third pixel line PL3, such as Figure 9As shown, the inverting inputs of the first source driver SD1 to the third source driver SD3 can be connected to the third pad PD3, and the outputs of the first source driver SD1 to the third source driver SD3 can be connected to the node from which the third pixel information PI3 is output. A sensing reference voltage VP can be applied to the non-inverting inputs of the first source driver SD1 to the third source driver SD3. The capacitor CC and the reset switch RST can be connected in parallel between the inverting inputs and outputs of the first source driver SD1 to the third source driver SD3. Therefore, in the sensing operation of pixel PX3 connected to the third pixel line PL3, when the first source drivers SD1 to the third source driver SD3 are connected in parallel or combined, an equivalent of a low-noise amplifier AMP can be used; the third pixel information PI3 can be sensed from pixel PX3 connected to the third pixel line PL3 using the first source drivers SD1 to the third source driver SD3.

[0076] Reference Figures 6 to 9 The described connection configuration between the source driver and the pad can be implemented via the switching operation of the switching circuit 110. (Refer to...) Figures 13 to 14 The configuration of the switching circuit 110 and the configuration and operation of the reset switch RST are described more fully.

[0077] As described above, the display driver integrated circuit according to the example embodiment can receive pixel information from the corresponding pixel using at least one source driver configured to control the pixel during pixel sensing operations. Therefore, since a separate low-noise amplifier for receiving pixel information can be omitted, the size and cost of the display driver integrated circuit can be reduced.

[0078] Figure 10 This is a circuit diagram illustrating the first source driver among a plurality of source drivers included in a column control block according to an example embodiment. (Refer to...) Figure 10 The example circuit diagram describes the first source driver SD1. However, for example, each of the plurality of source drivers may have the same or similar structure as the first source driver SD1, or may have a different structure. Figure 10 The structures shown are different.

[0079] Reference Figure 10 The first source driver SD1 may include multiple PMOS transistors MP1 to MP8 and multiple NMOS transistors MN1 to MN8. Figure 10 The transistor polarity (e.g., P-channel or N-channel) and transistor type shown in the circuit diagram are merely examples.

[0080] The first PMOS transistor MP1 can be connected between the power supply voltage VDD and the second PMOS transistor MP2, and can operate in response to the bias voltage VBP1. The second PMOS transistor MP2 can be connected between the first PMOS transistor MP1 and the fourth NMOS transistor MN4, and can operate in response to the inverted input signal INN. The inverted input signal INN can be a signal input to the inverted input terminal of the first source driver SD1. The third PMOS transistor MP3 can be connected between the first PMOS transistor MP1 and the sixth NMOS transistor MN6, and can operate in response to the non-inverted input signal INP. The non-inverted input signal INP can be a signal input to the non-inverted input terminal of the first source driver SD1.

[0081] The first NMOS transistor MN1 can be connected between the second NMOS transistor MN2 and ground voltage VSS, and can operate in response to bias voltage VBN1. The second NMOS transistor MN2 can be connected between the fourth PMOS transistor MP4 and the first NMOS transistor MN1, and can operate in response to the inverting input signal INN. The third NMOS transistor MN3 can be connected between the sixth PMOS transistor MP6 and the first NMOS transistor MN1, and can operate in response to the non-inverting input signal INP.

[0082] The fourth PMOS transistor MP4 can be connected between the power supply voltage VDD and the fifth PMOS transistor MP5, and can operate in response to the gate of the sixth PMOS transistor MP6. The fifth PMOS transistor MP5 can be connected between the fourth PMOS transistor MP4 and the first impedance circuit Z1, and can operate in response to the gate of the seventh PMOS transistor MP7.

[0083] The fourth NMOS transistor MN4 can be connected between the fifth NMOS transistor MN5 and the ground voltage VSS, and can operate in response to the gate of the sixth NMOS transistor MN6. The fifth NMOS transistor MN5 can be connected between the first impedance circuit Z1 and the fourth NMOS transistor MN4, and can operate in response to the gate of the seventh NMOS transistor MN7.

[0084] The sixth PMOS transistor MP6 can be connected between the power supply voltage VDD and the seventh PMOS transistor MP7, and can operate in response to the gate of the fourth PMOS transistor MP4. In an example embodiment, the gates of the fourth PMOS transistor MP4 and the sixth PMOS transistor MP6 can be connected to the node between the fifth PMOS transistor MP5 and the first impedance circuit Z1. The seventh PMOS transistor MP7 can be connected between the sixth PMOS transistor MP6 and the second impedance circuit Z2, and can operate in response to the gate of the fifth PMOS transistor MP5.

[0085] The sixth NMOS transistor MN6 can be connected between the seventh NMOS transistor MN7 and ground voltage VSS, and can operate in response to the gate of the fourth NMOS transistor MN4. In an example embodiment, the gates of the fourth NMOS transistor MN4 and the sixth NMOS transistor MN6 can be connected to the node between the first impedance circuit Z1 and the fifth NMOS transistor MN5. The seventh NMOS transistor MN7 can be connected between the second impedance circuit Z2 and the sixth NMOS transistor MN6, and can operate in response to the gate of the fifth NMOS transistor MN5.

[0086] The first capacitor C1 can be connected between the node between the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 and the output node from which the output signal OUT originates. The second capacitor C2 can be connected between the node between the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 and the output node from which the output signal OUT originates.

[0087] The eighth PMOS transistor MP8 can be connected between the power supply voltage VDD and the output node, and can operate in response to the node between the seventh PMOS transistor MP7 and the second impedance circuit Z2. The eighth NMOS transistor MN8 can be connected between the output node and the ground voltage VSS, and can operate in response to the node between the second impedance circuit Z2 and the seventh NMOS transistor MN7. In an example embodiment, the gate of the eighth PMOS transistor MP8 can be the first internal node VOP, and the gate of the eighth NMOS transistor MN8 can be the second internal node VON.

[0088] from Figure 10 As can be understood from the circuit diagram, the first source driver SD1 can amplify the difference between the non-inverting input signal INP and the inverting input signal INN, and can output the amplified difference as the output signal OUT.

[0089] Figure 11A and Figure 11BThis diagram illustrates a low-noise amplifier implemented by connecting or combining multiple source drivers in parallel. For the sake of brevity and ease of description, an embodiment is described where two source drivers SD1 and SD2 are connected or combined in parallel to implement a low-noise amplifier; however, it should be understood that the number of source drivers to be combined to implement a low-noise amplifier can vary.

[0090] Reference Figure 5 , Figure 11A and Figure 11B The column control block 100 may include a first source driver SD1 and a second source driver SD2. The first source driver SD1 may include a first amplifier amp1 and transistors MP81 and MN81. Transistors MP81 and MN81 may be connected in series between the power supply voltage VDD and the ground voltage VSS, and may operate in response to internal nodes VOP1 and VON1. The second source driver SD2 may include a second amplifier amp2 and transistors MP82 and MN82. Transistors MP82 and MN82 may be connected in series between the power supply voltage VDD and the ground voltage VSS, and may operate in response to internal nodes VOP2 and VON2.

[0091] In the example embodiment, each of the first source driver SD1 and the second source driver SD2 may have a reference. Figure 10 The circuit diagram configuration is described. In the example embodiment, transistors MP81, MN81, MP82, and MN82 may be referenced. Figure 10 A subset of the transistors described (e.g., MP8 and MN8).

[0092] As described above, for pixel sensing operations, column control block 100 can implement a low-noise amplifier by connecting multiple source drivers in parallel. For example, as Figure 11A As shown, the first source driver SD1 and the second source driver SD2 can be connected in parallel or combined. Therefore, the output terminals (i.e., the terminals or nodes from which their output voltage Vout is obtained) of the first source driver SD1 and the second source driver SD2 can be electrically connected to their inverting input terminals. In the example embodiment, the electrical connection between the output terminals of the first source driver SD1 and the second source driver SD2 and their inverting input terminals can be achieved through the aforementioned switching circuit 110.

[0093] In another implementation, the first source driver SD1 and the second source driver SD2 can be as follows: Figure 11BThe points shown are connected in parallel or can be combined. Therefore, the outputs and inverting inputs of the first source driver SD1 and the second source driver SD2 can be electrically connected, and the internal nodes VOP1 and VOP2 of the first source driver SD1 and the second source driver SD2 can be electrically interconnected, and the internal nodes VON1 and VON2 can be electrically interconnected.

[0094] Figure 12A and Figure 12B It is shown Figure 11A and Figure 11B A diagram illustrating the equivalent circuit of a parallel-connected source driver. (Refer to...) Figure 11A and Figure 12A It can be done Figure 12A The equivalent circuit expression is based on Figure 11A The circuit configuration of the embodiment, that is, the circuit configuration of the embodiment in which the input and output terminals of the first source driver SD1 and the second source driver SD2 are connected in parallel.

[0095] For example, the first source driver SD1 can be modeled as an amplifier with a first amplification gain A1 and an amplifier with a second amplification gain A2. The inverting input of the amplifier with the first amplification gain A1 can receive the output voltage Vout, and the non-inverting input of the amplifier with the first amplification gain A1 can receive the sensed reference voltage VP. The output of the amplifier with the first amplification gain A1 can be supplied to the input of the amplifier with the second amplification gain A2. In this case, a first offset voltage Vos11 can appear at the inverting input of the amplifier with the first amplification gain A1, and a first offset impedance Ro1 and a second offset voltage Vos12 can appear between the amplifier with the first amplification gain A1 and the amplifier with the second amplification gain A2. A second offset impedance Ro2 can appear at the output of the amplifier with the second amplification gain A2. The second source driver SD2 can be modeled as being similar in shape to the first source driver SD1; therefore, additional descriptions will be omitted to avoid redundancy. For ease of description, it is assumed that the internal parameters (i.e., offset impedance and amplification gain) of the first source driver SD1 and the second source driver SD2 are equal, although some parameters (e.g., offset voltages Vos21 and Vos22) are labeled with different reference numerals.

[0096] Reference Figure 11B and Figure 12B It can be done Figure 12B The equivalent circuit representation is based on the circuit configuration of the embodiment of FIG11B, that is, the circuit configuration of the embodiment in which the input and output terminals of the first source driver SD1 and the second source driver SD2 are connected in parallel or combined. Figure 12B The equivalent circuit shown is Figure 12A The equivalent circuit is similar, except that the node between the first offset impedance Ro1 and the offset voltage Vos12 of the first source driver SD1 is electrically connected to the node between the first offset impedance Ro1 and the offset voltage Vos22 of the second source driver SD2. Therefore, it can be referred to Figure 12B The above description and equations 1 and 2 below will be further described.

[0097] In an example embodiment, the following equation 1 can be used to express the following: Figure 12A The output voltage Vout and offset current Ios2 at the output node of the equivalent circuit.

[0098] [Equation 1]

[0099] V 12 =A2(A1(V) P -(V out +V OS11 ))+V OS12 )

[0100] V 22 =A2(A1(V) P -(V out +V OS21 ))+V OS22 )

[0101]

[0102]

[0103]

[0104] In Equation 1 above, "V12" represents the voltage at the output node of the amplifier with the first source driver SD1 and the second amplification gain A2, and "V22" represents the voltage at the output node of the amplifier with the second source driver SD2 and the second amplification gain A2. The remaining reference numerals have been described above; therefore, additional descriptions will be omitted to avoid redundancy.

[0105] In the example embodiment, the following equation 2 can be used to express the following: Figure 12B The output voltage Vout and offset current Ios2 at the output node of the equivalent circuit.

[0106] [Equation 2]

[0107] V 11 =A1(V P -(V out +V OS11 ))

[0108] V21 =A1(V P -(V out +V OS21 ))

[0109]

[0110]

[0111] V 12 =A2(V1+V OS12 )

[0112] V 22 =A2(V1+V OS22 )

[0113]

[0114]

[0115] In Equation 2 above, "V11" represents the output level of the amplifier with the first source driver SD1 and the first amplification gain A1, and "V21" represents the output level of the amplifier with the second source driver SD2 and the first amplification gain A1. The above describes or... Figure 12B The remaining reference numerals are shown; therefore, additional descriptions will be omitted to avoid redundancy.

[0116] From equations 1 and 2 above, we can understand that... Figure 12A and Figure 12B The output voltage Vout of the equivalent circuit is essentially the same. However, the internal nodes of the first source driver SD1 and the second source driver SD2 are as follows: Figure 12B In the connected configuration shown, the offset current caused by the amplifier with the first amplification gain A1 can be attenuated. For example, as understood from Equation 2, in Figure 12B In this embodiment, the second offset voltage Vos2, which affects the output node (i.e., the node from which the output voltage Vout is output), can be unaffected by the first amplification gain A1. Therefore, the amplitude of the second offset current Ios2 can be attenuated.

[0117] Figure 13 It is shown in detail Figure 5 The circuit diagram of the column control block is shown below. For simplicity, the labels associated with the switching circuit 110 may be omitted. It should be understood that the switching circuit 110 may include, in addition to those used for... Figure 5The column control block 100 includes components or switches other than those in the first source driver SD1 to the third source driver SD3. For simplicity, the switch signals for controlling multiple switches may be omitted, but it should be understood that, for example, the switch signals for controlling multiple switches may be included in the mode signal MS, or the switch signals for controlling multiple switches may be generated based on the mode signal MS.

[0118] Reference Figure 5 and Figure 13 The column control block 100 may include a first source driver SD1 to a third source driver SD3, multiple switches SW1 to SW9-3, and a capacitor CC. Below, to avoid inappropriate descriptions that may obscure understanding, details of the connection relationships of the multiple switches SW1 to SW9-3 may be omitted, and the functions of the multiple switches SW1 to SW9-3 will be primarily described. However, it is understood that the first source driver SD1 to the third source driver SD3, the multiple switches SW1 to SW9-3, and the capacitor CC can be configured as follows: Figure 13 The points shown are connected, or can be connected in various ways to implement the functions described below.

[0119] Reference Figure 5 and Figure 13 In sensing operation, capacitor CC can be connected between the inverting input and output terminals of the first source driver SD1 to the third source driver SD3.

[0120] In each of the first source driver SD1 to the third source driver SD3, the first switch SW1 can be a reference. Figures 7 to 9 The described reset switch RST can be configured to switch the inverting input and output of the corresponding first source driver SD1 to the third source driver SD3 during sensing operations.

[0121] The second switch SW2 can be an internal node connection switch, configured to connect or merge the internal nodes of the first source driver SD1 to the third source driver SD3 in parallel during sensing operations. In an example embodiment, the second switch SW2 can be omitted depending on the connection method of the first source driver SD1 to the third source driver SD3.

[0122] The third switch SW3 can be a sensing feedback switch, which is configured to connect the output terminals of the corresponding first source driver SD1 to the third source driver SD3 to the inverting input terminals of the corresponding first source driver SD1 to the third source driver SD3 during sensing operations.

[0123] The fourth switch SW4 can be a display feedback switch, which is configured to connect the output terminals of the corresponding first source driver SD1 to the third source driver SD3 and the inverting input terminal during display operation.

[0124] The fifth switch SW5 can be a sensing output switch, which is configured to connect the output terminals of the corresponding first source driver SD1 to the third source driver SD3 during sensing operations.

[0125] The sixth switch SW6 can be a selection switch configured to select the signals to be provided to the non-inverting inputs of the corresponding first source driver SD1 to the third source driver SD3. In the example embodiment, the sixth switch SW6 can be respectively connected to... Figure 5 The corresponding selection circuits MUX1 to MUX3 correspond to each other. Therefore, each sixth switch SW6 can be configured to select the sensing reference voltage VP or the corresponding decoding voltage (i.e., one of VDEC1, VDEC2 or VDEC3) according to the operating mode (e.g., sensing operation or display operation).

[0126] The seventh switch SW7-1 can be a sensing input switch, configured to connect the first pad PD1 to the inverting input of the first source driver SD1 during sensing operation. The seventh switch SW7-2 can be a sensing input switch, configured to connect the second pad PD2 to the inverting input of the second source driver SD2 during sensing operation. The seventh switch SW7-3 can be a sensing input switch, configured to connect the third pad PD3 to the inverting input of the third source driver SD3 during sensing operation.

[0127] The eighth switch SW8 can be a display output switch, which is configured to connect the output terminals of the corresponding first source driver SD1 to the third source driver SD3 to the first pad PD1 to the third pad PD3 respectively during display operation.

[0128] The ninth switch SW9-1 can be a sense reset switch, configured to provide reset data VDATA1 to the first pad PD1 to the third pad PD3 during a sensing operation. The ninth switch SW9-2 can be a sense reset switch, configured to provide reset data VDATA2 to the second pad PD2 during a sensing operation. The ninth switch SW9-3 can be a sense reset switch, configured to provide reset data VDATA3 to the third pad PD3 during a sensing operation.

[0129] As described above, each of the multiple switches SW1 to SW9-3 included in the column control block 100 can be selectively turned on or off according to the operating mode (e.g., sensing operation or display operation). Therefore, the first source driver SD1 to the third source driver SD3 can be as described in reference to... Figures 6 to 9 Connect as described.

[0130] Figure 14 It is used to describe Figure 13 The timing diagram of the operation of the column control block. Figure 15A to Figure 15C It shows the basis Figure 14 A diagram illustrating the configuration of column control blocks in a timing diagram. For brevity, an example is shown. Figure 14 The timing diagram is shown below; in the timing diagram, it is assumed that a high level indicates that the switch is turned on, making the switch conductive, and that a low level indicates that the switch is turned off, making the switch either open or non-conductive. Additionally, for simplicity, see Figures 15A to 1590. Figure 15C The text shows the on switch, while the off switch can be omitted.

[0131] Reference Figure 1 , Figure 13 and Figure 14 The display driver integrated circuit (DDI) can perform sensing operations S1, S2, and S3 after executing the display operation (DP). For example, in the display operation (DP), the fourth switch (SW4) and the eighth switch (SW8) can be turned on, and the sixth switch (SW6) can select the decoding voltage VDEC. The remaining switches (SW1, SW2, SW3, SW5, SW7-1, SW7-2, SW7-3, SW9-1, SW9-2, and SW9-3) can be turned off.

[0132] In this case, column control block 100 can be as follows: Figure 15AThis is implemented as shown. Therefore, the outputs and inverting inputs of the corresponding first source drivers SD1 to third source drivers SD3 can be connected via the fourth switch SW4 (i.e., feedback), and the outputs of the first source drivers SD1 to third source drivers SD3 can be connected to the first pads PD1 to third pads PD3 respectively via the eighth switch SW8. Furthermore, the first decoding voltage VDEC1 to third decoding voltage VDEC3 can be provided to the non-inverting inputs of the first source drivers SD1 to third source drivers SD3 respectively via the sixth switch SW6. Therefore, when the fourth switch SW4 and the eighth switch SW8 are turned on and the first decoding voltage VDEC1 to third decoding voltage VDEC3 is selected via the sixth switch SW6, the first source drivers SD1 to third source drivers SD3 can provide the first decoding voltage VDEC1 to third decoding voltage VDEC3 to the pixels connected to the first pads PD1 to third pads PD3 respectively.

[0133] After performing the display operation DP, you can execute... Figure 14 The first sensing operation to the third sensing operation S1, S2 and S3 are shown. The first sensing operation S1 can refer to the operation of sensing pixel information from a pixel connected to the first pad PD1, the second sensing operation S2 can refer to the operation of sensing pixel information from a pixel connected to the second pad PD2, and the third sensing operation S3 can refer to the operation of sensing pixel information from a pixel connected to the third pad PD3.

[0134] like Figure 14 As shown, the first sensing operations S1 to the third sensing operations S3 can be divided into corresponding reset cycles RP1 to RP3 and sensing cycles SP1 to SP3. For example, the first sensing operation S1 can be divided into a first reset cycle RP1 and a first sensing cycle SP1. In the first reset cycle RP1, the column control block 100 can perform a reset operation by providing the first reset data VDATA1 to the pixel connected to the first pad PD1. In the first sensing cycle SP1, the column control block 100 can be configured to sense the first pixel information PI1 of the pixel connected to the first pad PD1.

[0135] Specifically, in the first reset cycle RP1 of the first sensing operation S1, the first switch SW1, the second switch SW2, the third switch SW3 and the fifth switch SW5 can be turned on, the sixth switch SW6 can select the sensing reference voltage VP, one of the seventh switches SW7-1 to SW7-3, SW7-1 and the corresponding switch SW9-1 of the ninth switches SW9-1 to SW9-3 can be turned on, and the remaining switches SW4 and SW8 can be turned off.

[0136] In this case, it is possible to... Figure 15B The column control block 100 is implemented as shown. Therefore, the internal nodes of the first source driver SD1 to the third source driver SD3 can be connected in parallel via the second switch SW2, and the inverting inputs and outputs of the first source driver SD1 to the third source driver SD3 can be connected via the third switch SW3 and the fifth switch SW5. The first pad PD1 can be connected to the inverting input of the first source driver SD1 to the third source driver SD3 via one of the seventh switches SW7-1 to SW7-3 (SW7-1), and the first reset data VDATA1 can be provided to the first pad PD1 via one of the ninth switches SW9-1 to SW9-3 (SW9-1). Therefore, a specific node of the pixel connected to the first pad PD1 (e.g., Figure 2A The first node n1 can be reset to the level corresponding to the first reset data VDATA1 by one of the ninth switches SW9-1 to SW9-3. When the first switch SW1 (i.e., the reset switch RST) is turned on, the inverting input and output terminals of the first source driver SD1 to the third source driver SD3 can be reset to the level corresponding to the first reset data VDATA1.

[0137] Therefore, through the above reset operation, the input / output terminals of the merged first source driver SD1 to the third source driver SD3 and the corresponding specific nodes of the pixels can be reset.

[0138] Then, in the first sensing cycle SP1 of the first sensing operation S1, one of the ninth switches SW9-1 to SW9-3, switch SW9-1 and the first switch SW1, can be turned off, and the remaining switches can maintain the state in the first reset cycle RP1.

[0139] In this case, it is possible to... Figure 15C The column control block 100 is implemented as shown. Therefore, pixel information can be received from a specific node of a pixel connected to the first pad PD1 via the first pad PD1. This pixel information can be amplified by the merged first source driver SD1 to the third source driver SD3, and the amplified information can be output through the output terminals of the merged first source driver SD1 to the third source driver SD3. Therefore, as... Figure 15C As shown, in the first sensing operation S1, the first source driver SD1 to the third source driver SD3 can be used as a low-noise amplifier or integrator configured to sense pixel information.

[0140] In an example embodiment, the reset levels of the input / output terminals of the first source driver SD1 to the third source driver SD3, combined through the first reset cycle RP1, and the pixel information sensed in the first sensing cycle SP1, can be provided to the analog-to-digital converter 15 (see reference). Figure 1 The analog-to-digital converter 15 can perform correlated double sampling on each of the reset level and pixel information to output sense data DS.

[0141] The second reset cycle RP2 and the second sensing cycle SP2 of the second sensing operation S2, and the third reset cycle RP3 and the third sensing cycle SP3 of the third sensing operation S3 are similar to the first reset cycle RP1 and the first sensing cycle SP1 of the first sensing operation S1. The difference is that the switches that are turned on in the seventh switches SW7-1 to SW7-3 and the ninth switches SW9-1 to SW9-3 are different. Therefore, additional descriptions will be omitted to avoid redundancy.

[0142] In the example embodiment, Figure 14 The switch signal shown can be included in the mode signal MS from control block 13, or it can be generated based on the mode signal MS. Figure 14 The switch signal shown.

[0143] As described above, the display driver integrated circuit (DDI) according to the example embodiment can use the source driver as a data driving circuit for controlling pixels or as a low-noise amplifier for receiving pixel information from pixels, depending on the operating mode (e.g., display mode or sensing mode). Therefore, since a separate low-noise amplifier for receiving pixel information can be omitted, the size and cost of the display driver integrated circuit (DDI) can be reduced.

[0144] Figure 16 It is used to describe Figure 1 A timing diagram illustrating the operation of the display driver integrated circuit. For ease of description, components unnecessary for describing the operation of the display driver integrated circuit may be omitted, and control signals (e.g., VSYNC and HSYNC) used for the operation of the display driver integrated circuit can be simply represented. For ease of description, the term "display driver integrated circuit DDI" is used. The display driver integrated circuit DDI may include references to... Figure 1 The components described include control block 13, memory 14, analog-to-digital converter 15, and column control block 100.

[0145] Reference Figure 1 and Figure 16The display driver integrated circuit (DDI) can receive vertical synchronization signals VSYNC and horizontal synchronization signals HSYNC from external devices (e.g., AP, GPU, or host device). In response to the received signals VSYNC and HSYNC, the display driver integrated circuit (DDI) can control the pixels PX of the display panel 11 and sense pixel information PI from the pixels PX. Therefore, the display driver integrated circuit (DDI) can perform display operation DP and sensing operation "S" on the pixels in response to the received signals VSYNC and HSYNC.

[0146] For example, the vertical sync signal VSYNC can be a signal used to determine a frame to be displayed on the display panel 11. The horizontal sync signal HSYNC can be a signal used to determine a row of pixels to be displayed on the display panel 11. The display driver integrated circuit DDI can display a frame through the display panel 11 in sync with the vertical sync signal VSYNC. The display driver integrated circuit DDI can control multiple rows of pixels to be displayed through the display panel 11 in sync with the horizontal sync signal HSYNC.

[0147] In this case, the display driver integrated circuit DDI (or column control block 100) according to the example embodiment can repeatedly perform pixel display operations and pixel sensing operations in each cycle of the horizontal synchronization signal HSYNC. For example, in the first cycle of the horizontal synchronization signal HSYNC, the column control block 100 can perform at least one of the following: a pixel display operation DP in the first row and a pixel sensing operation "S" in at least one of the pixels in the first row.

[0148] In the example embodiment, as referred to Figure 14 and Figure 15A The description states that display operation DP can be performed by connecting the outputs of multiple source drivers to corresponding pixel lines via switching circuit 110. (See reference...) Figure 14 , Figure 15B and Figure 15C The description indicates that a sensing operation "S" can be performed when the switching circuit 110 connects multiple source drivers in parallel and connects at least one pixel line to the input terminal (e.g., the inverting input terminal) of the parallel-connected source drivers.

[0149] During the second cycle of the horizontal sync signal HSYNC, the column control block 100 can perform at least one of the following: a display operation DP for a pixel in the second row and a sensing operation "S" for at least one pixel in the second row. Similarly, during each cycle of the horizontal sync signal HSYNC, the column control block 100 can perform at least one of the following: a display operation DP for a pixel in the corresponding row and a sensing operation "S" for at least one pixel in the corresponding row. Therefore, the display driver integrated circuit DDI according to the example embodiment can perform a sensing operation on a specific pixel or a given pixel while performing a pixel display operation. In this case, the display driver integrated circuit DDI can perform both the display operation and the sensing operation using the same source driver.

[0150] Figure 16 The timing diagram shown is an example and can be changed. For example, during the operation of displaying one frame (i.e., during one cycle of the vertical sync signal VSYNC), the display driver integrated circuit DDI can perform sensing operations only on a portion of the row of pixels or a portion of the pixels.

[0151] Figure 17A and Figure 17B It is used to describe according to Figure 16 The timing diagram illustrates the display and sensing operations. For simplicity, components unnecessary for describing the display and sensing operations can be omitted, and for ease of description, it is assumed that the display panel 11 includes 4×6 pixels PX in the first row R1 to the fourth row R4 and the first column C1 to the sixth column C6.

[0152] Reference Figure 16 and Figure 17A The display driver integrated circuit (DDI) can perform display operations. For example, a display operation can be performed on the pixel at the first row R1. In this case, the first source driver SD1 to the sixth source driver SD6 of the display driver integrated circuit DDI can operate to provide the first decoding voltage VDEC11 to the sixth decoding voltage VDEC16 to the pixel PX at the first row R1 and the first column C1 to the sixth column C6. Therefore, the first source driver SD1 to the sixth source driver SD6 can be connected to the pixel lines corresponding to the first column C1 to the sixth column C6, respectively. This connection can be made by the switching circuit 110.

[0153] After performing the display operation DP on pixel PX at the first row R1, the display driver integrated circuit DDI can perform sensing operations "S" on some pixels among the pixels at the first row R1. For example, as Figure 17BAs shown, the display driver integrated circuit DDI can receive pixel information PI11 of pixel PX at the first row R1 and the first column C1, and pixel information PI14 of pixel PX at the first row R1 and the fourth column C4, respectively. In this case, as shown in the reference... Figures 1 to 15C The description states that the first source drivers SD1 to the third source drivers SD3 can be connected in parallel and combined, thus receiving, sensing, amplifying, or outputting pixel information PI11 from the pixel PX at the first row R1 and the first column C1. Similarly, the fourth source drivers SD4 to the sixth source drivers SD6 can be connected in parallel and combined, thus receiving, sensing, amplifying, or outputting pixel information PI14 from the pixel PX at the first row R1 and the fourth column C4. Therefore, in sensing operations, the first source drivers SD1 to the third source drivers SD3 can operate as a low-noise amplifier or integrator, and the fourth source drivers SD4 to the sixth source drivers SD6 can operate as another low-noise amplifier or integrator.

[0154] As described above, the display driver integrated circuit (DDI) according to the example embodiment can perform pixel display operations and sensing operations using multiple source drivers. Therefore, since a separate low-noise amplifier for pixel sensing operations can be eliminated, the size of the display driver integrated circuit (DDI) can be reduced.

[0155] In an example embodiment, when the number of source drivers included in the display driver integrated circuit (DDI) is "a×n" and the source drivers are combined in units of "n", pixel information can be received, sensed, amplified, or output from each of the "a" pixels in the same row through a single sensing operation. In the example embodiment, the unit in which the source drivers are combined, that is, the number of source drivers to be combined to implement a low-noise amplifier, can be 30 to 50.

[0156] Here, an example embodiment is described in which multiple source drivers are connected in parallel or combined during pixel sensing operations. However, for example, a single source driver can be configured to receive pixel information during sensing operations and control pixels during display operations. In this case, during sensing operations, the pixel line connected to the pixel can be connected to the inverting input of the source driver, and the output of the source driver can be connected to an analog-to-digital converter. During display operations, the pixel line connected to the pixel can be connected to both the output and inverting input of the source driver, and the source driver can amplify and output the decoded voltage received through its non-inverting input.

[0157] Figure 18 It is used to describe Figure 1The timing diagram shows the operation of the display driver integrated circuit. For ease of description, additional descriptions associated with the above components can be omitted to avoid redundancy. See also... Figure 1 and Figure 18 The display driver integrated circuit DDI can perform display operation DP and multiple sensing operations S1 to S3 in one cycle of the horizontal synchronization signal HSYNC.

[0158] In this context, a sensing operation (e.g., a first sensing operation S1) can refer to the operation of sensing pixel information from a given unit of pixels. For example, in display panel 11, suppose there are "a×n" pixels arranged in the first row, and the number of source drivers used to drive the "a×n" pixels is "a×n". In this case, when the "n" source drivers are combined (i.e., the combined unit of the source drivers is "n") to operate as a low-noise amplifier, pixel information can be sensed from "a" pixels through a single sensing operation. In this case, "n" sensing operations can be performed to sense the pixel information of all "a×n" pixels in the first row.

[0159] Therefore, in one cycle of the horizontal synchronization signal HSYNC, the display driver integrated circuit DDI can perform one display operation (i.e., the operation of controlling the pixels in a row) and multiple sensing operations (i.e., the sensing operation of sensing the pixel information of all pixels in a row).

[0160] In another example embodiment, the number of sensing operations performed within one cycle of the horizontal sync signal HSYNC can vary or be changed. For example, multiple sensing operations can be performed on some pixels in a specific row within one cycle of the horizontal sync signal HSYNC, and multiple sensing operations can be performed on the remaining pixels in that specific row within one cycle of the horizontal sync signal HSYNC in the next frame (i.e., the next cycle of the vertical sync signal VSYNC). The number of pixel sensing operations, the cycle of pixel sensing operations, or the position of the pixel targeted by the sensing operations can vary or be modified depending on the implementation of the display device 10.

[0161] Figure 19 It is used to describe Figure 1 The timing diagram shows the operation of the display driver integrated circuit. For ease of description, additional descriptions associated with the above components will be omitted to avoid redundancy. See also... Figure 1 and Figure 19The display driver integrated circuit (DDI) can perform display operation (DP) in each cycle of the horizontal sync signal (HSYNC), and can perform sensing operation (S) in some cycles of the horizontal sync signal (HSYNC). For example, when it is desired to sense pixel information from pixels in a specific row, the display driver integrated circuit (DDI) can perform sensing operation (S) on all or part of the pixels in the specific row during the cycle of the horizontal sync signal (HSYNC) that performs display operation (DP) on the specific row. Therefore, the display driver integrated circuit (DDI) can perform sensing operation only in some cycles while displaying a frame.

[0162] Figure 20 It is used to describe Figure 1 The timing diagram shows the operation of the display driver integrated circuit. For ease of description, additional descriptions associated with the above components will be omitted to avoid redundancy. See also... Figure 1 and Figure 20 The display driver integrated circuit (DDI) can perform display operation DP in each cycle of the horizontal synchronization signal HSYNC. The display driver integrated circuit (DDI) can perform multiple sensing operations S1 to Sn during the vertical blanking cycle VBLANK. For example, the vertical blanking cycle VBLANK can exist from when display operation DP is fully performed on all rows of the display panel 11 until the next vertical synchronization signal VSYNC is triggered. During the vertical blanking cycle VBLANK, the display driver integrated circuit (DDI) can perform multiple sensing operations S1 to Sn for sensing all or part of the pixel information of the pixels of the display panel 11.

[0163] In another example embodiment, the period for performing the sensing operation, the number of times the sensing operation is performed consecutively, etc., may vary or be modified depending on the implementation of the display panel 11, the pixel structure, the method of implementing the display driver integrated circuit (DDI), etc.

[0164] Figure 21 It is shown Figure 1 A block diagram of the compensation data generation method for the control block. Refer to Figure 1 and... Figure 21 The memory 14 can be based on a reference Figures 1 to 20 The described operation stores sensing data DS (i.e., pixel information PI) from multiple pixels.

[0165] Control block 13 may include data modulation block 13a and compensation module 13g. Compensation module 13g may determine a compensation value based on sensing data DS stored in memory 14. For example, as described above, sensing data DS stored in memory 14 may refer to pixel information PI for each of the plurality of pixels PX, and pixel information PI may include information about the degree of degradation of the corresponding pixel (e.g., the degree of degradation of a transistor or an organic light-emitting diode). Compensation module 13g may determine a compensation value that can compensate for the degradation of the corresponding pixel based on sensing data DS.

[0166] Data modulation block 13a can receive display data DD from an external device (e.g., an AP, GPU, or host device). Data modulation block 13a can modulate or compensate the display data DD based on a compensation value determined by compensation module 13g to output compensated data DD_C. For example, when controlling pixels individually based on display data DD provided by an external device, the expected brightness may not be achieved due to the degradation of each pixel. When controlling pixels based on compensated data DD_C, because the degradation of each pixel is compensated, each pixel in the pixel can exhibit the expected brightness. The data compensation scheme of control block 13 described above is an example.

[0167] Figure 22 This is a block diagram illustrating a display device according to an example embodiment. For ease of description, repeated descriptions of the above components may be omitted to avoid redundancy. See also... Figure 22 The display device 1000 may include a display panel 1100, a gate driver 1200, and a display driver integrated circuit DDI. The display driver integrated circuit DDI may include a timing controller 1300, multiple source driver integrated circuits (ICs) 1411 to 141n, and multiple switch blocks 1421 to 142n. The display panel 1100, gate driver 1200, and timing controller 1300 have been described above; therefore, additional descriptions may be omitted to avoid redundancy.

[0168] Each of the multiple source driver ICs 1411 to 141n may include multiple source drivers. The multiple source drivers can be configured to control multiple pixels included in the display panel 1100 as described above.

[0169] Multiple switching blocks 1421 to 142n can perform switching operations between multiple source driver ICs 1411 to 141n and the display panel 1100. For example, under the control of the timing controller 1300, the multiple switching blocks 1421 to 142n can perform switching operations such that each of the multiple source driver ICs 1411 to 141n includes multiple source drivers that control multiple pixels of the display panel 1100 or receive pixel information PI from multiple pixels. In an example embodiment, each of the multiple switching blocks 1421 to 142n can be a reference... Figures 1 to 21 The described switching circuit.

[0170] In an example embodiment, during sensing operations, the multiple source drivers included in each of the multiple source driver ICs 1411 to 141n can be combined in a given unit. For example, if the number of source drivers included in a single source driver IC (e.g., 1411) is "a×m", the source drivers can be combined in units of "m". In this case, during sensing operations, the number of low-noise amplifiers or integrators implemented in a single source driver IC (e.g., 1411) can be "a". If the number of source driver ICs included in a display device 1000 is "n", the number of low-noise amplifiers or integrators implemented using source drivers during sensing operations can be "a×n". Therefore, during a sensing operation, pixel information PI can be sensed from "a×n" pixels.

[0171] Figure 23 This is a block diagram illustrating an electronic device according to an example embodiment. (Refer to...) Figure 23 The electronic device 2000 may include a main processor 2100, a touch panel 2200, a touch driver integrated circuit 2202, a display panel 2300, a display driver integrated circuit 2302, a system memory 2400, a storage device 2500, an audio processor 2600, a communication block 2700, and an image processor 2800. In an example embodiment, the electronic device 2000 may be one of various electronic devices such as a portable communication terminal, a personal digital assistant (PDA), a portable media player (PMP), a digital camera, a smartphone, a tablet computer, a laptop computer, and a wearable device.

[0172] The main processor 2100 can control the overall operation of the electronic device 2000. The main processor 2100 can control / manage the operation of the components of the electronic device 2000. The main processor 2100 can handle various operations for the purpose of operating the electronic device 2000.

[0173] Touch panel 2200 can be configured to sense user touch input under the control of touch driver integrated circuit (TDI) 2202. Display panel 2300 can be configured to display image information under the control of display driver integrated circuit (DDI) 2302. In an example embodiment, DDI 2302 may be a reference Figures 1 to 22 The described display driver integrated circuit (DDI) or may be based on the reference Figures 1 to 22 Perform the operation according to the described method.

[0174] System memory 2400 may store data for the operation of electronic device 2000. For example, system memory 2400 may include volatile memory such as static random access memory (SRAM), dynamic RAM (DRAM), or synchronous DRAM (SDRAM) and / or non-volatile memory such as phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), or ferroelectric RAM (FRAM).

[0175] Storage device 2500 can store data regardless of whether power is provided. For example, storage device 2500 may include at least one of various non-volatile memories (such as flash memory, PRAM, MRAM, ReRAM, and FRAM). For example, storage device 2500 may include the built-in memory and / or removable memory of electronic device 2000.

[0176] The audio processor 2600 can process audio signals using the audio signal processor 2610. The audio processor 2600 can receive audio input via the microphone 2620 or provide audio output via the speaker 2630.

[0177] Communication block 2700 can exchange signals with external devices / systems via antenna 2710. The transceiver 2720 and modulator / demodulator (MODEM) of communication block 2700 can process signals exchanged with external devices / systems based on at least one of various wireless communication protocols (Long Term Evolution (LTE), Global Microwave Access Interoperability (WiMax), Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Bluetooth, Near Field Communication (NFC), Wi-Fi, and Radio Frequency Identification (RFID)).

[0178] The image processor 2800 can receive light through the lens 2810. The image device 2820 and image signal processor (ISP) 2830 included in the image processor 2800 can generate image information about external objects based on the received light.

[0179] By summarizing and reviewing, it is understood that the transistors and organic light-emitting diodes (OLEDs) of a pixel may degrade over time. When transistors and OLEDs degrade, the amount of current flowing through the OLEDs may change, and therefore, the pixel brightness may differ from the target brightness. Therefore, the display device can implement a sensing operation to measure the degree of pixel degradation, as well as a compensation operation to compensate for the pixel degradation as a result of the sensing operation.

[0180] As previously described, the embodiments may provide a display device that uses a source driver to sense pixel information for external compensation of the display device, without requiring a separate low-noise amplifier.

[0181] According to an example embodiment, the display driver integrated circuit can use multiple source drivers to drive multiple pixels during pixel display operations, and can use multiple source drivers to sense pixel information from multiple pixels during pixel sensing operations. Therefore, since a separate low-noise amplifier or integrator for receiving pixel information used in external compensation of the display device can be omitted, the size and cost of the display driver integrated circuit can be reduced.

[0182] The components described in the specification using terms such as "part," "unit," "module," and "block," and the functional blocks shown in the accompanying drawings, can be implemented using software, hardware, or a combination thereof. For example, software can be machine code, firmware, embedded code, and application software. Hardware can include circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive components, or a combination thereof.

[0183] Exemplary embodiments have been disclosed herein. Although specific terminology has been used, its use and interpretation are limited to a general and descriptive meaning and are not intended to be limiting. In some instances, as will be apparent to one of ordinary skill in the art upon filing this application, unless otherwise specifically stated, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the following claims.

Claims

1. A display driver integrated circuit for a display panel, the display driver integrated circuit comprising: Timing controller; The first source driver includes a first inverting input terminal, a first non-inverting input terminal, and a first output terminal; The second source driver includes a second inverting input terminal, a second non-inverting input terminal, and a second output terminal; as well as A switching circuit, connected to the display panel via a first pad and a second pad, includes a plurality of switches connected between the first pad and the second pad and the first source driver and the second source driver. Under the control of the timing controller, the switching circuit is configured to perform one of the following operations: First switch operation: Control the plurality of switches such that the first inverting input terminal and the first output terminal are connected to the first pad, a first decoding voltage is applied to the first non-inverting input terminal, the second inverting input terminal and the second output terminal are connected to the second pad, and a second decoding voltage is applied to the second non-inverting input terminal; as well as Second switch operation: Control the plurality of switches such that a sensed reference voltage is applied to the first non-inverting input terminal and the second non-inverting input terminal, the first output terminal and the second output terminal are connected to an output node, and the first inverting input terminal and the second inverting input terminal are connected to one of the first pad and the second pad.

2. The display driver integrated circuit according to claim 1, wherein, The switching circuit is configured to perform the first switching operation, and when the switching circuit performs the first switching operation, the first source driver outputs the first decoding voltage to the display panel through the first pad, and the second source driver outputs the second decoding voltage to the display panel through the second pad.

3. The display driver integrated circuit according to claim 1, wherein, The switching circuit is configured to perform the second switching operation, and when the switching circuit performs the second switching operation, the first source driver and the second source driver receive pixel information provided by one of the first pads and the second pads through the first inverting input terminal and the second inverting input terminal, and output the received pixel information through the first output terminal and the second output terminal.

4. The display driver integrated circuit according to claim 3, wherein, The pixel information indicates the degree of degradation of a pixel among the plurality of pixels included in the display panel that is connected to one of the first pads and the second pads.

5. The display driver integrated circuit according to claim 3, further comprising: An analog-to-digital converter configured to convert pixel information output through the first output terminal and the second output terminal into sensing data; as well as A memory configured to store the sensed data.

6. The display driver integrated circuit according to claim 1, wherein, The plurality of switches includes: A first display output switch is connected between the first output terminal and the first pad; A first display feedback switch is connected between the first output terminal and the first inverting input terminal; A first sensing feedback switch is connected between the first inverting input terminal and the input node; A first sensing output switch is connected between the first output terminal and the output node; A first sensing input switch is connected between the input node and the first pad; A first sensing reset switch is connected between the first pad and the first reset data node; A first selection switch is configured to select one of the first decoding voltage and the sensing reference voltage to provide it to the first non-inverting input. A second display output switch is connected between the second output terminal and the second pad; The second display feedback switch is connected between the second output terminal and the second inverting input terminal; A second sensing feedback switch is connected between the second inverting input terminal and the input node; A second sensing output switch is connected between the second output terminal and the output node; A second sensing input switch is connected between the input node and the second pad; A second sensing reset switch is connected between the second pad and the second reset data node; A second selection switch is configured to select one of the second decoding voltage and the sensed reference voltage to provide it to the second non-inverting input. A reset switch, connected between the input node and the output node; and A capacitor is connected between the input node and the output node.

7. The display driver integrated circuit according to claim 6, wherein, The switching circuit is configured to perform the first switching operation, and when the switching circuit performs the first switching operation, the first display output switch and the second display output switch, as well as the first display feedback switch and the second display feedback switch, are turned on; the first selection switch selects the first decoding voltage to provide it to the first non-inverting input terminal; the second selection switch selects the second decoding voltage to provide it to the second non-inverting input terminal; and the first sensing feedback switch and the second sensing feedback switch, the first sensing output switch and the second sensing output switch, the first sensing input switch and the second sensing input switch, the first sensing reset switch and the second sensing reset switch, and the reset switch are turned off.

8. The display driver integrated circuit according to claim 6, wherein: The switching circuit is configured to perform the second switching operation. The second switching operation includes a reset cycle and a sensing cycle, and During the reset cycle, one of the first sensor reset switch and the second sensor reset switch is turned on, one of the first sensor input switch and the second sensor input switch is turned on, the first sensor feedback switch and the second sensor feedback switch, the first sensor output switch and the second sensor output switch, and the reset switch are turned on, and the first display output switch and the second display output switch, as well as the first display feedback switch and the second display feedback switch, are turned off.

9. The display driver integrated circuit according to claim 8, wherein, During the reset cycle, when the first sensing reset switch of the first sensing reset switch and the second sensing reset switch is turned on, the first sensing input switch of the first sensing input switch and the second sensing input switch is turned on, and when the second sensing reset switch of the first sensing reset switch and the second sensing reset switch is turned on, the second sensing input switch of the first sensing input switch and the second sensing input switch is turned on.

10. The display driver integrated circuit according to claim 8, wherein, During the sensing cycle following the reset cycle, the first sensing reset switch, the second sensing reset switch, and the reset switch are disconnected.

11. The display driver integrated circuit according to claim 1, wherein, The timing controller controls the switching circuit such that the second switching operation is performed at least once during one cycle of the vertical synchronization signal received from the external device.

12. A display driver integrated circuit for a display panel, the display driver integrated circuit comprising: Timing controller; A column control block includes a plurality of source drivers and is configured to, under the control of the timing controller, control the voltage of a plurality of pixel lines connected to the display panel by connecting the plurality of source drivers in a first configuration, wherein each source driver is connected one-to-one to each pixel line, and to receive pixel information through the plurality of pixel lines by connecting the plurality of source drivers in a second configuration, wherein at least two source drivers are commonly connected to a single pixel line. An analog-to-digital converter configured to convert pixel information received by the column control block into sensing data; as well as A memory configured to store the sensed data.

13. The display driver integrated circuit according to claim 12, wherein, The column control block further includes a switching circuit configured to connect between the plurality of source drivers and the plurality of pixel lines in either the first configuration or the second configuration under the control of the timing controller.

14. The display driver integrated circuit according to claim 13, wherein, The switching circuit includes: Multiple display output switches are connected between the multiple pixel lines and the multiple source drivers; Multiple display feedback switches are connected between the output terminals and the inverting input terminals of the multiple source drivers; Multiple sensing feedback switches are connected between the inverting input terminals of the multiple source drivers and the input nodes; Multiple sensing output switches are connected between the output terminals and output nodes of the multiple source drivers; Multiple sensing input switches are connected between the input node and the multiple pixel lines; Multiple selection switches are configured to select multiple decoding voltages or sensing reference voltages to provide them to the non-inverting inputs of the multiple source drivers; Multiple sense reset switches are configured to selectively provide multiple sense reset data to the multiple pixel lines, respectively; A reset switch, connected between the input node and the output node; and A capacitor is connected between the input node and the output node.

15. The display driver integrated circuit according to claim 14, wherein, When the plurality of display output switches and the plurality of display feedback switches are turned on, the plurality of selection switches select the plurality of decoding voltages respectively, and the plurality of sensing feedback switches, the plurality of sensing output switches, the plurality of sensing input switches, the plurality of sensing reset switches and the reset switch are turned off, and the plurality of source drivers control the voltage of the plurality of pixel lines.

16. The display driver integrated circuit according to claim 14, wherein, When the plurality of display output switches and the plurality of display feedback switches are turned off, the plurality of selection switches select the sensing reference voltage, and a corresponding one of the plurality of sensing input switches, a corresponding one of the plurality of sensing reset switches, the plurality of sensing feedback switches, the plurality of sensing output switches, and the reset switch are turned on. The plurality of source drivers output a reset voltage, and... Specifically, after the reset voltage is output from the plurality of source drivers, when the corresponding one of the plurality of sensing reset switches and the reset switch are disconnected, the plurality of source drivers receive the pixel information from the pixel line connected to the corresponding one of the plurality of sensing input switches and output the received pixel information.

17. A display device, comprising: The display panel includes multiple pixels; as well as A display driver integrated circuit configured to control the plurality of pixels, the display driver integrated circuit including a plurality of source drivers connected to the plurality of pixels via a plurality of pixel lines. In the display operation of the plurality of pixels, each of the plurality of source drivers is connected one-to-one to each of the plurality of pixel lines, so as to output the plurality of decoding voltages to the plurality of pixel lines respectively. In the pixel sensing operation among the plurality of pixels, at least two of the plurality of source drivers are commonly connected to a single pixel line among the plurality of pixel lines, and the single pixel line is to be connected to the pixel and receive pixel information from the pixel.

18. The display device according to claim 17, wherein, The multiple pixels are arranged in multiple rows and columns in the display panel. The display operation refers to the operation of controlling the brightness of a pixel located in one of the multiple rows, and The sensing operation refers to the operation of receiving pixel information from at least one pixel in one row of the multiple rows.

19. The display device according to claim 18, wherein, The display operation is performed once in each cycle of the horizontal synchronization signal, and The sensing operation is performed m times in n cycles of the horizontal synchronization signal, where m and n are natural numbers.

20. The display device according to claim 18, wherein, The display operation is performed once in each cycle of the horizontal synchronization signal, and The sensing operation is performed "m" times during the vertical blank period, where m is a natural number.

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