Display device

Abstract

A display device is provided. The display device includes an active area, an inactive area, a plurality of inactive fan-out wirings, a plurality of signal wirings, and a plurality of connection wirings, wherein the active area includes a plurality of pixels arranged in a matrix shape, the inactive area is disposed on one side of the active area in a first direction and includes pad units, the plurality of inactive fan-out wirings are disposed in the inactive area and connected to the pad units, the plurality of signal wirings extend in the first direction to pass through the active area and are connected to the plurality of pixels, and each of the plurality of connection wirings at least partially passes through the active area and the plurality of connection wirings connects some of the inactive fan-out wirings and some of the signal wirings.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2020-0019503, filed on February 18, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This invention relates to display devices. Background Technology

[0004] With the development of multimedia, the importance of display devices has increased. Correspondingly, various types of display devices have been developed, such as liquid crystal displays (LCDs), organic light-emitting diode displays (OLEDs), and inorganic light-emitting diode displays.

[0005] The display device includes an effective area for displaying an image and a non-effective area arranged around the effective area. Wiring for applying signals to the effective area is arranged in the non-effective area.

[0006] Recently, display devices with thin bezels have become preferred. When the area of ​​the non-effective region is too small for a thin bezel, the path for the signal to pass through becomes insufficient due to fan-out wiring.

[0007] To ensure the path of fan-out wiring even in narrow bezel structures, one approach is to have some of the fan-out wiring pass through the active region. However, when fan-out wiring passes through the active region, the order of data signals is altered, and therefore, additional mapping of the driver chip may be required. Furthermore, signal wiring may be made of different conductive layers for each region, and in this case, brightness differences may occur for each region due to the process dispersion of each conductive layer. Summary of the Invention

[0008] Aspects of the present invention will provide a display device including interconnect wiring through an effective area and capable of employing a general-purpose driver chip and reducing brightness differences in each area due to process dispersion of each conductive layer.

[0009] However, the invention is not limited to those described herein. The above and other aspects of the invention will become more apparent to those skilled in the art from the following detailed description of the invention.

[0010] According to embodiments of the present disclosure, a display device includes an effective area, an ineffective area, a plurality of ineffective fan-out wirings, a plurality of signal wirings, and a plurality of connection wirings. The effective area includes a plurality of pixels arranged in a matrix shape and receiving data signals via data lines. The ineffective area is disposed on one side of the effective area in a first direction and includes pad units. The plurality of ineffective fan-out wirings are disposed in the ineffective area and connected to the pad units. The plurality of signal wirings extend in the first direction through the effective area and are connected to the plurality of pixels. Each of the plurality of connection wirings at least partially passes through the effective area and connects some of the ineffective fan-out wirings and some of the signal wirings. Each of the plurality of connection wirings includes a first extension extending in the first direction, a second extension extending in a second direction intersecting the first direction, and a third extension extending in the first direction. At least two pixels are disposed between corresponding extensions of two adjacent connection wirings, and the at least two pixels are arranged in a direction spaced apart from each other along the corresponding extensions.

[0011] The plurality of pixels may include a plurality of pixel columns and a plurality of pixel rows, each of the plurality of pixel columns including pixels arranged in a first direction, each of the plurality of pixel rows including pixels arranged in a second direction, and a second extension of the connecting wiring may be disposed between two adjacent pixel rows in the plurality of pixel rows.

[0012] At least two of the multiple pixel rows may be arranged between the second extensions of two adjacent connecting wires.

[0013] The display device may further include a first dummy wiring pattern disposed between the connecting wires, wherein the first dummy wiring pattern may include a first sub-pattern disposed between second extensions of two adjacent connecting wires, and the first sub-pattern may extend in a second direction.

[0014] The first sub-pattern can be arranged in the space between two adjacent pixel rows in a plurality of pixel rows, and the second extension of the connecting wiring can be not arranged in this space.

[0015] The first dummy wiring pattern may include a plurality of second sub-patterns, wherein the plurality of second sub-patterns are separated from the second extension portions of the two connecting wirings and are arranged on an imaginary extension line that the second extension portions reach if the second extension portions extend further.

[0016] At least some of the first dummy wiring patterns can be directly connected to the connection wiring.

[0017] The effective area may include an effective fan-out area and a main effective area. In the effective fan-out area, the connecting wiring is arranged to be adjacent to the ineffective area. The main effective area is the area in the effective area other than the effective fan-out area and no connecting wiring is arranged in the main effective area. The display device may also include a second dummy wiring pattern arranged in the main effective area and extending in a second direction, and a third dummy wiring pattern arranged in the main effective area and extending in a first direction.

[0018] The second dummy wiring pattern can intersect with the signal wiring and be arranged above multiple pixel columns.

[0019] The third dummy wiring pattern is arranged in the space between the pixel columns in the pixel rows of the main effective area.

[0020] Each of the multiple signal wirings can be arranged between pixel columns, and each of the first and third extensions of the connecting wirings can be arranged in a space between different pixel columns.

[0021] At least two of the multiple pixel columns may be arranged between the first extensions of two adjacent connection wires.

[0022] The first and third extensions of at least one of the multiple connection wirings may be arranged in the space between two adjacent pixel columns.

[0023] Multiple signal wirings may be included in a first data conductive layer, and multiple connection wirings may be included in a second data conductive layer that is different from the first data conductive layer.

[0024] Ineffective fan-out wiring may include a first ineffective fan-out wiring connected to a connection wiring and a second ineffective fan-out wiring directly connected to a signal wiring, and the first ineffective fan-out wiring and the second ineffective fan-out wiring may be included in different conductive layers.

[0025] According to another embodiment of this disclosure, the display device includes an effective region, an ineffective region, a plurality of ineffective fan-out wirings, a plurality of signal wirings, a plurality of connection wirings, and a plurality of dummy wiring patterns. The effective region contains a plurality of pixels. The ineffective region is located on one side of the effective region in a first direction. The plurality of ineffective fan-out wirings are located in the ineffective region and include a first ineffective fan-out wiring and a second ineffective fan-out wiring arranged alternately along a second direction intersecting the first direction. The plurality of signal wirings extend in the first direction, including an inner effective region within the effective region that overlaps with the ineffective fan-out wirings when they extend in the first direction, and an outer effective region within the effective region that does not overlap with the ineffective fan-out wirings. The plurality of connection wirings connect the ineffective fan-out wirings and the signal wirings located in the outer effective region via the effective region. The plurality of dummy wiring patterns are located in the effective region and do not intersect with the connection wirings. The connection wirings are arranged along the space between the plurality of pixels, and the length of the extension of the connection wirings in the first direction is longer than the length of the extension of the connection wirings in the second direction.

[0026] Multiple connection wirings and multiple dummy wiring patterns can be included in the same conductive layer.

[0027] The plurality of connection wirings may include a first extension extending in a first direction, a second extension extending in a second direction intersecting the first direction, and a third extension extending in the first direction, and at least two of the plurality of pixels may be arranged between the second extensions of two adjacent connection wirings in the plurality of connection wirings.

[0028] The dummy wiring pattern may include a first dummy wiring pattern arranged between connecting wirings and extending in a second direction, a second dummy wiring pattern extending in a second direction in an area of ​​the effective region where no connecting wirings are arranged, and a third dummy wiring pattern extending in a first direction and not intersecting with the first and second dummy wiring patterns.

[0029] The first dummy wiring pattern may include a first sub-pattern and a plurality of second sub-patterns, wherein the first sub-pattern is arranged between the second extensions of two adjacent connecting wires, the first sub-pattern extends in a second direction, and the plurality of second sub-patterns are separated from the second extensions of the two connecting wires and arranged on an imaginary extension line that the second extensions reach if the second extensions extend further, and at least some of the plurality of third dummy wiring patterns may be arranged between the second extensions of the connecting wires and the first sub-pattern. Attached Figure Description

[0030] The above and other aspects and features of the present invention will become more apparent from the detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0031] Figure 1 This is a plan view of the display device according to the embodiment;

[0032] Figure 2 yes Figure 1 A side view of the display device;

[0033] Figure 3 This is a layout view showing the pixel arrangement of a display device according to an embodiment;

[0034] Figure 4 This is a circuit diagram of a pixel of a display device according to an embodiment;

[0035] Figure 5 It is a cross-sectional view of one pixel of the display device;

[0036] Figure 6 This is a layout view of some wiring of a display device according to an embodiment;

[0037] Figure 7 This is a layout view showing the signal wiring constituting a data line according to an embodiment;

[0038] Figure 8 It is along Figure 7 A cross-sectional view taken by line VIII-VIII';

[0039] Figure 9 It is along Figure 7 A cross-sectional view taken by line IX-IX';

[0040] Figure 10 This is a schematic layout view showing the arrangement of a plurality of wires in the effective area of ​​the display device according to the embodiment;

[0041] Figure 11 This is a partial layout view showing the pixel arrangement according to an embodiment;

[0042] Figure 12 It is shown Figure 11 A partial layout view of the arrangement of data lines in the pixel arrangement;

[0043] Figure 13 This is a schematic layout view showing the arrangement of dummy wiring patterns in the main effective area of ​​the display device according to the embodiment;

[0044] Figure 14 This is a schematic layout view showing the wiring arrangement of a display device according to another embodiment;

[0045] Figure 15 It shows the arrangement in Figure 14 A partial layout view of the arrangement of data lines in the effective fan-out area of ​​the display device;

[0046] Figure 16 This is a partial layout view showing the arrangement of data lines within the effective fan-out area of ​​a display device according to another embodiment;

[0047] Figure 17 This is a partial layout view showing the arrangement of data lines within the effective fan-out area of ​​a display device according to another embodiment;

[0048] Figure 18 This is a schematic layout view showing the arrangement of dummy wiring patterns in the main effective area of ​​a display device according to another embodiment;

[0049] Figure 19 This is a perspective view of a display device according to another embodiment; and

[0050] Figure 20 yes Figure 19 An expanded view of the display device. Detailed Implementation

[0051] The invention will now be described more fully below with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. However, the invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0052] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer may be directly on the other layer or substrate, or there may be an intermediate layer. Throughout the specification, the same reference numerals indicate the same parts.

[0053] It will be understood that while terms such as "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element discussed below may be referred to as a second element without departing from the teachings of the invention. Similarly, a second element may also be referred to as a first element.

[0054] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless expressly indicated otherwise, the singular forms “a” and “the” as used herein are also intended to include the plural forms, which include “at least one”. “At least one” should not be construed as limiting “a”. “Or” means “and / or”. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that the term “comprising,” when used in this specification, indicates the presence of the stated features, areas, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, areas, integers, steps, operations, elements, components, and / or clusters thereof. Embodiments of the invention will be described below with reference to the accompanying drawings.

[0055] Figure 1 This is a plan view of the display device 1 according to the embodiment. Figure 1 The planar shape of the display device 1 before bending is shown. In the accompanying drawings, the first direction DR1 indicates the vertical direction in the plan view, and the second direction DR2 indicates the horizontal direction in the plan view. Figure 2 yes Figure 1 A side view of the display device 1. Figure 2 The side profile of the display device 1 is shown when it is bent in the thickness direction. Here, the thickness direction is the direction perpendicular to the plane defined by the first direction DR1 and the second direction DR2.

[0056] Reference Figure 1 and Figure 2 The display device 1 is a device for displaying moving or still images, and can be used as a display screen for various products such as televisions, laptops, monitors, billboards and devices related to the Internet of Things, as well as portable electronic devices such as mobile phones, smartphones, personal computers (PCs), smartwatches, watch phones, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigation devices and ultra-mobile PCs (UMPs).

[0057] The display device 1 may include a display panel 10. The display panel 10 may be a flexible substrate, and the flexible substrate may include a flexible polymer material, such as polyimide. Accordingly, the display panel 10 may be warped, bent, folded, or rolled.

[0058] Display panel 10 may include an effective area AAR for displaying images and a non-effective area NAR for not displaying images. In a plan view, display panel 10 may be divided into the effective area AAR and the non-effective area NAR. The non-effective area NAR may be arranged around the effective area AAR.

[0059] The effective region AAR may include multiple pixels PX (PX1, PX2, and PX3) (see [link]). Figure 3 Multiple pixels PX (PX1, PX2, and PX3) may be arranged in a matrix shape. Each pixel may include an emissive layer and a circuit layer that controls the amount of light emitted from the emissive layer. The circuit layer may include wiring, electrodes, and at least one transistor. The emissive layer may include an organic light-emitting material. The emissive layer may be sealed by an encapsulation film. The specific configuration of each pixel PX will be described later.

[0060] The display panel 10 may include a main region MR and a bent region BR connected to one side of the main region MR in a first direction DR1. The display panel 10 may also include a sub-region SR, which is connected to the bent region BR in the first direction DR1 at one side of the bent region BR (i.e., the side of the bent region BR opposite to the main region MR) and is bent in the thickness direction relative to a bending axis extending along a second direction DR2 to overlap with the main region MR in the thickness direction.

[0061] The main region (MR) may include the active region (AAR). The inactive region (NAR) may be located at the outer edge of the active region (AAR) of the main region (MR).

[0062] The main region MR may have a shape similar to the planar appearance of the display device 1. The main region MR may be a flat area located in a plane. However, the invention is not limited thereto. In another embodiment, at least one of the remaining edges of the main region MR, except for the edge (or one side) connected to the bent region BR, may be bent in the main region MR to form a curved surface or bend in the vertical direction.

[0063] When at least one of the remaining edges, except for the edge (or side) connected to the bending region BR, can be bent or folded in the main region MR, the effective region AAR can also be arranged at the corresponding edge. However, the invention is not limited thereto. In another embodiment, the ineffective region NAR, which does not display an image, can be arranged at the bent or folded edge, or both the effective region AAR and the ineffective region NAR can be arranged at the bent or folded edge.

[0064] The inactive area NAR of the main region MR can be located in the area from the outer boundary of the active region AAR to the edge of the display panel 10. The signal wiring or drive circuit for applying signals to the active region AAR can be arranged in the inactive area NAR of the main region MR.

[0065] The bent area BR can be connected to the lower short side of the main area MR. The width of the bent area BR in the second direction DR2 can be smaller than the width of the main area MR in the second direction DR2 (short width). The connection between the main area MR and the bent area BR can have an L-shaped cut to reduce the width of the border.

[0066] Within the bending region BR, the display panel 10 can be bent with curvature in the opposite direction to the display surface. Here, the display surface is the surface through which light emitted from the pixels passes in the effective area AAR. As the display panel 10 is bent within the bending region BR, the surface of the display panel 10 can be reversed. That is, one upward-facing surface of the display panel 10 can be bent to face one side and then downward-facing through the bending region BR.

[0067] The sub-region SR extends from the bending region BR. Immediately after the bending is completed, the sub-region SR may extend in a direction parallel to the main region MR. In the bent state, the sub-region SR may overlap with the main region MR in the thickness direction of the display panel 10. The sub-region SR may overlap with the ineffective region NAR at the edge of the main region MR, and may overlap with the effective region AAR of the main region MR in the bent state. The width of the sub-region SR in the second direction DR2 may be equal to the width of the bending region BR, but the present invention is not limited thereto.

[0068] Pad units may be arranged in the sub-region SR of the display panel 10. Figure 6 (PDR in the context of the circuit). External devices may be mounted (or attached) on the pad unit. Examples of external devices may include driver chips 20, driver substrates 30 such as flexible or rigid printed circuit boards, and the like. Additionally, wiring connection films, connectors, etc., may also be mounted on the pad unit as external devices. One or more external devices may be mounted in the sub-region SR. For example, such as... Figure 1 and Figure 2 As shown, the driver chip 20 may be disposed in a sub-region SR of the display panel 10, and the driver substrate 30 may be attached to an end of the sub-region SR. In this case, the display panel 10 may include pad units connected to the driver chip 20 and pad units connected to the driver substrate 30. In another embodiment, the driver chip may be mounted on a film, and the film may be attached to the sub-region SR of the display panel 10.

[0069] The driver chip 20 can be mounted on the same surface of the display panel 10 as the display surface. Here, as described above, when the bending region BR is bent in reverse, the driver chip 20 can be mounted on the surface of the display panel 10 that is facing downwards in the thickness direction, so that the upper surface of the driver chip 20 faces downwards.

[0070] The driver chip 20 can be attached to the display panel 10 via an anisotropic conductive film or via ultrasonic bonding. The width of the driver chip 20 in the horizontal direction (e.g., the second direction DR2) can be smaller than the width of the display panel 10 in the horizontal direction. The driver chip 20 can be arranged at the center of the sub-region SR in the horizontal direction (e.g., the second direction DR2), and the left and right edges of the driver chip 20 can be spaced apart from the left and right edges of the sub-region SR, respectively.

[0071] The driver chip 20 may include an integrated circuit that drives the display panel 10. In some embodiments, the integrated circuit may be a data driver integrated circuit that generates and provides data signals, but the invention is not limited thereto. The driver chip 20 is connected to the wiring pads in the pad unit disposed on the display panel 10. Figure 6 The WR_PD in the code provides data signals to the routing pads. The routing connected to the routing pads (...) Figure 6 The WR in the image extends toward the pixel to apply the data signal to each pixel.

[0072] Figure 3 This is a layout view showing the pixel arrangement of a display device according to an embodiment.

[0073] Reference Figure 3 Pixel PX may include a first color pixel PX1, a second color pixel PX2, and a third color pixel PX3. In an embodiment, the first color pixel PX1 may be a red pixel, the second color pixel PX2 may be a blue pixel, and the third color pixel PX3 may be a green pixel. The corresponding pixels PX may be arranged alternately in a matrix form.

[0074] Each pixel PX may include a light-emitting region EMA and a non-light-emitting region NEA surrounding the light-emitting region EMA. The sizes of the light-emitting regions EMA in the first color pixel PX1, the second color pixel PX2, and the third color pixel PX3 may be different from each other. For example, the light-emitting region EMA of the second color pixel PX2 may be larger than the light-emitting region EMA of the first color pixel PX1, and the light-emitting region EMA of the third color pixel PX3 may be smaller than the light-emitting region EMA of the first color pixel PX1. The shape of the light-emitting region EMA of each pixel PX may typically be octagonal, but the invention is not limited thereto, and the light-emitting region EMA may have a hexagonal shape, a circular shape, a rhombus shape, or other polygonal shapes, or in another embodiment, it may have a polygonal shape with rounded edges.

[0075] In each of some pixel columns PXC (hereinafter, the first pixel column PXC1), first-color pixels PX1 and second-color pixels PX2 are arranged alternately along a first direction DR1 (i.e., the column-forward direction). In each of other pixel columns PXC (hereinafter, the second pixel column PXC2), third-color pixels PX3 are arranged repeatedly along the first direction DR1. The first pixel column PXC1 and the second pixel column PXC2 are arranged alternately along a second direction DR2 (i.e., the row-forward direction). For example, odd-numbered pixel columns PXC can be the first pixel column PXC1, and even-numbered pixel columns PXC can be the second pixel column PXC2.

[0076] The luminous areas (EMAs) belonging to a pixel column PXC can be substantially aligned along a first direction DR1. The luminous areas (EMAs) of a pixel column PXC can be staggered relative to the luminous areas (EMAs) of adjacent pixel columns PXCs in a second direction DR2. For example, the first color pixel PX1 and the second color pixel PX2 of the first pixel column PXC1 can be arranged along the second direction DR2 to be spatially aligned with the adjacent third color pixel PX3 of the adjacent second pixel column PXC2, and the third color pixel PX3 of the second pixel column PXC2 can be arranged along the second direction DR2 to be spatially aligned with the adjacent first color pixel PX1 and the second color pixel PX2.

[0077] A pixel row PXR has a shape in which first color pixels PX1 and second color pixels PX2 are alternately arranged with a third color pixel PX3 located therebetween. The first pixel row PXR1 may have repeating arrangement units of first color pixels PX1, third color pixels PX3, second color pixels PX2, and third color pixels PX3, and the second pixel row PXR2 may also have repeating arrangement units of second color pixels PX2, third color pixels PX3, first color pixels PX1, and third color pixels PX3. The first pixel row PXR1 and the second pixel row PXR2 are arranged alternately along a first direction DR1 (e.g., the column forward direction). For example, an odd-numbered pixel row PXR may be the first pixel row PXR1, and an even-numbered pixel row PXR may be the second pixel row PXR2. In a pixel row PXR, the respective luminous areas EMA of the first color pixels PX1 and the second color pixels PX2 may be biased to the opposite side of the luminous area EMA of the third color pixel PX3 along the first direction DR1. That is, in a pixel row PXR, the luminous regions EMA of multiple pixels PX can be staggered along the second direction DR2.

[0078] Pixels PX belonging to the same column can receive data signals from the same data line, and pixels PX belonging to the same row can receive gate signals from the same gate line. Each pixel PX can be driven by pixel circuitry. Pixel circuitry may include multiple transistors and at least one capacitor. Figure 4 A circuit diagram of an exemplary pixel circuit is shown.

[0079] Figure 4 This is a circuit diagram of a pixel of a display device according to an embodiment.

[0080] Reference Figure 4 The pixel circuit may include a first transistor TR1, a second transistor TR2, a capacitor Cst, and an organic light-emitting diode EL. Each pixel PX is connected to a scan line SL, a data line DL, and a first power supply voltage line ELVDDL.

[0081] The first transistor TR1 can be a driving transistor, and the second transistor TR2 can be a switching transistor. Although both the first transistor TR1 and the second transistor TR2 are shown as PMOS transistors in the accompanying drawings, one or both of the first transistor TR1 and the second transistor TR2 can be NMOS transistors.

[0082] The first electrode (i.e., source electrode) of the first transistor TR1 is connected to the first power supply voltage line ELVDDL, and its second electrode (i.e., drain electrode) is connected to the pixel electrode (or anode electrode) of the organic light-emitting diode EL. The first electrode (i.e., source electrode) of the second transistor TR2 is connected to the data line DL, and its second electrode (i.e., drain electrode) is connected to the gate electrode of the first transistor TR1. A capacitor Cst is connected between the gate electrode and the first electrode of the first transistor TR1. The common electrode (or cathode electrode) of the organic light-emitting diode EL receives a second power supply voltage ELVSS. The second power supply voltage ELVSS may be a voltage lower than the first power supply voltage supplied from the first power supply voltage line ELVDDL.

[0083] The second transistor TR2 can output a data signal applied to the data line DL in response to a scan signal applied to the scan line SL. The capacitor Cst can be charged with a voltage corresponding to the data signal received from the second transistor TR2. The first transistor TR1 can control the drive current flowing through the organic light-emitting diode EL in response to the amount of charge stored in the capacitor Cst.

[0084] Figure 4 The equivalent circuit is only one implementation, and in another implementation, the pixel circuit may include more (e.g., 7) transistors and capacitors.

[0085] Figure 5 This is a cross-sectional view of one pixel (PX) of the display device. Figure 5 In the example, it is shown in the form of a thin-film transistor. Figure 4 The first transistor is TR1, and the second transistor is TR2, which is not shown.

[0086] Reference Figure 5 The cross-sectional structure of pixel PX is described in detail. This display panel 10 may include a substrate 100, a buffer layer 105, a semiconductor layer 110, a first insulating layer 121, a first gate conductive layer 130, a second insulating layer 122, a second gate conductive layer 140, a third insulating layer 123, a first data conductive layer 150, a fourth insulating layer 124, a second data conductive layer 160, a fifth insulating layer 125, a pixel electrode 170, a pixel defining layer 126 defining an opening exposing the pixel electrode 170, an organic layer 190 disposed in the opening of the pixel defining layer 126, and a common electrode 180 disposed on the organic layer 190 and the pixel defining layer 126. Each of the above layers may be formed as a single layer, but in another embodiment, it may also be formed as a stacked film comprising multiple layers. Another layer may also be disposed between the other layers.

[0087] Substrate 100 supports each layer disposed thereon. Substrate 100 may be made of an insulating material such as a polymer resin. Examples of polymer resins may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), and combinations thereof. Substrate 100 may be a flexible substrate capable of bending, folding, rolling, or similar deformation. Examples of materials constituting a flexible substrate may include, but are not limited to, polyimide (PI).

[0088] A buffer layer 105 is disposed on the substrate 100. The buffer layer 105 prevents the diffusion of impurity ions, prevents the penetration of moisture or external air, and performs surface planarization. The buffer layer 105 may include silicon nitride, silicon oxide, or silicon oxynitride. Depending on the type of substrate 100 or the process conditions, the buffer layer 105 may be omitted.

[0089] Semiconductor layer 110 may be disposed on buffer layer 105. Semiconductor layer 110 forms the channel of thin-film transistor. Semiconductor layer 110 may include polycrystalline silicon. However, the invention is not limited thereto, and semiconductor layer 110 may include monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor. Examples of oxide semiconductors may include binary compounds (AB) each comprising indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), or magnesium (Mg). x ), ternary compounds (AB) x C y ) and quaternary compounds (AB) x C y D z ).

[0090] The first insulating layer 121 may be a gate insulating layer with gate insulation function. The first insulating layer 121 may include silicon compounds, metal oxides, or the like. For example, the first insulating layer 121 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. These may be used alone or in combination with each other. The first insulating layer 121 may be a single-layer film or a multilayer film, wherein the multilayer film is formed as a stack of different materials.

[0091] A first insulating layer 121 is disposed on the semiconductor layer 110. The first insulating layer 121 may typically be disposed over the entire surface of the substrate 100.

[0092] A first gate conductive layer 130 is disposed on a first insulating layer 121. The first gate conductive layer 130 may include the gate electrode 131 of the thin-film transistor of the pixel PX, a scan line connected to the gate electrode 131, and a first electrode 132 of a storage capacitor. The first ineffective fan-out wiring of the ineffective region NAR (Network Area Reduction) Figure 8 The NFW_1 in the first gate conductive layer 130 can also be included in the first gate conductive layer 130.

[0093] The first gate conductive layer 130 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first gate conductive layer 130 may be a single-layer film or a multilayer film.

[0094] The second insulating layer 122 may be disposed on the first gate conductive layer 130. The second insulating layer 122 may be an interlayer insulating film or a gate insulating film. The second insulating layer 122 may include inorganic insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide.

[0095] A second gate conductive layer 140 is disposed on the second insulating layer 122. The second gate conductive layer 140 may include the second electrode of the storage capacitor. The second ineffective fan-out wiring of the ineffective region NAR ( Figure 8 The NFW_2 in the first gate conductive layer 130 may also be included in the second gate conductive layer 140. The second gate conductive layer 140 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The second gate conductive layer 140 may be made of the same material as the first gate conductive layer 130 or may include the same material as the first gate conductive layer 130, but the invention is not limited thereto. The second gate conductive layer 140 may be a single-layer film or a multilayer film.

[0096] A third insulating layer 123 is disposed on the second gate conductive layer 140. The third insulating layer 123 may be an interlayer insulating film. The third insulating layer 123 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide, or may include organic insulating materials such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). The third insulating layer 123 may be a single-layer film or a multilayer film, wherein the multilayer film is formed as a stack of different materials.

[0097] A first data conductive layer 150 is disposed on a third insulating layer 123. The first data conductive layer 150 may be a first source / drain conductive layer. The first data conductive layer 150 may include a first electrode 151 and a second electrode 152 of the thin-film transistor of the pixel PX. Signal wiring may also be included in the first data conductive layer 150. Figure 8 (SW1 and SW2 in the diagram). The first electrode 151 and the second electrode 152 of the thin-film transistor can be electrically connected to the source and drain regions of the semiconductor layer 110 through contact holes penetrating the third insulating layer 123, the second insulating layer 122 and the first insulating layer 121. The first power supply voltage electrode 153 of the pixel PX can also be included in the first data conductive layer 150.

[0098] The first data conductive layer 150 may include at least one metal selected from aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first data conductive layer 150 may be a single-layer film or a multilayer film. For example, the first data conductive layer 150 may be formed as a stacked structure having Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu.

[0099] A fourth insulating layer 124 is disposed on the first data conductive layer 150. The fourth insulating layer 124 covers the first data conductive layer 150. The fourth insulating layer 124 may be an interlayer insulating film or a via layer. The fourth insulating layer 124 may include organic insulating materials, such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0100] The second data conductive layer 160 is disposed on the fourth insulating layer 124. The second data conductive layer 160 may be a second source / drain conductive layer. The second data conductive layer 160 may include connection electrodes 161 of the pixel PX. The second data conductive layer 160 may also include connection wiring. Figure 7 (CNW in the image). The connecting electrode 161 can be electrically connected to the second electrode 152 of the thin-film transistor of the pixel PX through a contact hole penetrating the fourth insulating layer 124.

[0101] The second data conductive layer 160 may include at least one metal selected from aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The second data conductive layer 160 may be a single-layer film or a multilayer film. The second data conductive layer 160 may be made of the same material as the first data conductive layer 150, but the invention is not limited thereto.

[0102] A fifth insulating layer 125 is disposed on the second data conductive layer 160. The fifth insulating layer 125 covers the second data conductive layer 160. The fifth insulating layer 125 may be a via layer. The fifth insulating layer 125 may include the same material as the fourth insulating layer 124 described above, or may include at least one material selected from the constituent materials shown as the fourth insulating layer 124.

[0103] Pixel electrode 170 is disposed on the fifth insulating layer 125. Pixel electrode 170 may be the anode electrode of a light-emitting element. Pixel electrode 170 may be electrically connected to a connection electrode 161 included in the second data conductive layer 160 through contact holes penetrating the fifth insulating layer 125, and may also be electrically connected to the second electrode 152 of the thin-film transistor. Pixel electrode 170 may at least partially overlap with the light-emitting region EMA of pixel PX.

[0104] The pixel electrode 170 may have a multilayer film structure in which a high work function material layer and a reflective material layer are stacked. The high work function material layer includes indium-tin-oxide (ITO), indium-zinc-oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3), and the reflective material layer includes silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or mixtures thereof. The high work function material layer may be disposed above the reflective material layer to be closer to the organic layer 190. The pixel electrode 170 may have a multilayer structure of ITO / Mg, ITO / MgF2, ITO / Ag, and ITO / Ag / ITO, but the invention is not limited thereto.

[0105] A pixel defining layer 126 may be disposed on a pixel electrode 170. The pixel defining layer 126 may at least partially overlap with the non-light-emitting region NEA of the pixel PX. The pixel defining layer 126 may include an opening exposing the pixel electrode 170. The pixel defining layer 126 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide, or may include an organic insulating material such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). The pixel defining layer 126 may be a single-layer film or a multilayer film, wherein the multilayer film is formed as a stack of different materials.

[0106] A light-emitting layer is disposed in the opening of the pixel defining layer 126. The light-emitting layer may be made of inorganic or organic materials. In an exemplary embodiment, the light-emitting layer may include an organic layer 190. The organic layer 190 may include an organic light-emitting layer, a hole injection / transport layer, and an electron injection / transport layer. The organic layer 190 may overlap with the light-emitting region EMA.

[0107] A common electrode 180 is disposed on the organic layer 190 and the pixel defining layer 126. The common electrode 180 may be the cathode electrode of a light-emitting element. The common electrode 180 may be disposed in the non-light-emitting region NEA and the light-emitting region EMA of a pixel PX. That is, the common electrode 180 may be disposed above the entire surface of multiple pixels PX. The common electrode 180 may include a low work function material layer comprising Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF2, Ba, their compounds, or mixtures thereof (e.g., a mixture of Ag and Mg). The common electrode 180 may also include a transparent metal oxide layer disposed on the low work function material layer.

[0108] Although not shown in the accompanying drawings, an encapsulation film may be disposed on the common electrode 180. The encapsulation film may include an inorganic film. In an embodiment, the encapsulation film may include a first inorganic layer, an organic layer located on the first inorganic layer, and a second inorganic layer located on the organic layer.

[0109] Figure 6 This is a layout view of some wiring of a display device according to an embodiment.

[0110] Reference Figure 6 The width of the pad unit PDR with wiring pads WR_PD arranged in the second direction DR2 is smaller than the width of the effective area AAR in the second direction DR2. To cover more of the effective area AAR, multiple wiring pads WR can gradually extend from the wiring pads WR_PD toward the effective area AAR in the second direction DR2. That is, the total width of the multiple wiring pads WR_PD in the second direction DR2 increases along the first direction DR1. The optimal arrangement of the multiple wiring pads WR will be configured such that the multiple wiring pads WR extend in the second direction DR2 to cover the entire effective area AAR. However, when the bezel of the display device is reduced, the space for distributing the multiple wiring pads WR may be insufficient. When the display device has a bezel such as... Figure 6 When the L-shaped cut shown or some wiring WR fails to cross the corresponding space because other wiring WR are arranged in the corners, the space for extension may be insufficient. As a result, the width of the arrangement of multiple wirings extending from the pad cell PDR in the non-effective area NAR adjacent to the effective area AAR on the second direction DR2 may be smaller than the width of the effective area AAR on the second direction DR2.

[0111] Based on the relative arrangement area of ​​the multiple routing wrappers (WRs), the effective region AAR can be divided into an inner effective region AAR_I and an outer effective region AAR_L (AAR_L1, AAR_L2), and the multiple routing wrappers extend from the pad cells PDR in the non-effective region NAR adjacent to the effective region AAR. When the multiple routing wrappers extending from the pad cells PDR in the non-effective region NAR adjacent to the effective region AAR extend to the first direction DR1 (i.e., Figure 6 When the inner effective region AAR_I extends from the pad cell PDR in the non-effective region NAR adjacent to the effective region AAR to the other side of the first direction DR1, the outer effective region AAR_L is defined as an effective region that does not overlap with the arrangement of the plurality of wiring WRs. Although the figures show the inner effective region AAR_I located at the center of the effective region AAR, the first outer effective region AAR_L1 located on one side of the inner effective region AAR_I in the second direction DR2, and the second outer effective region AAR_L2 located on the other side of the inner effective region AAR_I in the second direction DR2, the invention is not limited thereto. In another embodiment, the number and position of the inner effective region AAR_I and the outer effective region AAR_L may be varied depending on the position of the row in which the wiring pad WR_PD of the pad cell PDR is located.

[0112] In the inner effective region AAR_I, each wiring WR can extend from the ineffective region NAR adjacent to the inner effective region AAR_I (i.e., the inner ineffective region NAR) in the first direction DR1, and can therefore be arranged adjacent to the pixel PX of the corresponding region to apply a signal. Conversely, in the outer effective region AAR_L, after each bypass wiring WR_CN can extend from the inner ineffective region NAR to the outside (one side or the other side on the second direction DR2), each wiring WR can extend from the corresponding position (i.e., the end of the bypass wiring WR_CN in the outer effective region AAR_L) in the first direction DR1, and can therefore be arranged adjacent to the pixel PX of the corresponding region to apply a signal. The bypass wiring WR_CN can extend from the inner effective region AAR_I to the ineffective region NAR adjacent to the outer effective region AAR_L (i.e., the outer ineffective region NAR). Since the other wiring WRs are arranged in the effective area AAR through which the bypass wiring WR_CN passes, the bypass wiring WR_CN can be included in a conductive layer on a different layer than the other wiring WRs in the effective area AAR to prevent short circuits between the wiring WRs.

[0113] Figure 7This is a layout view showing the signal routing that constitutes the data line DL according to an embodiment. Figure 8 It is along Figure 7 The cross-sectional view taken by line VIII-VIII', and Figure 9 It is along Figure 7 The cross-sectional view taken by line IX-IX'.

[0114] Reference Figures 7 to 9 The data line DL includes a first data line DL1 and a second data line DL2. The first data line DL1 provides a first data signal to pixels PX belonging to the first pixel column PXC1, and the second data line DL2 provides a second data signal to pixels PX belonging to the second pixel column PXC2. The first data line DL1 and the second data line DL2 can be connected from the pad unit PDR to the pixels PX in the effective area AAR using multiple conductive layers. The first data line DL1 and the second data line DL2 can be arranged alternately one after another along the second direction DR2 throughout the entire effective area AAR.

[0115] Each of the first data line DL1 and the second data line DL2 can be divided into an internal data line and an external data line. The internal data line is a data line that provides data signals to pixels PX located in the internal effective region AAR_I, and the external data line is a data line that provides data signals to pixels PX located in the external effective region AAR_L.

[0116] The internal data lines may include a first inactive fan-out routing NFW_1 and a second inactive fan-out routing NFW_2, as well as a first signal routing SW1 and a second signal routing SW2. The first inactive fan-out routing NFW_1 and the second inactive fan-out routing NFW_2 may be arranged in the internal inactive area NAR, and the first signal routing SW1 and the second signal routing SW2 may be arranged from the internal inactive area NAR to the active area AAR.

[0117] The first data line DL1 corresponding to the internal data line may include a second ineffective fan-out routing NFW_2 and a first signal routing SW1. The second data line DL2 corresponding to the internal data line may include a first ineffective fan-out routing NFW_1 and a second signal routing SW2.

[0118] At the internal wiring contact CNI located in the inactive region NAR adjacent to the internal active region AAR_I, the first inactive fan-out wiring NFW_1 and the first signal wiring SW1 of the internal data line can be connected to each other, and the second inactive fan-out wiring NFW_2 and the second signal wiring SW2 of the internal data line can be connected to each other. Within the internal wiring contact CNI, the first inactive fan-out wiring NFW_1 and the first signal wiring SW1 of the internal data line can be in direct contact with each other, and the second inactive fan-out wiring NFW_2 and the second signal wiring SW2 of the internal data line can also be in direct contact with each other.

[0119] In addition to the first ineffective fan-out wiring NFW_1 and the second ineffective fan-out wiring NFW_2, as well as the first signal wiring SW1 and the second signal wiring SW2, the external data lines may also include bypass wiring. Figure 6 The connection cabling CNW in WR_CN. The first ineffective fan-out cabling NFW_1 and the second ineffective fan-out cabling NFW_2 can be arranged in the internal ineffective area NAR, and the first signal cabling SW1, the second signal cabling SW2, and the connection cabling CNW can be arranged from the internal ineffective area NAR to the effective area AAR.

[0120] The first data line DL1 corresponding to the external data line may include a first ineffective fan-out routing NFW_1, a connection routing CNW, and a first signal routing SW1. The second data line DL2 corresponding to the external data line may include a second ineffective fan-out routing NFW_2, a connection routing CNW, and a second signal routing SW2. The connection routing CNW may be an effective fan-out routing that passes through the effective area AAR.

[0121] The external data line's connection wiring CNW and the first ineffective fan-out wiring NFW_1 and the second ineffective fan-out wiring NFW_2 can be connected to each other in the internal wiring contact CNI located in the inner ineffective region NAR. At the internal wiring contact CNI, each of the first ineffective fan-out wiring NFW_1 and the second ineffective fan-out wiring NFW_2, as well as the connection wiring CNW, can be in direct contact with each other. The connection wiring CNW and the first signal wiring SW1 and the second signal wiring SW2 can be connected to each other at the external wiring contact located in the ineffective region NAR adjacent to the outer effective region AAR_L. At the external wiring contact, each of the connection wiring CNW and the first signal wiring SW1 and the second signal wiring SW2 can be connected via the contact electrode CNE. However, the invention is not limited thereto, and in another embodiment, the connection wiring CNW and the first signal wiring SW1 and the second signal wiring SW2 can be in direct contact with each other at the external wiring contact without the contact electrode CNE. In this case, at the external wiring contact portion, at least one of the connecting wiring CNW and the first signal wiring SW1 and the second signal wiring SW2 also includes a structure corresponding to the shape of the contact electrode CNE shown (e.g., a bend from the wiring in the second direction DR2).

[0122] The aforementioned internal data lines, serving as data lines, can be referred to as direct-connection data lines or direct lines. In these data lines, the first ineffective fan-out wiring NFW_1 and the second ineffective fan-out wiring NFW_2 can be directly connected to the first signal wiring SW1 and the second signal wiring SW2, respectively, without the presence of a connecting wiring CNW intersecting with the effective area AAR. Conversely, the external data lines, serving as data lines, can be referred to as indirect-connection data lines, through-hole data lines, or indirect data lines. In these data lines, the first ineffective fan-out wiring NFW_1 and the second ineffective fan-out wiring NFW_2 can be connected to the first signal wiring SW1 and the second signal wiring SW2, respectively, via connecting wiring CNW.

[0123] The first ineffective fan-out wiring NFW_1 and the second ineffective fan-out wiring NFW_2, the first signal wiring SW1 and the second signal wiring SW2, and the connection wiring CNW may be included in conductive layers located on different layers. In an embodiment, the first ineffective fan-out wiring NFW_1 and the second ineffective fan-out wiring NFW_2 may be included in the first gate conductive layer 130 and the second gate conductive layer 140, and the first signal wiring SW1, the second signal wiring SW2, and the connection wiring CNW may be included in different first data conductive layers 150 and second data conductive layers 160.

[0124] Specifically, regardless of whether the data line is an internal or external data line, the first ineffective fan-out wiring NFW_1 may be included in the first gate conductive layer 130, and the second ineffective fan-out wiring NFW_2 may be included in the second gate conductive layer 140. However, the present invention is not limited thereto, and the first ineffective fan-out wiring NFW_1 may be included in the second gate conductive layer 140, and the second ineffective fan-out wiring NFW_2 may be included in the first gate conductive layer 130.

[0125] Regardless of whether the data line is an internal or external data line, the first signal wiring SW1 and the second signal wiring SW2 can be included in the first data conductive layer 150, and the connection wiring CNW can be included in the second data conductive layer 160. However, the applied conductive layers can be reversed.

[0126] Although the accompanying drawings show that the connection wiring CNW is included in a conductive layer and the signal wirings SW (e.g., SW1, SW2) are made of a different conductive layer than the connection wiring CNW, the invention is not limited thereto. In some embodiments, the connection wiring CNW is partially separated and made of one or more conductive layers, and some of these separated connection wiring CNWs may be made of the same conductive layer as the signal wiring SW. For example, a portion of the connection wiring CNW extending in the first direction DR1 in the same manner as the signal wiring SW may be included in a conductive layer disposed on the same layer as the signal wiring SW, and a portion of the connection wiring CNW extending in the second direction DR2 may be included in a conductive layer disposed on a different layer than the signal wiring SW.

[0127] The contact electrode CNE may be included in a conductive layer disposed on a different layer than the connection wiring CNW and the first signal wiring SW1 and the second signal wiring SW2. For example, as shown in the figures, the contact electrode CNE may be included in the second gate conductive layer 140, but may also be included in the first gate conductive layer 130.

[0128] The first ineffective fan-out wiring NFW_1 and the second ineffective fan-out wiring NFW_2 are connected to the wiring pad WR_PD and can extend to another conductive layer in between. For example, after the bending region BR passes through the first data conductive layer 150 or the second data conductive layer 160, in the sub-region SR, the bending region BR can be extended using the first gate conductive layer 130 or the second gate conductive layer 140. The wiring pad WR_PD may include the first gate conductive layer 130 and the second gate conductive layer 140, as well as the first data conductive layer 150 and the second data conductive layer 160 connected to the first gate conductive layer 130 and the second gate conductive layer 140 through contact holes. When the conductive layer is changed in the extension of the wiring, contact holes connecting the conductive layers can be defined in the corresponding portion.

[0129] Figure 10 This is a schematic layout view showing the arrangement of multiple wires in the effective area AAR of the display device 1 according to an embodiment. Figure 10 For ease of description, only the relative arrangement of the connection cabling CNW, the dummy cabling pattern DMP, and the signal cabling SW arranged in the effective area AAR is shown.

[0130] Reference Figure 10 Multiple wirings in the effective area AAR of the display device 1 can be arranged to intersect each other. In the effective area AAR, an effective fan-out area AAR_F with connecting wiring CNW can be defined in the region adjacent to the ineffective area NAR where the first ineffective fan-out wiring NFW_1 and the second ineffective fan-out wiring NFW_2 are arranged. In the effective area AAR, a main effective area AAR_M without connecting wiring CNW can be defined in the region other than the effective fan-out area AAR_F. The connecting wiring CNW arranged in the effective fan-out area AAR_F can be arranged to connect the first ineffective fan-out wiring NFW_1 and the second ineffective fan-out wiring NFW_2 arranged in the inner effective area AAR_I with the signal wiring SW arranged in the outer effective area AAR_L, and therefore, can be arranged only in a portion of the effective area AAR. Unlike the signal wiring SW that extends in the first direction DR1, the connecting wiring CNW may include a portion that extends in the second direction DR2, and therefore, in areas where only the connecting wiring CNW is arranged, there may be defects in the wiring that extends in the second direction DR2 that are visually (to the naked eye) identifiable.

[0131] To prevent defects, dummy wiring patterns DMP with a shape similar to the connecting wiring CNW can be arranged in the main effective area AAR_M, excluding the effective fan-out area AAR_F. The dummy wiring patterns DMP can extend in either the first direction DR1 or the second direction DR2. The dummy wiring patterns DMP can be included in a conductive layer located on the same layer as the connecting wiring CNW, and some of the dummy wiring patterns DMP can be arranged between the connecting wiring CNW in the effective fan-out area AAR_F. The dummy wiring patterns DMP prevent the effective fan-out area AAR_F, where the connecting wiring CNW is arranged, and the main effective area AAR_M from being observed separately on the entire surface of the effective area AAR. The wiring arrangement structure of the display device 1 will be described in detail below with reference to other accompanying drawings.

[0132] Figure 11 This is a partial layout view showing the pixel arrangement according to an embodiment. Figure 12 It is shown Figure 11 A partial layout view of the arrangement of data lines in the pixel arrangement, and Figure 13 This is a schematic layout view showing the arrangement of dummy wiring patterns (DMPs) in the main effective area AAR_M of a display device according to an embodiment. Figures 11 to 13 For ease of description, the shape of each pixel PX is simplified to a rectangle. Figure 12 The arrangement in the effective fan-out region AAR_F is shown. Figure 11 Data lines in the pixel arrangement, Figure 13 The arrangement in the main effective region AAR_M is shown. Figure 11 The dummy wiring pattern (DMP) and signal wiring (SW) in the pixel arrangement. Figures 11 to 13 The concept shows a space covered by a pixel PX without considering the shape of the luminous area EMA of each pixel PX, which can be applied in the same way not only when the luminous area EMA of each pixel PX has an actual rectangular shape, but also when the luminous area EMA of each pixel PX has an interlaced arrangement.

[0133] Reference Figures 11 to 13The first signal wiring SW1 and the second signal wiring SW2 can be arranged along the boundary of pixel PX (or the space between pixels). Here, the boundary of pixel PX is the edge of the space occupied by pixel PX, and can refer to the space outside the light-emitting area EMA of pixel PX. In the following embodiment, the first signal wiring SW1 and the second signal wiring SW2 are arranged at the boundary of pixel PX as an example, but in another embodiment, the first signal wiring SW1 and the second signal wiring SW2 can be arranged to partially overlap with the light-emitting area EMA of pixel PX. When the display device is a front-emitting display device, even if the first signal wiring SW1 and the second signal wiring SW2 intersect with pixel PX and overlap with the light-emitting area EMA, the light emission brightness will not be affected.

[0134] To the outer valid region AAR_L (arranged in the valid region AAR) Figure 12 and Figure 13 The first signal wiring SW1 or the second signal wiring SW2 providing a data signal for each of the multiple pixel columns (e.g., the first pixel column PXC#1, the second pixel column PXC#2, the third pixel column PXC#3, and the fourth pixel column PXC#4) in the AAR_L2 can be arranged on the second direction DR2 adjacent to the other side of the corresponding pixel column PXC. Conversely, the first signal wiring SW1 or the second signal wiring SW2 providing a data signal for each of the multiple pixel columns (e.g., the fifth pixel column PXC#5, the sixth pixel column PXC#6, the seventh pixel column PXC#7, and the eighth pixel column PXC#8) arranged in the inner effective region AAR_I of the effective region AAR can be arranged on the second direction DR2 adjacent to one side of the corresponding pixel column PXC. However, the invention is not limited to this, and the first signal wiring SW1 and the second signal wiring SW2 can be arranged on the second direction DR2 in the same manner on one side or the other side of the corresponding pixel column PXC. Alternatively, the first signal wiring SW1 and the second signal wiring SW2 may be alternately arranged on one side or the other side of the corresponding pixel column PXC in the second direction DR2.

[0135] Multiple first signal routings SW1 and multiple second signal routings SW2 can be arranged in the spaces PXT_C#12, PXT_C#23, PXT_C#34, PXT_C#45, PXT_C#56, PXT_C#67, and PXT_C#78 between pixel columns. However, the first signal routings SW1 and the second signal routings SW2 may not be arranged in the space PXT_C#45 between pixel columns located at the boundary between the outer effective region AAR_L2 and the inner effective region AAR_I. The signal routings SW can be arranged in a symmetrical structure based on the boundary between the inner effective region AAR_I and the outer effective region AAR_L2.

[0136] The connection wiring CNW can be arranged along the boundary of pixel PX in the effective region AAR. The connection wiring CNW may include a bent structure. In an embodiment, the connection wiring CNW may include a first extension CNW_1 and a third extension CNW_3 extending in a first direction DR1, and a second extension CNW_2 extending in a second direction DR2.

[0137] The first extension CNW_1 can extend from the internal inactive region NAR to the internal active region AAR_I (i.e., one side on the first direction DR1). The first end of the first extension CNW_1 can be located in the internal inactive region NAR, and its second end can be located in the internal active region AAR_I. The first end of the first extension CNW_1 can be connected to the inactive fan-out wiring NFW at the internal wiring contact CNI.

[0138] The second extension CNW_2 can be connected to the first extension CNW_1 and can extend to the other side (or one side) in the second direction DR2. The second extension CNW_2 can extend from the inner effective region AAR_I to the outer effective region AAR_L2. The first end of the second extension CNW_2 can be located in the inner effective region AAR_I, and the second end of the second extension CNW_2 can be located in the outer effective region AAR_L2.

[0139] The first end of the second extension CNW_2 can be connected to the second end of the first extension CNW_1. The first bend of the connecting wiring CNW can be located at the first end of the second extension CNW_2 and / or the second end of the first extension CNW_1. The entire second extension CNW_2 can be arranged within the effective area AAR.

[0140] The third extension CNW_3 can be connected to the second extension CNW_2 and can extend from the external active region AAR_L2 to the external inactive region NAR (i.e., one side on the first direction DR1). The first end of the third extension CNW_3 can be located in the external active region AAR_L2, and its second end can be located in the external inactive region NAR. The first end of the third extension CNW_3 can be connected to the second end of the second extension CNW_2. The second bend of the connecting wiring CNW can be arranged at the first end of the third extension CNW_3 and / or the second end of the second extension CNW_2. The second end of the third extension CNW_3 can be connected at the external wiring contact to the contact electrode CNE and / or the first signal wiring SW1 and the second signal wiring SW2 connected thereto.

[0141] As the first signal routing SW1 and the second signal routing SW2 of the external data lines move further away from the internal effective region AAR_I, the first signal routing SW1 and the second signal routing SW2 of the external data lines can be connected to the ineffective fan-out routing NFW arranged further away from the internal effective region AAR_I. That is, among the multiple first signal routings SW1 and second signal routings SW2 of external data lines, the first signal routing SW1 and the second signal routing SW2 adjacent to the internal effective region AAR_I can be connected to the relatively close ineffective fan-out routing NFW. As the first signal routings SW1 and the second signal routing SW2 of the external data lines move away from the other side on the second direction DR2, the ineffective fan-out routing NFW located on the other side of the second direction DR2 can be connected to the first signal routings SW1 and the second signal routing SW2 of the external data lines. In a plan view, the connecting routing CNW of the external data lines located on the relatively outer side can be arranged in a shape surrounding the connecting routing CNW of the external data lines located on the inner side.

[0142] exist Figure 12 The diagram illustrates a 5x8 pixel arrangement within the second outer effective region AAR_L2 and its adjacent inner effective region AAR_I. The wiring arrangement of the first outer effective region AAR_L1 and its adjacent inner effective region AAR_I can be compared to... Figure 12 The wiring arrangement has a roughly symmetrical relationship.

[0143] In the attached diagram, the leftmost column is called column 1, and the column numbers increase to the right. Similarly, the bottommost row is called row 1, and the row numbers increase upwards. The space between pixels is described by writing down the pixel number to the left of adjacent pixels. For example, the space between the first pixel and the second pixel is described as "first space." Connecting routes (CNW) are numbered in ascending order of path length.

[0144] The first pixel column PXC#1, the third pixel column PXC#3, the fifth pixel column PXC#5, and the seventh pixel column PXC#7 correspond to the first pixel column PXC1, and the second pixel column PXC#2, the fourth pixel column PXC#4, the sixth pixel column PXC#6, and the eighth pixel column PXC#8 correspond to the second pixel column PXC2. The first pixel column PXC#1, the second pixel column PXC#2, the third pixel column PXC#3, and the fourth pixel column PXC#4 are pixel columns PXC arranged in the outer effective area AAR_L2, and the fifth pixel column PXC#5, the sixth pixel column PXC#6, the seventh pixel column PXC#7, and the eighth pixel column PXC#8 are pixel columns PXC arranged in the inner effective area AAR_I. In the attached diagram, each pixel column PXC is represented as C#n (n is an integer from 1 to 8), but these can be understood to mean the first pixel column PXC#1 to the eighth pixel column PXC#8 respectively.

[0145] Similarly, the multiple pixel rows PXR arranged in the effective area AAR are also defined as the first pixel row PXR#1 starting from the other side on the first direction DR1, and can be referred to as the second pixel row PXR#2, the third pixel row PXR#3, the fourth pixel row PXR#4, and the fifth pixel row PXR#5 on the side facing the first direction DR1. In the attached figures, each pixel row PXR is represented as "R#n (n is an integer from 1 to 5)," but these can be understood to respectively mean the first pixel row PXR#1 to the fifth pixel row PXR#5.

[0146] Eight ineffective fan-out wirings (NFWs) are arranged within the internal ineffective region NAR. In the attached diagram, from left to right, the first ineffective fan-out wiring NFW#1, the third ineffective fan-out wiring NFW#3, the fifth ineffective fan-out wiring NFW#5, and the seventh ineffective fan-out wiring NFW#7 are the first ineffective fan-out wiring NFW_1 belonging to the second data line DL2, and are connected to the second pixel column PXC2 connected to the connecting wiring CNW. In the attached diagram, from left to right, the second ineffective fan-out wiring NFW#2, the fourth ineffective fan-out wiring NFW#4, the sixth ineffective fan-out wiring NFW#6, and the eighth ineffective fan-out wiring NFW#8 are the second ineffective fan-out wiring NFW_2 belonging to the first data line DL1, and are directly connected to the signal wiring SW.

[0147] The first ineffective fan-out wiring NFW#1 is connected to the signal wiring SW, which is connected to the fourth pixel column PXC#4, via the first connection wiring CNW#1. The first extension CNW_1 of the first connection wiring CNW#1 is disposed in the space PXT_C#45 between the fourth pixel columns PXC#4 in the first pixel row PXR#1. The second extension CNW_2 of the first connection wiring CNW#1 is disposed in the space PXT_C#45 between the fourth pixel columns at the space PXT_R#12 between the first pixel rows. The third extension CNW_3 of the first connection wiring CNW#1 is disposed in the space PXT_C#45 between the fourth pixel columns PXC#4 in the first pixel row PXR#1, and is located on the other side of the first extension CNW_1 in the second direction DR2. The third extension CNW_3 of the first connection wiring CNW#1 is connected to the signal wiring SW disposed in the space PXT_R#34 between the third pixel columns via the contact electrode CNE.

[0148] The second ineffective fan-out wiring NFW#2 is connected to the signal wiring SW arranged in the space PXT_C#56 between the fifth pixel columns, and is also connected to the fifth pixel column PXC#5.

[0149] Similarly, the third ineffective fan-out wiring NFW#3, the fifth ineffective fan-out wiring NFW#5, and the seventh ineffective fan-out wiring NFW#7 are connected to the second connecting wiring CNW#2, the third connecting wiring CNW#3, and the fourth connecting wiring CNW#4, respectively. The fourth ineffective fan-out wiring NFW#4, the sixth ineffective fan-out wiring NFW#6, and the eighth ineffective fan-out wiring NFW#8 can be directly connected to their respective signal wiring SW.

[0150] The first extension CNW_1 and the third extension CNW_3 of the multiple connecting wiring CNWs can be located in the spaces PXT_C#12, PXT_C#23, PXT_C#34, PXT_C#45, PXT_C#56, PXT_C#67, and PXT_C#78 between pixel columns in the effective area AAR, respectively. Conversely, the second extension CNW_2 of the connecting wiring CNW can be arranged only in the spaces between some pixel rows in the effective area AAR.

[0151] The first extension CNW_1 and the third extension CNW_3 of the connecting wiring CNW that passes through the space between pixel columns PXT_C do not overlap with the first signal wiring SW1 and the second signal wiring SW2. However, the second extension CNW_2 of the connecting wiring CNW that passes through the space PXT_R between pixel rows may intersect with the first signal wiring SW1 and the second signal wiring SW2 and partially overlap with the first signal wiring SW1 and the second signal wiring SW2 at the corresponding intersection point.

[0152] The connection lines CNWs, which connect to different first signal lines SW1 and second signal lines SW2, are arranged spaced apart from each other to avoid short-circuiting. In an embodiment, the first extensions CNW_1 and third extensions CNW_3 of the plurality of connection lines CNW are arranged in a plurality of spaces PXT_C between corresponding pixel columns, while their second extensions CNW_2 may be arranged one after another in spaces PXT_R between at least two pixel rows.

[0153] For example, the first extension CNW_1 and the third extension CNW_3 of the first connecting wiring CNW#1 are arranged in the space PXT_C#45 between the fourth pixel columns. The first extension CNW_1 of the second connecting wiring CNW#2 is arranged in the space PXT_C#56 between the fifth pixel columns, and its third extension CNW_3 is arranged in the space PXT_C#34 between the third pixel columns. Similarly, the first extension CNW_1 and the third extension CNW_3 of the third connecting wiring CNW#3 and the fourth connecting wiring CNW#4 can be arranged in the spaces PXT_C#12, PXT_C#23, PXT_C#67, and PXT_C#78 in the corresponding pixel columns. The spacing between the first extension CNW_1 or the third extension CNW_3 of the first connecting wiring CNW#1, the second connecting wiring CNW#2, the third connecting wiring CNW#3, and the fourth connecting wiring CNW#4 can be constant. A pixel column PXC can be arranged between two adjacent first extensions CNW_1, and the spacing between them can be similar to the width of each pixel PX in the second direction DR2.

[0154] Conversely, the second extensions CNW_2 of the multiple connection routes CNW can be arranged one after another in the space PXT_R between at least two pixel rows. For example, the second extension CNW_2 of the first connection route CNW#1 can be arranged in the space PXT_R#12 between the first pixel rows at the space PXT_C#45 between the fourth pixel columns, and the second extension CNW_2 of the second connection route CNW#2 can be arranged to extend from space PXT_C#34 to space PXT_C#56 in space PXT_R#34. The second extensions CNW_2 of the connection route CNW may not be arranged in the space PXT_R#23 between the second pixel rows. Similarly, the second extension CNW_2 of the third connection route CNW#3 can be arranged in the space PXT_R between the fifth pixel rows, and the second extension CNW_2 of the third connection route CNW#3 may not be arranged in the space PXT_R#45 between the fourth pixel rows. Here, for example, "between the first pixel rows" can be defined as meaning "between the first pixel row and the second pixel row".

[0155] Therefore, at least two pixel rows (PXR) can be arranged between the second extensions (CNW_2) of adjacent first connection wiring CNW#1, second connection wiring CNW#2, third connection wiring CNW#3 and fourth connection wiring CNW#4.

[0156] Meanwhile, as described above, the connection cabling CNW can be arranged only in the effective fan-out area AAR_F adjacent to the ineffective area NAR within the effective area AAR. In this case, an appearance defect may occur where the connection cabling CNW is only visible from the outside, appearing to be arranged only in a portion of the entire effective area AAR. To prevent this appearance defect, multiple dummy cabling patterns DMP (DMP_1, DMP_2, and DMP_3) can be arranged on the front surface of the effective area AAR.

[0157] The dummy wiring pattern (DMP) can be included in the same conductive layer as the connection wiring (CNW). When the connection wiring (CNW) is included in the second data conductive layer 160, the dummy wiring pattern (DMP) is also included in the second data conductive layer 160. The dummy wiring pattern (DMP) can be formed together (synchronously) with the connection wiring (CNW).

[0158] The dummy wiring pattern (DMP) can be separated from the connector wiring (CNW). That is, the dummy wiring pattern (DMP) is formed on the same layer as the connector wiring (CNW), but can be arranged to be spaced apart from the connector wiring (CNW). The dummy wiring pattern (DMP) can be a floating wiring pattern that does not directly receive electrical signals. However, the invention is not limited to this, and the dummy wiring pattern (DMP) can be connected to a portion of the connector wiring (CNW).

[0159] The dummy routing pattern DMP may include a first dummy routing pattern DMP_1 and a second dummy routing pattern DMP_2 extending in the second direction DR2, and a third dummy routing pattern DMP_3 extending in the first direction DR1. The first dummy routing pattern DMP_1 may be arranged in the effective fan-out area AAR_F, and the second dummy routing pattern DMP_2 and the third dummy routing pattern DMP_3 may be arranged in the main effective area AAR_M.

[0160] The first dummy wiring pattern DMP_1 can be arranged in the space PXT_R between pixel rows in the effective fan-out region AAR_F. Since the first dummy wiring pattern DMP_1 is arranged in the space PXT_R between pixel rows where the second extension CNW_2 of the connecting wiring CNW is not arranged, the second extension CNW_2 of the connecting wiring CNW is less likely to be observed externally in the effective fan-out region AAR_F.

[0161] The first dummy wiring pattern DMP_1 may include a first sub-pattern DMP#1 disposed between second extensions CNW_2 of different connecting wirings CNW. The first sub-pattern DMP#1 may be disposed in the space PXT_R#23 between second pixel rows and the space PXT_R#45 between fourth pixel rows, extending in the second direction DR2, where spaces PXT_R#23 and PXT_R#45 are spaces PXT_R between pixel rows where the second extensions CNW_2 are not disposed. The first sub-pattern DMP#1 may be disposed above multiple adjacent pixels PX in the second direction DR2 within the space PXT_R between pixel rows. For example, the first sub-pattern DMP#1 disposed between the second extensions CNW_2 of the first connecting wiring CNW#1 and the second connecting wiring CNW#2 may be disposed in the space PXT_R#23 between second pixel rows and may be disposed above the fourth pixel column PXC#4 and the fifth pixel column PXC#5. The first subpattern DMP#1 may have a length extending in the second direction DR2, which is greater than the width of each pixel column PXC or pixel PX in the second direction DR2.

[0162] Furthermore, the first dummy wiring pattern DMP_1 is arranged in the space PXT_R between pixel rows that are the same as the pixel rows of the second extension CNW_2 of the connecting wiring CNW, and may include a second sub-pattern DMP#2 arranged in the space PXT_C between pixel columns where the second extension CNW_2 is not arranged. For example, the second extension CNW_2 of the first connecting wiring CNW#1 is arranged in the space PXT_C#45 between the fourth pixel columns at the space PXT_R#12 between the first pixel rows. The second sub-pattern DMP#2 may be arranged in the spaces between other pixel columns in the space PXT_R#12 between the first pixel rows, except for the space PXT_C#45 between the fourth pixel columns. The second sub-pattern DMP#2 may have a length extending in the second direction DR2 that is substantially equal to the width of each pixel column PXC or pixel PX in the second direction DR2. The first dummy wiring pattern DMP_1 may be included in a conductive layer disposed on the same layer as the connecting wiring CNW, and may be arranged to be spaced apart from the connecting wiring CNW to prevent electrical short circuits caused by intersection with the connecting wiring CNW. Here, for example, "between the fourth pixel column" can be defined as meaning "between the fourth pixel column and the fifth pixel column".

[0163] The second dummy wiring pattern DMP_2 can be arranged in the main active region AAR_M and can extend in the second direction DR2. The second dummy wiring pattern DMP_2 is arranged in the space PXT_R between pixel rows in the main active region AAR_M and extends in the second direction DR2. As the second dummy wiring pattern DMP_2 is arranged from the outer active region AAR_L2 to the inner active region AAR_I, the second dummy wiring pattern DMP_2 can be arranged in multiple pixel columns PXC and the space PXT_C between pixel columns. Accordingly, the second dummy wiring pattern DMP_2 can intersect with the signal wiring SW.

[0164] The third dummy wiring pattern DMP_3 may be arranged in the main active region AAR_M and extend in the first direction DR1. The third dummy wiring pattern DMP_3 is arranged in the space PXT_C between pixel columns of the main active region AAR_M, and may be spaced apart from the second dummy wiring pattern DMP_2 so as not to intersect with it. The third dummy wiring pattern DMP_3 may be arranged to sit on the extension line extending in the first direction DR1 of the first extension CNW_1 or the third extension CNW_3 of the connecting wiring CNW. Accordingly, the third dummy wiring pattern DMP_3 may not be arranged in the space PXT_R between pixel rows, but may be arranged in the space PXT_C between pixel columns on one side of the adjacent pixel PX in the second direction DR2. For example, the third dummy wiring pattern DMP_3 may be arranged on the opposite side of the second direction DR2 based on the signal wiring SW that provides data signals to each pixel PX and the corresponding pixel PX. However, the invention is not limited thereto.

[0165] The second dummy wiring pattern DMP_2, arranged in the main effective area AAR_M, can be arranged as a single, non-separated extension, and the first dummy wiring pattern DMP_1 and the third dummy wiring pattern DMP_3 can include multiple patterns separated from each other so as not to intersect with other wirings arranged on the same layer. In an embodiment, the length of the second dummy wiring pattern DMP_2, measured in the second direction DR2, can be longer than the length of each of the first dummy wiring patterns DMP_1, measured in the second direction DR2. Furthermore, the length of the second dummy wiring pattern DMP_2, measured in the second direction DR2, can be longer than the length of the third dummy wiring pattern DMP_3, measured in the first direction DR1, and can be longer than the length of the second extension CNW_2 of the connecting wiring CNW.

[0166] Within the effective area AAR, multiple dummy wiring patterns DMP, each having a shape similar to the connecting wiring CNW, are arranged corresponding to it. Among these, multiple wirings extending in the second direction DR2 can be arranged in the effective fan-out area AAR_F and the main effective area AAR_M. The second extension CNW_2 of the connecting wiring CNW and the first dummy wiring pattern DMP_1 can be arranged in the effective fan-out area AAR_F, and the second dummy wiring pattern DMP_2 can be arranged in the main effective area AAR_M.

[0167] The connecting wiring CNW and the dummy wiring pattern DMP can be included in a conductive layer (e.g., the second data conductive layer 160) disposed on the same layer. A fifth insulating layer 125 is disposed on the second data conductive layer 160, and the pixel electrode 170 is disposed on the fifth insulating layer 125. As described above, the second dummy wiring pattern DMP_2 is included in an extended wiring, but the first dummy wiring pattern DMP_1 and the third dummy wiring pattern DMP_3 can be included in multiple separate wiring patterns. At a portion where the wirings disposed on the second data conductive layer 160 are separated from and spaced apart from each other, the upper surface of the fifth insulating layer 125 disposed thereon can be stepped, and the pixel electrode 170 disposed on that portion where the wirings disposed on the second data conductive layer 160 are spaced apart from each other can also be stepped. In this case, the reflectivity of light incident from the outside can vary depending on the area of ​​the pixel electrode 170 disposed above the entire surface of the effective area AAR, and the pattern can be visually identified from the outside due to the difference in reflectivity.

[0168] Specifically, when each of the multiple connecting wirings CNW is arranged to have the shortest path in the space PXT_C between pixel columns or the space PXT_R between pixel rows, the first dummy wiring pattern DMP_1 may only include a second sub-pattern DMP#2 with a short length. In this case, among the wirings extending in the second direction DR2, the second sub-pattern DMP#2 arranged in the effective fan-out area AAR_F and the second extension CNW_2 of the connecting wiring CNW are different from the second dummy wiring pattern DMP_2 arranged in the main effective area AAR_M in terms of arrangement, length, and similar properties, so that the difference in reflectivity between the multiple effective areas AAR is further increased, and the possibility of recognizing some wirings as patterns from an external visual perspective can be increased. Because the effective fan-out region AAR_F contains a second sub-pattern DMP#2 with a short length, and the main effective region AAR_M contains a second dummy wiring pattern DMP_2 with a long length, the difference in reflectivity between the effective fan-out region AAR_F and the main effective region AAR_M is increased, so that the effective fan-out region AAR_F and the main effective region AAR_M can be divided into different regions.

[0169] In the display device 1 according to the embodiment, each connection wiring CNW does not have a shortest path in the space PXT_C between pixel columns or in the space PXT_R between pixel rows, and is formed as a path between two or more pixel rows PXR or pixel columns PXC. For example, as Figure 12 As shown, compared to the second direction DR2, the connecting wires CNW are arranged along a path having a shape extending in the first direction DR1. The length of the portion of the connecting wires CNW extending in the first direction DR1 can be longer than the length of the portion of the connecting wires CNW extending in the second direction DR2, and space can be ensured between multiple connecting wires CNW to arrange dummy wiring patterns DMP. In the effective fan-out area AAR_F, a first dummy wiring pattern DMP_1, similar to the second dummy wiring pattern DMP_2 and the third dummy wiring pattern DMP_3 arranged in the main effective area AAR_M, is arranged between the connecting wires CNW, and thus, appearance defects caused by the arrangement of dummy wiring patterns DMP can be mitigated. In the effective area AAR of the display device 1, dummy wiring patterns DMP are arranged in the area where connecting wires CNW are arranged (or the effective fan-out area AAR_F) and in the area where connecting wires CNW are not arranged (or the main effective area AAR_M), respectively, to prevent the dummy wiring patterns DMP from being divided into different areas and visually identifiable. The display device 1 includes a dummy wiring pattern DMP arranged similarly to the connecting wiring CNW, and furthermore, the path of the connecting wiring CNW is provided so that the dummy wiring pattern DMP can be arranged above the entire effective area AAR, thereby preventing appearance defects caused by the connecting wiring CNW passing through the effective area AAR.

[0170] In the following description, various embodiments of the display device will be described with reference to the other accompanying drawings.

[0171] Figure 14 This is a schematic layout view showing the wiring arrangement of a display device 2 according to another embodiment, and Figure 15 It shows the arrangement in Figure 14 A partial layout view of the arrangement of data lines in the effective fan-out area AAR_F of the display device 2.

[0172] Reference Figure 14 and Figure 15In the display device 2, a third dummy wiring pattern DMP_3 may be arranged even within the effective fan-out area AAR_F. In addition to the first dummy wiring pattern DMP_1, the third dummy wiring pattern DMP_3 extending in the first direction DR1 may also be arranged within the effective fan-out area AAR_F. The characteristic of this embodiment is that the third dummy wiring pattern DMP_3 is arranged above the entire effective area AAR, thereby preventing appearance defects caused by wiring extending in the first direction DR1.

[0173] In the space between pixel columns, a third dummy wiring pattern DMP_3 arranged in the effective fan-out region AAR_F can be arranged in the pixel row PXR where the first extension CNW_1 and the third extension CNW_3 of the connecting wiring CNW are not arranged. In an exemplary embodiment, at least some of the plurality of third dummy wiring patterns DMP_3 can be arranged between the second extension CNW_2 of the connecting wiring CNW and the first sub-pattern DMP#1 of the first dummy wiring pattern DMP_1. Furthermore, at least some of the plurality of third dummy wiring patterns DMP_3 can be arranged to be placed on the extension lines extending from the first extension CNW_1 and the third extension CNW_3 of the connecting wiring CNW.

[0174] For example, some of the multiple third dummy wiring patterns DMP_3 may be located in the second pixel row PXR#2, the third pixel row PXR#3, the fourth pixel row PXR#4, and the fifth pixel row PXR#5 respectively in the space PXT_C#45 between the fourth pixel columns. The multiple third dummy wiring patterns DMP_3 may be spaced apart from each other between the second extension CNW_2 of the connecting wiring CNW extending in the second direction DR2 and the first sub-pattern DMP#1 of the first dummy wiring pattern DMP_1, so as not to intersect with the second extension CNW_2 of the connecting wiring CNW and the first sub-pattern DMP#1 of the first dummy wiring pattern DMP_1 between them. The multiple third dummy wiring patterns DMP_3 arranged in the space PXT_C#45 between the fourth pixel columns may be arranged to sit on the same line extending from the first extension CNW_1 and the third extension CNW_3 of the first connecting wiring CNW#1 in the first direction DR1.

[0175] Similarly, some of the multiple third dummy wiring patterns DMP_3 can be arranged in the fourth pixel row PXR#4 and the fifth pixel row PXR#5, respectively, in the space between the third pixel column PXT_C#34 and the space between the fifth pixel column PXT_C#56. The third dummy wiring patterns DMP_3 arranged in the space between the third pixel column PXT_C#34 and the space between the fifth pixel column PXT_C#56 can be arranged to sit on the same line extending from the first extension CNW_1 and the third extension CNW_3 of the first connecting wiring CNW#2 in the first direction DR1.

[0176] In the connecting wiring CNW arranged in the effective fan-out region AAR_F and the dummy wiring pattern DMP arranged in the main effective region AAR_M, the wiring extending in the first direction DR1 has different shapes from each other. The first extension CNW_1 and the third extension CNW_3 of the connecting wiring CNW can be arranged above multiple pixel rows PXR, while the third dummy wiring pattern DMP_3 arranged in the main effective region AAR_M can be arranged in only one pixel row PXR. The reason for this can be understood from the fact that only the wiring extending in the first direction DR1 that is disconnected in the first direction DR1 is arranged in the main effective region AAR_M, and only the wiring that is connected in one direction DR1 and is not disconnected is arranged in the effective fan-out region AAR_F. Similar to the wiring extending in the second direction DR2, the main effective region AAR_M and the effective fan-out region AAR_F can be identified as separate regions by the arrangement of the wiring extending in the first direction DR1. The connecting cabling CNW can be arranged to ensure space between the second extensions CNW_2, such that the first sub-pattern DMP#1 arranged on the second direction DR2 is arranged in the effective fan-out area AAR_F.

[0177] According to an embodiment, the display device 2 may also be provided with a third dummy wiring pattern DMP_3 arranged in a space secured by the connecting wiring CNW with the same pattern as the main effective area AAR_M, thereby arranging wiring with nearly similar patterns in the main effective area AAR_M and the effective fan-out area AAR_F. Accordingly, the difference in reflectivity of external light for each area is reduced, and appearance defects that are visually perceived as separate areas are further prevented. Since other descriptions are the same as those described above, their detailed descriptions will be omitted.

[0178] Figure 16 This is a partial layout view showing the arrangement of data lines in the effective fan-out area AAR_F of the display device 3 according to another embodiment.

[0179] Reference Figure 16In the display device 3 according to another embodiment, a plurality of dummy wiring patterns DMP can be connected to other wirings (e.g., connection wiring CNW). Although the dummy wiring patterns DMP can be arranged in a floating state in the active area AAR, the dummy wiring patterns DMP can be connected to the connection wiring CNW to transmit the same electrical signal as in this embodiment. The first dummy wiring pattern DMP_1 and the third dummy wiring pattern DMP_3 arranged in the active fan-out area AAR_F can be directly connected to either of the adjacent connection wiring CNW. The feature of this embodiment is that the dummy wiring patterns DMP arranged in the active fan-out area AAR_F are not arranged in a floating state.

[0180] The first sub-pattern DMP#1 of the first dummy wiring pattern DMP_1 can be further extended to one side of the second direction DR2 to directly connect to the third extension CNW_3 of the connecting wiring CNW. The second sub-pattern DMP#2 of the first dummy wiring pattern DMP_1 can be further extended to one side of the second direction DR2 to directly connect to the first extension CNW_1 or the third extension CNW_3 of the connecting wiring CNW. The third dummy wiring pattern DMP_3 can be further extended to one side of the first direction DR1 to directly connect to the second extension CNW_2 of the adjacent connecting wiring CNW.

[0181] However, the first dummy wiring pattern DMP_1 and the third dummy wiring pattern DMP_3 are connected to a single connection wiring CNW, but not to another connection wiring CNW. When a dummy wiring pattern DMP is connected to multiple connection wiring CNWs, unwanted signals can be transmitted to multiple data lines that transmit data signals to each pixel PX. To prevent this problem, the dummy wiring pattern DMP can be directly connected to only one connection wiring CNW.

[0182] Dummy wiring patterns (DMPs) can be pre-arranged and connected to the connecting wiring (CNW), but the invention is not limited thereto. In embodiments, the dummy wiring patterns (DMPs) can extend according to random rules to connect to the connecting wiring (CNW). For example, some first sub-patterns (DMPs) #1 can extend to one side of the second direction (DR2) to connect to the first extension (CNW_1) of the connecting wiring (CNW), and other first sub-patterns (DMPs) #1 can extend to the other side of the second direction (DR2) to connect to the third extension (CNW_3) of the connecting wiring (CNW). Because the dummy wiring patterns (DMPs) extend without direction, it is possible to prevent the dummy wiring patterns (DMPs) in the effective fan-out area (AAR_F) from being identified as specific patterns.

[0183] Figure 17 This is a partial layout view showing the arrangement of data lines in the effective fan-out area AAR_F of the display device 4 according to another embodiment.

[0184] Reference Figure 17 In a display device 4 according to another embodiment, the plurality of connection wirings CNW can be arranged in a path that extends in the second direction DR2 instead of the first direction DR1. That is, the second extension CNW_2 of the connection wirings CNW can be arranged in the space PXT_R between the pixel rows arranged in the effective fan-out area AAR_F, and the first extension CNW_1 and the third extension CNW_3 of the connection wirings CNW can be arranged outside the portion of the space PXT_C between the pixel columns. The feature of this embodiment is that the paths in which the connection wirings CNW are arranged are different.

[0185] For example, the second extension CNW_2 of the first connecting wiring CNW#1 can be arranged in the space PXT_R#12 between the first pixel rows, and the second extension CNW_2 of the second connecting wiring CNW#2 can be arranged in the space PXT_R#23 between the second pixel rows. Similarly, the second extension CNW_2 of the third connecting wiring CNW#3 and the second extension CNW_2 of the fourth connecting wiring CNW#4 can be arranged in the spaces PXT_R#34 and PXT_R#45 between the third and fourth pixel rows, respectively. Figure 12 In different implementations, the distance between the second extensions CNW_2 of the plurality of connecting wiring CNWs can be substantially the same as the width of each pixel row PXR in the first direction DR1. Each of the plurality of second extensions CNW_2 can be arranged in the space PXT_R between the pixel rows.

[0186] The first extension CNW_1 and the third extension CNW_3 of the first connecting wiring CNW#1 are arranged in the space PXT_C#45 between the fourth pixel columns. The first extension CNW_1 and the third extension CNW_3 of the second connecting wiring CNW#2 are arranged in the spaces PXT_C#23 between the second pixel columns and PXT_C#67 between the sixth pixel columns, respectively. The first extension CNW_1 and the third extension CNW_3 of the connecting wiring CNW may not be arranged in the spaces PXT_C#34 between the third pixel columns and PXT_C#56 between the fifth pixel columns. At least two pixel columns PXC may be arranged between the first extension CNW_1 or the third extension CNW_3 of adjacent connecting wiring CNWs.

[0187] The first dummy wiring pattern DMP_1 can be arranged together with the second extension CNW_2 of the connecting wiring CNW in the space PXT_R between pixel rows. Since the second extension CNW_2 of the connecting wiring CNW is arranged in the space PXT_R between pixel rows, the first dummy wiring pattern DMP_1 can be arranged to sit on the imaginary extension line that the second extension CNW_2 would reach if it were to extend further in the second direction DR2, rather than being arranged between the second extensions CNW_2. That is, the first dummy wiring pattern DMP_1 can have a connection with the second sub-pattern ( Figure 12 The permutation of DMP#2 is the same as that in the permutation.

[0188] The third dummy wiring pattern DMP_3 can be arranged in the space PXT_C between pixel columns. Some of the multiple third dummy wiring patterns DMP_3 can be arranged in the space PXT_C between the first extension CNW_1 and the third extension CNW_3 of the connecting wiring CNW, in a pixel column where the first extension CNW_1 and the third extension CNW_3 are not arranged. For example, the third dummy wiring pattern DMP_3 can be arranged in the space PXT_C#34 between the third pixel column and the space PXT_C#56 between the fifth pixel column, and these spaces are located between the first extension CNW_1 and the third extension CNW_3 of the first connecting wiring CNW#1 and the second connecting wiring CNW#2. The third dummy wiring pattern DMP_3 can be arranged between the first extension CNW_1 and the third extension CNW_3 of adjacent connecting wiring CNWs.

[0189] Furthermore, the third dummy wiring pattern DMP_3 can also be arranged in the space PXT_C between the pixel column where the first extension CNW_1 and the third extension CNW_3 of the connecting wiring CNW are arranged. These third dummy wiring patterns DMP_3 can be arranged on the extension lines extending in the first direction DR1 of the first extension CNW_1 and the third extension CNW_3 of the connecting wiring CNW.

[0190] The display device 4 according to this embodiment is characterized in that the connecting wiring CNW is arranged in a path having a shape extending in the second direction DR2 rather than in the first direction DR1. However, compared with Figure 12 Similarly, in the implementation, a space for dummy wiring patterns (DMPs) can be ensured between the connecting cabling CNWs, and the first dummy wiring pattern DMP_1 and the third dummy wiring pattern DMP_3 can be arranged in this space. Accordingly, appearance defects caused by dummy wiring patterns DMPs arranged in the effective fan-out area AAR_F and the main effective area AAR_M can be prevented.

[0191] Figure 18This is a schematic layout view showing the arrangement of dummy wiring patterns DMP in the main effective area AAR_M of the display device 5 according to another embodiment.

[0192] Reference Figure 18 In the display device 5 according to the embodiment, the third dummy wiring pattern DMP_3 of the main effective area AAR_M can extend in the first direction DR1 to be arranged above a plurality of pixel rows PXR, and the second dummy wiring pattern DMP_2 can extend in the second direction DR2, but can be arranged for each pixel column PXC. In the space PXT_C between pixel columns, the second dummy wiring pattern DMP_2 can be separated from another adjacent second dummy wiring pattern DMP_2. The feature of this embodiment is that the shapes of the dummy wiring patterns DMP in the main effective area AAR_M are different from each other.

[0193] The dummy routing pattern (DMP) is arranged to prevent the connection routing CNW from being visually identified as a specific pattern within the active area AAR. The dummy routing pattern (DMP) arranged in the main active area AAR_M can be arranged in a similar shape to the connection routing CNW arranged in the active fan-out area AAR_F to more effectively prevent appearance defects.

[0194] As described above, the connection wiring CNW can be arranged in a path having a shape extending in the first direction DR1 rather than in the second direction DR2. In this case, the length of each of the first extension CNW_1 and the third extension CNW_3 measured in the first direction DR1 in the connection wiring CNW can be longer than the length of the second extension CNW_2 measured in the second direction DR2. The connection wiring CNW arranged in the effective fan-out area AAR_F can be visually identified as having a shape extending in the first direction DR1. In response, the dummy wiring pattern DMP arranged in the main effective area AAR_M can include a third dummy wiring pattern DMP_3 extending in the first direction DR1 and a second dummy wiring pattern DMP_2 extending in the second direction DR2, which are separated from each other. In particular, since the signal wiring SW arranged in the first data conductive layer 150 also extends in the first direction DR1, the dummy wiring patterns DMP can be arranged in a similar shape. In the display device 5, the dummy wiring pattern DMP is arranged in a shape more similar to the connecting wiring CNW, and the area between the main effective area AAR_M and the effective fan-out area AAR_F is separated to further prevent visually identifiable appearance defects.

[0195] Figure 19 This is a perspective view of a display device 6 according to another embodiment, and Figure 20 yes Figure 19 The unfolded view of the display device 6. Figure 19 and Figure 20 The display device 6 is shown to be applicable as a multi-faceted display device.

[0196] Reference Figure 19 and Figure 20 The display device 6 according to this embodiment includes a front effective area AAR0, a plurality of side effective areas AAR1, AAR2, AAR3 and AAR4, and a plurality of corner areas C1, C2, C3 and C4.

[0197] The front effective region AAR0 and multiple side effective regions AAR1, AAR2, AAR3 and AAR4 can be included in the effective region AAR of the displayed image. The multiple side effective regions AAR1, AAR2, AAR3 and AAR4 can be bent at an angle of 30° to 120° relative to the front effective region AAR0.

[0198] Multiple corner regions C1, C2, C3, and C4 can be located between multiple lateral effective regions AAR1, AAR2, AAR3, and AAR4. For example... Figure 20 As shown, multiple corner regions C1, C2, C3, and C4 may include a first corner region C1, a second corner region C2, a third corner region C3, and a fourth corner region C4 located between a first-side effective region AAR1, a second-side effective region AAR2, a third-side effective region AAR3, and a fourth-side effective region AAR4, respectively. The first corner regions C1, C2, C3, and C4 may be arranged so that they are adjacent to the four corners where they intersect the long and short sides of the preceding effective region AAR0, respectively. Except for their positions, the first corner regions C1, C2, C3, and C4 may have substantially the same function or configuration. The multiple corner regions C1, C2, C3, and C4 are non-effective regions NAR that do not display images and provide space for wiring to pass through.

[0199] In this embodiment, compared with the reference Figure 6 Similarly, in the second direction DR2, the width of the pad cell PDR is smaller than the width of the entire effective area AAR. Accordingly, signals can be transmitted via direct routing to the first-side effective area AAR1, the front effective area AAR0, and the third-side effective area AAR3, which overlap with the arrangement area of ​​the routing extending from the pad cell PDR in the first direction DR1. However, it is difficult to ensure space for the ineffective area NAR where signals can be transmitted via direct routing in the second-side effective area AAR2 or the fourth-side effective area AAR4. For the second-side effective area AAR2 or the fourth-side effective area AAR4, as described above, signals can be transmitted via via-hole routing using bypass routing WD_CN that passes through the effective area AAR. Since the detailed method has already been described above, a repeated description will be omitted.

[0200] The display device according to an embodiment includes connecting wires passing through an effective area and dummy wiring patterns arranged in an area where no connecting wires are arranged. In the effective area, the connecting wires may be arranged in a shape extending vertically compared to the horizontal direction, and a plurality of pixels may be arranged between the horizontal extensions of adjacent connecting wires. The plurality of connecting wires ensures space between them where other dummy wiring patterns may be arranged, thereby allowing the plurality of dummy wiring patterns to be arranged between the connecting wires.

[0201] Accordingly, within the effective area of ​​the display device, dummy wiring patterns are arranged in areas where connecting wires are arranged and areas where no connecting wires are arranged, thereby preventing the dummy wiring patterns from being divided into distinct and visually identifiable areas. The display device includes dummy wiring patterns arranged in a similar manner to connecting wires, and furthermore, the paths of the connecting wires are configured such that the dummy wiring patterns can be arranged above the entire effective area, thereby preventing appearance defects caused by connecting wires passing through the effective area.

[0202] In concluding this detailed description, those skilled in the art will recognize that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the invention. Therefore, the preferred embodiments of the invention disclosed herein are used only in a general and descriptive sense and not for purposes of limitation.

Claims

1. A display device, comprising: The effective area includes multiple pixels arranged in a matrix shape and receiving data signals through data lines; Non-active region, the non-active region being arranged on one side of the active region in a first direction and including pad units; Multiple ineffective fan-out routings are arranged in the ineffective area and connected to the pad cell; Multiple signal wirings extend in the first direction to pass through the effective area and are connected to the multiple pixels; as well as Multiple connection wires, each of which at least partially passes through the effective area, and the multiple connection wires connect some of the multiple ineffective fan-out wires and some of the multiple signal wires. Each of the plurality of connecting wires includes a first extension extending in the first direction, a second extension extending in a second direction intersecting the first direction, and a third extension extending in the first direction. At least two of the plurality of pixels are arranged between corresponding extensions of two adjacent connection wires in the plurality of connection wires, and the at least two pixels are arranged in a direction that is spaced apart from each other along the corresponding extensions.

2. The display device as claimed in claim 1, wherein, The plurality of pixels includes a plurality of pixel columns and a plurality of pixel rows, each of the plurality of pixel columns including pixels arranged in the first direction, and each of the plurality of pixel rows including pixels arranged in the second direction. The second extension of the connecting wiring is disposed between two adjacent pixel rows in the plurality of pixel rows.

3. The display device as claimed in claim 2, wherein, At least two of the plurality of pixel rows are arranged between the second extensions of the two adjacent connecting wires.

4. The display device as claimed in claim 2, further comprising: A first dummy wiring pattern is arranged between the connecting wires. The first dummy wiring pattern includes a first sub-pattern arranged between the second extensions of the two adjacent connecting wirings, and the first sub-pattern extends in the second direction.

5. The display device as claimed in claim 4, wherein, The first sub-pattern is arranged in the space between two adjacent pixel rows in the plurality of pixel rows, and the second extension of the connecting wiring is not arranged in the space.

6. The display device as claimed in claim 4, wherein, The first dummy wiring pattern includes: Multiple second sub-patterns, which are separated from the second extension portions of the two connecting wires, are arranged on an imaginary extension line that the second extension portion would reach if the second extension portion were to extend further.

7. The display device as claimed in claim 4, wherein, At least some of the first dummy wiring patterns are directly connected to the connection wiring.

8. The display device as claimed in claim 4, wherein, The effective area includes an effective fan-out area and a main effective area. In the effective fan-out area, the connecting cabling is arranged adjacent to the ineffective area. The main effective area is the area within the effective area excluding the effective fan-out area, and no connecting cabling is arranged in the main effective area. The display device further includes: A second dummy wiring pattern is arranged in the main effective region and extends in the second direction; and A third dummy wiring pattern is arranged in the main effective area and extends in the first direction.

9. The display device as claimed in claim 8, wherein, The second dummy wiring pattern intersects with the signal wiring and is arranged above the plurality of pixel columns.

10. The display device as claimed in claim 8, wherein, The third dummy wiring pattern is arranged in the space between the pixel columns at the pixel row of the main effective region.

11. The display device as claimed in claim 2, wherein, Each of the plurality of signal wirings is arranged between the pixel columns, and Each of the first and third extensions of the connecting wiring is arranged in a space between different pixel columns.

12. The display device as claimed in claim 11, wherein, At least two of the plurality of pixel columns are arranged between the first extensions of two adjacent connection wires.

13. The display device as claimed in claim 2, wherein, The first and third extensions of at least one of the plurality of connection wires are arranged in the space between two adjacent pixel columns.

14. The display device as claimed in claim 1, wherein, The plurality of signal wirings are included in the first data conductive layer, and The plurality of connection wirings are included in a second data conductive layer, which is different from the first data conductive layer.

15. The display device as claimed in claim 14, wherein, The ineffective fan-out wiring includes a first ineffective fan-out wiring connected to the connection wiring and a second ineffective fan-out wiring directly connected to the signal wiring, and The first ineffective fan-out wiring and the second ineffective fan-out wiring are included in different conductive layers.

16. A display device, comprising: The effective region contains a plurality of pixels; Ineffective region, the ineffective region being arranged on one side of the effective region in a first direction; Multiple ineffective fan-out wirings are arranged in the ineffective region and include first and second ineffective fan-out wirings arranged alternately along a second direction intersecting the first direction. Multiple signal wirings extend in the first direction, are arranged in the inner effective region of the effective region where they overlap with the ineffective fan-out wiring when the ineffective fan-out wiring extends in the first direction, and are arranged in the outer effective region of the effective region where they do not overlap with the ineffective fan-out wiring. Multiple connection cablings connect the ineffective fan-out cablings and the signal cablings arranged in the outer effective area via the effective area; as well as Multiple dummy wiring patterns are arranged in the effective area and do not intersect with the connecting wiring. The connecting wires are arranged along the space between the plurality of pixels, and the length of the extension of the connecting wires in the first direction is longer than the length of the extension of the connecting wires in the second direction.

17. The display device as claimed in claim 16, wherein, The plurality of connection wirings and the plurality of dummy wiring patterns are included in the same conductive layer.

18. The display device as claimed in claim 16, wherein, The plurality of connecting wires includes a first extension extending in the first direction, a second extension extending in a second direction intersecting the first direction, and a third extension extending in the first direction. At least two of the plurality of pixels are arranged between the second extensions of two adjacent connection wires in the plurality of connection wires.

19. The display device as claimed in claim 18, wherein, The dummy wiring pattern includes: A first dummy wiring pattern is arranged between the connecting wires and extends in the second direction; A second dummy wiring pattern extends in the second direction in the area of ​​the effective area where no connecting wiring is arranged; and A third dummy wiring pattern extends in the first direction and does not intersect with the first dummy wiring pattern and the second dummy wiring pattern.

20. The display device as claimed in claim 19, wherein, The first dummy wiring pattern includes: A first sub-pattern, the first sub-pattern being arranged between the second extensions of the two adjacent connecting wires, the first sub-pattern extending in the second direction; and Multiple second sub-patterns, which are separated from the second extension portions of the two connecting wires, are arranged on an imaginary extension line that the second extension portion would reach if it were to extend further. At least some of the third dummy wiring patterns are arranged between the second extension of the connecting wiring and the first sub-pattern.

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