Display device including a data driver and method of operating the display device

Abstract

A display device and a method of operating the display device are provided. The display device includes a display panel, a controller, and a data driver. Among them, the display panel includes a plurality of pixels. The controller provides a clock-embedded data signal that includes image data during an active period and includes training samples during a blanking period. The data driver recovers the image data from the clock-embedded data signal based on an internal clock signal during the active period to supply data voltages corresponding to the image data to the plurality of pixels, and performs a training operation for the internal clock signal by using the training samples included in the clock-embedded data signal during the blanking period. The training samples during the blanking period include a first training clock signal modulated in a first modulation period during a first time, and include a second training clock signal modulated in a second modulation period different from the first modulation period after the first time.

Description

[0001] The technical field relates to a display device and a method of operating the display device. Background Art

[0002] A display device may include pixels, a data driver that provides a data voltage to the pixels, a gate driver that provides a gate signal to the pixels, and a controller that controls the data driver and the gate driver.

[0003] The controller transfers image data to the data driver, and the data driver provides a data voltage corresponding to the image data to the pixels. To transfer the image data, a high-speed interface may be used between the controller and the data driver, such as a Unified Standard Interface for TVs (USI-T interface), a Unified Standard Interface for notebooks and monitors (USI-GF interface), etc.

[0004] In a display device using the USI-T interface or the USI-GF interface, the controller may transfer a clock-embedded data signal, and the data driver may recover a clock signal from the clock-embedded data signal by using a Clock Data Recovery (CDR) circuit, and may sample and restore the data signal by using the recovered clock signal. To allow the recovered clock signal to have a desired frequency and / or a desired phase, the controller may transfer periodically switched training samples as the clock-embedded data signal, and the data driver may perform a clock training operation (or a locking operation) by using the training samples.

[0005] When the frame frequency changes sharply, for example, when the frame frequency changes to half of the original value, a locking sensing error may occur in which the data driver determines a recovered clock signal in an unlocked state as a locked state, a clock signal corresponding to the changed frame frequency may not be recovered, and thus, an operation error of the data driver may occur. Summary of the Invention

[0006] Some embodiments may relate to a display device capable of preventing an operation error of a data driver even when the frame frequency changes sharply.

[0007] Some embodiments may relate to a method of operating a display device capable of preventing an operation error of a data driver even when the frame frequency changes sharply.

[0008] According to an embodiment, a display device may include the following elements: a display panel, a controller, and a data driver. The display panel includes a plurality of pixels. The controller is configured to provide a clock-embedded data signal that includes image data during an active period and includes training samples during a blanking period. The data driver is configured to recover the image data from the clock-embedded data signal based on an internal clock signal during the active period, provide a data voltage corresponding to the image data to the plurality of pixels during the active period, and perform a training operation for the internal clock signal by using the training samples included in the clock-embedded data signal during the blanking period. The training samples during the blanking period include a first training clock signal modulated in a first modulation period during a first time, and include a second training clock signal modulated in a second modulation period different from the first modulation period after the first time.

[0009] The display device may include a shared reverse channel electrically connected between the controller and the data driver. The data driver may include a clock data recovery circuit and a data conversion circuit. The clock data recovery circuit is configured to recover the image data from the clock-embedded data signal during the active period, perform a training operation for training the internal clock signal based on the first training clock signal modulated in the first modulation period, and notify the controller of the locked state of the internal clock signal through the shared reverse channel in response to the second training clock signal modulated in the second modulation period. The data conversion circuit is configured to convert the image data into a data voltage during the active period and provide the data voltage to the plurality of pixels during the active period.

[0010] The clock data recovery circuit may include the following elements: a data recovery circuit, a clock recovery circuit, and a lock sensing circuit. The data recovery circuit is configured to recover the image data from the clock-embedded data signal in response to the internal clock signal during the active period. The clock recovery circuit is electrically connected to the data recovery circuit. The clock recovery circuit is configured to generate the internal clock signal and is configured to perform a training operation for the internal clock signal in response to a training enable signal. The lock sensing circuit is electrically connected to at least one of the data recovery circuit and the clock recovery circuit. The lock sensing circuit is configured to detect whether the internal clock signal is in a locked state or an unlocked state by determining whether the clock-embedded data signal has an edge in each clock period of the internal clock signal and is configured to provide the training enable signal to the clock recovery circuit when the internal clock signal is in the unlocked state.

[0011] In an embodiment, in response to a first training clock signal modulated in a first modulation period, a lock sensing circuit may provide a training enable signal to a clock recovery circuit and may notify a controller of an unlocked state of an internal clock signal through a shared reverse channel, and in response to a second training clock signal modulated in a second modulation period, the lock sensing circuit may notify the controller of a locked state of the internal clock signal through the shared reverse channel.

[0012] The first time may be a standard defined clock phase lock time of an interface between a graphics controller and a data driver.

[0013] The first modulation period may correspond to three times the clock period of the internal clock signal, and the second modulation period may correspond to two times the clock period of the internal clock signal.

[0014] The first modulation period may correspond to four times the clock period of the internal clock signal, and the second modulation period may correspond to two times the clock period of the internal clock signal.

[0015] A display device may include a shared reverse channel electrically connected between a data driver and a controller. The data driver may detect an unlocked state of the internal clock signal and may notify the controller of the unlocked state of the internal clock signal through the shared reverse channel. In response to the unlocked state of the internal clock signal received in an activation period, the controller may stop transmitting a clock embedded data signal including image data and may transmit a clock embedded data signal including training samples in the activation period.

[0016] The training samples in the activation period may be substantially the same as the training samples in a blanking period.

[0017] The training samples in the activation period may be different from the training samples in the blanking period.

[0018] The training samples in the activation period may include only a second training clock signal modulated in a second modulation period.

[0019] The second modulation period may correspond to two times the clock period of the internal clock signal.

[0020] The data driver may include a plurality of data driver integrated circuits, and the plurality of data driver integrated circuits may share the shared reverse channel.

[0021] According to an embodiment, a display device may include the following elements: a display panel, a controller, and a data driver. The display panel includes a plurality of pixels. The controller is configured to provide a clock-embedded data signal that includes image data during an active period and includes training samples during a blanking period. The data driver is configured to receive the clock-embedded data signal, recover the image data from the clock-embedded data signal based on an internal clock signal during the active period, provide data voltages corresponding to the recovered image data to the plurality of pixels during the active period, and perform a training operation for the internal clock signal by using the training samples included in the clock-embedded data signal during the blanking period. The controller detects whether the frame frequency changes and transmits the training samples. During the blanking period, when the frame frequency is changed or after that, the training samples include a first training clock signal modulated in a first modulation period during a first time period and a second training clock signal modulated in a second modulation period different from the first modulation period after the first time period.

[0022] In an embodiment, when the frame frequency does not change, the controller may transmit training samples including only the second training clock signal modulated in the second modulation period during the blanking period.

[0023] The first modulation period may correspond to three times the clock period of the internal clock signal, and the second modulation period may correspond to two times the clock period of the internal clock signal.

[0024] The first modulation period may correspond to four times the clock period of the internal clock signal, and the second modulation period may correspond to two times the clock period of the internal clock signal.

[0025] An embodiment may relate to a method of operating a display device. In this method, the controller of the display device transmits a clock-embedded data signal including image data to the data driver of the display device during the active period. The data driver recovers the image data from the clock-embedded data signal based on the internal clock signal to provide data voltages corresponding to the recovered image data to the plurality of pixels of the display panel of the display device during the active period. The controller transmits a clock-embedded data signal including training samples to the data driver during the blanking period, and the data driver performs a training operation for the internal clock signal by using the training samples included in the clock-embedded data signal during the blanking period. During the blanking period, the training samples include a first training clock signal modulated in a first modulation period during a first time period and a second training clock signal modulated in a second modulation period different from the first modulation period after the first time period.

[0026] The data driver may detect an unlocked state of the internal clock signal, and the data driver may notify the controller of the unlocked state of the internal clock signal through a shared reverse channel.

[0027] The controller may stop transmitting a clock-embedded data signal including image data in response to an unlocked state of an internal clock signal received during an activation period, and the controller may transmit a clock-embedded data signal including training samples to the data driver during the activation period.

[0028] According to an embodiment, during a blanking period, the training samples transmitted from the controller to the data driver may include a first training clock signal modulated in a first modulation period during a first time and a second training clock signal modulated in a second modulation period different from the first modulation period after the first time. Accordingly, even if the frame frequency of the display device is changed, a lock sensing error of the data driver can be prevented, and an operation error of the data driver can be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a block diagram showing a display device according to an embodiment.

[0030] Figure 2 is a block diagram showing a clock data recovery circuit included in a display device according to an embodiment.

[0031] Figure 3 is a diagram showing a clock-embedded data signal, an internal clock signal, a training clock signal modulated in a modulation period corresponding to two clock periods, a training clock signal modulated in a modulation period corresponding to three clock periods, and a training clock signal modulated in a modulation period corresponding to four clock periods according to an embodiment.

[0032] Figure 4 is a diagram for describing an example of a lock sensing error in the case where the frame frequency is changed according to an embodiment.

[0033] Figure 5 is a flowchart showing a method of operating a display device according to an embodiment.

[0034] Figure 6 is a timing diagram for describing an example of an operation of a display device according to an embodiment.

[0035] Figure 7 is a timing diagram for describing an example of an operation of a display device according to an embodiment.

[0036] Figure 8 is a flowchart showing a method of operating a display device according to an embodiment.

[0037] Figure 9 is a timing diagram for describing an example of an operation of a display device according to an embodiment.

[0038] Figure 10It is a timing diagram for describing an example of the operation of a display device according to an embodiment.

[0039] Figure 11 It is a flowchart showing a method of operating a display device according to an embodiment.

[0040] Figure 12 It is a timing diagram for describing an example of the operation of a display device according to an embodiment.

[0041] Figure 13 It is a timing diagram for describing an example of the operation of a display device according to an embodiment.

[0042] Figure 14 It is a block diagram showing an electronic device including a display device according to an embodiment. Detailed Embodiments

[0043] Exemplary embodiments will be described with reference to the accompanying drawings. Although terms such as "first", "second", etc. may be used to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another. Without departing from the teachings of one or more embodiments, the first element may be referred to as the second element. The description of an element as a "first" element may not require or imply the existence of a second element or other elements. Terms such as "first", "second", etc. may be used to distinguish different categories or groups of elements. For the sake of brevity, terms such as "first", "second", etc. may respectively represent "first type (or first group)", "second type (or second group)", etc.

[0044] The expression "during the first / second time" may mean "(substantially) throughout the first / second time" and / or "for a period of the first / second time".

[0045] Figure 1 It is a block diagram showing a display device 100 according to an embodiment. Figure 2 It is a block diagram showing a clock data recovery circuit included in the display device 100 according to an embodiment. Figure 3 It is a diagram showing a clock-embedded data signal, an internal clock signal, a training clock signal modulated with a modulation period corresponding to two clock periods, a training clock signal modulated with a modulation period corresponding to three clock periods, and a training clock signal modulated with a modulation period corresponding to four clock periods.

[0046] Refer to Figure 1, the display device 100 may include a display panel 110 including a plurality of pixels PX, a gate driver 120 that provides a gate signal GS to the plurality of pixels PX, a data driver 130 that provides a data voltage DV to the plurality of pixels PX, and a controller 160 that controls the gate driver 120 and the data driver 130.

[0047] The display panel 110 may include a plurality of data lines, a plurality of gate lines, and a plurality of pixels PX coupled to the plurality of data lines and the plurality of gate lines. Each pixel PX may include a switching transistor and a liquid crystal capacitor coupled to the switching transistor, and the display panel 110 may be a liquid crystal display (LCD) panel. Each pixel PX may include at least two transistors, at least one capacitor, and an organic light emitting diode (OLED), and the display panel 110 may be an OLED display panel. Each pixel PX may include an inorganic light emitting diode or a quantum dot light emitting diode, and the display panel 110 may be an inorganic light emitting diode display panel or a quantum dot light emitting diode display panel.

[0048] The gate driver 120 may generate a gate signal GS based on a gate control signal GCTRL received from the controller 160, and may provide the gate signal GS to the plurality of pixels PX through the plurality of gate lines. The gate control signal GCTRL may include a gate start signal and a gate clock signal. The gate driver 120 may be an amorphous silicon gate (ASG) driver integrated into a peripheral portion of the display panel 110. The gate driver 120 may be implemented with one or more gate integrated circuits (ICs). The gate driver 120 may be directly mounted on the display panel 110, or may be coupled to the display panel 110 in the form of a chip on film (COF).

[0049] The data driver 130 may receive a clock embedded data signal CEDS including image data IDAT from the controller 160, may generate a data voltage DV based on the clock embedded data signal CEDS, and may provide the data voltage DV to the plurality of pixels PX through the plurality of data lines. As Figure 1As shown in the figure, the data driver 130 can be implemented by a plurality of data driver ICs 132, ..., 134. The plurality of data driver ICs 132, ..., 134 can respectively receive corresponding clock-embedded data signals CEDS from the controller 160 through clock-embedded data lines. The plurality of data driver ICs 132, ..., 134 can be directly mounted on the display panel 110, or can be connected to the display panel 110 in the form of COF. The data driver 130 can be implemented by a single data driver IC, or can be integrated into the peripheral part of the display panel 110.

[0050] The controller 160 (e.g., a Timing Controller (TCON)) can receive image data IDAT and a control signal CTRL from an external host processor (e.g., a Graphic Processing Unit (GPU) or a graphics card). The image data IDAT can be RGB image data including red image data, green image data, and blue image data. The control signal CTRL can include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a main clock signal, and / or similar signals. The controller 160 can generate a clock-embedded data signal CEDS and a gate control signal GCTRL based on the image data IDAT and the control signal CTRL. The controller 160 can control the operation of the gate driver 120 by providing the gate control signal GCTRL to the gate driver 120, and can control the operation of the data driver 130 by providing the clock-embedded data signal CEDS to the data driver 130.

[0051] In the display device 100, a high-speed interface for transmitting the image data IDAT (such as at least one of a Unified Standard Interface for TVs (USI-T interface), a Unified Standard Interface for notebooks and monitors (USI-GF), etc.) can be used between the controller 160 and the data driver 130, and the image data IDAT can be transmitted from the controller 160 to the data driver 130 in the form of a clock-embedded data signal CEDS, and the clock-embedded data signal CEDS is defined by the standard of the high-speed interface. For example, as Figure 3 shown in the figure, the clock-embedded data signal CEDS can have a format including a plurality of data bits D0, D1, D2, D3, D4, D5, D6, D7, and D8 and an additional bit AD added to the plurality of data bits D0 to D8. The additional bit AD can have a level opposite to the level of the last data bit D8, and thus, the clock-embedded data signal CEDS can have a regular edge between the last data bit D8 and the additional bit AD. The data driver 130 can generate an internal clock signal of the data driver 130 based on the regular edge of the clock-embedded data signal CEDS.

[0052] In the display device 100, the controller 160 may transmit a clock-embedded data signal CEDS including image data IDAT to the data driver 130 during an active period of a frame period of the display device 100, and may transmit a clock-embedded data signal CEDS including training samples to the data driver 130 during a blanking period of the frame period. The data driver 130 may recover the image data IDAT from the clock-embedded data signal CEDS based on an internal clock signal during the active period, and may supply a data voltage DV corresponding to the recovered image data RDAT to a plurality of pixels PX during the active period. During the blanking period, the data driver 130 may perform a training operation for the internal clock signal by using the training samples included in the clock-embedded data signal CEDS. The training operation (or locking operation) for the internal clock signal may be an operation of adjusting the frequency and / or phase of the internal clock signal to allow the internal clock signal to have a desired frequency and / or a desired phase corresponding to the training samples.

[0053] The display device 100 may further include a shared forward channel SFC and a shared reverse channel SBC between the controller 160 and the data driver 130. The shared forward channel SFC is for the controller 160 to notify the data driver 130 that training samples have been transmitted as the clock-embedded data signal CEDS, and the shared reverse channel SBC is for the data driver 130 to notify the controller 160 of the locked state or unlocked state of the internal clock signal. The controller 160 may notify the data driver 130 of the transmission of training samples by changing the shared forward channel SFC to a low level. The data driver 130 may notify the controller 160 of the unlocked state of the internal clock signal by changing the shared reverse channel SBC to a low level, and may notify the controller 160 of the locked state of the internal clock signal by changing the shared reverse channel SBC to a high level. As Figure 1 shown, the data driver 130 may be implemented with a plurality of data driver ICs 132,..., 134, and the plurality of data driver ICs 132,..., 134 may share the shared forward channel SFC and the shared reverse channel SBC. Accordingly, the controller 160 may notify the plurality of data driver ICs 132,..., 134 of the transmission of training samples by using a single shared forward channel SFC, and the plurality of data driver ICs 132,..., 134 may notify the controller 160 of the locked state or unlocked state of their internal clock signals by using a single shared reverse channel SBC. If any one of the plurality of internal clock signals of the plurality of data driver ICs 132,..., 134 is in an unlocked state, the single shared reverse channel SBC may be changed to a low level.

[0054] To supply a data voltage DV to a plurality of pixels PX during an activation period and perform a training operation for an internal clock signal during a blanking period, the data driver 130 may include a clock data recovery (CDR) circuit 140 and a data conversion circuit 150. The clock data recovery circuit 140 may generate a recovered image data RDAT by using a clock embedded data signal CEDS during the activation period, and may perform a training operation for the internal clock signal by using training samples during the blanking period. The data conversion circuit 150 may convert the recovered image data RDAT into the data voltage DV during the activation period, and may supply the data voltage DV to the pixel PX during the activation period. When the data driver 130 includes a plurality of data driver ICs 132, ..., 134, each of the plurality of data driver ICs 132, ..., 134 may include a clock data recovery circuit 140 and a data conversion circuit 150.

[0055] As Figure 2 shown, the clock data recovery circuit 140 may include a data recovery circuit 141, a clock recovery circuit 142, and a lock sensing circuit 147. The data recovery circuit 141 may receive an internal clock signal ICLK from the clock recovery circuit 142, and may generate the recovered image data RDAT from the clock embedded data signal CEDS in response to the internal clock signal ICLK during the activation period (e.g., by sampling image data IDAT included in the clock embedded data signal CEDS). The data recovery circuit 141 may receive a multi-phase internal clock signal ICLK having a plurality of phases (ten phases) from the clock recovery circuit 142, and based on the multi-phase internal clock signal ICLK, may generate the recovered image data RDAT by sampling the clock embedded data signal CEDS in units of 1 unit interval (UI).

[0056] The clock recovery circuit 142 can generate an internal clock signal ICLK and can perform a training operation for the internal clock signal ICLK in response to a training enable signal TES. The clock recovery circuit 142 can include a phase detector 143, a charge pump 144, a low-pass filter 145, and a voltage-controlled oscillator 146. The phase detector 143 can generate a signal (e.g., an up signal and / or a down signal) corresponding to the phase difference between the internal clock signal ICLK and the clock-embedded data signal CEDS. In response to the signal of the phase detector 143, the charge pump 144 can supply current to the low-pass filter 145 or can draw current from the low-pass filter 145. In response to the positive or negative current from the charge pump 144, the low-pass filter 145 can increase or decrease the control voltage. The charge pump 144 can remove or reduce the high-frequency noise component of the internal clock signal ICLK. The voltage-controlled oscillator 146 can adjust the frequency and / or phase of the internal clock signal ICLK in response to the control voltage from the low-pass filter 145. The clock recovery circuit 142 can be implemented as a Phase Locked Loop (PLL) circuit as shown in Figure 2 . The clock recovery circuit 142 can be implemented as a Delay Locked Loop (DLL) circuit. The clock recovery circuit 142 implemented as a DLL circuit can include a phase comparator, a digital loop filter, and a delay line.

[0057] The lock sensing circuit 147 can detect whether the internal clock signal ICLK is in a locked state or an unlocked state (or lock failure) by determining whether the clock-embedded data signal CEDS has an edge in each clock period of the internal clock signal ICLK (e.g., not only in the blanking period but also in the active period). For example, as shown in Figure 3As shown, during each clock period T of the internal clock signal ICLK, the lock sensing circuit 147 can determine whether the clock embedded data signal CEDS has an edge between the last data bit D8 of the multiple data bits D0 to D8 and the additional bit AD. During a period with a certain time margin relative to the time point between the last data bit D8 and the additional bit AD, the lock sensing circuit 147 can determine whether the clock embedded data signal CEDS has an edge. In the case where the clock embedded data signal CEDS has an edge during a period from about 1UI before the time point between the last data bit D8 and the additional bit AD to about 1UI after the time point between the last data bit D8 and the additional bit AD, the lock sensing circuit 147 can determine that the internal clock signal ICLK is in a locked state. When / if the clock embedded data signal CEDS does not have an edge during this period, the lock sensing circuit 147 can determine that the internal clock signal ICLK is in an unlocked state (or lock failure), and can provide a training enable signal TES to the clock recovery circuit 142. The clock recovery circuit 142 can perform a training operation for the internal clock signal ICLK in response to the training enable signal TES from the lock sensing circuit 147. The training sample can be notified to the lock sensing circuit 147 as the clock embedded data signal CEDS through the shared forward channel SFC, and the lock sensing circuit 147 can notify the controller 160 of the locked state or unlocked state of the internal clock signal ICLK through the shared reverse channel SBC.

[0058] The data conversion circuit 150 may include a shift register array that sequentially stores the recovered image data RDAT, a data latch array that latches the recovered image data RDAT stored in the shift register array in response to a load signal, a digital-to-analog conversion array that converts the recovered image data RDAT output from the data latch array into a data voltage DV by using a gamma voltage, and an output buffer array that outputs the data voltage DV to a plurality of data lines.

[0059] As Figure 3As shown, in the display device 100, a training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T of the internal clock signal ICLK, a training clock signal 3T_TCLK modulated with a modulation period corresponding to three clock periods 3T of the internal clock signal ICLK, and / or a training clock signal 4T_TCLK modulated with a modulation period corresponding to four clock periods 4T of the internal clock signal ICLK can be used as training samples. The training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T can periodically have a high period of approximately 6UI, a low period of approximately 4UI, a high period of approximately 4UI, and a low period of approximately 6UI. The training clock signal 3T_TCLK modulated with a modulation period corresponding to three clock periods 3T can periodically have a high period of approximately 4UI, a low period of approximately 5UI, a high period of approximately 7UI, a low period of approximately 5UI, a high period of approximately 4UI, and a low period of approximately 5UI. The training clock signal 4T_TCLK modulated with a modulation period corresponding to four clock periods 4T can periodically have a high period of approximately 4UI, a low period of approximately 7UI, a high period of approximately 5UI, a low period of approximately 4UI, a high period of approximately 4UI, a low period of approximately 5UI, a high period of approximately 7UI, and a low period of approximately 4UI. UI can correspond to the time for one data bit allocated to the transmission clock embedded data signal CEDS.

[0060] Referring to Figure 3, when / if the lock sensing circuit 147 receives a training clock signal 3T_TCLK modulated with a modulation period corresponding to three clock periods 3T or a training clock signal 4T_TCLK modulated with a modulation period corresponding to four clock periods 4T as a training sample, even if the frame frequency of the display device 100 remains unchanged and the internal clock signal ICLK is in a locked state synchronously with the clock embedded data signal CEDS, the lock sensing circuit 147 may determine that the training clock signal 3T_TCLK modulated with a modulation period corresponding to three clock periods 3T or the training clock signal 4T_TCLK modulated with a modulation period corresponding to four clock periods 4T does not have an edge between the last data bit D8 and the additional bit AD, and thus, may erroneously determine that the internal clock signal ICLK is in an unlocked state. That is, in the case where the controller 160 transmits a training clock signal 3T_TCLK or 4T_TCLK modulated with a modulation period corresponding to three clock periods 3T or four clock periods 4T as a training sample, even if the frame frequency remains unchanged and the internal clock signal ICLK is in a locked state, the data driver 130 may continuously hold the shared reverse channel SBC at a low level to notify the unlocked state caused by erroneously determining that the internal clock signal ICLK is in an unlocked state, and the controller 160 may also continuously transmit the training sample as the clock embedded data signal CEDS in response to the shared reverse channel SBC continuously held at a low level. To prevent the lock sensing circuit 147 from erroneously determining that the internal clock signal ICLK is in an unlocked state even when the frame frequency remains unchanged and the internal clock signal ICLK is in a locked state synchronously with the clock embedded data signal CEDS, only a training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T of the internal clock signal ICLK can be used as a training sample.

[0061] Refer to Figure 4, although the training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T is used as a training sample, when / if the frame frequency of the display device 100 changes sharply, for example, when / if the frame frequency of the display device 100 changes from about 120 Hz to about 60 Hz, the frequency of the training clock signal 2T_TCLK can be reduced to half of the original value, and the clock period of the training clock signal 2T_TCLK can be increased to twice the original value. However, the lock sensing circuit 147 may erroneously determine that the internal clock signal ICLK corresponding to the frame frequency of about 120 Hz before the change is still in the locked state after the frame frequency change. Accordingly, even if the frame frequency of the display device 100 changes from about 120 Hz to about 60 Hz, in the case where the training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T is used as a training sample, the data driver 130 may not perform the training operation for the internal clock signal ICLK. That is, when the frame frequency changes sharply, a lock sensing error may occur (the lock sensing circuit 147 erroneously determines that the internal clock signal ICLK in the unlocked state is in the locked state), and thus, an operation error of the data driver 130 may occur. When / if the frame frequency of the display device 100 changes from about 60 Hz to about 120 Hz and the training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T is used as a training sample, a lock sensing error may occur in which the lock sensing circuit 147 erroneously determines that the internal clock signal ICLK corresponding to the frame frequency of about 60 Hz before the change is still in the locked state after the frame frequency change. Refer to Figure 3, when a training clock signal 3T_TCLK modulated with a modulation period corresponding to three clock periods 3T or a training clock signal 4T_TCLK modulated with a modulation period corresponding to four clock periods 4T is used as a training sample, the lock sensing circuit 147 can determine that the internal clock signal ICLK is in an unlocked state, regardless of whether the frame frequency changes. Therefore, if a training clock signal 3T_TCLK or 4T_TCLK modulated with a modulation period corresponding to three clock periods 3T or four clock periods 4T is used as a training sample, the lock sensing circuit 147 can determine that the internal clock signal ICLK is in an unlocked state not only when the frame frequency does not change but also when the frame frequency changes, and the clock data recovery circuit 140 can train the internal clock signal ICLK corresponding to the changed frame frequency based on the training clock signal 3T_TCLK or 4T_TCLK corresponding to the changed frame frequency. Accordingly, in the display device 100, by utilizing the feature that if a training clock signal 3T_TCLK or 4T_TCLK modulated with a modulation period corresponding to three clock periods 3T or four clock periods 4T is used as a training sample, the lock sensing circuit 147 determines that the internal clock signal ICLK is in an unlocked state not only when the frame frequency does not change but also when the frame frequency changes, a combination of a training clock signal 3T_TCLK or 4T_TCLK modulated with a modulation period corresponding to three clock periods 3T or four clock periods 4T and a training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T can be used as a training sample.

[0062] Therefore, in the display device 100, the training sample transmitted from the controller 160 to the data driver 130 as the clock embedded data signal CEDS in the blanking period may include a first training clock signal modulated with a first modulation period during a first time period, and may include a second training clock signal modulated with a second modulation period different from the first modulation period after the first time. The first time may be a (minimum) clock phase lock time, for example, about 4500 clock periods (4500T), and the clock phase lock time is defined by the standard of an interface (e.g., USI-T interface or USI-GF interface) between the controller 160 and the data driver 130.

[0063] The first modulation period of the first training clock signal may correspond to 3T (i.e., three times the clock period T of the internal clock signal ICLK), and the second modulation period of the second training clock signal may correspond to 2T (i.e., twice the clock period T of the internal clock signal ICLK). Thus, as a training sample in the blanking period, the controller 160 may transmit, during a first time period, a training clock signal 3T_TCLK modulated with a modulation period corresponding to three clock periods 3T, and may transmit, after the first time period, a training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T. In response to the training clock signal 3T_TCLK modulated with a modulation period corresponding to three clock periods 3T, the lock sensing circuit 147 may determine that the internal clock signal ICLK is in an unlocked state, may provide a training enable signal TES to the clock recovery circuit 142, and may notify the controller 160 of the unlocked state of the internal clock signal ICLK via the shared reverse channel SBC. When the training clock signal 3T_TCLK modulated with a modulation period corresponding to three clock periods 3T is transmitted, the clock recovery circuit 142 may perform a training operation for the internal clock signal ICLK in response to the training enable signal TES. Since the training clock signal 3T_TCLK modulated with a modulation period corresponding to three clock periods 3T is transmitted during a first time period (e.g., during a clock phase lock time defined by the USI-T interface standard or the USI-GF interface standard), and a training operation for the internal clock signal ICLK is performed during the first time period, the lock sensing circuit 147 may determine that the internal clock signal ICLK is in an unlocked state during the first time period, but the internal clock signal ICLK generated by the clock recovery circuit 142 may actually be in a locked state at a certain time point after the first time period. If the training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T is transmitted after the first time period, then in response to the training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T, the lock sensing circuit 147 may determine that the internal clock signal ICLK is in a locked state, and may notify the controller 160 of the locked state of the internal clock signal ICLK via the shared reverse channel SBC. The controller 160 may stop transmitting training samples in response to the locked state of the internal clock signal ICLK received via the shared reverse channel SBC.

[0064] The first modulation period of the first training clock signal may correspond to 4T (i.e., four times the clock period T of the internal clock signal ICLK), and the second modulation period of the second training clock signal may correspond to 2T (i.e., twice the clock period T of the internal clock signal ICLK). Thus, as a training sample in the blanking period, the controller 160 may transmit, during a first time period, a training clock signal 4T_TCLK modulated with a modulation period corresponding to four clock periods 4T, and may transmit, after the first time period, a training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T. The clock data recovery circuit 140 may perform a training operation for the internal clock signal ICLK based on the training clock signal 4T_TCLK modulated with a modulation period corresponding to four clock periods 4T during the first time period, and may notify the controller 160 of the locked state of the internal clock signal ICLK via the shared reverse channel SBC in response to the training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T after the first time period.

[0065] Even if the frame frequency of the display device 100 changes abruptly (e.g., from about 120 Hz to about 60 Hz, or from about 60 Hz to about 120 Hz), since the training clock signal 3T_TCLK modulated with a modulation period corresponding to three clock periods 3T or the training clock signal 4T_TCLK modulated with a modulation period corresponding to four clock periods 4T is transmitted during a first time period, the lock sensing circuit 147 can determine that the internal clock signal ICLK is in an unlocked state in response to the training clock signal 3T_TCLK modulated with a modulation period corresponding to three clock periods 3T or the training clock signal 4T_TCLK modulated with a modulation period corresponding to four clock periods 4T, and thus can prevent a potential lock sensing error (the training clock signal 2T_TCLK in the unlocked state is erroneously determined to be in the locked state). Therefore, when the frame frequency of the display device 100 changes abruptly from about 120 Hz to about 60 Hz, the lock sensing circuit 147 can determine that the internal clock signal ICLK is in an unlocked state, and the clock data recovery circuit 140 can perform training on the internal clock signal ICLK corresponding to the changed frame frequency of about 60 Hz based on the training clock signal 3T_TCLK or 4T_TCLK corresponding to the changed frame frequency of about 60 Hz during the first time period. That is, in the display device 100, even if the frame frequency of the display device 100 changes abruptly, the internal clock signal ICLK can be trained corresponding to the changed frame frequency, and thus problems potentially caused by erroneously determining that the internal clock signal ICLK is in the locked state (assuming that only the training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T is used as a training sample) can be prevented. In addition, since the training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T is transmitted after the first time period, a potential problem that the shared reverse channel SBC cannot be changed to a high level for notifying the locked state (assuming that only the training clock signal 3T_TCLK or 4T_TCLK modulated with a modulation period corresponding to three clock periods 3T or four clock periods 4T is used as a training sample) can be prevented.

[0066] The lock sensing circuit 147 can detect the unlocked state of the internal clock signal ICLK in each clock period of the internal clock signal ICLK not only during the blanking period but also during the active period, and can notify the controller 160 of the unlocked state of the internal clock signal ICLK through the shared reverse channel SBC. When / if electrostatic discharge occurs in the data driver 130, the internal clock signal ICLK can become unlocked, and the lock sensing circuit 147 can notify the controller 160 of the unlocked state of the internal clock signal ICLK by changing the shared reverse channel SBC to a low level. Once the controller 160 is notified of the unlocked state of the internal clock signal ICLK through the shared reverse channel SBC, the controller 160 can stop transmitting the clock-embedded data signal CEDS including the image data IDAT, and can transmit the clock-embedded data signal CEDS including the training sample during the active period. If the transmission of the training sample is completed during the active period, the controller 160 can resume transmitting the clock-embedded data signal CEDS including the image data IDAT.

[0067] The training samples during the active period can be substantially the same as the training samples during the blanking period. For example, as the training samples during the active period, the controller 160 can transmit a training clock signal 3T_TCLK modulated with a modulation period corresponding to three clock periods 3T during a first time period, and can transmit a training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T after the first time period. In another example, as the training samples during the active period, the controller 160 can transmit a training clock signal 4T_TCLK modulated with a modulation period corresponding to four clock periods 4T during a first time period, and can transmit a training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T after the first time period.

[0068] The training samples during the active period can be different from the training samples during the blanking period. The training samples during the active period can only include a second training clock signal modulated with a second modulation period. Therefore, as the training samples during the active period, the controller 160 can only transmit a training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T. In an example, the controller 160 can transmit a training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T during approximately 2000 clock periods (2000T).

[0069] In the display device 100, the controller 160 may detect whether the frame frequency of the display device 100 is changed. The controller 160 may detect the change in the frame frequency by detecting the change in the input frame frequency IFF of the image data IDAT. When the frame frequency is not changed, the controller 160 may transmit a training sample including only a second training clock signal modulated in a second modulation period (e.g., a training clock signal 2T_TCLK modulated in a modulation period corresponding to two clock periods 2T). When the frame frequency is changed, as a training sample, the controller 160 may transmit a first training clock signal modulated in a first modulation period (e.g., a training clock signal 3T_TCLK modulated in a modulation period corresponding to three clock periods 3T or a training clock signal 4T_TCLK modulated in a modulation period corresponding to four clock periods 4T) during a first time period, and may transmit a second training clock signal modulated in a second modulation period (e.g., a training clock signal 2T_TCLK modulated in a modulation period corresponding to two clock periods 2T) after the first time period.

[0070] In the display device 100, as a training sample, the controller 160 may transmit a first training clock signal modulated in a first modulation period (e.g., a training clock signal 3T_TCLK or a training clock signal 4T_TCLK) during a first time period, and may transmit a second training clock signal modulated in a second modulation period different from the first modulation period (e.g., a training clock signal 2T_TCLK) after the first time period. Accordingly, even if the frame frequency of the display device 100 is changed, a lock sensing error of the data driver 130 may be prevented, and an operation error of the data driver 130 may be prevented.

[0071] Figure 5 is a flowchart illustrating a method of operating a display device 100 according to an embodiment. Figure 6 is a timing diagram for describing an example of the operation of the display device 100 according to an embodiment. Figure 7 is a timing diagram for describing an example of the operation of the display device 100 according to an embodiment.

[0072] Referring to Figures 1 to 7 , in the method of operating the display device 100, the controller 160 may transmit a clock embedded data signal CEDS including image data IDAT to the data driver 130 during an activation period AP (S310). When / if the internal clock signal ICLK of the data driver 130 is in a locked state (S320: No), the data driver 130 may recover the image data IDAT from the clock embedded data signal CEDS based on the internal clock signal ICLK during the activation period AP to provide a data voltage DV corresponding to the recovered image data RDAT to a plurality of pixels PX (S330).

[0073] During the blanking period BP, the controller 160 may transmit a clock-embedded data signal CEDS including training samples to the data driver 130, and the data driver 130 may perform a training operation for the internal clock signal ICLK by using the training samples included in the clock-embedded data signal CEDS (S340, S345, S350, and S355). The training samples in the blanking period BP may include a first training clock signal modulated in a first modulation period during a first time, and may include a second training clock signal modulated in a second modulation period different from the first modulation period after the first time.

[0074] Referring to Figure 6 , during the blanking period BP, the controller 160 may transmit, during a first time (e.g., about 4500T), a training clock signal 3T_TCLK modulated in a modulation period corresponding to three clock periods 3T as a first training clock signal modulated in a first modulation period, to the data driver 130 (S340). The controller 160 may notify the data driver 130 that the training clock signal 3T_TCLK modulated in the modulation period corresponding to three clock periods 3T has been transmitted by changing the shared forward channel SFC to a low level. In response to the training clock signal 3T_TCLK modulated in the modulation period corresponding to three clock periods 3T, the data driver 130 may determine that the internal clock signal ICLK is in an unlocked state, may notify the controller 160 of the unlocked state of the internal clock signal ICLK by changing the shared backward channel SBC to a low level, and may perform a training operation for the internal clock signal ICLK (S345). After the first time, the controller 160 may transmit a training clock signal 2T_TCLK modulated in a modulation period corresponding to two clock periods 2T as a second training clock signal modulated in a second modulation period, to the data driver 130 (S350). In response to the training clock signal 2T_TCLK modulated in the modulation period corresponding to two clock periods 2T, the data driver 130 may determine that the internal clock signal ICLK is in a locked state, and may notify the controller 160 of the locked state of the internal clock signal ICLK by changing the shared backward channel SBC to a high level (S355). In response to the locked state of the internal clock signal ICLK received through the shared backward channel SBC, the controller 160 may change the shared forward channel SFC to a high level, and may stop transmitting the training samples.

[0075] Referring to Figure 7During the blanking period BP, the controller 160 may transmit, during a first time (e.g., about 4500T), a training clock signal 4T_TCLK modulated with a modulation period corresponding to four clock periods 4T as a first training clock signal modulated with a first modulation period to the data driver 130 (S340). The controller 160 may notify the data driver 130 that the training clock signal 4T_TCLK modulated with a modulation period corresponding to four clock periods 4T has been transmitted by changing the shared forward channel SFC to a low level. In response to the training clock signal 4T_TCLK modulated with a modulation period corresponding to four clock periods 4T, the data driver 130 may determine that the internal clock signal ICLK is in an unlocked state, may notify the controller 160 of the unlocked state of the internal clock signal ICLK by changing the shared reverse channel SBC to a low level, and may perform a training operation for the internal clock signal ICLK (S345). After the first time, the controller 160 may transmit, to the data driver 130, a training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T as a second training clock signal modulated with a second modulation period (S350). In response to the training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T, the data driver 130 may determine that the internal clock signal ICLK is in a locked state, and may notify the controller 160 of the locked state of the internal clock signal ICLK by changing the shared reverse channel SBC to a high level (S355). In response to the locked state of the internal clock signal ICLK received through the shared reverse channel SBC, the controller 160 may change the shared forward channel SFC to a high level and may stop transmitting training samples.

[0076] Not only during the blanking period BP, but also during the activation period AP, the data driver 130 may detect the unlocked state of the internal clock signal ICLK in each clock period T of the internal clock signal ICLK. When / if the internal clock signal ICLK is determined to be in an unlocked state during the activation period AP (S320: Yes), the data driver 130 may notify the controller 160 of the unlocked state of the internal clock signal ICLK through the shared reverse channel SBC (S360). In response to the unlocked state of the internal clock signal ICLK received during the activation period AP, the controller 160 may stop transmitting the clock-embedded data signal CEDS including the image data IDAT (S365), and may transmit the clock-embedded data signal CEDS including the training samples to the data driver 130 during the activation period AP (S340 to S355).

[0077] Referring to Figure 6When / If an electrostatic discharge (ESD) occurs in the data driver 130, the data driver 130 can notify the controller 160 of the unlocked state of the internal clock signal ICLK by changing the shared reverse channel (SBC) to a low level. In response to the low level of the shared reverse channel SBC, the controller 160 can stop transmitting the clock-embedded data signal CEDS (including the image data IDAT) (S365), and can transmit a training clock signal 3T_TCLK modulated with a modulation period corresponding to three clock periods 3T to the data driver 130 during a first time period (e.g., 4500T) (S340). The controller 160 can notify the data driver 130 that the training clock signal 3T_TCLK modulated with a modulation period corresponding to three clock periods 3T has been transmitted by changing the shared forward channel (SFC) to a low level. The data driver 130 can perform a training operation for the internal clock signal ICLK based on the training clock signal 3T_TCLK modulated with a modulation period corresponding to three clock periods 3T (S345). The controller 160 can transmit a training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T to the data driver 130 after the first time period (S350). In response to the training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T, the data driver 130 can notify the controller 160 of the locked state of the internal clock signal ICLK by changing the shared reverse channel SBC to a high level (S355). In response to the locked state of the internal clock signal ICLK received through the shared reverse channel SBC, the controller 160 can change the shared forward channel SFC to a high level and can stop transmitting the training samples.

[0078] Referring to Figure 7 When / If an electrostatic discharge (ESD) occurs in the data driver 130, the controller 160 can stop transmitting the clock-embedded data signal CEDS (including the image data IDAT) (S365), and can transmit a training clock signal 4T_TCLK modulated with a modulation period corresponding to four clock periods 4T to the data driver 130 during a first time period (e.g., 4500T) (S340). The data driver 130 can perform a training operation for the internal clock signal ICLK based on the training clock signal 4T_TCLK modulated with a modulation period corresponding to four clock periods 4T (S345). The controller 160 can transmit a training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T to the data driver 130 after the first time period (S350). In response to the training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T, the data driver 130 can notify the controller 160 of the locked state of the internal clock signal ICLK through the shared reverse channel SBC (S355).

[0079] In the method of operating the display device 100, as a training sample, the controller 160 may transmit a first training clock signal modulated in a first modulation period (e.g., training clock signal 3T_TCLK or training clock signal 4T_TCLK) during a first time period, and may transmit a second training clock signal modulated in a second modulation period different from the first modulation period (e.g., training clock signal 2T_TCLK) after the first time period. Accordingly, even if the frame frequency of the display device 100 changes, a lock sensing error of the data driver 130 can be prevented, and an operation error of the data driver 130 can be prevented.

[0080] Figure 8 is a flowchart showing a method of operating the display device 100 according to an embodiment. Figure 9 is a timing diagram for describing an example of the operation of the display device 100 according to an embodiment. Figure 10 is a timing diagram for describing an example of the operation of the display device 100 according to an embodiment.

[0081] Except that the training sample in the activation period AP is different from the training sample in the blanking period BP, Figure 8 the method of operating the display device 100 shown in Figure 5 may be substantially the same as the method of operating the display device 100 shown in

[0082] Referring to Figures 1 to 3 and Figures 8 to 10, in the method of operating the display device 100, not only in the blanking period BP but also in the activation period AP, the data driver 130 can detect the unlocked state of the internal clock signal ICLK in each clock period T of the internal clock signal ICLK. When / if the internal clock signal ICLK is determined to be in the unlocked state during the activation period AP (S320: Yes), the data driver 130 can notify the controller 160 of the unlocked state of the internal clock signal ICLK through the shared reverse channel SBC (S360). In response to the unlocked state of the internal clock signal ICLK received during the activation period AP, the controller 160 can stop transmitting the clock-embedded data signal CEDS including the image data IDAT (S365), and can transmit the clock-embedded data signal CEDS including the training samples to the data driver 130 during the activation period AP (S470, S475, and S480). Since the internal clock signal ICLK has been determined to be in the unlocked state, a lock sensing error (erroneously determining the unlocked internal clock signal ICLK as being in the locked state) may not occur. Different from the training samples in the blanking period BP, the training samples in the activation period AP may only include the second training clock signal modulated in the second modulation period, for example, the training clock signal 2T_TCLK modulated in the modulation period corresponding to two clock periods 2T. The controller 160 can transmit the training clock signal 2T_TCLK modulated in the modulation period corresponding to two clock periods 2T to the data driver 130 during the second time period (S470). The data driver 130 can perform the training operation for the internal clock signal ICLK based on the training clock signal 2T_TCLK modulated in the modulation period corresponding to two clock periods 2T (S475), and if the internal clock signal ICLK is locked due to the training operation, it can notify the controller 160 of the locked state of the internal clock signal ICLK through the shared reverse channel SBC (S480). The length of the second time period can be about 2000T.

[0083] Referring to Figure 9 , as the training samples in the blanking period BP, the controller 160 can transmit the training clock signal 3T_TCLK modulated in the modulation period corresponding to three clock periods 3T to the data driver 130 during the first time period (e.g., about 4500T) (S340), and can transmit the training clock signal 2T_TCLK modulated in the modulation period corresponding to two clock periods 2T to the data driver 130 after the first time period (S350). As the training samples in the activation period AP, the controller 160 can transmit the training clock signal 2T_TCLK modulated in the modulation period corresponding to two clock periods 2T to the data driver 130 during the second time period (e.g., about 2000T) (S470).

[0084] Reference Figure 10 As a training sample in the blanking period BP, the controller 160 may transmit a training clock signal 4T_TCLK modulated with a modulation period corresponding to four clock periods 4T to the data driver 130 during a first time period (S340), and may transmit a training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T to the data driver 130 after the first time period (S350). As a training sample in the activation period AP, the controller 160 may transmit a training clock signal 2T_TCLK modulated with a modulation period corresponding to two clock periods 2T to the data driver 130 during a second time period (S470).

[0085] Figure 11 is a flowchart showing a method of operating the display device 100 according to an embodiment. Figure 12 is a timing diagram for describing an example of the operation of the display device 100 according to an embodiment. Figure 13 is a timing diagram for describing an example of the operation of the display device 100 according to an embodiment.

[0086] Except for using different training samples according to whether the frame frequency of the display device 100 is changed, Figure 11 the method of operating the display device 100 shown in Figure 5 or Figure 8 is substantially the same as the method of operating the display device 100 shown in

[0087] Reference Figures 1 to 3 and Figures 11 to 13 In the method of operating the display device 100, the controller 160 may detect a change in the frame frequency of the display device 100 (S570). The controller 160 may detect the change in the frame frequency by detecting a change in the input frame frequency IFF of the image data IDAT.

[0088] When / if the frame frequency changes (S570: Yes), the controller 160 may transmit a first training clock signal modulated with a first modulation period during a first time period (S340), and the data driver 130 may perform a training operation for the internal clock signal ICLK based on the first training clock signal modulated with the first modulation period (S345). The controller 160 may transmit a second training clock signal modulated with a second modulation period after the first time period (S350), and in response to the second training clock signal modulated with the second modulation period, the data driver 130 may notify the controller 160 of the locked state of the internal clock signal ICLK through the shared reverse channel SBC (S355).

[0089] When / if the frame frequency is not changed (S570: No), the controller 160 may transmit a second training clock signal modulated in a second modulation period to the data driver 130 during a second time period (S580). The data driver 130 may perform a training operation on the internal clock signal ICLK based on the second training clock signal modulated in the second modulation period (S585), and if the internal clock signal ICLK is locked due to the training operation, may notify the controller 160 of the locked state of the internal clock signal ICLK through the shared reverse channel SBC (S590).

[0090] Referring to Figure 12 , if the frame frequency is not changed, as a training sample in the blanking period BP or the activation period AP, the controller 160 may transmit a training clock signal 2T_TCLK modulated in a modulation period corresponding to two clock periods 2T to the data driver 130 during a second time (e.g., about 2000T). If the frame frequency is changed, as a training sample in the blanking period BP or the activation period AP of the frame period in which the frame frequency is changed, the controller 160 may transmit a training clock signal 3T_TCLK modulated in a modulation period corresponding to three clock periods 3T to the data driver 130 during a first time (e.g., about 4500T), and may transmit a training clock signal 2T_TCLK modulated in a modulation period corresponding to two clock periods 2T to the data driver 130 after the first time.

[0091] Referring to Figure 13 , when / if the frame frequency is not changed, as a training sample in the blanking period BP or the activation period AP, the controller 160 may transmit a training clock signal 2T_TCLK modulated in a modulation period corresponding to two clock periods 2T to the data driver 130 during a second time (e.g., about 2000T). When / if the frame frequency is changed, as a training sample in the blanking period BP or the activation period AP of the frame period in which the frame frequency is changed, the controller 160 may transmit a training clock signal 4T_TCLK modulated in a modulation period corresponding to four clock periods 4T to the data driver 130 during a first time (e.g., about 4500T), and may transmit a training clock signal 2T_TCLK modulated in a modulation period corresponding to two clock periods 2T to the data driver 130 after the first time.

[0092] Figure 14 is a block diagram showing an electronic device 1100 including a display device according to an embodiment.

[0093] Referring to Figure 14, the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and a display device 1160 that are electrically connected to each other. The electronic device 1100 may also include a port for communicating with at least one of a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0094] The processor 1110 may perform various computing functions or tasks. The processor 1110 may be / include at least one of an application processor (AP), a microprocessor, a central processing unit (CPU), and the like. The processor 1110 may be connected to other components via an address bus, a control bus, a data bus, and the like. The processor 1110 may also be connected to an expansion bus, such as a peripheral component interconnection (PCI) bus.

[0095] The memory device 1120 can store data for the operation of the electronic device 1100. The memory device 1120 can include at least one non-volatile memory device and / or at least one volatile memory device. Among them, the at least one non-volatile memory device can be, for example, at least one of an Erasable Programmable Read-Only Memory (EPROM) device, an Electrically Erasable Programmable Read-Only Memory (EEPROM) device, a flash memory device, a Phase Change Random Access Memory (PRAM) device, a Resistance Random Access Memory (RRAM) device, a Nano Floating Gate Memory (NFGM) device, a Polymer Random Access Memory (PoRAM) device, a Magnetic Random Access Memory (MRAM) device, or a Ferroelectric Random Access Memory (FRAM) device, etc. And the at least one volatile memory device can be, for example, at least one of a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, or a Mobile Dynamic Random Access Memory (mobile DRAM) device, etc.

[0096] The storage device 1130 can be / include at least one of a Solid State Drive (SSD) device, a Hard Disk Drive (HDD) device, a CD-ROM device, etc. The I / O device 1140 can be / include an input device such as at least one of a keyboard, a keypad, a mouse, a touch screen, etc. and / or an output device such as at least one of a printer, a speaker, etc. The power supply 1150 can supply power for the operation of the electronic device 1100. The display device 1160 can be connected to other components through a bus and / or other communication links.

[0097] In the display device 1160, the training samples transmitted from the controller to the data driver may include a first training clock signal modulated in a first modulation period during a first time period and a second training clock signal modulated in a second modulation period different from the first modulation period after the first time period. Accordingly, even if the frame frequency of the display device 1160 is changed, a lock sensing error of the data driver can be prevented, and an operation error of the data driver can be prevented.

[0098] Embodiments may be applied to an electronic device 1100 including the display device 1160. Embodiments may be applied to at least one of a television (TV), a digital TV, a 3D TV, a mobile phone, a smartphone, a tablet computer, a virtual reality (VR) device, a wearable electronic device, a personal computer (PC), a home appliance, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, etc.

[0099] Although exemplary embodiments have been described, many modifications are possible in the exemplary embodiments. Accordingly, all such modifications are intended to be included within the scope of the claims.

Claims

1. A display device, comprising: a display panel including a plurality of pixels; a controller configured to provide a clock-embedded data signal that includes image data during an active period and includes training samples during a blanking period; and a data driver configured to receive the clock-embedded data signal, recover the image data based on an internal clock signal during the active period, provide data voltages corresponding to the image data to the plurality of pixels during the active period, and perform a training operation for the internal clock signal by using the training samples, wherein the training samples during the blanking period include a first training clock signal modulated in a first modulation period during a first time period and include a second training clock signal modulated in a second modulation period different from the first modulation period after the first time period, wherein the first modulation period corresponds to three or four times the clock period of the internal clock signal, and wherein the second modulation period corresponds to twice the clock period of the internal clock signal.

2. The display device according to claim 1, comprising: a shared reverse channel electrically connected between the controller and the data driver, wherein the data driver includes: a clock data recovery circuit configured to recover the image data, perform the training operation for training the internal clock signal based on the first training clock signal modulated in the first modulation period, and notify the locking state of the internal clock signal to the controller through the shared reverse channel in response to the second training clock signal modulated in the second modulation period; and a data conversion circuit configured to convert the image data into the data voltages during the active period and provide the data voltages to the plurality of pixels during the active period.

3. The display device according to claim 2, wherein the clock data recovery circuit includes: a data recovery circuit configured to recover the image data from the clock-embedded data signal in response to the internal clock signal during the active period; a clock recovery circuit electrically connected to the data recovery circuit, configured to generate the internal clock signal, and configured to perform the training operation for the internal clock signal in response to a training enable signal; and a lock sensing circuit electrically connected to at least one of the data recovery circuit and the clock recovery circuit, configured to detect whether the internal clock signal is in the locked state or the unlocked state by determining whether the clock-embedded data signal has an edge in each clock period of the internal clock signal, and configured to provide the training enable signal to the clock recovery circuit when the internal clock signal is in the unlocked state.

4. The display device according to claim 3, wherein In response to the first training clock signal modulated in the first modulation period, the lock sensing circuit provides the training enable signal to the clock recovery circuit, and notifies the controller of the unlocked state of the internal clock signal through the shared reverse channel, and wherein, in response to the second training clock signal modulated in the second modulation period, the lock sensing circuit notifies the controller of the locked state of the internal clock signal through the shared reverse channel.

5. The display device according to claim 1, wherein, the first time is a clock phase locking time defined by a standard of an interface between the controller and the data driver.

6. The display device according to claim 1, comprising: a shared reverse channel electrically connected between the data driver and the controller, wherein the data driver detects an unlocked state of the internal clock signal and notifies the controller of the unlocked state of the internal clock signal through the shared reverse channel, and wherein, in response to the unlocked state of the internal clock signal received during the activation period, the controller stops transmitting the clock-embedded data signal including the image data and transmits the clock-embedded data signal including the training samples during the activation period.

7. A display device, comprising: a display panel including a plurality of pixels; a controller configured to provide a clock-embedded data signal including image data during an activation period and including training samples during a blanking period; and a data driver configured to receive the clock-embedded data signal, recover the image data based on an internal clock signal during the activation period, provide a data voltage corresponding to the image data to the plurality of pixels during the activation period, and perform a training operation for the internal clock signal by using the training samples, wherein the controller detects whether the frame frequency changes and transmits the training samples, and during the blanking period, when the frame frequency is changed or after the frame frequency is changed, the training samples include a first training clock signal modulated in a first modulation period during a first time and include a second training clock signal modulated in a second modulation period different from the first modulation period after the first time, wherein the first modulation period corresponds to three or four times the clock period of the internal clock signal, and wherein the second modulation period corresponds to twice the clock period of the internal clock signal.

8. A method of operating a display device, the method comprising: during an activation period, providing a clock-embedded data signal including image data to a data driver of the display device by using a controller of the display device; During the activation period, the image data is restored by using the data driver based on an internal clock signal to provide data voltages corresponding to the image data to a plurality of pixels of a display panel of the display device; During the blanking period, the clock embedded data signal including the training samples is provided to the data driver by using the controller; and by using the data driver, a training operation for the internal clock signal is performed by using the training samples, wherein, during the blanking period, the training samples include a first training clock signal modulated in a first modulation period during a first time period and include a second training clock signal modulated in a second modulation period different from the first modulation period after the first time period, wherein, the first modulation period corresponds to three or four times the clock period of the internal clock signal, and wherein, the second modulation period corresponds to twice the clock period of the internal clock signal.

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