Display device

Abstract

A display apparatus is provided, including a display panel including a plurality of pixels and a power line and displaying an image in a normal mode or a power saving mode, a data driver providing a data signal to the plurality of pixels, and a power supply supplying a source driving voltage to the data driver and a first power voltage to the power line in the normal mode. The data driver supplies a first auxiliary power voltage to the power line in the power saving mode, and the power supply outputs the first power voltage by reducing a voltage level of the first power voltage to a first power saving voltage level in a vertical blanking period in which the plurality of pixels do not display the image during a first switching period when the normal mode is changed to the power saving mode.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0027302, filed on March 4, 2020, the contents of which are incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The disclosure relates to a display apparatus. BACKGROUND

[0003] The driving frequency of pixels of a display apparatus can vary according to a display mode. For example, in a normal image display mode (normal mode), the pixels can be driven at a relatively high frequency. Also, in a standby mode (power saving mode) in which only minimum information (e.g., time) is displayed, the pixels can be driven at a relatively low frequency.

[0004] Various solutions are being researched to reduce power consumption of a display apparatus when driving pixels of the display apparatus at a low frequency. However, when such a solution is applied, a side effect in which luminance deviation due to rapid voltage or current change is recognized by a user can occur in the process of changing the driving frequency. SUMMARY

[0005] It is a feature and / or advantage of the disclosure to provide a display apparatus that minimizes luminance deviation that can occur at the time of display mode switching.

[0006] In addition, it is another feature and / or advantage of the disclosure to provide a display apparatus that can further reduce power consumption in a low power display mode.

[0007] The features and / or advantages of the disclosure are not limited to the above-described features and / or advantages, and other technical features and / or advantages that are not described will be clearly understood by those skilled in the art from the following description.

[0008] A display apparatus according to an embodiment of the disclosure includes a display panel including a plurality of pixels and a power line, and displaying an image in a normal mode or a power saving mode; a data driver providing a data signal to the plurality of pixels; and a power supply supplying a source driving voltage to the data driver and a first power voltage to the power line in the normal mode. The data driver supplies a first auxiliary power voltage to the power line in the power saving mode, the power supply outputs the first power voltage by reducing a voltage level of the first power voltage to a first power saving voltage level in a vertical blanking period of a first switching period in which the plurality of pixels do not display the image, and the first switching period is a transition period from the normal mode to the power saving mode.

[0009] The power supply can include a first converter generating a first power voltage, the first converter can include a switching unit including a first inductor and first and second transistors, and connected between a first input terminal to which an external input voltage is applied and a first output terminal from which the first power voltage is output, and a discharge circuit connected between the first output terminal and a ground, and including a variable resistor and a discharge transistor, and the first converter can alternately turn on the first and second transistors to output the first power voltage.

[0010] The discharge transistor can be turned on in response to a discharge control signal provided in a vertical blanking period, and the first converter can decrease a voltage level of the first power voltage to a first power saving voltage level after the discharge control signal is provided.

[0011] The power supply can include a second converter generating a source driving voltage, the second converter can include a second inductor connected between a second input terminal to which an external input voltage is applied and a node, a third transistor connected between the node and a ground, and turned on in response to a first control signal, a fourth transistor connected between a second output terminal from which the source driving voltage is output and the node, and turned on in response to a second control signal, and a switching controller generating a switching control signal including the first and second control signals, and a first period in which the switching control signal is provided in a normal mode can be different from a second period in which the switching control signal is provided in a power saving mode.

[0012] The second period can be set to be longer than the first period.

[0013] In the power saving mode, when a ripple voltage of the source driving voltage is equal to or less than a first set value, the switching controller can turn on the third transistor or the fourth transistor, and when the ripple voltage of the source driving voltage is equal to or greater than a second set value, the switching controller can turn off the third transistor or the fourth transistor.

[0014] The display panel can display a normal image in a normal mode, and display a power saving image having a load smaller than that of the normal image in a power saving mode, the plurality of pixels can display the normal image at a first driving frequency in the normal mode, and the plurality of pixels can display the power saving image at a second driving frequency smaller than the first driving frequency in the power saving mode.

[0015] The display apparatus can further include a gate driver providing a gate signal to the plurality of pixels, the data driver can generate a first auxiliary power voltage and a gate driving voltage based on the source driving voltage, and the gate driver can generate the gate signal based on the gate driving voltage.

[0016] When switching from the normal mode to the power saving mode, the power supply can output the source driving voltage by reducing a voltage level of the source driving voltage to a second power saving voltage level during a first period, the data driver can output the gate driving voltage by reducing a voltage level of the gate driving voltage to a third power saving voltage level during a second period shorter than the first period, and a difference between the voltage level of the source driving voltage and the voltage level of the gate driving voltage can maintain a preset reference value or more.

[0017] The voltage level of the source driving voltage can be gradually reduced in a stepwise manner during the first period.

[0018] When the source driving voltage and the gate driving voltage are reduced, a slew rate of the source driving voltage can be smaller than a slew rate of the gate driving voltage.

[0019] The power supply can output the source driving voltage by reducing a voltage level of the source driving voltage in the power saving mode after the first switching period, and the data driver can output the gate driving voltage by reducing a voltage level of the gate driving voltage in the first switching period.

[0020] The power supply can reduce the voltage level of the source driving voltage in a next frame after the voltage level of the gate driving voltage is reduced.

[0021] The power supply can increase the voltage level of the source driving voltage in the power saving mode in response to a mode control signal, and the data driver can increase the voltage level of the gate driving voltage in a second switching period in which the normal mode is changed to the power saving mode.

[0022] The data driver can provide a black image data signal to the plurality of pixels in the first switching period.

[0023] A display apparatus according to another embodiment disclosed includes a display panel including a plurality of pixels and a power line and displaying an image in a normal mode or a power saving mode, a data driver providing a data signal to the plurality of pixels, and a power supply supplying a source driving voltage to the data driver and a first power voltage to the power line in the normal mode. The data driver generates a first auxiliary power voltage and a first gamma voltage based on an external input voltage and the source driving voltage, the data driver supplies the first auxiliary power voltage to the power line in the power saving mode, the data driver outputs the first gamma voltage by reducing a voltage level of the first gamma voltage in a period in which the normal mode is changed to the power saving mode, the power supply outputs the first power voltage by reducing a voltage level of the first power voltage, and a difference between the voltage level of the first power voltage and the voltage level of the first gamma voltage is constant in the normal mode and the power saving mode.

[0024] The data driver may include: a power converter that generates a first auxiliary power voltage and the first gamma voltage using a source driving voltage; a gray voltage generator that generates a gray voltage based on the first gamma voltage; and a data signal generator that generates a data signal based on the gray voltage and the source driving voltage.

[0025] The data driver may further include a gap controller generating a second gamma voltage whose voltage level is adjusted based on the first gamma voltage, the first power voltage, and the reference power voltage, and the gray voltage generator may generate a gray voltage based on the second gamma voltage.

[0026] The gap controller may include: a first driver that compares the first gamma voltage with the first power voltage to generate a reference voltage difference; a second driver that sums the reference voltage difference with the reference power voltage to generate a reference gamma voltage; and a third driver that outputs a second gamma voltage based on the reference gamma voltage.

[0027] The third driver may include: an amplifier, including a first input terminal connected to the second driver to receive a reference gamma voltage, a second input terminal to receive a feedback voltage of the second gamma voltage, and an output terminal to output the second gamma voltage; and a voltage divider, connected to the output terminal and the second input terminal, and providing a feedback voltage of the second gamma voltage to the second input terminal of the amplifier.

[0028] Specific details of other embodiments are included in the detailed description and accompanying drawings.

[0029] The display device according to the disclosed embodiment can minimize power consumption by applying first and second power voltages to the display panel through a power supply in a normal mode and supplying first and second auxiliary power voltages through a data driver in a power saving mode.

[0030] In addition, the display device according to the disclosed embodiment can minimize power consumption by reducing the voltage levels (or absolute values ​​of the voltage levels) of voltages generated by the power supply and data drivers in the power saving mode.

[0031] In addition, the display device according to the disclosed embodiment can prevent the brightness difference of the displayed image between the normal mode and the power saving mode caused by the change in the power voltage level from being recognized by the user by quickly reducing the voltage level of the first power voltage to the first power saving voltage level during the vertical blank period when the image is not displayed.

[0032] In addition, the display device according to the disclosed embodiments can maintain the difference between the voltage level of the source driving voltage and the voltage level of the first gate driving voltage at a preset reference value or more and generate and supply the voltage smoothly by sequentially reducing the voltage level of the source driving voltage for a time period longer than a time period of the voltage level of the first gate driving voltage.

[0033] In addition, the display device according to the disclosed embodiments can minimize power consumption by reducing the number of switching per unit time of the transistor of the power supply in the power saving mode.

[0034] The effects according to the embodiments are not limited by the details of the examples above, and more various effects are included in the present specification. BRIEF DESCRIPTION OF DRAWINGS

[0035] The disclosed embodiments will become more fully understood from the detailed description and accompanying drawings, wherein:

[0036] Figure 1 is a diagram illustrating a display device according to the disclosed embodiments;

[0037] Figure 2 is a diagram illustrating an example of a data driver included in the display device of Figure 1 ;

[0038] Figure 3 is a diagram illustrating an example of a power supply included in the display device of Figure 1 ;

[0039] Figure 4A is a circuit diagram illustrating an example of a first converter included in the power supply of Figure 3 ;

[0040] Figure 4B is a circuit diagram illustrating an example of a third converter included in the power supply of Figure 3 ;

[0041] Figure 5 is a waveform diagram illustrating an example of an operation of the display device of Figure 1 ;

[0042] Figure 6 is an enlarged waveform diagram of a Q1 region of Figure 5 and is a diagram for describing a change in the first power voltage during a vertical blanking period;

[0043] Figure 7 is an enlarged waveform diagram of a Q2 region of Figure 5 and is a diagram for describing changes in the source driving voltage and the first gate driving voltage;

[0044] Figure 8is a diagram for describing a change of a ripple voltage of a source driving voltage and a switching control signal in a power saving mode;

[0045] Figure 9 is a waveform diagram illustrating an operation of a display apparatus including Figure 1

[0046] Figure 10 is a diagram illustrating another example of a data driver included in the display apparatus of Figure 1

[0047] Figure 11 is a diagram illustrating an example of a gap controller included in the data driver of Figure 10

[0048] Figure 12 is a waveform diagram illustrating an operation of a display apparatus including Figure 10 DETAILED DESCRIPTION

[0049] The advantages and features of the disclosure and a method of achieving them will become apparent by referring to the following detailed description in conjunction with the accompanying drawings, which is presented as examples. However, the disclosure according to the present disclosure is not limited to the following disclosed examples and can be implemented in various different forms. The present embodiments are provided so that the disclosure will be thorough and complete, and fully convey the scope of the disclosure to those skilled in the art to which the disclosure pertains. The disclosure is limited only by the scope of the claims. Figure 1 Throughout the specification, the same reference numerals designate the same components. Shapes, sizes, ratios, angles, and numbers disclosed in the drawings for describing the embodiments are exemplary, and thus the disclosure according to the present disclosure is not limited thereto.

[0050]

[0051] ​​​​​Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, within the disclosed technical spirit, the first component mentioned below can be a second component. Unless the context clearly indicates otherwise, singular expressions include plural expressions. The terms used here are only for the purpose of describing specific embodiments, rather than intended to limit. As used herein, unless the context clearly indicates otherwise, the singular forms "one", "one (kind / person)" and "said / the" are also intended to include plural forms containing "at least one". "At least one" will not be interpreted as being limited to "one" or "one (kind / person)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that when the terms "comprises," "includes," and / or variations thereof are used in this specification, it indicates the presence of the stated features, regions, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0052] Each of the features of the various disclosed embodiments can be combined or combined with each other in part or in whole, and various close connections and drives are possible in technology. Each embodiment can be implemented independently of each other, and their associations can be implemented together.

[0053] Hereinafter, disclosed embodiments will be described in detail with reference to the accompanying drawings.

[0054] Figure 1 is a diagram illustrating a display device according to a disclosed embodiment.

[0055] Reference Figure 1 , the display device 10 includes a display panel 100 , a gate driver 200 , a data driver 300 , a timing controller 400 and a power supply 500 .

[0056] The display panel 100 may display an image and may include gate lines SL1 to SLn (n is a natural number equal to or greater than 2), data lines DL1 to DLm (m is a natural number equal to or greater than 2), power lines PL, and pixels PX.

[0057] The pixels PX may be placed in areas divided by the gate lines SL1 to SLn and the data lines DL1 to DLm.

[0058] The pixel PX can include a light emitting element, a switching transistor, a driving transistor, and a storage capacitor. The light emitting element can be electrically connected between a line supplying a first power voltage VDD and a line supplying a second power voltage VSS. Here, the first power voltage VDD and the second power voltage VSS can be a high potential voltage and a low potential voltage required for driving the pixel PX, respectively. The first power voltage VDD can have a voltage level greater than that of the second power voltage VSS, and can be supplied through a power line PL. The light emitting element can be an organic light emitting element or an inorganic light emitting element. The switching transistor can transfer a data signal supplied through one of data lines DL1 to DLm to the storage capacitor in response to a gate signal supplied through one of gate lines SL1 to SLn. The storage capacitor can store the data signal. The driving transistor can be connected between the power line PL supplying the first power voltage VDD and the light emitting element, and can transfer a driving current corresponding to the data signal to the light emitting element from the power line PL supplying the first power voltage VDD.

[0059] The display panel 100 is described as an organic light emitting display panel or an inorganic light emitting display panel, but the display panel 100 according to the present application is not limited thereto. For example, the display panel 100 can be implemented as a liquid crystal display panel, and in another embodiment, can control an emission amount of light provided from a light source.

[0060] In an embodiment, the display panel 100 can display an image in a normal mode (or a first mode) or a power saving mode (or a second mode).

[0061] The display panel 100 can display a normal image (e.g., a video) in the normal mode, and display a power saving image (e.g., a less loaded image such as a clock) in the power saving mode. Since the power saving image can require relatively less power than the normal image, power consumption in the power saving mode can be minimized.

[0062] The power saving mode can minimize power consumption by limiting a maximum luminance of the display panel 100 to a preset luminance or less. For example, the power saving mode can be an always-on display ("AOD") mode that always displays simple display information, and a predetermined display mode that displays a screen with an ultra-low luminance in a dark environment, etc.

[0063] In the normal mode and the power saving mode, the pixels PX of the display panel 100 can display an image at different driving frequencies. As an embodiment, in the normal mode, the pixels PX can display a normal image at a first driving frequency, and in the power saving mode, the pixels PX can display a power saving image at a second driving frequency smaller than the first driving frequency. The first driving frequency can be equal to or greater than 20 Hz (e.g., 60 Hz), and the second driving frequency can be less than 20 Hz (e.g., 1 Hz).

[0064] In the power saving mode, the operation of some components included in the display device 10 can be completely or partially changed compared to the normal mode. Accordingly, unnecessary power consumption can be reduced by cutting off or minimizing the power supply of various functional blocks not used in the power saving mode. The normal mode and the power saving mode can be determined by a mode selection signal provided from the outside, or can be determined by the timing controller 400 based on an image provided from the outside.

[0065] The gate driver 200 can receive a gate control signal GCS from the timing controller 400, generate a gate signal based on the gate control signal GCS, and sequentially provide the gate signal to the gate lines SL1 to SLn.

[0066] The data driver 300 can receive a data control signal DCS and image data D-RGB from the timing controller 400, generate a data signal corresponding to the image data D-RGB, and provide the data signal to the data lines DL1 to DLm.

[0067] In addition, the data driver 300 can receive a source driving voltage VLIN from the power supply 500, generate a first gate driving voltage VGH and a second gate driving voltage VGL based on the source driving voltage VLIN and a first external input voltage VCI provided from the outside, and provide the first gate driving voltage VGH and the second gate driving voltage VGL to the gate driver 200.

[0068] One of the first gate driving voltage VGH and the second gate driving voltage VGL can have an on voltage level to turn on a transistor included in the data driver 300 and the gate driver 200, and the other of the first gate driving voltage VGH and the second gate driving voltage VGL can have an off voltage level to turn off the transistor included in the data driver 300 and the gate driver 200.

[0069] In an embodiment, the data driver 300 can generate a first auxiliary power voltage U_VDD and a second auxiliary power voltage U_VSS based on the first external input voltage VCI and the source driving voltage VLIN. Here, the first auxiliary power voltage U_VDD can have a voltage level equal to or similar to a voltage level of the first power voltage VDD, and the second auxiliary power voltage U_VSS can have a voltage level equal to or similar to a voltage level of the second power voltage VSS.

[0070] For example, the data driver 300 can generate the first gate driving voltage VGH, the second gate driving voltage VGL, the first auxiliary power voltage U_VDD, and the second auxiliary power voltage U_VSS through a power converter including a boost circuit and a regulation circuit.

[0071] In addition, the data driver 300 can supply the generated first auxiliary power voltage U_VDD and the second auxiliary power voltage U_VSS to the display panel 100 in the power saving mode. The first auxiliary power voltage U_VDD can be supplied to the pixels PX through the power lines PL.

[0072] The data driver 300 can block the connection to the display panel 100 or the current moving path from the display panel 100 in the normal mode. For example, in the normal mode, the data driver 300 can increase the impedance of the output terminal outputting the first auxiliary power voltage U_VDD and the second auxiliary power voltage U_VSS so as to block the transmission of the first auxiliary power voltage U_VDD and the second auxiliary power voltage U_VSS to the display panel 100.

[0073] The timing controller 400 can control the gate driver 200, the data driver 300, and the power supply 500. The timing controller 400 can receive a control signal (for example, a control signal including a clock signal) from the outside, and generate a gate control signal GCS and a data control signal DCS based on the control signal from the outside. In addition, the timing controller 400 can generate a power control signal CS, and supply the power control signal CS to the power supply 500. In this case, the power supply 500 can determine a driving method (or a voltage control method) based on the power control signal CS. As another embodiment, the timing controller 400 can also supply the power control signal CS to the data driver 300. In this case, the data driver 300 can determine a driving method (or a voltage control method) based on the power control signal CS.

[0074] The timing controller 400 can rearrange input data (or original image data) supplied from the outside (for example, a graphic processor) to generate image data D-RGB, and supply the image data D-RGB to the data driver 300.

[0075] The power supply 500 can generate a first power voltage VDD, a second power voltage VSS, and a source driving voltage VLIN based on a second external input voltage VBAT supplied from the outside power. The power supply 500 can supply the source driving voltage VLIN to the data driver 300. The power supply 500 can supply the first power voltage VDD and the second power voltage VSS to the display panel 100 in the normal mode. The first power voltage VDD can be supplied to the pixels PX through the power lines PL. Similarly to the data driver 300, the power supply 500 can cut off the connection to the display panel 100 in the power saving mode, and stop supplying the first power voltage VDD and the second power voltage VSS to the display panel 100 in the power saving mode.

[0076] In an embodiment, the power supply 500 can be driven differently in the normal mode and the power saving mode. For example, a voltage level of a voltage generated by the power supply 500 can be changed in the power saving mode compared to the normal mode. The power supply 500 can reduce a voltage level of the first power voltage VDD to a first power saving voltage level in the power saving mode. Also, the power supply 500 can reduce a voltage level of the source driving voltage VLIN to a second power saving voltage level in the power saving mode.

[0077] Similarly to the voltage generated by the power supply 500, a voltage level of a voltage generated by the data driver 300 can also be changed in the power saving mode compared to the normal mode. For example, the data driver 300 can reduce a voltage level of the first gate driving voltage VGH to a third power saving voltage level in the power saving mode.

[0078] The power supply 500 and the data driver 300 can minimize power consumption of the display device 10 by reducing the voltage level (or the absolute value of the voltage level) of each of the generated voltages in the power saving mode.

[0079] The power supply 500 can rapidly change the voltage level of the first power voltage VDD in a black period (or a vertical blanking period) in which all pixels PX of the display panel 100 do not display an image. Accordingly, when switching from the normal mode to the power saving mode during the vertical blanking period, the display device 10 can prevent a luminance difference of an image between the normal mode and the power saving mode due to the reduction of the first power voltage VDD from being recognized by a user.

[0080] As described with reference to Figure 2 The display device 10 can reduce or minimize power consumption by applying the first power voltage VDD and the second power voltage VSS to the display panel 100 through the power supply 500 in the normal mode and supplying the first auxiliary power voltage U_VDD and the second auxiliary power voltage U_VSS through the data driver 300 in the power saving mode.

[0081] Also, the display device 10 can reduce or minimize power consumption by reducing the voltage level (or the absolute value of the voltage level) of each of the voltages generated by the power supply 500 and the data driver 300 in the power saving mode.

[0082] Figure 1 is a diagram illustrating an example of a data driver included in a display device according to an embodiment of the disclosure. Figure 3

[0083] The data driver 300 according to an embodiment of the disclosure can include a power converter 310, a gray voltage generator 320, and a data signal generator 330.

[0084] ​The power converter 310 can receive the source driving voltage VLIN and convert the source driving voltage VLIN to provide the first gate driving voltage VGH and the second gate driving voltage VGL for control of the pixels PX to the output terminal. As described above, the first gate driving voltage VGH and the second gate driving voltage VGL can be provided to the gate driver 200.

[0085] As an example, when the display device 10 operates in the power saving mode, the power converter 310 can receive the source driving voltage VLIN and convert the source driving voltage VLIN to generate the first auxiliary power voltage U_VDD and the second auxiliary power voltage U_VSS. The first auxiliary power voltage U_VDD and the second auxiliary power voltage U_VSS can be provided to the display panel 100.

[0086] The power converter 310 can receive the source driving voltage VLIN and the first external input voltage VCI and provide a gamma voltage VREG for control of the pixels PX to the output terminal based on the source driving voltage VLIN and the first external input voltage VCI. The gamma voltage VREG can be provided to the grayscale voltage generator 320.

[0087] Here, the size (or voltage level) of the gamma voltage VREG can vary according to the display mode (e.g., the normal mode and the power saving mode). For example, the voltage level of the gamma voltage VREG of the normal mode can be greater than the voltage level of the gamma voltage VREG of the power saving mode.

[0088] The power converter 310 can receive the source driving voltage VLIN and the first external input voltage VCI and provide a reference voltage VREF for control of the pixels PX to the output terminal based on the source driving voltage VLIN and the first external input voltage VCI. The reference voltage VREF can be provided to the grayscale voltage generator 320.

[0089] Here, the size (or voltage level) of the reference voltage VREF can vary according to the display mode (e.g., the normal mode and the power saving mode).

[0090] The grayscale voltage generator 320 can generate grayscale voltages GV using the gamma voltage VREG and the reference voltage VREF. Since the grayscale voltages GV generated by the grayscale voltage generator 320 are used for display of an image frame, it is necessary to provide grayscale voltages GV corresponding to colors of the pixels PX. Accordingly, the grayscale voltage generator 320 can include a first color grayscale voltage generator, a second color grayscale voltage generator, and a third color grayscale voltage generator. Here, for example, the first color can be red, the second color can be green, and the third color can be blue.

[0091] The data control signal DCS received from the timing controller 400 can be provided to the data signal generator 330. The data control signal DCS can include a source start pulse SSP, a source shift clock SSC, a grayscale value GD, a source output enable signal SOE, etc.

[0092] The data signal generator 330 can include a shift register 331, a sampling latch 332, a holding latch 333, a digital-to-analog converter 334, and an output buffer 335.

[0093] The shift register 331 can sequentially generate sampling signals while shifting the source start pulse SSP at each period of the source shift clock SSC. The number of the sampling signals can correspond to the number of the data lines DL1 to DLm. For example, the number of the sampling signals can be the same as the number of the data lines DL1 to DLm. For another example, when the display device 10 further includes a demultiplexer between the data driver 300 and the data lines DL1 to DLm, the number of the sampling signals can be less than the number of the data lines DL1 to DLm. For convenience of description, it is assumed that there is no demultiplexer in the following description.

[0094] The sampling latch 332 can include a number of sampling latch units corresponding to the number of the data lines DL1 to DLm, and sequentially receive the grayscale values GD for an image frame from the timing controller 400. The sampling latch 332 can store the grayscale values GD sequentially provided from the timing controller 400 in corresponding sampling latch units in response to the sampling signals sequentially supplied from the shift register 331.

[0095] The holding latch 333 can include a number of holding latch units corresponding to the number of the data lines DL1 to DLm. When the source output enable signal SOE is input, the holding latch 333 can store the grayscale values GD stored in the sampling latch units in the holding latch units.

[0096] The digital-to-analog converter 334 can include a number of digital-to-analog conversion units corresponding to the number of the data lines DL1 to DLm. For example, the number of the digital-to-analog conversion units can be the same as the number of the data lines DL1 to DLm. Each of the digital-to-analog conversion units can apply a grayscale voltage GV corresponding to the grayscale value GD stored in the corresponding holding latch 333 to the corresponding data line.

[0097] The output buffer 335 can include buffer units. For example, each of the buffer units can be an operational amplifier. Each of the buffer units can be configured in the form of a voltage follower to apply the output of the digital-to-analog conversion unit to the corresponding data line. For example, the inverting terminal of each of the buffer units can be connected with its output terminal, and the non-inverting terminal can be connected with the output terminal of the digital-to-analog conversion unit. The output of the buffer unit can be a data voltage.

[0098] For example, the buffer units can receive a buffer power voltage and a ground power voltage. At this time, the buffer power voltage can be the source driving voltage VLIN. The buffer power voltage can determine the upper limit of the output voltage (i.e., the data voltage) of the buffer units. In addition, the ground power voltage can determine the lower limit of the output voltage of the buffer units.

[0099] Figure 1 is a diagram illustrating an example of a power supply included in a display device of Figure 3 .

[0100] Referring to Figure 4A , the power supply 500 can convert the second external input voltage VBAT into a first power voltage VDD, a second power voltage VSS, and a source driving voltage VLIN, and output the first power voltage VDD to the display panel 100, the second power voltage VSS to the display panel 100, and the source driving voltage VLIN to the data driver 300. The power supply 500 can be controlled by a power control signal CS. The power supply 500 can include a first converter 510, a second converter 520, and a third converter 530.

[0101] The first converter 510 can convert the voltage of the second external input voltage VBAT into the first power voltage VDD, the second converter 520 can convert the voltage of the second external input voltage VBAT into the second power voltage VSS, and the third converter 530 can convert the voltage of the second external input voltage VBAT into the source driving voltage VLIN. Here, the first converter 510 and the third converter 530 can be boost converters, and the second converter 520 can be an inverting buck converter. The first converter 510 and the second converter 520 can operate in a normal mode, and the third converter 530 can operate in both the normal mode and a power saving mode.

[0102] As described above, the power supply 500 includes the first converter 510, the second converter 520, and the third converter 530. The first converter 510, the second converter 520, and the third converter 530 are driven in the normal mode, but only the third converter 530 is driven in the power saving mode. Accordingly, power consumption can be reduced in the power saving mode.

[0103] A detailed description of the power supply 500 will be described later with reference toFigure 4B and Figure 4A More specific configurations and operations of the first converter 510 and the third converter 530 are described.

[0104] Figure 3 is a circuit diagram illustrating an example of the first converter included in Figure 4A a power supply of the electronic device.

[0105] Referring to Figure 3 , the first converter 510 can include a first switching controller 511, a first switching unit 512, and a discharging unit 513 (or a discharging circuit).

[0106] The first converter 510 can convert a second external input voltage VBAT to output a first power voltage VDD.

[0107] The first switching controller 511 can generate switching control signals including a first control signal G1 and a second control signal G2, and provide the switching control signals to the first switching unit 512. Although not shown in the drawings, the first control signal G1 and the second control signal G2 can be signals controlled by a power control signal CS of the electronic device. Figure 3

[0108] The first switching unit 512 can include a first inductor L1, a first transistor M1, and a second transistor M2.

[0109] The first inductor L1 can be connected between a first node N1 and a first input terminal to which the second external input voltage VBAT is applied. The first power voltage VDD can be controlled based on a first inductor current I_IND1 flowing through the first inductor L1.

[0110] The first transistor M1 can be connected between the first node N1 and a ground (or a ground voltage). The first transistor M1 can be turned on by receiving the first control signal G1 from the first switching controller 511, and control the first inductor current I_IND1 flowing through the first inductor L1.

[0111] The second transistor M2 can be connected between the first node N1 and a first output terminal from which the first power voltage VDD is output. The second transistor M2 can be turned on alternately with the first transistor M1. Thus, after the first transistor M1 is turned on and an electromotive force is generated in the first inductor L1, the second transistor M2 can be turned on so that a voltage of the first node N1 is converted into the first power voltage VDD. The second transistor M2 can be turned on by receiving the second control signal G2 from the first switching controller 511.

[0112] ​The discharge unit 513 can include a discharge transistor M_FD and a variable resistor R_FD. The discharge transistor M_FD and the variable resistor R_FD can be connected in series with each other between the first output terminal and the ground. The first converter 510 can further include a capacitor C1 connected between the first output terminal and the ground.

[0113] The discharge transistor M_FD can be turned on by receiving the discharge control signal FD during a switching period in which the display mode is switched from the normal mode to the power saving mode. In particular, the discharge control signal FD can be provided in a vertical blanking period in which all pixels PX of the display panel 100 do not display an image.

[0114] Here, the discharge control signal FD can be included in the power control signal CS of Figure 4B and is provided from the timing controller 400. For example, the discharge transistor M_FD can be turned on in response to the discharge control signal FD of the turned-on voltage level and be turned off in response to the discharge control signal FD of the turned-off voltage level.

[0115] The first converter 510 can turn on the discharge transistor M_FD in the switching period, in particular, the vertical blanking period, to rapidly decrease the voltage level of the first power voltage VDD to the first power saving voltage level before entering the power saving mode. That is, since the voltage level of the first power voltage VDD can be changed before displaying the power saving image, it is possible to prevent a user from recognizing a difference in brightness of the display image between the normal mode and the power saving mode due to the change in the voltage level of the first power voltage VDD.

[0116] Figure 3 is a circuit diagram illustrating an example of a third converter included in a power supply of Figure 4B .

[0117] Referring to Figure 3 , the third converter 530 can include a second switching controller 531 and a second switching unit 532.

[0118] The third converter 530 can convert the second external input voltage VBAT to output the source driving voltage VLIN.

[0119] The second switching controller 531 can generate a switching control signal including a third control signal G3 and a fourth control signal G4 and provide the switching control signal to the second switching unit 532. Although not illustrated in the drawings, the third control signal G3 and the fourth control signal G4 can be signals controlled by the power control signal CS of Figure 3 .

[0120] The second switching unit 532 can include a second inductor L2, a third transistor M3, and a fourth transistor M4.

[0121] The second inductor L2 can be connected between the second node N2 and a second input terminal to which the second external input voltage VBAT is applied. The source driving voltage VLIN can be controlled based on a second inductor current I_IND2 flowing through the second inductor L2.

[0122] The third transistor M3 can be connected between the second node N2 and a ground (or a ground voltage). The third transistor M3 can be turned on by receiving a third control signal G3 from the second switching controller 531 and control the second inductor current I_IND2 flowing through the second inductor L2.

[0123] The fourth transistor M4 can be connected between the second node N2 and a second output terminal from which the source driving voltage VLIN is output. The fourth transistor M4 can be turned on alternately with the third transistor M3. Thus, after the third transistor M3 is turned on and an electromotive force is generated in the second inductor L2, the fourth transistor M4 can be turned on so that the voltage of the second node N2 is converted into the source driving voltage VLIN. The fourth transistor M4 can be turned on by receiving a fourth control signal G4 from the second switching controller 531.

[0124] The third converter 530 can change the turn-on periods of the third transistor M3 and the fourth transistor M4 according to a display mode (e.g., a power saving mode and a normal mode). For example, the second switching controller 531 of the third converter 530 can receive a mode signal MCS, and the provision periods of the third control signal G3 and the fourth control signal G4 can be controlled by the mode signal MCS. Here, the mode signal MCS can include data for a display mode of the display device 10, and the mode signal MCS can be included in the power control signal CS of Figures 5 to 8 and provided from the timing controller 400. The third converter 530 can further include a capacitor C2 connected between the second output terminal and the ground.

[0125] When the third transistor M3 and the fourth transistor M4 are alternately operated, power loss can occur due to internal configurations (e.g., the second inductor L2). The third converter 530 can increase the turn-on periods of the third transistor M3 and the fourth transistor M4 in the power saving mode to be longer than those in the normal mode. That is, in the power saving mode, since the third transistor M3 and the fourth transistor M4 are turned on less frequently per unit time than in the normal mode, power loss of the display device 10 (or the power supply 500) according to the switching of the third transistor M3 and the fourth transistor M4 can be minimized.

[0126] A detailed description of the third converter 530 will be given later with reference to Figure 5A detailed description is given of a specific control method of the on-periods of the third transistor M3 and the fourth transistor M4 in the power saving mode.

[0127] Figure 1 is a waveform diagram showing an example of the operation of the display device of Figure 6 Figure 5 is an enlarged waveform diagram of the Q1 region of Figure 7 and is a diagram for describing the change of the first power voltage during the vertical blanking period. Figure 5 is an enlarged waveform diagram of the Q2 region of Figure 8 and is a diagram for describing the changes of the source driving voltage and the first gate driving voltage. Figures 1 to 5 is a diagram for describing the changes of the source driving voltage and the ripple voltage of the switching control signal in the power saving mode.

[0128] Referring to Figure 5 , the display panel 100 can display a normal image in a normal mode (or a first mode) MD1 and a power saving image whose load is small in a power saving mode (or a second mode) MD2.

[0129] The mode control signal MD_SEL can be normally in the disabled state in the normal mode MD1 and can be normally in the enabled state in the power saving mode MD2.

[0130] When the mode control signal MD_SEL becomes in the enabled state in the normal mode MD1, the mode of the display panel 100 can be switched to the power saving mode MD2 after a first switching period TP1 (i.e., a transition period). In the power saving mode MD2, the mode control signal MD_SEL can be maintained in the enabled state. Thereafter, when the mode control signal MD_SEL becomes in the disabled state in the power saving mode MD2, the display panel 100 can be switched to the normal mode MD1 after a second switching period TP2 (i.e., a transition period).

[0131] According to an embodiment, the display panel 100 can display a black image in the first switching period TP1 and the second switching period TP2. That is, a black image data signal can be provided to the pixels PX of the display panel 100 in the first switching period TP1 and the second switching period TP2.

[0132] ​The vertical synchronization signal V_SYNC can be a signal indicating the start of an image frame displayed by the display panel 100. The vertical blanking signal TE can be set to overlap the vertical synchronization signal V_SYNC. The vertical blanking signal TE can be a signal defining a vertical blanking period. Here, the vertical blanking period can be a period in which the pixels PX of the display panel 100 do not display an image. For example, the vertical blanking signal TE can be a signal defining a back dummy period of a previous image frame and a front dummy period of a current image frame. When the vertical blanking signal TE is in a high (or enabled) state, all of the pixels PX of the display panel 100 can not display a display image (e.g., a normal image and a power saving image).

[0133] The power supply 500 and the data driver 300 of the display apparatus 10 can generate various voltages to drive the display panel 100. The power supply 500 can generate a source driving voltage VLIN, a first power voltage VDD, and a second power voltage VSS, and the data driver 300 can generate a first gate driving voltage VGH, a second gate driving voltage VGL, and a gamma voltage VREG. Here, the source driving voltage VLIN, the first gate driving voltage VGH, the gamma voltage VREG, and the first power voltage VDD can be voltages having a positive voltage level, and the second power voltage VSS and the second gate driving voltage VGL can be voltages having a negative voltage level.

[0134] The voltages generated by the power supply 500 and the data driver 300 can have different voltage levels. For example, as shown in FIG. 2, the source driving voltage VLIN can have the largest voltage level, and the first gate driving voltage VGH, the gamma voltage VREG, the first power voltage VDD, the second power voltage VSS, and the second gate driving voltage VGL can have gradually smaller voltage levels. That is, the second gate driving voltage VGL can have the lowest voltage level. Figure 5

[0135] After the mode control signal MD_SEL becomes an enabled state in the normal mode MD1, the first switching period TP1 can start in the next image frame. That is, as shown in FIG. 3, at a first time point t1, the first switching period TP1 can start, and black image data signals can be provided to the pixels PX of the display panel 100. Figure 6

[0136] Thereafter, at a second time point t2 to a third time point t3, the vertical blanking signal TE can become in an enabled state. As described above, when the vertical blanking signal TE becomes in an enabled state (or a high level), all of the pixels PX of the display panel 100 can not display an image. ​​

[0137] Between the second time point t2 and the third time point t3, the power supply 500 and the data driver 300 can change the voltage level of the generated voltage. As an embodiment, the power supply 500 and the data driver 300 can change the voltage level of the generated voltage in response to the power control signal CS.

[0138] The change (e.g., voltage drop) of the first power voltage VDD between the second time point t2 and the third time point t3 can be described with reference to Figure 4A

[0139] In addition, with reference to Figure 6 and Figure 6 , the power supply 500 can reduce the voltage level of the first power voltage VDD in the vertical blank period VBLNK in which the vertical blank signal TE is in the enabled state. That is, the power supply 500 can stop the generation and output of the first power voltage VDD. For example, the power supply 500 can reduce (e.g., drop) the voltage level of the first power voltage VDD from the first reference voltage level V1 to the first power saving voltage level V2.

[0140] During the vertical blank period VBLNK, the discharge control signal FD can be provided to the first converter 510 at a discharge time point tFD after the vertical synchronization signal V_SYNC is provided. As described above, when the discharge control signal FD is input, the discharge transistor M_FD of the first converter 510 can be turned on, and thus the first power voltage VDD can be rapidly discharged. The discharge control signal FD can be enabled during a discharge period TS, which can be within the vertical blank period VBLNK.

[0141] In addition, the data driver 300 can generate and output the first auxiliary power voltage U_VDD in the vertical blank period VBLNK. Since the output of the data driver 300 is relatively small compared to the output of the first converter 510, and the load of the power saving image is relatively small compared to the load of the normal image, even if the first power voltage VDD and the first auxiliary power voltage U_VDD are partially overlapped, the influence of the operation of the data driver 300 on the first converter 510 can be negligible.

[0142] After the third time point t3, the first auxiliary power voltage U_VDD can be provided to the power lines PL of the display panel 100 in the power saving mode MD2. At this time, the voltage level of the first auxiliary power voltage U_VDD can be the first power saving voltage level V2.

[0143] ​As described above, the black image data signal can be provided to the pixels PX of the display panel 100 in the first switching period TP1, but when the black image data signal is sequentially provided to the pixel rows, the black image data signal can be provided to some of the pixels PX and the normal image data signal (e.g., data signal of the normal image or the power saving image) can be simultaneously provided to the other pixels PX.

[0144] When the voltage level of the first power voltage VDD is changed (e.g., decreased) while the normal image data signal is provided to the pixels PX, the driving current amount provided to the light emitting elements of the pixels PX can be changed, and thus a brightness difference can occur in the display image displayed by some of the pixels PX or a display defect (e.g., screen flicker, etc.) can occur.

[0145] As described above with reference to FIGS. 1 to 4, since the power supply 500 changes the voltage level of the first power voltage VDD in the vertical blanking period VBLNK in which all of the pixels PX do not display an image, the brightness difference of the display image between the normal mode and the power saving mode can be prevented from being recognized by a user. Figure 5

[0146] In addition, the power supply 500 reduces the voltage level of the first power voltage VDD from the first reference voltage level V1 to the first power saving voltage level V2 in the power saving mode MD2, thereby minimizing power consumption.

[0147] Again with reference to FIGS. 1 to 4, Figure 7 The voltage level of the other voltages generated by the power supply 500 can be changed between the second time point t2 and the third time point t3. For example, the power supply 500 can reduce the voltage level of the source driving voltage VLIN. In addition, the power supply 500 can increase the voltage level of the second power voltage VSS. As described above, the second power voltage VSS can be a voltage having a negative voltage level, and the power supply 500 can reduce the absolute value of the voltage level of the second power voltage VSS.

[0148] The data driver 300 can reduce the voltage level of the first gate driving voltage VGH and the voltage level of the gamma voltage VREG, and reduce the absolute value of the voltage level of the second gate driving voltage VGL.

[0149] After the third time point t3, the display panel 100 can display the power saving image in the power saving mode MD2. In the power saving mode MD2, the power supply 500 and the data driver 300 can maintain the voltage levels of the first gate driving voltage VGH, the second gate driving voltage VGL, the gamma voltage VREG, the first power voltage VDD, and the second power voltage VSS, the voltage levels of which are changed.

[0150] ​However, the voltage level of the source driving voltage VLIN can be gradually decreased in the power saving mode MD2. The change of the voltage level of the source driving voltage VLIN and the voltage level of the first gate driving voltage VGH can be described with reference to Figure 7

[0151] With further reference to Figure 7 , the power supply 500 can decrease (e.g., ramp down) the voltage level of the source driving voltage VLIN from the second reference voltage level V3 to a second power saving voltage level V4 during the first period P1. The voltage level of the source driving voltage VLIN can be gradually (or sequentially) decreased in a stepwise manner during the first period P1. The data driver 300 can decrease (e.g., ramp down) the voltage level of the first gate driving voltage VGH from the third reference voltage level V5 to a third power saving voltage level V6 during the second period P2.

[0152] The voltage level of the source driving voltage VLIN and the voltage level of the first gate driving voltage VGH can start to decrease at the same time point during the first switching period TP1. The voltage level of the source driving voltage VLIN can be decreased during the first period P1, and the voltage level of the first gate driving voltage VGH can be decreased during a second period P2 that is shorter than the first period P1. However, the timing of the change of the voltage level of the source driving voltage VLIN and the voltage level of the first gate driving voltage VGH according to the present application is not limited thereto. As another embodiment, the voltage level of the source driving voltage VLIN can start to decrease at a time point earlier than the time point at which the voltage level of the first gate driving voltage VGH starts to decrease. Even in this case, the voltage level of the source driving voltage VLIN can be decreased during a period that is longer than the period of the decrease of the voltage level of the first gate driving voltage VGH.

[0153] The voltage level of the first gate driving voltage VGH can be changed within the first switching period TP1 and can be maintained thereafter, but the voltage level of the source driving voltage VLIN can be changed during the first switching period TP1 and some periods of the power saving mode MD2. Since the source driving voltage VLIN is not a voltage directly provided to the pixels PX of the display panel 100, even if the voltage level of the source driving voltage VLIN is changed during the power saving mode MD2 in which the display panel 100 displays a power saving image, a brightness difference can not occur or a display defect can not occur.

[0154] ​The voltage level difference of the source driving voltage VLIN (e.g., the difference between the second reference voltage level V3 and the second power saving voltage level V4) can be equal to or greater than the voltage level difference of the first gate driving voltage VGH (e.g., the difference between the third reference voltage level V5 and the third power saving voltage level V6), but the present application is not limited thereto. In another embodiment, the voltage level difference of the source driving voltage VLIN can be less than the voltage level difference of the first gate driving voltage VGH. As an embodiment, the voltage level of the source driving voltage VLIN after the voltage level change (e.g., the second power saving voltage level V4) can be less than the voltage level of the first gate driving voltage VGH (e.g., the third reference voltage level V5), but the present application is not limited thereto.

[0155] When the voltage level of the source driving voltage VLIN and the voltage level of the first gate driving voltage VGH decrease, the slew rate of the source driving voltage VLIN can be less than the slew rate of the first gate driving voltage VGH. Here, the slew rate of the source driving voltage VLIN can be proportional to a value obtained by dividing the voltage level difference of the source driving voltage VLIN (e.g., the difference between the second reference voltage level V3 and the second power saving voltage level V4) by the voltage level change period (e.g., the first period P1), and the slew rate of the first gate driving voltage VGH can be proportional to a value obtained by dividing the voltage level difference of the first gate driving voltage VGH (e.g., the difference between the third reference voltage level V5 and the third power saving voltage level V6) by the voltage level change period (e.g., the second period P2).

[0156] That is, unlike the present embodiment, when the voltage level of the source driving voltage VLIN rapidly decreases in the same period as the voltage level of the first gate driving voltage VGH, it can not be possible to maintain a predetermined gap between the voltage level of the source driving voltage VLIN and the voltage level of the first gate driving voltage VGH, or a voltage inversion in which the voltage level of the first gate driving voltage VGH is higher than the voltage level of the source driving voltage VLIN can occur. In this case, voltage generation and supply of the power supply 500 and the data driver 300 can become unstable, and a display defect problem can occur.

[0157] As described with reference to FIGS. 1 to 4, Figure 4B As described with reference to FIGS. 1 to 4,

[0158] Referring toFigure 5 and Figure 5 In the normal mode MD1 and the power saving mode MD2, the second switching controller 531 of the third converter 530 may output a switching control signal LX having a specific driving frequency. Here, Figure 5 The switching control signal LX shown in FIG can be one of the third control signal G3 and the fourth control signal G4 output by the second switching controller 531. For example, Figure 8 The switching control signal LX may be a signal corresponding to the fourth control signal G4, but the present invention is not limited thereto. In another embodiment, the switching control signal LX may be a signal corresponding to the third control signal G3. The second switching controller 531 may output the third control signal G3 and the fourth control signal G4, each having a turn-on voltage level and a turn-off voltage level, at a specific period.

[0159] The third transistor M3 and the fourth transistor M4 may be alternately turned on corresponding to the third control signal G3 and the fourth control signal G4 , and the source driving voltage VLIN may be controlled based on the second inductor current I_IND2 flowing through the second inductor L2 .

[0160] In the normal mode MD1 and the power saving mode MD2, the second switching controller 531 may output the switching control signal LX at different periods. Figure 8 The different cycles of the switching control signal LX in the normal mode MD1 and the power saving mode MD2 are described below.

[0161] Also refer to Figure 4B , Figure 4B The third converter 530 may generate and supply the source driving voltage VLIN. When switching from the normal mode MD1 (or the first mode) to the power saving mode MD2 (or the second mode), the third converter 530 may output the source driving voltage VLIN by reducing the voltage level of the source driving voltage VLIN.

[0162] Figure 8The second switching controller 531 of the third converter 530 can output a switching control signal LX having a different period in the normal mode MD1 (or the first switching period TP1) and in the power saving mode MD2. For example, in the normal mode MD1, the switching control signal LX can have a first period Ca, while in the power saving mode MD2, the switching control signal LX can have a second period Cb. As an embodiment, the second period Cb can be set to be longer than the first period Ca. That is, the number of times the third transistor M3 and the fourth transistor M4 are turned on per unit time in the normal mode MD1 can be more than the number of times the third transistor M3 and the fourth transistor M4 are turned on per unit time in the power saving mode MD2. In some embodiments, the second switching controller 531 can output the switching control signal LX in response to a mode signal MCS. As described above, the mode signal MCS can be a signal including information about the normal mode MD1 and the power saving mode MD2.

[0163] When the number of times the third transistor M3 or the fourth transistor M4 is turned on per unit time decreases, the ripple voltage Rip of the source driving voltage VLIN can increase. Here, the ripple voltage Rip of the source driving voltage VLIN can represent an AC voltage component included in the source driving voltage VLIN. In the power saving mode MD2, since the display panel 100 displays a power saving image whose load is small and the amplitude of the ripple voltage Rip can be proportional to the size of the load, the amplitude of the ripple voltage Rip can be completely reduced. In other words, since the load of the display image decreases, even though the number of times the transistors M3 and M4 are turned on decreases and the amplitude of the ripple voltage Rip increases, since the amplitude of the ripple voltage Rip can be adjusted within a predetermined range, the display quality of the display apparatus 10 can not be abnormal.

[0164] In some embodiments, the ripple voltage Rip of the source driving voltage VLIN can be controlled within a predetermined range in the power saving mode MD2. For example, the second switching controller 531 can turn on the third transistor M3 or the fourth transistor M4 by providing the switching control signal LX of the on level at an on time point t_on at which the ripple voltage Rip of the source driving voltage VLIN becomes equal to or smaller than a first set value RP_L. In addition, the second switching controller 531 can turn off the third transistor M3 or the fourth transistor M4 by providing the switching control signal LX of the off level at an off time point t_off at which the ripple voltage Rip of the source driving voltage VLIN becomes equal to or larger than a second set value RP_H. Accordingly, the third converter 530 can reduce the number of times the third transistor M3 or the fourth transistor M4 is turned on while maintaining the amplitude of the ripple voltage Rip of the source driving voltage VLIN at a constant level.

[0165] As described with reference to Figure 5 The display apparatus 10 can minimize power consumption by reducing the number of switching (or the number of turning on) of the transistors M3 and M4 per unit time in the third converter 530. In addition, although the number of switching of the transistors M3 and M4 per unit time is reduced, since the ripple voltage Rip of the source driving voltage VLIN can be controlled within a predetermined range, no abnormality occurs in display quality.

[0166] Referring again to Figures 5 to 8 The state of the mode control signal MD_SEL can change to a disabled state (or a low voltage level) during the power saving mode MD2. As described above, when the mode control signal MD_SEL changes to the disabled state, the display panel 100 can switch to the normal mode MD1 after the second switching period TP2. In the second switching period TP2, the black image data signal can be provided to the pixels PX of the display panel 100.

[0167] The power supply 500 and the data driver 300 can change the voltage level of the generated voltage in the second switching period TP2 from the fourth time point t4 to the sixth time point t6. As an embodiment, the power supply 500 and the data driver 300 can change the voltage level of the generated voltage in response to the power control signal CS.

[0168] In particular, between the fourth time point t4 and the fifth time point t5, the vertical blanking signal TE can change to the enabled state. That is, all of the pixels PX of the display panel 100 can not display a display image (e.g., a normal image or a power saving image).

[0169] The power supply 500 can increase the voltage level of the source driving voltage VLIN during the enabled period of the vertical blanking signal TE during the second switching period TP2. The voltage level of the source driving voltage VLIN can be immediately increased, but the disclosure is not limited thereto. As another example, the voltage level of the source driving voltage VLIN can be gradually increased during a period longer than the change period of the first gate driving voltage VGH.

[0170] In addition, the power supply 500 can increase the voltage level of the first power voltage VDD and decrease the voltage level of the second power voltage VSS which is a negative voltage level. That is, the power supply 500 can increase the absolute value of the voltage level of each of the first power voltage VDD and the second power voltage VSS.

[0171] According to an embodiment, the voltage level change time point of the second power voltage VSS may be different from the voltage level change time point of the first power voltage VDD. For example, the voltage level of the second power voltage VSS may be changed after the voltage level of the first power voltage VDD is changed. As another example, the voltage level of the second power voltage VSS may be changed after the voltage level change of the second gate drive voltage VGL is completed. In other words, the voltage level of the second power voltage VSS may be changed after the fifth time point t5.

[0172] During the enable period of the vertical blank signal TE during the second switching period TP2, the data driver 300 may change the voltage levels of the first gate drive voltage VGH, the second gate drive voltage VGL, and the gamma voltage VREG. For example, the data driver 300 may increase the voltage levels of the first gate drive voltage VGH and the gamma voltage VREG, and decrease the voltage level of the second gate drive voltage VGL, which is a negative voltage level. In other words, the data driver 300 may increase the absolute value of the voltage level of each of the first gate drive voltage VGH, the second gate drive voltage VGL, and the gamma voltage VREG.

[0173] After the sixth time point t6 , the second switching period TP2 may end, and the pixels PX of the display panel 100 may operate in the normal mode MD1 to display a normal image again.

[0174] As reference Figure 9 As described above, since the disclosed display device 10 quickly changes the voltage level of the first power voltage VDD during the vertical blank period VBLNK in which the vertical blank signal TE is enabled, it is possible to prevent the brightness difference between the normal mode and the power saving mode due to the voltage drop from being recognized by the user. To this end, the display device 10 can provide the discharge control signal FD to the first converter 510, and quickly discharge the first power voltage VDD through the discharge unit 513 of the first converter 510.

[0175] When switching from the normal mode MD1 to the power saving mode MD2, the display device 10 can gradually reduce the voltage level of the source driving voltage VLIN. Therefore, the difference between the voltage level of the source driving voltage VLIN and the voltage level of the first gate driving voltage VGH can be maintained equal to or greater than the preset reference value RV, and the driving stability of the display device 10 can be improved.

[0176] In addition, the display device 10 can minimize power consumption by reducing the number of switching times (or turn-on times) per unit time of the transistors M3 and M4 in the third converter 530 in the power saving mode MD2 compared to the normal mode MD1 .

[0177] Hereinafter, other embodiments of the display device will be described. In the following embodiments, the same components as those of the previously described embodiments will be indicated by the same reference numerals, the description thereof will be omitted or simplified, and the differences will be mainly described.

[0178] Figure 1 is a waveform chart showing another example of the operation of the display device of Figure 9

[0179] Figure 5 The embodiment of Figure 5 The embodiment of Figure 9 The embodiment of

[0180] Referring to Figure 9 The voltage level of the source driving voltage VLIN can be changed during the power saving mode MD2 when switching from the normal mode MD1 to the power saving mode MD2 or from the power saving mode MD2 to the normal mode MD1.

[0181] Specifically, when switching from the normal mode MD1 to the power saving mode MD2, the data driver 300 can change the voltage level of the first gate driving voltage VGH within the first switching period TP1.

[0182] After the voltage level of the first gate driving voltage VGH is changed, the power supply 500 can change the voltage level of the source driving voltage VLIN in response to the power supply control signal CS. For example, the voltage level of the source driving voltage VLIN can be changed at a first change point tcl when a delay period PD elapses after the voltage level of the first gate driving voltage VGH is changed. Here, the first change point tcl can be a point in time under the power saving mode MD2. As an embodiment, the voltage level of the source driving voltage VLIN can be decreased in the next image frame after the voltage level of the first gate driving voltage VGH is changed. That is, the delay period PD between the change point (e.g., t3) of the first gate driving voltage VGH and the change point (e.g., tcl) of the source driving voltage VLIN can be a period corresponding to one image frame. However, the delay period PD according to the present application is not limited thereto, and can be a period corresponding to the periods of two or more image frames in another embodiment.

[0183] ​Thereafter, when switching from the power saving mode MD2 to the normal mode MD1, the data driver 300 may change the voltage level of the first gate drive voltage VGH within the second switching period TP2. The voltage level of the source drive voltage VLIN may not change during the second switching period TP2 and may change in the power saving mode MD2 before the first gate drive voltage VGH changes. As an embodiment, the source drive voltage VLIN may change together with the mode control signal MD_SEL at the second change time point tc2 when the mode control signal MD_SEL becomes disabled in the power saving mode MD2.

[0184] As reference Figure 10 As described, since the change time points of the voltage level of the source driving voltage VLIN and the voltage level of the first gate driving voltage VGH do not overlap with each other, even if the source driving voltage VLIN changes immediately within a short period of time, a sufficient gap can be maintained between the voltage level of the source driving voltage VLIN and the voltage level of the first gate driving voltage VGH, and the display device 10 can be stably driven.

[0185] Figure 11 is a diagram illustrating a data driver according to another example. Figure 10 It is shown that the Figure 12 Schematic diagram of an example of a gap controller in a data driver. Figure 10 It is shown that Figure 10 FIG2 is a waveform diagram of the operation of the data driver of the display device.

[0186] according to Figure 2 The data driver 300 'of the embodiment is the same as that according to Figure 10 The data driver 300 of the embodiment is different in that, according to Figures 2 to 5 The data driver 300' of the embodiment further includes a gap controller 340 for maintaining the gap between the first power voltage VDD and the gamma voltage VREG, and other configurations may be substantially the same or similar. Figure 1 The differences in the embodiments.

[0187] Reference Figures 10 to 12 as well as Figure 11 , the data driver 300 ′ may include a gap controller 340 .

[0188] The gap controller 340 may receive the first power voltage VDD, the first gamma voltage VREG, and the reference power voltage VDD_REF. The reference power voltage VDD_REF may be a separately set value. The reference power voltage VDD_REF may be a preset value set during the manufacturing process of the display device or a value set by the user after the display device is manufactured.

[0189] The gap controller 340 can generate a second gamma voltage VREG' (or an adjusted first gamma voltage) based on the first power voltage VDD, the first gamma voltage VREG, and the reference power voltage VDD_REF. At this time, the second gamma voltage VREG' can be a voltage that maintains a constant gap (or difference) from the first power voltage VDD. The gap controller 340 can provide the generated second gamma voltage VREG' to the grayscale voltage generator 320.

[0190] The grayscale voltage generator 320 can generate a grayscale voltage GV based on the reference voltage VREF and the second gamma voltage VREG' provided from the gap controller 340, and provide the grayscale voltage GV to the data signal generator 330.

[0191] According to an embodiment, the gap controller 340 can further receive a gap control enable signal (not shown) from the outside. When the gap controller 340 becomes in an enabled state through the control signal, the grayscale voltage generator 320 can generate the grayscale voltage GV based on the second gamma voltage VREG', and when the gap controller 340 becomes in a disabled state through the control signal, the grayscale voltage generator 320 can generate the grayscale voltage GV based on the first gamma voltage VREG.

[0192] Even if the voltage level of the first power voltage VDD changes according to the display mode, the gap controller 340 can adjust the voltage level of the second gamma voltage VREG' so that the difference VD of the voltage levels of the first power voltage VDD and the second gamma voltage VREG' can be maintained as constant.

[0193] Specifically, as shown in FIG. 4A, the gap controller 340 can include a first driver 341, a second driver 342, and a third driver 343. Figures 10 to 12

[0194] The first driver 341 can receive the first gamma voltage VREG and the first power voltage VDD, and generate a reference voltage difference VD_REF proportional to the difference between the first gamma voltage VREG and the first power voltage VDD. The first driver 341 can be configured as a comparator. To this end, the first driver 341 can include an operational amplifier or the like.

[0195] In some embodiments, when digital signals for the first gamma voltage VREG and the first power voltage VDD are applied to the first driver 341, the first driver 341 can include a digital-to-analog converter to generate the reference voltage difference VD_REF by converting the digital signals for the first gamma voltage VREG and the first power voltage VDD into corresponding analog signals.

[0196] ​The second driver 342 can generate a reference gamma voltage VREG_REF by summing the reference voltage difference VD_REF received from the first driver 341 and a reference power voltage VDD_REF inputted from the outside.

[0197] The third driver 343 can output a second gamma voltage VREG' based on the reference gamma voltage VREG_REF received from the second driver 342. The reference gamma voltage VREG_REF provided to the third driver 343 can have a voltage level reduced at a predetermined ratio to prevent internal circuit elements from being damaged in a voltage control process. Accordingly, the third driver 343 can amplify the reference gamma voltage VREG_REF at the same ratio as the reduction ratio to generate the second gamma voltage VREG' and output the second gamma voltage VREG' to the grayscale voltage generator 320.

[0198] In an embodiment, the third driver 343 can be configured as a non-inverting amplifier. To this end, the third driver 343 can include an amplifier AMP and a voltage divider VDV.

[0199] The amplifier AMP can include a first input terminal receiving the reference gamma voltage VREG_REF, a second input terminal receiving a feedback voltage of the second gamma voltage VREG', and an output terminal outputting the second gamma voltage VREG'. Here, the first input terminal can be a positive input terminal, and the second input terminal can be a negative input terminal, but the invention is not limited thereto.

[0200] The voltage divider VDV can include a plurality of resistors R1 and R2, and can feed back a portion of the second gamma voltage VREG' output to the output terminal toward the second input terminal. That is, the voltage divider VDV can be connected to the output terminal and the second input terminal to provide the second gamma voltage VREG' to the second input terminal of the amplifier AMP as a feedback voltage.

[0201] As described above, the amplifier AMP and the voltage divider VDV of the third driver 343 can configure a non-inverting amplifier, and the reference gamma voltage VREG_REF input to the first input terminal can be amplified and output to the output terminal according to a ratio of the resistors R1 and R2 included in the voltage divider VDV. For example, the second gamma voltage VREG' can be a voltage output by amplifying the reference gamma voltage VREG_REF by (1+R2 / R1) times.

[0202] Although not shown in the drawings, the power supply 500 may receive a reference power voltage VDD_REF from the outside. The power supply 500 may include an amplifier circuit including an amplifier (e.g., a non-inverting amplifier). The power supply 500 may amplify the reference power voltage VDD_REF to generate a regulated first power voltage and provide the regulated first power voltage to the display panel 100.

[0203] As reference ​ As described above, although the voltage level of the first power voltage VDD changes, since the difference VD between the voltage level of the second gamma voltage VREG′ and the voltage level of the first power voltage VDD is maintained constant by the gap controller 340, the amount of driving current supplied to the light emitting element of the pixel PX can be maintained constant. That is, although the voltage level of the first power voltage VDD changes, a brightness difference does not occur in the image displayed by the display panel 100 and switching between the normal mode and the power saving mode can be performed without a separate switching period in which a black image data signal is supplied to the pixel PX.

[0204] Although the disclosed embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that the disclosed embodiments may be implemented in other specific forms without changing the technical spirit and essential features of the disclosed embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all aspects and not restrictive.

Claims

1. A display device, comprising: a display panel including a plurality of pixels and power lines and displaying an image in a normal mode or a power saving mode; a data driver for providing data signals to the plurality of pixels; as well as a power supply for supplying a source driving voltage to the data driver and a first power voltage to the power line in the normal mode, wherein the data driver supplies a first auxiliary power voltage to the power line in the power saving mode, the power supply outputting the first power voltage by reducing a voltage level of the first power voltage to a first power saving voltage level in a vertical blank period of a first switching period, The plurality of pixels do not display an image during the vertical blank period, The first switching period is a transition period from the normal mode to the power saving mode, and The power supply includes a first converter generating the first power voltage, The first converter includes: a switching unit including a first inductor and a first transistor and a second transistor, and connected between a first input terminal to which an external input voltage is applied and a first output terminal from which the first power voltage is output; and a discharge circuit connected between the first output terminal and ground and including a variable resistor and a discharge transistor.

2. The display device according to claim 1, wherein The first converter alternately turns on the first transistor and the second transistor to output the first power voltage.

3. The display device according to claim 2, wherein: The discharge transistor is turned on in response to a discharge control signal provided in the vertical blank period, and After providing the discharge control signal, the first converter reduces the voltage level of the first power voltage to the first power saving voltage level.

4. The display device according to claim 1, wherein The power supply includes a second converter that generates the source driving voltage. The second converter comprises: a second inductor connected between a second input terminal to which an external input voltage is applied and the node; a third transistor connected between the node and ground and turned on in response to a first control signal; a fourth transistor connected between the second output terminal from which the source driving voltage is output and the node, and turned on in response to a second control signal; and a switching controller that generates a switching control signal including the first control signal and the second control signal, and A first period for providing the switching control signal in the normal mode is different from a second period for providing the switching control signal in the power saving mode.

5. The display device according to claim 4, wherein The second period is set to be longer than the first period. The display device according to claim 5 , wherein: In the power saving mode, when the ripple voltage of the source drive voltage is equal to or less than a first set value, the switching controller turns on the third transistor or the fourth transistor, and when the ripple voltage of the source drive voltage is equal to or greater than a second set value, the switching controller turns off the third transistor or the fourth transistor.

7. The display device according to claim 1, wherein the display panel displays a normal image in the normal mode, and displays a power saving image having a smaller load than that of the normal image in the power saving mode, The plurality of pixels display the normal image at a first driving frequency in the normal mode, and the plurality of pixels display the power saving image at a second driving frequency lower than the first driving frequency in the power saving mode.

8. The display device according to claim 1, further comprising: a gate driver providing gate signals to the plurality of pixels, wherein the data driver generates the first auxiliary power voltage and the gate driving voltage based on the source driving voltage, and The gate driver generates the gate signal based on the gate driving voltage.

9. The display device according to claim 8, wherein When switching from the normal mode to the power saving mode, the power supply outputs the source driving voltage by reducing the voltage level of the source driving voltage to a second power saving voltage level during a first period, The data driver outputs the gate driving voltage by reducing the voltage level of the gate driving voltage to a third power saving voltage level during a second period shorter than the first period, and A difference between the voltage level of the source driving voltage and the voltage level of the gate driving voltage maintains a preset reference value or more.

10. The display device according to claim 9, wherein The voltage level of the source driving voltage gradually decreases in a step-wise manner during the first period.

11. The display device according to claim 9, wherein When the source driving voltage and the gate driving voltage decrease, a slew rate of the source driving voltage is smaller than a slew rate of the gate driving voltage.

12. The display device according to claim 8, wherein The power supply outputs the source driving voltage by reducing a voltage level of the source driving voltage in the power saving mode after the first switching period, and The data driver outputs the gate driving voltage by reducing a voltage level of the gate driving voltage in the first switching period.

13. The display device according to claim 12, wherein: The power supply reduces the voltage level of the source driving voltage in a next frame after the voltage level of the gate driving voltage is reduced.

14. The display device according to claim 12, wherein: The power supply increases the voltage level of the source driving voltage in response to a mode control signal in the power saving mode, and The data driver increases the voltage level of the gate driving voltage in a second switching period from the power saving mode to the normal mode.

15. The display device according to claim 1, wherein The data driver provides a black image data signal to the plurality of pixels in the first switching period.

16. A display device, comprising: a display panel including a plurality of pixels and power lines and displaying an image in a normal mode or a power saving mode; a data driver for providing data signals to the plurality of pixels; as well as a power supply that supplies a source driving voltage to the data driver and a first power voltage to the power line in the normal mode, wherein the data driver generates a first auxiliary power voltage and a first gamma voltage based on an external input voltage and the source driving voltage, the data driver supplies the first auxiliary power voltage to the power line in the power saving mode, In a period of changing from the normal mode to the power saving mode, the data driver outputs the first gamma voltage by reducing a voltage level of the first gamma voltage, and the power supply outputs the first power voltage by reducing a voltage level of the first power voltage, and In the normal mode and the power saving mode, a difference between the voltage level of the first power voltage and the voltage level of the first gamma voltage is constant.

17. The display device according to claim 16, wherein: The data driver includes: a power converter, generating the first auxiliary power voltage and the first gamma voltage using the source driving voltage; a grayscale voltage generator that generates a grayscale voltage based on the first gamma voltage; and A data signal generator generates the data signal based on the grayscale voltage and the source driving voltage.

18. The display device according to claim 17, wherein: The data driver further includes a gap controller generating a second gamma voltage whose voltage level is adjusted based on the first gamma voltage, the first power voltage, and a reference power voltage, and The gray voltage generator generates the gray voltage based on the second gamma voltage.

19. The display device according to claim 18, wherein The gap controller comprises: a first driver that compares the first gamma voltage with the first power voltage to generate a reference voltage difference; a second driver that sums the reference voltage difference and the reference power voltage to generate a reference gamma voltage; and The third driver outputs the second gamma voltage based on the reference gamma voltage.

20. The display device according to claim 19, wherein The third driver includes: an amplifier including a first input terminal connected to the second driver to receive the reference gamma voltage, a second input terminal to receive a feedback voltage of the second gamma voltage, and an output terminal to output the second gamma voltage; and A voltage divider is connected to the output terminal and the second input terminal and provides the feedback voltage of the second gamma voltage to the second input terminal of the amplifier.

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