Display device

Abstract

The display device includes: a first active pattern; a first conductive pattern including a gate electrode overlapping the first active pattern, a first gate line overlapping the first active pattern and extending in a first direction, and a second gate line extending in the first direction; a second conductive pattern disposed on the first conductive pattern and including a third gate line extending in the first direction and a fourth gate line extending in the first direction; a second active pattern disposed on the second conductive pattern and including a material different from that of the first active pattern; and a third conductive pattern disposed on the second active pattern and including a first upper electrode overlapping and connected to the third gate line and a second upper electrode overlapping and connected to the fourth gate line.

Description

Technical Field

[0001] Embodiments relate to a display device. More specifically, embodiments relate to a display device having a reduced bezel area. Background Art

[0002] Display devices may be applied to smart phones, tablet personal computers (PCs), laptop computers, monitors, and televisions (TVs), etc. Many studies are being conducted to reduce the size and weight of display devices. To reduce the size and weight of a display device, it is necessary to expand the display area and to reduce the non-display area (e.g., the bezel area). When the connection lines included in the display device bypass the display area, the non-display area can be reduced. Summary of the Invention

[0003] Embodiments provide a display device having a reduced non-display area.

[0004] In an embodiment, a display device may include: a first active pattern; a first conductive pattern including a gate electrode overlapping the first active pattern, a first gate line overlapping the first active pattern and extending in a first direction, and a second gate line extending in the first direction; a second conductive pattern disposed on the first conductive pattern and including a third gate line extending in the first direction and a fourth gate line extending in the first direction; a second active pattern disposed on the second conductive pattern and including a material different from that of the first active pattern; and a third conductive pattern disposed on the second active pattern and including a first upper electrode overlapping and electrically connected to the third gate line and a second upper electrode overlapping and electrically connected to the fourth gate line.

[0005] In an embodiment, the display device may further include a fourth conductive pattern disposed on the third conductive pattern and including a horizontal connection line extending in the first direction and to which a first data voltage is applied.

[0006] In an embodiment, the display device may further include a fifth conductive pattern disposed on the fourth conductive pattern and including a data line extending in a second direction intersecting the first direction and to which a first data voltage is applied, a vertical connection line extending in the second direction and to which a first data voltage is applied, and a high power voltage line extending in the second direction and to which a high power voltage is applied.

[0007] In an embodiment, the fourth conductive pattern may further include a data voltage pad, and the data line may overlap and be electrically connected to the data voltage pad.

[0008] In an embodiment, the vertical connection line may overlap and be electrically connected to the horizontal connection line.

[0009] In an embodiment, the fourth conductive pattern may further include a shielding pattern, and the high-power voltage line may overlap with the shielding pattern and be electrically connected to the shielding pattern.

[0010] In an embodiment, a first gate signal may be applied to the first gate line, a second gate signal may be applied to the third gate line, and a third gate signal may be applied to the fourth gate line.

[0011] In an embodiment, a light emission control signal may be applied to the second gate line.

[0012] In an embodiment, the second conductive pattern may further include a gate initialization voltage line.

[0013] In an embodiment, the display device further includes a fourth conductive pattern disposed on the third conductive pattern, and the fourth conductive pattern may further include a gate initialization voltage connection pattern.

[0014] In an embodiment, the gate initialization voltage connection pattern may overlap with the gate initialization voltage line and be electrically connected to the gate initialization voltage line.

[0015] In an embodiment, the gate initialization voltage connection pattern may overlap with the second active pattern and be electrically connected to the second active pattern.

[0016] In an embodiment, the first active pattern may include a silicon semiconductor, and the second active pattern may include an oxide semiconductor.

[0017] In an embodiment, a part of the first gate line and a part of the first active pattern that overlap each other may constitute an n-channel metal oxide semiconductor (NMOS) transistor.

[0018] In an embodiment, a part of the second gate line and a part of the first active pattern that overlap each other may constitute an NMOS transistor.

[0019] In an embodiment, a part of the gate electrode and a part of the first active pattern that overlap each other may constitute an NMOS transistor.

[0020] In an embodiment, a part of the first upper electrode and a part of the second active pattern that overlap each other may constitute a p-channel metal oxide semiconductor (PMOS) transistor.

[0021] In an embodiment, a part of the second upper electrode and a part of the second active pattern that overlap each other may constitute a PMOS transistor.

[0022] The display device in the embodiment may include: a first active pattern; a first conductive pattern including a gate electrode overlapping with the first active pattern, a first gate line overlapping with the first active pattern and extending in a first direction, and a second gate line extending in the first direction; a second conductive pattern disposed on the first conductive pattern and including a third gate line extending in the first direction and a fourth gate line extending in the first direction; a second active pattern disposed on the second conductive pattern and including a material different from that of the first active pattern; and a third conductive pattern disposed on the second active pattern and including a first upper electrode overlapping with and electrically connected to the third gate line and a second upper electrode overlapping with and electrically connected to the fourth gate line.

[0023] Accordingly, the display device may bypass and transmit a gate signal through a contact hole electrically connecting the third gate line and the upper electrode and a contact hole connecting the fourth gate line and the second upper electrode. Accordingly, a space in which additional lines and patterns are disposed may be additionally disposed in the third conductive pattern. Accordingly, since the fourth conductive pattern and the fifth conductive pattern may transmit a data voltage to the display area without adding a separate conductive pattern, the fan-out lines used in the prior art are removed, so that the non-display area of the display device may be reduced. By doing so, the size and weight of the display device may be reduced.

[0024] It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Features, advantages, and embodiments of the present invention will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0026] Figure 1 is a plan view illustrating an embodiment of a display device according to the present invention.

[0027] Figure 2 is illustrated Figure 1 an enlarged view of lines included in the display device.

[0028] Figure 3 is illustrated Figure 1 an example circuit diagram of a pixel circuit included in the display device.

[0029] Figures 4 to 16 is for describing Figure 1 a plan view of a pixel structure included in the display device.

[0030] Figure 17 is a cross-sectional view taken along line I-I' of Figure 16 the same.

[0031] Figure 18 is a sectional view taken along line II-II' of Figure 16 . DETAILED DESCRIPTION OF THE INVENTION

[0032] Embodiments of the display device of the present invention will be described below with reference to the accompanying drawings in which embodiments are shown. The same or similar reference numerals may be used for the same or similar elements in the drawings.

[0033] Embodiments of the present invention may have various modifications and may be embodied in different forms, and the embodiments will be described in detail with reference to the accompanying drawings. However, the embodiments of the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, all modifications, equivalents, and alternatives included within the spirit and scope of the present invention should be included.

[0034] In the drawings, for clarity of illustration, the dimensions of the structures are exaggerated. It will be understood that although terms such as "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element may be referred to as a second element without departing from the teachings of the present invention. Similarly, a second element may be referred to as a first element. As used herein, the singular form is also intended to include the plural form unless the context clearly indicates otherwise.

[0035] In the specification and claims, the term "and / or" for purposes of its meaning and interpretation is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunctive or disjunctive sense and may be understood to be equivalent to "and / or".

[0036] The phrase "at least one of..." for purposes of its meaning and interpretation is intended to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" may be understood to mean "A, B, or A and B". When following a list of elements, the term "at least one of..." modifies the entire list of elements and not individual elements in the list.

[0037] It will be further understood that when used in this specification, the terms "comprises" and / or "comprising" specify the presence of the stated features, numbers, steps, operations, elements, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, parts, or groups thereof.

[0038] It will also be understood that when a layer, film, region, plate, etc. is referred to as being "on" or "above" another part, the layer, film, region, plate, etc. can be "directly on" the other part, or an intermediate layer may also exist. It will also be understood that when a layer, film, region, plate, etc. is referred to as being "under" or "below" another part, the layer, film, region, plate, etc. can be "directly under" the other part, or an intermediate layer may also exist. When an element is referred to as being disposed "on" another element, the element can be disposed under the other element.

[0039] For ease of description, spatial relative terms such as "under", "beneath", "lower", "above", or "upper" may be used herein to describe the relationship between one element or component and another as illustrated in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatial relative terms are intended to encompass different orientations of the device during use or operation. For example, in the case where the device illustrated in the drawings is flipped, a device disposed "under" or "beneath" another device can be placed "above" the other device. Thus, the illustrative term "under" can include both lower and upper positions. The device can also be oriented in other directions, and thus the spatial relative terms can be interpreted differently depending on the orientation.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly defined in the specification.

[0041] Figure 1 is a plan view illustrating an embodiment of a display device according to the present invention, Figure 2 is illustrated Figure 1 an enlarged view of a line included in the display device, and Figure 3 is illustrated Figure 1 a circuit diagram of an example of a pixel circuit included in the display device.

[0042] Referring to Figures 1 to 3 , the display device 20 may include a display area DA, a non-display area NDA surrounding the display area DA, a bendable bend area BA, a peripheral area SA between the display area DA and the bend area BA, and a pad area PA.

[0043] For example, in an embodiment, the pixel structure PX may be disposed in the display area DA, and a driver for driving the pixel structure PX may be disposed in the non-display area NDA. For example, in an embodiment, the pad portion PD and the data driver DDV may be disposed in the pad area PA, and the bending area BA may be bent based on a virtual bending axis. For example, in an embodiment, since the pixel structure PX is not disposed in the peripheral area SA, the width of the peripheral area SA extending in the second direction D2 may be defined as a dead zone of the display device 20.

[0044] The pixel structure PX may be disposed in the display area DA. In addition, the data line DL, the gate line GL, the emission control line EML, the driving voltage line PL, and the connection line FL connected to the pixel structure PX may be disposed in the display area DA.

[0045] The connection line FL may be electrically connected to the data driver DDV and the data line DL. The connection line FL may receive the data voltage DATA from the data driver DDV and provide the data voltage DATA to the data line DL.

[0046] The driving unit may include a gate driver GDV, a data driver DDV, an emission driver EDV, and a pad portion PD. In addition, the driver may include a timing controller, and the timing controller may control the gate driver GDV, the data driver DDV, and the emission driver EDV.

[0047] In an embodiment, as Figure 1 and Figure 2 illustrated, the data line DL and the connection line FL may be disposed in the display area DA. For example, in an embodiment, the first to fourth data lines DL1, DL2, DL3, and DL4, the first connection line FL1, and the second connection line FL2 may be disposed in the display area DA. For example, in an embodiment, the connection line FL may be a fan-out line electrically connecting the data driver DDV and the data line DL.

[0048] In an embodiment, the pixel structure PX may include first to fourth pixel structures disposed along a first direction D1 intersecting the second direction D2. In an embodiment, the second direction D2 may be perpendicular to the first direction D1. The first data line DL1 may be connected to the first pixel structure, the second data line DL2 may be connected to the second pixel structure, the third data line DL3 may be connected to the third pixel structure, and the fourth data line DL4 may be connected to the fourth pixel structure.

[0049] In an embodiment, the first connection line FL1 may include a first vertical connection line VFL1 and a first horizontal connection line HFL1, and the second connection line FL2 may include a second vertical connection line VFL2 and a second horizontal connection line HFL2. For example, in an embodiment, the first vertical connection line VFL1 and the second vertical connection line VFL2 may extend in a second direction D2, and the first horizontal connection line HFL1 and the second horizontal connection line HFL2 may extend in a first direction D1.

[0050] The first connection line FL1 may electrically connect the data driver DDV and the first data line DL1. For example, in an embodiment, a first data voltage may be provided to the first pixel structure through the first connection line FL1 and the first data line DL1.

[0051] In an embodiment, the first vertical connection line VFL1 may be connected to a first input transmission line SCL1, the first input transmission line SCL1 may be connected to a first bent transmission line BCL1, and the first bent transmission line BCL1 may be connected to a first output transmission line DCL1.

[0052] For example, in an embodiment, the first vertical connection line VFL1 may extend from the peripheral area SA to the display area DA and may be disposed on a first layer (e.g., a layer on which Figure 15 and Figure 16 the fifth conductive pattern 2700 is disposed). The first input transmission line SCL1 is disposed in the peripheral area SA and may be disposed on a second layer disposed below the first layer (e.g., a layer on which Figure 6 the first conductive pattern 2200 is disposed). The first bent transmission line BCL1 may be disposed in the bent area BA and may be disposed in the first layer. The first output transmission line DCL1 may be disposed in the pad area PA and may receive the first data voltage from the data driver DDV.

[0053] The second connection line FL2 may electrically connect the data driver DDV and the second data line DL2. For example, in an embodiment, a second data voltage may be provided to the second pixel structure through the second connection line FL2 and the second data line DL2.

[0054] In an embodiment, the second vertical connection line VFL2 may be connected to the second input transmission line SCL2, the second input transmission line SCL2 may be connected to the second bent transmission line BCL2, and the second bent transmission line BCL2 may be connected to the second output transmission line DCL2. However, since the structures of the second vertical connection line VFL2, the second input transmission line SCL2, the second bent transmission line BCL2, and the second output transmission line DCL2 are substantially the same as those of the first vertical connection line VFL1, the first input transmission line SCL1, the first bent transmission line BCL1, and the first output transmission line DCL1, detailed descriptions thereof will be omitted.

[0055] The third data line DL3 may be connected to the data driver DDV. For example, in an embodiment, the third data voltage may be provided to the third pixel structure through the third data line DL3.

[0056] In an embodiment, the third data line DL3 may be connected to the third input transmission line SCL3, the third input transmission line SCL3 may be connected to the third bent transmission line BCL3, and the third bent transmission line BCL3 may be connected to the third output transmission line DCL3.

[0057] For example, in an embodiment, the third data line DL3 may extend from the peripheral area SA to the display area DA and may be disposed on the first layer. The third input transmission line SCL3 may be disposed in the peripheral area SA and may be disposed in the third layer (e.g., the layer on which Figure 7 the second conductive pattern 2300 is disposed) below the first layer. The third bent transmission line BCL3 may be disposed in the bent area BA and may be disposed in the first layer. The third output transmission line DCL3 may be disposed in the pad area PA and may receive the third data voltage from the data driver DDV.

[0058] The fourth data line DL4 may be connected to the data driver DDV. For example, in an embodiment, the fourth data voltage may be provided to the fourth pixel structure through the fourth data line DL4.

[0059] In an embodiment, the fourth data line DL4 may be connected to the fourth input transmission line SCL4, the fourth input transmission line SCL4 may be connected to the fourth bent transmission line BCL4, and the fourth bent transmission line BCL4 may be connected to the fourth output transmission line DCL4. However, since the structures of the fourth data line DL4, the fourth input transmission line SCL4, the fourth bent transmission line BCL4, and the fourth output transmission line DCL4 are substantially the same as those of the third data line DL3, the third input transmission line SCL3, the third bent transmission line BCL3, and the third output transmission line DCL3, detailed descriptions thereof will be omitted.

[0060] In an embodiment, the second layer may be disposed below the third layer. For example, in an embodiment, the first transmission line SCL1 and the second transmission line SCL2 may be disposed below the third transmission line SCL3 and the fourth transmission line SCL4. Therefore, the space of the second layer (or the third layer of the peripheral area SA) of the peripheral area SA can be ensured, and additional lines can be further disposed in the peripheral area SA. However, the present invention is not limited thereto, and the connection structure and the arrangement position of the lines described above can be set as needed.

[0061] Since the connection line FL is disposed in the display area DA, the display device 20 of the present invention can have a reduced width extending in the second direction D2 of the peripheral area SA compared to a conventional display device. In other words, the dead zone of the display device 20 can be reduced.

[0062] The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a storage capacitor CST, and a boost capacitor CBS. The pixel circuit PC is electrically connected to the organic light emitting diode OLED and can supply a driving current to the organic light emitting diode OLED.

[0063] The organic light emitting diode OLED may include a first terminal (e.g., an anode terminal) and a second terminal (e.g., a cathode terminal). The first terminal of the organic light emitting diode OLED may be connected to the first transistor T1 through the sixth transistor T6 to receive a driving current, and the second terminal may be supplied with a low power voltage ELVSS. The organic light emitting diode OLED can generate light having a brightness corresponding to the driving current.

[0064] The storage capacitor CST may include a first terminal and a second terminal. The first terminal of the storage capacitor CST may be connected to the first transistor T1, and the second terminal of the storage capacitor CST may receive a high power voltage ELVDD. The storage capacitor CST can maintain the voltage level of the gate terminal of the first transistor T1 during the non-active period of the first gate signal GW.

[0065] The boost capacitor CBS may include a first terminal and a second terminal. The first terminal of the boost capacitor CBS may be connected to the first terminal of the storage capacitor CST, and the second terminal of the boost capacitor CBS may receive the first gate signal GW. When the supply of the first gate signal GW is stopped, the boost capacitor CBS can compensate for the voltage drop of the gate terminal by increasing the voltage of the gate terminal of the first transistor T1.

[0066] The first transistor T1 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the first transistor T1 may be connected to the first terminal of the storage capacitor CST. The first terminal of the first transistor T1 may be connected to the second transistor T2 to receive a data voltage DATA. The second terminal of the first transistor T1 may be connected to the organic light-emitting diode OLED through the sixth transistor T6 to provide a driving current. The first transistor T1 may generate a driving current based on the voltage difference between the gate terminal and the first terminal. For example, in an embodiment, the first transistor T1 may also be referred to as a driving transistor.

[0067] The second transistor T2 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the second transistor T2 may receive a first gate signal GW through a gate line GL.

[0068] The second transistor T2 may be turned on or off in response to the first gate signal GW. For example, in an embodiment, when the second transistor T2 is a p-channel metal oxide semiconductor (PMOS) transistor, the second transistor T2 is turned off when the first gate signal GW has a positive voltage level and is turned on when the first gate signal GW has a negative voltage level. The first terminal of the second transistor T2 may receive the data voltage DATA through a data line DL. The second terminal of the second transistor T2 may provide the data voltage DATA to the first terminal of the first transistor T1 while the second transistor T2 is turned on. For example, in an embodiment, the second transistor T2 may also be referred to as a switching transistor.

[0069] The third transistor T3 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the third transistor T3 may receive a second gate signal GC. The first terminal of the third transistor T3 may be connected to the gate terminal of the first transistor T1. The second terminal of the third transistor T3 may be connected to the second terminal of the first transistor T1.

[0070] The third transistor T3 may be turned on or off in response to the second gate signal GC. For example, in an embodiment, when the third transistor T3 is an n-channel metal oxide semiconductor (NMOS) transistor, the third transistor T3 is turned on when the second gate signal GC has a positive voltage level and is turned off when the second gate signal GC has a negative voltage level.

[0071] During a period when the third transistor T3 is turned on in response to the second gate signal GC, the third transistor T3 can diode-connect the first transistor T1. Since the first transistor T1 is diode-connected, a voltage difference equal to the threshold voltage of the first transistor T1 can appear between the gate terminal of the first transistor T1 and the first terminal of the first transistor T1. Therefore, at the gate terminal of the first transistor T1, a voltage obtained by adding the voltage difference to the data voltage DATA supplied to the first terminal of the first transistor T1 can be supplied to the gate terminal of the first transistor T1 during the on-period of the third transistor T3. Therefore, the third transistor T3 can compensate for the threshold voltage of the first transistor T1. For example, in an embodiment, the third transistor T3 may also be referred to as a compensation transistor.

[0072] The fourth transistor T4 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the fourth transistor T4 may receive a third gate signal GI. The first terminal of the fourth transistor T4 may receive a gate initialization voltage VINT. The second terminal of the fourth transistor T4 may be connected to the gate terminal of the first transistor T1.

[0073] The fourth transistor T4 may be turned on or off in response to the third gate signal GI. For example, in an embodiment, when the fourth transistor T4 is an NMOS transistor, the fourth transistor T4 is turned on when the third gate signal GI has a positive voltage level and is turned off when the third gate signal GI has a negative voltage level.

[0074] During a period when the fourth transistor T4 is turned on in response to the third gate signal GI, the gate initialization voltage VINT may be supplied to the gate terminal of the first transistor T1. Therefore, the fourth transistor T4 can initialize the gate terminal of the first transistor T1 using the gate initialization voltage VINT. For example, in an embodiment, the fourth transistor T4 may also be referred to as a gate initialization transistor.

[0075] The fifth transistor T5 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the fifth transistor T5 may receive an emission control signal EM. The first terminal of the fifth transistor T5 may receive a high-power voltage ELVDD. The second terminal of the fifth transistor T5 may be connected to the first terminal of the first transistor T1. When the fifth transistor T5 is turned on in response to the emission control signal EM, the fifth transistor T5 can supply the high-power voltage ELVDD to the first transistor T1.

[0076] The sixth transistor T6 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the sixth transistor T6 may receive an emission control signal EM. The first terminal of the sixth transistor T6 may be connected to the second terminal of the first transistor T1. The second terminal of the sixth transistor T6 may be connected to the first terminal of the organic light emitting diode OLED. When the sixth transistor T6 is turned on in response to the emission control signal EM, the sixth transistor T6 may transmit the driving current generated by the first transistor T1 to the organic light emitting diode OLED.

[0077] The seventh transistor T7 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the seventh transistor T7 may receive a fourth gate signal GB. The first terminal of the seventh transistor T7 may receive an anode initialization voltage AINT. The second terminal of the seventh transistor T7 may be connected to a first terminal of the organic light emitting diode OLED. When the seventh transistor T7 is turned on in response to the fourth gate signal GB, the seventh transistor T7 may provide the anode initialization voltage AINT to the organic light emitting diode OLED. Therefore, the seventh transistor T7 may initialize the first terminal of the organic light emitting diode OLED using the anode initialization voltage AINT.

[0078] Figure 3 The connection structure of the pixel circuit PC illustrated in the figure is exemplary and may be variously changed. For example, in the embodiment, the pixel circuit PC may not include the third to seventh transistors T3, T4, T5, T6 and T7 and the boost capacitor CBS. In this case, the connection structure between the components in the pixel circuit PC may be changed to form a connection structure between the components included in the pixel circuit PC (i.e., the first transistor T1 and the second transistor T2, the storage capacitor CST and the organic light emitting diode OLED).

[0079] Figures 4 to 16 Is used to describe Figure 1 A plan view of a pixel structure included in a display device.

[0080] refer to Figure 4 , the display device 20 may include a pixel structure PX and a symmetrical pixel structure PX1 adjacent to the pixel structure PX. For example, in an embodiment, the structure of the symmetrical pixel structure PX1 may be substantially the same as the structure of the pixel structure PX that is symmetrical with respect to the imaginary symmetry line SL. Hereinafter, for ease of description, the pixel structure PX will be described.

[0081] refer to Figure 5 , the pixel structure PX may include a substrate SUB and a first active pattern 2100 disposed on the substrate SUB.

[0082] The substrate SUB may include a glass substrate, a quartz substrate, a plastic substrate, or the like. In an embodiment, the substrate SUB may include a plastic substrate, and thus the display device 20 may have a flexible characteristic. In this case, the substrate SUB may have a structure in which at least one organic film layer and at least one barrier layer are alternately stacked. For example, in an embodiment, the organic film layer may be provided using an organic material such as polyimide, and the barrier layer may be provided using an inorganic material.

[0083] A buffer layer (e.g., Figure 17 the buffer layer BUF) may be disposed on the substrate SUB. The buffer layer may prevent metal atoms or impurities from diffusing from the substrate SUB into the first active pattern 2100. In addition, the buffer layer may uniformly form the first active pattern 2100 by controlling the heat supply rate during a crystallization process for forming the first active pattern 2100.

[0084] The first active pattern 2100 may be disposed on the buffer layer. In an embodiment, the first active pattern 2100 may include a silicon semiconductor. For example, in an embodiment, the silicon semiconductor may include amorphous silicon or polycrystalline silicon, or the like.

[0085] In an embodiment, ions may be selectively implanted into the first active pattern 2100. For example, in an embodiment, when the first transistor T1 and the second transistor T2 are PMOS transistors, the first active pattern 2100 may include a source region and a drain region into which positive ions are implanted and a channel region into which positive ions are not implanted.

[0086] A first gate insulating layer (e.g., Figure 17 the first gate insulating layer GI1 in ) may cover the first active pattern 2100 and may be disposed on the substrate SUB. The first gate insulating layer may include an insulating material. For example, in an embodiment, the first gate insulating layer may include silicon oxide, silicon nitride, titanium oxide, or tantalum oxide, or the like.

[0087] Referring to Figure 6 , a first conductive pattern 2200 may be disposed on the first gate insulating layer. The first conductive pattern 2200 may include a first gate line 2210, a gate electrode 2220, and a second gate line 2230.

[0088] The first gate line 2210 may be disposed on the first active pattern 2100 and may extend in a first direction D1. For example, in an embodiment, the first gate line 2210 may form the second transistor T2 together with a part of the first active pattern 2100. To this end, a first gate signal GW may be provided to the first gate line 2210.

[0089] For example, in an embodiment, the first gate line 2210 may form the seventh transistor T7 together with another part of the first active pattern 2100. To this end, the fourth gate signal GB may be provided to the first gate line 2210. For example, in an embodiment, the first gate signal GW and the fourth gate signal GB may have substantially the same waveform (with a time difference).

[0090] The gate electrode 2220 may form the first transistor T1 together with a part of the first active pattern 2100.

[0091] The second gate line 2230 may be disposed on the first active pattern 2100 and may extend in the first direction D1. For example, in an embodiment, the second gate line 2230 may form the fifth transistor T5 and the sixth transistor T6 together with a part of the first active pattern 2100. For example, in an embodiment, the second gate line 2230 may also be referred to as an emission control line.

[0092] For example, in an embodiment, the first conductive pattern 2200 may include metals, alloys, conductive metal oxides, and transparent conductive materials, etc. For example, in an embodiment, the first conductive pattern 2200 may include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0093] The first intermediate insulating layer (e.g., Figure 17 the first intermediate insulating layer ILD1) may cover the first conductive pattern 2200 and may be disposed on the first gate insulating layer. The first intermediate insulating layer may include an insulating material.

[0094] The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be substantially the same as the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 described with reference to Figure 3 For example, in an embodiment, the gate electrode 2220 may correspond to the gate terminal of the first transistor T1 described with reference to Figure 3 In addition, the gate terminal, the first terminal, and the second terminal described with reference to Figure 3 may substantially correspond to the conductive patterns to be described later. However, this correspondence will not be described in detail, and this correspondence will be obvious to those skilled in the art to which the present invention pertains.

[0095] Reference Figure 7 and Figure 8, a second conductive pattern 2300 may be disposed on the first intermediate insulating layer. The second conductive pattern 2300 may include a gate initialization voltage line 2310, a third gate line 2320, a fourth gate line 2330, and a storage capacitor electrode 2340.

[0096] The gate initialization voltage line 2310 may extend in a first direction D1. In an embodiment, the gate initialization voltage line 2310 may provide a gate initialization voltage VINT to the fourth transistor T4. For example, in an embodiment, the gate initialization voltage line 2310 may provide a gate initialization voltage VINT to a second active pattern (e.g., Figure 9 the second active pattern 2400) to be described later.

[0097] The third gate line 2320 may extend in the first direction D1. In an embodiment, the third gate line 2320 may provide a second gate signal GC to the third transistor T3. For example, in an embodiment, the third gate line 2320 may contact a first upper electrode (e.g., Figure 12 the first upper electrode 2530) to be described later.

[0098] The fourth gate line 2330 may extend in the first direction D1. In an embodiment, the fourth gate line 2330 may provide a third gate signal GI to the fourth transistor T4. For example, in an embodiment, the fourth gate line 2330 may contact a second upper electrode (e.g., Figure 12 the second upper electrode 2540) to be described later.

[0099] The storage capacitor electrode 2340 may extend in the first direction D1. In an embodiment, the storage capacitor electrode 2340 may form a storage capacitor CST together with the gate electrode 2220. To this end, the storage capacitor electrode 2340 may overlap with the gate electrode 2220, and a high power voltage ELVDD may be provided to the storage capacitor electrode 2340.

[0100] In an embodiment, an opening H exposing the upper surface of the gate electrode 2220 may be defined in the storage capacitor electrode 2340. Through the opening H, the gate electrode 2220 may contact a first connection pattern (e.g., Figure 12 the first connection pattern 2520) to be described later. For example, in an embodiment, through the opening H, the gate terminal of the first transistor T1 may be electrically connected to the first terminal of the third transistor T3.

[0101] For example, in an embodiment, the second conductive pattern 2300 may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material, etc.

[0102] A second intermediate insulating layer (e.g., Figure 17The second intermediate insulating layer (ILD2) may cover the second conductive pattern 2300 and may be disposed on the first intermediate insulating layer. The second intermediate insulating layer may include an insulating material.

[0103] Reference Figure 9 and Figure 10 , the second active pattern 2400 may be disposed on the second intermediate insulating layer. For example, in an embodiment, the second active pattern 2400 may overlap with the third gate line 2320 and the fourth gate line 2330.

[0104] In an embodiment, the second active pattern 2400 may be disposed in a different layer from the first active pattern 2100 and may not overlap with the first active pattern 2100. In other words, the second active pattern 2400 may be spaced apart from the first active pattern 2100. For example, in an embodiment, the first active pattern 2100 may include a silicon semiconductor, and the second active pattern 2400 may include an oxide semiconductor.

[0105] In an embodiment, the pixel structure PX may include a first transistor T1, a second transistor T2, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 that are silicon-based semiconductors, and may include a third transistor T3 and a fourth transistor T4 that are oxide-based semiconductors. For example, in an embodiment, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be PMOS transistors, and the third transistor T3 and the fourth transistor T4 may be NMOS transistors.

[0106] The second gate insulating layer (e.g., Figure 17 the second gate insulating layer GI2 in

[0107] Reference Figure 11 and Figure 12 ) may cover the second active pattern 2400 and may be disposed on the second intermediate insulating layer. The second gate insulating layer may include an insulating material.

[0108] In an embodiment, the third connection pattern 2510 may provide an anode initialization voltage AINT to the seventh transistor T7. For example, in an embodiment, the third connection pattern 2510 may provide an anode initialization voltage AINT to a fourth connection pattern (e.g., Figure 13 the fourth connection pattern 2630 in

[0109] In an embodiment, the third connection pattern 2510 may overlap with the first gate line 2210, the fourth gate line 2330, and a vertical connection line (e.g., Figure 15 the vertical connection line 2720) to be described later.

[0110] In an embodiment, the first connection pattern 2520 may electrically connect the gate terminal of the first transistor T1 and the first terminal of the third transistor T3. To this end, the first connection pattern 2520 may contact the gate electrode 2220 and a second connection pattern (e.g., Figure 13 the second connection pattern 2660) to be described later. For example, in an embodiment, the gate electrode 2220, the opening H of the storage capacitor electrode 2340, and the first connection pattern 2520 may overlap each other. In other words, the first connection pattern 2520 may overlap with a contact hole. The contact hole may overlap with the opening H of the storage capacitor electrode 2340. The first connection pattern 2520 may contact the gate electrode 2220 through the contact hole.

[0111] In an embodiment, the first upper electrode 2530 may provide the second gate signal GC to the third transistor T3. To this end, the first upper electrode 2530 may contact the third gate line 2320. For example, in an embodiment, the first upper electrode 2530 may overlap with the third gate line 2320 and the second active pattern 2400.

[0112] In an embodiment, the second upper electrode 2540 may provide the third gate signal GI to the fourth transistor T4. To this end, the second upper electrode 2540 may contact the fourth gate line 2330. For example, in an embodiment, the second upper electrode 2540 may overlap with the fourth gate line 2330 and the second active pattern 2400.

[0113] A third intermediate insulating layer (e.g., Figure 17 the third intermediate insulating layer ILD3 in

[0114] may cover the third conductive pattern 2500 and may be disposed on the second gate insulating layer. The third intermediate insulating layer may include an insulating material. Figure 13 and Figure 14 Referring to

[0115] The horizontal connection line 2610 may extend in a first direction D1. In an embodiment, the horizontal connection line 2610 may supply a data voltage DATA to the second transistor T2. To this end, the horizontal connection line 2610 may contact a vertical connection line 2720 and a data line 2710, which will be described later. For example, in an embodiment, the horizontal connection line 2610 may correspond to Figure 2 the first horizontal connection line HFL1 or the second horizontal connection line HFL2.

[0116] In an embodiment, the horizontal connection line 2610 may overlap with the third connection pattern 2510. Accordingly, the area on the plane of the pixel structure PX may be reduced. In addition, the third connection pattern 2510 may overlap with the fourth gate line 2330 and the horizontal connection line 2610. Accordingly, the third connection pattern 2510 may prevent a crosstalk phenomenon that may occur between the fourth gate line 2330 and the horizontal connection line 2610.

[0117] The data voltage pad 2620 may supply the data voltage DATA to the first active pattern 2100. To this end, the data voltage pad 2620 may contact the first active pattern 2100 and a data line, which will be described later. For example, in an embodiment, the data voltage pad 2620 may overlap with the first active pattern 2100 and the data line.

[0118] In an embodiment, the fourth connection pattern 2630 may supply an anode initialization voltage AINT to the seventh transistor T7. For example, in an embodiment, the fourth connection pattern 2630 may supply the anode initialization voltage AINT to the first active pattern 2100. To this end, the fourth connection pattern 2630 may contact the first active pattern 2100.

[0119] In an embodiment, the fourth connection pattern 2630 may overlap with the first gate line 2210, the third gate line 2320, and a vertical connection line (for example, Figure 15 the vertical connection line 2720) which will be described later.

[0120] The gate initialization voltage connection pattern 2640 may supply a gate initialization voltage VINT to the fourth transistor T4. For example, in an embodiment, the gate initialization voltage connection pattern 2640 may supply the gate initialization voltage VINT to the second active pattern 2400. To this end, the gate initialization voltage connection pattern 2640 may contact the gate initialization voltage line 2310 and the second active pattern 2400.

[0121] The shielding pattern 2650 may supply a high power voltage ELVDD to the first active pattern 2100. In an embodiment, the shielding pattern 2650 may supply a high power voltage line (for example, Figure 15The high-power voltage line 2740 is electrically connected to the first active pattern 2100. For example, in an embodiment, the shielding pattern 2650 may extend in the first direction D1 and may contact the high-power voltage line and the first active pattern 2100. To this end, the shielding pattern 2650 may overlap the high-power voltage line and the first active pattern 2100.

[0122] In an embodiment, the shielding pattern 2650 may overlap the vertical connection line and the second gate line 2230. Accordingly, the shielding pattern 2650 may prevent a crosstalk phenomenon that may occur between the vertical connection line and the second gate line 2230.

[0123] In an embodiment, the shielding pattern 2650 may be disposed between the vertical connection line and the first connection pattern 2520. Accordingly, the shielding pattern 2650 may prevent a crosstalk phenomenon that may occur between the vertical connection line and the first connection pattern 2520.

[0124] In an embodiment, the second connection pattern 2660 may electrically connect the gate terminal of the first transistor T1 and the first terminal of the third transistor T3. To this end, the second connection pattern 2660 may contact the second active pattern 2400 and the first connection pattern 2520. For example, in an embodiment, the second connection pattern 2660 may overlap the second active pattern 2400 and the first connection pattern 2520.

[0125] The first pad 2670 may provide an anode initialization voltage AINT to the first electrode (e.g., Figure 17 the first electrode 2810) of the organic light-emitting device OLED to be described later.

[0126] The compensation connection pattern 2680 may electrically connect the second active pattern 2400 and the first active pattern 2100. For example, in an embodiment, the second terminal (e.g., the drain terminal of the third transistor T3) of the third transistor T3 may be connected to the second terminal (e.g., the drain terminal of the first transistor T1) of the first transistor T1 through the compensation connection pattern 2680.

[0127] The first via insulating layer (e.g., Figure 17 the first via insulating layer VIA1 in

[0128] Reference Figure 15 and Figure 16, the fifth conductive pattern 2700 may be disposed on the first via insulating layer. The fifth conductive pattern 2700 may include a data line 2710, a vertical connection line 2720, a second pad 2730, and a high-power voltage line 2740.

[0129] The data line 2710 may extend in the second direction D2. In an embodiment, the data line 2710 may supply a data voltage DATA to the second transistor T2. To this end, the data line 2710 may contact the data voltage pad 2620.

[0130] In an embodiment, the data line 2710 may supply the data voltage DATA from the data driver DDV to the data voltage pad 2620. In this case, the data line 2710 may correspond to Figure 2 the third data line DL3 or the fourth data line DL4. In another embodiment, the data line 2710 may supply the data voltage DATA from the horizontal connection line to the data voltage pad 2620. In this case, the data line 2710 may correspond to Figure 2 the first data line DL1 or the second data line DL2.

[0131] The vertical connection line 2720 may extend in the second direction D2. In an embodiment, the vertical connection line 2720 may supply the data voltage DATA to the second transistor T2. To this end, the vertical connection line 2720 may contact the horizontal connection line 2610. For example, in an embodiment, the vertical connection line 2720 may correspond to Figure 2 the first vertical connection line VFL1 or the second vertical connection line VFL2.

[0132] In an embodiment, the fourth gate line 2330, the third connection pattern 2510, and the vertical connection line 2720 may overlap each other. In addition, the first gate line 2210, the third connection pattern 2510, the fourth connection pattern 2630, and the vertical connection line 2720 may overlap each other. In addition, the third gate line 2320, the fourth connection pattern 2630, and the vertical connection line 2720 may overlap each other.

[0133] In an embodiment, the second gate line 2230, the shielding pattern 2650, and the vertical connection line 2720 may overlap each other.

[0134] The high-power voltage line 2740 may extend in the second direction D2. In an embodiment, the high-power voltage line 2740 may supply a high-power voltage ELVDD to the shielding pattern 2650. To this end, the high-power voltage line 2740 may contact the shielding pattern 2650.

[0135] In an embodiment, the high-power voltage line 2740 may overlap with the second active pattern 2400. For example, in an embodiment, the second active pattern 2400 may include an oxide semiconductor. When the oxide semiconductor is exposed to light, leakage current may be generated through the third transistor T3 and the fourth transistor T4 including the oxide semiconductor. For example, the light may be external light or light generated by the organic light-emitting diode OLED. Since the high-power voltage line 2740 overlaps with the second active pattern 2400, the second active pattern 2400 may not be exposed to light.

[0136] Figure 17 is a cross-sectional view taken along Figure 16 line I-I' of.

[0137] Refer to Figures 4 to 17 , Figure 17 The pixel structure PX illustrated in may have a structure in which the substrate SUB, the buffer layer BUF, the first active pattern 2100, the first gate insulating layer GI1, the first gate line 2210, the first intermediate insulating layer ILD1, the fourth gate line 2330, the second intermediate insulating layer ILD2, the second gate insulating layer GI2, the third connection pattern 2510, the third intermediate insulating layer ILD3, the horizontal connection line 2610, the data voltage pad 2620, the first via insulating layer VIA1, the data line 2710, the vertical connection line 2720, the second via insulating layer VIA2, the pixel defining layer PDL, the first electrode 2810, the emission layer 2820, and the second electrode 2830 are sequentially disposed therein. The first electrode 2810, the emission layer 2820, and the second electrode 2830 may constitute the organic light-emitting structure 2800. For example, in an embodiment, the organic light-emitting structure 2800 may correspond to the organic light-emitting diode OLED described above.

[0138] In an embodiment, the horizontal connection line 2610 may overlap with the vertical connection line 2720. The horizontal connection line 2610 may be electrically connected to the vertical connection line 2720. The horizontal connection line 2610 may be electrically connected to the vertical connection line 2720 through a contact hole defined by etching a first portion of the first via insulating layer VIA1. Additionally, in an embodiment, the data voltage pad 2620 may overlap with the data line 2710. The data voltage pad 2620 may be electrically connected to the data line 2710. The data voltage pad 2620 may be electrically connected to the data line 2710 through a contact hole defined by etching a second portion of the first via insulating layer VIA1.

[0139] The fourth conductive pattern 2600 and the fifth conductive pattern 2700 may be electrically connected to each other through contact holes. A signal such as a data voltage DATA may flow in a first direction D1 and a second direction D2. By doing so, the fourth conductive pattern 2600 and the fifth conductive pattern 2700 may replace conventional fan-out wirings. As a result, a non-display area (e.g., a dead zone, a bezel area, etc.) of the display device 20 may be reduced.

[0140] Figure 18 is a cross-sectional view taken along Figure 16 line II-II' of.

[0141] Refer to Figures 4 to 18 , Figure 18 The pixel structure PX illustrated in may have a structure in which the substrate SUB, the buffer layer BUF, the first active pattern 2100, the first gate insulating layer GI1, the first gate line 2210, the second gate line 2230, the first intermediate insulating layer ILD1, the third gate line 2320, the fourth gate line 2330, the storage capacitor electrode 2340, the second intermediate insulating layer ILD2, the second gate insulating layer GI2, the first upper electrode 2530, the second upper electrode 2540, the third intermediate insulating layer ILD3, the first pad 2670, the fourth connection pattern 2630, the shielding pattern 2650, the first via insulating layer VIA1, the second pad 2730, the high power voltage line 2740, the second via insulating layer VIA2, the pixel defining layer PDL, the first electrode 2810, the emission layer 2820, and the second electrode 2830 are sequentially disposed therein.

[0142] In an embodiment, the third gate line 2320 and the first upper electrode 2530 may overlap. The third gate line 2320 and the first upper electrode 2530 may be electrically connected. The third gate line 2320 and the first upper electrode 2530 may be electrically connected through a contact hole defined by etching a first portion of the second intermediate insulating layer ILD2 and a first portion of the second gate insulating layer GI2. Additionally, in an embodiment, the fourth gate line 2330 and the second upper electrode 2540 may overlap. The fourth gate line 2330 and the second upper electrode 2540 may be electrically connected. The fourth gate line 2330 and the second upper electrode 2540 are electrically connected through a contact hole defined by etching a second portion of the second intermediate insulating layer ILD2 and a second portion of the second gate insulating layer GI2.

[0143] In an embodiment, the first pad 2670 and the second pad 2730 may overlap. The first pad 2670 and the second pad 2730 may be electrically connected. The first pad 2670 and the second pad 2730 may be electrically connected through a contact hole defined by etching a third portion of the first via insulating layer VIA1. Additionally, in an embodiment, the shielding pattern 2650 and the high-power voltage line 2740 may overlap. The shielding pattern 2650 and the high-power voltage line 2740 may be electrically connected. The shielding pattern 2650 and the high-power voltage line 2740 may be electrically connected through a contact hole defined by etching a fourth portion of the first via insulating layer VIA1.

[0144] In this way, since the third gate line 2320 and the first upper electrode 2530 are electrically connected, and the fourth gate line 2330 and the second upper electrode 2540 are electrically connected, the gate signal can flow through the second conductive pattern 2300 and the third conductive pattern 2500. By doing so, a space for arranging the third connection pattern 2510 and the first connection pattern 2520 can be ensured. Additionally, since the space is ensured, a plurality of lines, patterns, and pads extending in the first direction D1 and the second direction D2 can be provided in the fourth conductive pattern 2600 and the fifth conductive pattern 2700. As a result, the non-display area (e.g., dead zone, border area, etc.) of the display device 20 can be reduced.

[0145] Embodiments of the present invention can be applied to a display device and an electronic device including the display device. For example, in an embodiment, the present invention can be applied to a smart phone, a cellular phone, a video phone, a smart tablet, a smart watch, a tablet personal computer (PC), a car navigation system, a television, a computer monitor, a laptop computer, a head-mounted display device, an MP3 player, etc.

[0146] The foregoing is an illustration of the embodiments and should not be construed as a limitation of the embodiments. Although the embodiments have been described, those skilled in the art will readily understand that many modifications are possible in the embodiments without substantially departing from the novel teachings and advantages of the present invention. Therefore, all such modifications are intended to be included within the scope of the present invention as defined in the claims. Accordingly, it should be understood that the foregoing is an illustration of the embodiments and should not be construed as limited to the disclosed embodiments.

Claims

1. A display device, comprising: A first active pattern; A first conductive pattern, comprising: A gate electrode overlapping with the first active pattern; A first gate line overlapping with the first active pattern and extending in a first direction; and A second gate line extending in the first direction; A second conductive pattern disposed on the first conductive pattern and comprising: A third gate line extending in the first direction; and A fourth gate line extending in the first direction; A second active pattern disposed on the second conductive pattern and comprising a material different from that of the first active pattern; and A third conductive pattern disposed on the second active pattern and comprising: A first upper electrode overlapping with the third gate line and electrically connected to the third gate line; and A second upper electrode overlapping with the fourth gate line and electrically connected to the fourth gate line.

2. The display device according to claim 1, further comprising: A fourth conductive pattern disposed on the third conductive pattern and comprising a horizontal connection line extending in the first direction and to which a first data voltage is applied.

3. The display device according to claim 2, further comprising: A fifth conductive pattern disposed on the fourth conductive pattern, and comprising: a data line extending in a second direction intersecting with the first direction and to which the first data voltage is applied, a vertical connection line extending in the second direction and to which the first data voltage is applied, and a high power voltage line extending in the second direction and to which a high power voltage is applied.

4. The display device according to claim 3, wherein, The fourth conductive pattern further comprises a data voltage pad, and wherein the data line overlaps with the data voltage pad and is electrically connected to the data voltage pad.

5. The display device according to claim 3, wherein, The vertical connection line overlaps with the horizontal connection line and is electrically connected to the horizontal connection line.

6. The display device according to claim 3, wherein, The fourth conductive pattern further comprises a shielding pattern, and wherein the high power voltage line overlaps with the shielding pattern and is electrically connected to the shielding pattern.

7. The display device according to claim 1, wherein, A light emission control signal is applied to the second gate line.

8. The display device according to claim 1, wherein, The second conductive pattern further comprises a gate initialization voltage line.

9. The display device according to claim 8, further comprising: A fourth conductive pattern disposed on the third conductive pattern, wherein the fourth conductive pattern further comprises a gate initialization voltage connection pattern, wherein the gate initialization voltage connection pattern overlaps with the gate initialization voltage line and is electrically connected to the gate initialization voltage line, and wherein the gate initialization voltage connection pattern overlaps with the second active pattern and is electrically connected to the second active pattern.

10. The display device according to claim 1, wherein, The first active pattern comprises a silicon semiconductor, and the second active pattern comprises an oxide semiconductor.

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