Memory cell, semiconductor device and method for forming the same

Abstract

A memory cell includes a thin film transistor located above a semiconductor substrate. The thin film transistor includes: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium compound containing a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. Embodiments of the present application also provide a semiconductor device and a method for forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to memory cells, semiconductor devices, and methods of forming the same. Background Art

[0002] Semiconductor memory is used in integrated circuits for electronic applications, such as radios, televisions, cell phones, and personal computing devices. Semiconductor memory includes two major categories. One is volatile memory; the other is non-volatile memory. Volatile memory includes random access memory (RAM), which can be further divided into two subcategories, namely static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they will lose the information they store when there is no power.

[0003] On the other hand, non-volatile memory can save the data stored on it. One type of non-volatile semiconductor memory is ferroelectric random access memory (FeRAM or FRAM). Its advantages are fast write / read speed and small size. Summary of the invention

[0004] In some embodiments, a memory cell includes: a thin film transistor located above a semiconductor substrate, the thin film transistor including: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-containing compound, and the hafnium-containing compound including a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line.

[0005] In some embodiments, a device includes: a semiconductor substrate; a first memory cell located above the semiconductor substrate, the first memory cell including a first thin film transistor, wherein the first thin film transistor includes: a first portion of a ferroelectric material, the first portion of the ferroelectric material is on a side wall of a first word line, and the ferroelectric material includes a rare earth metal; and a first channel region located on the side wall of the ferroelectric material, the first channel region includes an oxide semiconductor material; and a second memory cell located above the first memory cell.

[0006] In some embodiments, a method includes: patterning a first trench extending through a first conductive line; depositing a ferroelectric (FE) material along sidewalls and a bottom surface of the first trench, wherein depositing the FE material includes an atomic layer deposition (ALD) process to deposit a hafnium-containing compound, and wherein the hafnium-containing compound also includes a rare earth metal; and depositing an oxide semiconductor (OS) layer over the FE material, the OS layer extending along the sidewalls and the bottom surface of the first trench.

[0007] Embodiments of the present application provide a memory array gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1A , Figure 1B and Figure 1C A perspective view, a circuit diagram, and a top view of a memory array according to some embodiments are shown.

[0010] Figure 2 , Figure 3A , Figure 3B , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 9C , Fig.9D , Fig.9E , Fig.9F , Figure 9G , Fig. 10A , Fig. 10B , Fig.11 , Fig.12 , Fig.13 , Fig.14A , Fig. 14B , Fig. 14C , Fig.15A , Fig. 15B , Fig. 15C , Fig.16A , Fig. 16B , Fig. 16C , Fig.17A , Fig. 17B , Fig. 17C , Fig.18A , Fig.18B , Fig.18C , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26A , Fig.26B , Fig. 27 , Fig.28A , Fig.28B , Fig.28C and Fig.28D Various views of fabricating a memory array are shown in accordance with some embodiments.

[0011] Fig.29 , Fig.30 and Fig.31 Various views of a memory array are shown in accordance with some embodiments.

[0012] Fig.32 A table showing the ionic radii and preferred phases of various elements.

[0013] Fig.33 Phase diagrams of examples of hafnium-containing compounds are shown. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be similarly interpreted accordingly.

[0016] Various embodiments provide a 3D memory array having a plurality of vertically stacked memory cells. Each memory cell includes a thin film transistor (TFT) having a word line region used as a gate electrode, a bit line region used as a first source / drain electrode, and a source line region used as a second source / drain electrode. Each TFT also includes a ferroelectric (FE) material (e.g., as a gate dielectric layer) and an oxide semiconductor (OS) channel region.

[0017] Figure 1A , Figure 1B and Figure 1C An example of a memory array according to some embodiments is shown. Figure 1A An example of a portion of a memory array 200 is shown in a three-dimensional view; Figure 1B A circuit diagram of a memory array 200 is shown; Figure 1C A top view of a memory array 200 is shown according to some embodiments. The memory array 200 includes a plurality of memory cells 202 that may be arranged in a grid of rows and columns. The memory cells 202 may also be stacked vertically to provide a three-dimensional memory array, thereby increasing device density. The memory array 200 may be disposed in a back end of line (BEOL) of a semiconductor die. For example, the memory array may be disposed in an interconnect layer of a semiconductor die, such as above one or more active devices (e.g., transistors) formed on a semiconductor substrate.

[0018] In some embodiments, the memory array 200 is a flash memory array, such as a NOR flash memory array, etc. Each memory cell 202 may include a thin film transistor (TFT) 204 having a ferroelectric (FE) material 90 as a gate dielectric. In some embodiments, the gate of each TFT 204 is electrically coupled to a corresponding word line (e.g., conductive line 72), the first source / drain region of each TFT 204 is electrically coupled to a corresponding bit line (e.g., conductive line 106), and the second source / drain region of each TFT 204 is electrically coupled to a corresponding source line (e.g., conductive line 108), which electrically couples the second source / drain region to ground. The memory cells 202 in the same horizontal row of the memory array 200 may share a common word line, and the memory cells in the same vertical column of the memory array 200 may share a common source line and a common bit line.

[0019] The memory array 200 includes a plurality of vertically stacked conductive lines 72 (eg, word lines) with a dielectric layer 52 disposed between adjacent conductive lines 72. The conductive lines 72 extend in a direction parallel to a major surface of an underlying substrate (in a direction parallel to a major surface of an underlying substrate). Figure 1A and Figure 1B (not shown in the figure). The conductive line 72 may have a stepped structure, such that the lower conductive line 72 is longer than the upper conductive line 72 and extends laterally beyond the end point of the upper word line 72. Figure 1A , multiple stacked layers of conductive lines 72 are shown, wherein the topmost conductive line 72 is the shortest and the bottommost conductive line 72 is the longest. The respective lengths of conductive lines 72 may increase in a direction toward the underlying substrate. In this manner, a portion of each of conductive lines 72 may be accessed from above memory array 200, and conductive contact may be made to the exposed portion of each of conductive lines 72.

[0020] The memory array 200 also includes a plurality of conductive lines 106 (e.g., bit lines) and conductive lines 108 (e.g., source lines). The conductive lines 106 and 108 may each extend in a direction perpendicular to the conductive lines 72. The dielectric material 98 is disposed between and isolates adjacent conductive lines 106 and 108. The conductive line pairs 106 and 108, together with the intersecting conductive lines 72, define the boundaries of each memory cell 202, and the dielectric material 102 is disposed between and isolates adjacent conductive line pairs 106 and 108. In some embodiments, the conductive line 108 is electrically coupled to ground. Although Figure 1A A particular arrangement of conductive lines 106 relative to conductive lines 108 is shown, but it should be understood that in other embodiments, the arrangement of conductive lines 106 and 108 may be reversed.

[0021] The memory array 200 may further include an oxide semiconductor (OS) layer 92. The OS layer 92 may provide a channel region for the TFT 204 of the memory cell 202. For example, when an appropriate voltage (e.g., higher than a corresponding threshold voltage (V th ), the area of ​​OS layer 92 that intersects conductive line 72 may allow current to flow from conductive line 106 to conductive line 108 (eg, in the direction indicated by arrow 206).

[0022] FE material 90 is disposed between conductive line 72 and OS layer 92, and FE material 90 may provide gate dielectric for TFT 204. Accordingly, memory array 200 may also be referred to as a ferroelectric random access memory (FERAM) array. In some embodiments, FE material 90 may be a hafnium-based compound including a rare earth metal. Rare earth metals may have an ionic radius greater than that of hafnium. For example, rare earth metals may be lanthanum, yttrium, gadolinium, cerium, strontium, and the like. Including rare earth metals may allow FE material 90 to achieve an orthorhombic crystal structure with a relatively low temperature annealing process (e.g., at a temperature of about 400° C. or less). For example, rare earth dopants in FE material 90 may expand the composition range of a stable orthorhombic phase of FE layer 90. Therefore, FE layer 90 including embodiment rare earth metals provides improved low thermal budget, back-end of line (BEOL) integration for memory array 200. In addition, by including rare earth metals in FE material 90, the inherent fatigue performance and durability of FE material 90 may be improved. For example, in experimental data, the durability of the FE material 90 can be improved by at least ten times compared to the FE material without the embodiment rare earth metal, and the FE material 90 can allow at least 10 8 poling cycles without significant degradation of the FE material 90. Thus, various embodiments improve the reliability and ease of manufacturability of the resulting device.

[0023] The FE material 90 can be polarized in one of two different directions, and the polarization direction can be changed by applying an appropriate voltage difference across the FE material 90 and generating an appropriate electric field. The polarization can be relatively localized (e.g., generally contained within each boundary of the memory cell 202), and a continuous region of the FE material 90 can extend across multiple memory cells 202. Depending on the polarization direction of a particular region of the FE material 90, the threshold voltage of the corresponding TFT 204 changes and a digital value (e.g., 0 or 1) can be stored. For example, when a region of the FE material 90 has a first electrical polarization direction, the corresponding TFT 204 can have a relatively low threshold voltage, and when a region of the FE material 90 has a second electrical polarization direction, the corresponding TFT 204 can have a relatively high threshold voltage. The difference between the two threshold voltages can be referred to as a threshold voltage shift. A larger threshold voltage shift can make it easier (e.g., less prone to error) to read the digital value stored in the corresponding memory cell 202.

[0024] In order to perform a write operation on a specific memory cell 202, a write voltage is applied to the region of the FE material 90 corresponding to the memory cell 202. For example, the write voltage can be applied by applying appropriate voltages to the corresponding conductive line 72 (e.g., word line) and the corresponding conductive line 106 / 108 (e.g., bit line / source line). By applying the write voltage to the portion of the FE material 90, the polarization direction of the region of the FE material 90 can be changed. Therefore, the corresponding threshold voltage of the corresponding TFT 204 can also be switched from a low threshold voltage to a high threshold voltage (or vice versa), and a digital value can be stored in the memory cell 202. Because the conductive line 72 intersects the conductive lines 106 and 108, individual memory cells 202 can be selected for write operations.

[0025] To perform a read operation on a memory cell 202, a read voltage (a voltage between a low threshold voltage and an upper threshold voltage) is applied to a corresponding conductive line 72 (e.g., a word line). Depending on the polarization direction of the corresponding region of FE material 90, the TFT 204 of the memory cell 202 may or may not be conducting. As a result, the conductive line 106 may or may not be discharged through the conductive line 108 (e.g., a source line coupled to ground), and the digital value stored in the memory cell 202 may be determined. Because the conductive line 72 intersects the conductive lines 106 and 108, an individual memory cell 202 may be selected for a read operation.

[0026] Figure 1AReference cross sections of memory array 200 used in subsequent figures are also shown. Cross section BB' is along the longitudinal axis of conductive line 72 and in a direction, for example, parallel to the current flow direction of TFT 204. Cross section CC' is perpendicular to cross section BB' and parallel to the longitudinal axis of conductive line 72. Cross section CC' extends through conductive line 106. Cross section D-D' is parallel to cross section CC' and extends through dielectric material 102. For clarity, subsequent figures refer to these reference cross sections.

[0027] Figures 2 to 28B 2 are various views of intermediate stages of manufacturing memory array 200 provided in some embodiments. Figures 2 to 8B In some embodiments, a multilayer stack 58 is formed and trenches are formed in the multilayer stack 58 to define conductive lines 72. The conductive lines 72 may correspond to word lines in the memory array 200, and the conductive lines 72 may also provide gate electrodes for the resulting TFTs of the memory array 200. The three-dimensional view shows Figure 3A and Fig. 8A . Figure 2 , Figure 3B , Figure 4 , Figure 5 , Figure 6 , Figure 7 as well as Figure 8B is along Figure 1A The reference section CC' shown in FIG.

[0028] exist Figure 2 In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped or undoped (e.g., with a p-type or n-type dopant). The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide, aluminum indium arsenide, gallium arsenide, indium arsenide, indium phosphide and / or indium gallium arsenide, or a combination thereof.

[0029] Figure 2Also shown are circuits that may be formed on the substrate 50. These circuits include active devices (e.g., transistors) at the top surface of the substrate 50. The transistor may include a gate dielectric layer 202 on the top surface of the substrate 50 and a gate electrode 204 on the gate dielectric layer 202. Source / drain regions 206 are disposed on the substrate 50 on opposite sides of the gate dielectric layer 202 and the gate electrode 204. Gate spacers 208 are formed along the sidewalls of the gate dielectric layer 202 and separate the source / drain regions 206 from the gate electrode 204 by an appropriate lateral distance. In some embodiments, the transistor may be a planar field effect transistor (FET), a fin field effect transistor (finFET), a nano field effect transistor (nanoFET), etc.

[0030] The first ILD 210 surrounds and isolates the source / drain regions 206, the gate dielectric layer 202, and the gate electrode 204, and the second ILD 212 is above the first ILD 210. The source / drain contacts 214 extend through the second ILD 212 and the first ILD 210 and are electrically coupled to the source / drain regions 206, and the gate contact 216 extends through the second ILD 212 and is electrically coupled to the gate electrode 204. An interconnect structure 220 including one or more stacked dielectrics 224 and conductive features 222 formed in the one or more dielectrics 224 is above the second ILD 212, the source / drain contacts 214, and the gate contact 216. Although Figure 2 Two stacked dielectrics 224 are shown, but it should be understood that the interconnect structure 200 may include any number of dielectrics 224 having conductive features 222 disposed therein. The interconnect structure 220 may be electrically connected to the gate contact 216 and the source / drain contacts 214 to form a functional circuit. In some embodiments, the functional circuit formed by the interconnect structure 220 may include a logic circuit, a memory circuit, a sense amplifier, a controller, an input / output circuit, an image sensor circuit, etc., or a combination thereof. Although Figure 2 Transistors formed on substrate 50 are discussed, but other active devices (eg, diodes, etc.) and / or passive devices (eg, capacitors, resistors, etc.) may also be formed as part of the functional circuits.

[0031] exist Figure 3A and Figure 3B in Figure 2The multilayer stack 58 is formed on the structure of the substrate 50. For the purpose of simplicity and clarity, the substrate 50, transistors, ILDs, and interconnect structure 120 may be omitted from subsequent figures. Although the multilayer stack 58 is shown as contacting the dielectric 224 of the interconnect structure 220, any number of intermediate layers may be disposed between the substrate 50 and the multilayer stack 58. For example, one or more additional interconnect layers including conductive features in an insulating layer (e.g., a low-k dielectric) may be disposed between the substrate 50 and the multilayer stack 58. In some embodiments, the conductive features may be patterned to provide power, ground, and / or signal lines for active devices on the substrate 50 and / or the memory array 200 (see Figure 1A and 1B ).

[0032] The multilayer stack 58 includes alternating conductive line layers 72A-D (collectively referred to as conductive layers 54) and dielectric layers 52A-C (collectively referred to as dielectric layers 52). The conductive layers 54 may be patterned in a subsequent step to define conductive lines 72 (e.g., word lines). The conductive layers 54 may include conductive materials such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, and the like, and the dielectric layers 52 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, and the like. The conductive layers 54 and the dielectric layers 52 may be formed using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), and the like, respectively. Although Figure 3A and Figure 3B A particular number of conductive layers 54 and dielectric layers 52 are shown, but other embodiments may include different numbers of conductive layers 54 and dielectric layers 52 .

[0033] exist Figure 4 In the embodiment of the present invention, a hard mask 80 and a photoresist 82 are deposited on the multilayer stack 58. The hard mask layer 80 may include, for example, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. For example, the photoresist 82 may be formed by using a spin coating technique.

[0034] exist Figure 5 In the embodiment of the present invention, the photoresist 82 is patterned to form the groove 86. The photoresist can be patterned using acceptable photolithography techniques. For example, the photoresist 82 is exposed to light for patterning. After the exposure process, the photoresist 82 can be developed to remove the exposed or unexposed portions of the photoresist, depending on whether a negative or positive resist is used, thereby defining the patterning that forms the groove 86.

[0035] exist Figure 6In the embodiment of the present invention, the pattern of the photoresist 82 is transferred to the hard mask 84 using an acceptable etching process (such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof). The etching can be anisotropic. Thus, a trench 86 extending through the hard mask 84 is formed. For example, the photoresist 82 can be removed by an ashing process.

[0036] exist Figure 7 In the embodiment of the present invention, the pattern of hard mask 84 is transferred to multilayer stack 58 using one or more acceptable etching processes (such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof). The etching process can be anisotropic. Thus, trenches 86 and conductive lines 72 (e.g., word lines) extending through multilayer stack 58 are formed from conductive layer 54. Adjacent conductive lines 72 can be separated from each other by etching trenches 86 through conductive layer 54. Subsequently, in Fig. 8A and Figure 8B In the embodiment of the present invention, the hard mask 84 may be removed by an acceptable process such as a wet etching process, a dry etching process, a planarization process, a combination thereof, or the like.

[0037] FIG. 9A to FIG. 14C The formation and patterning of the channel region for TFT 204 in trench 86 is shown (see Figure 1B ). Displayed in 3D Fig.9A , Fig. 10A and Fig.14A .exist Fig. 9B , Fig. 9C , Fig.9D , Fig. 10B , Fig.11 , Fig.12 , Fig.13 and Fig. 14B In, along Figure 1A Line CC' provides a cross-sectional view. Fig. 14C The corresponding top view of the TFT structure is shown.

[0038] exist Fig.9A and Fig. 9B , FE material 90 is conformally deposited in trench 86. FE material 90 may have a material that can be switched between two different polarization directions by applying an appropriate voltage difference across FE material 90. For example, the polarization of FE material 90 may be changed due to an electric field generated by applying a voltage difference.

[0039] For example, the FE material 90 may be a high-k dielectric material, such as a hafnium (Hf)-based dielectric material, etc. In some embodiments, the FE material 90 is a hafnium-containing compound, such as hafnium zirconium oxide (HfZnO), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium cerium oxide (HfCeO), hafnium oxide (HfO), hafnium gadolinium oxide (HfGdO), hafnium silicon oxide (HfSiO), hafnium zirconium lanthanum oxide (HfZrLaO), hafnium zirconium gadolinium oxide (HfZrGdO), hafnium zirconium yttrium oxide (HfZrYO), hafnium zirconium cerium oxide (HfZrCeO), hafnium zirconium strontium oxide (HfZrSrO), etc. For example, the hafnium-containing compound may further include a rare earth metal, such as a rare earth metal having an ionic radius greater than that of hafnium. In some embodiments, the rare earth metal may be cerium (Ce), yttrium (Y), gadolinium (Gd), lanthanum (La), strontium (Sr), or the like. Fig.32 A table 300 is provided that shows the ionic radius of various elements and the corresponding preferred phase (e.g., tetragonal (t) or tetragonal / cubic (t / c)) of each element. As shown, rare earth metals having higher ionic radii than hafnium can have both tetragonal and cubic (t / c) preferred phases. By including these rare earth metals having a preferred t / c phase in the hafnium-containing compound of the FE material 90, an orthorhombic lattice structure can be achieved in the FE material 90 at a relatively low annealing temperature (e.g., a temperature of about 400° C. or less). For example, Fig.33 A phase diagram 302 of hafnium dioxide (HfO2), zirconium dioxide (ZrO2), and rare earth metal oxides (ZrO2) is shown. Fig.33 In the embodiment, the composition range 304 of the orthorhombic phase is relatively large, and may be greater than the orthorhombic composition range of the hafnium-based compound without the rare earth metal of the embodiment. By including the rare earth metal, the orthorhombic lattice structure in the FE material 90 may be relatively easily achieved (e.g., at a lower temperature), and the FE material 90 may be formed within a relatively low thermal budget of the BEOL process (e.g., at a temperature that does not damage the front end of line (FEOL) features, such as active devices formed on the substrate 50).

[0040] In some embodiments, the FE material 90 is formed using an ALD process. Fig. 9C , Fig. 9C , Fig.9E and Fig.9FA detailed view of a FE material 90 during an ALD process according to some embodiments is shown. The ALD process may include forming a plurality of monolayers 90A-C, wherein each monolayer has a thickness of one molecule. Monolayer 90A may be a monolayer of a rare earth metal oxide, such as a rare earth metal oxide having an ionic radius greater than that of hafnium. In some embodiments, monolayer 90A is CeO, YO, GdO, LaO, SrO, etc. Monolayer 90B may be a monolayer of zirconium dioxide (ZrO2), etc., while monolayer 90C may be a monolayer of hafnium dioxide (HfO2), etc. The material of each monolayer 90A, 90B, 90C may be formed by flowing one or more appropriate precursors into the ALD deposition chamber in the form of a groove 86. For example, to form lanthanum oxide, La(fAMD)3, etc. can be flowed into the ALD chamber as a precursor; to form yttrium oxide, Y(CpBut)3, etc. can be flowed into the ALD chamber as a precursor; to form gadolinium oxide, Gd(DPDMG)3, etc. can be flowed into the ALD chamber as a precursor; to form cerium oxide, Ce(iPrCp)2(N-iPr-amd), etc. can be flowed into the ALD chamber as a precursor; and to form yttrium oxide, Y(CpBut)3, etc. can be flowed into the ALD chamber as a precursor. Other precursors can be used in other embodiments.

[0041] Monolayers 90A, 90B, and 90C may be deposited in any suitable order. For example, Fig. 9C An embodiment of depositing monolayers 90A, 90B, and 90C in a repeating pattern of monolayer 90C, monolayer 90B deposited directly on monolayer 90C, and monolayer 90A deposited directly on monolayer 90B is shown. For example, Fig.9D An embodiment of depositing monolayers 90A, 90B, and 90C in a repeating pattern of monolayer 90C, monolayer 90A deposited directly on monolayer 90C, and monolayer 90B deposited directly on monolayer 90A is shown. As another example, Fig.9E An embodiment of depositing monolayers 90A, 90B, and 90C in a repeating pattern of monolayer 90A, monolayer 90C deposited directly on monolayer 90A, and monolayer 90B deposited directly on monolayer 90C is shown. As yet another example, Fig.9D Embodiments of forming a plurality of monolayers 90C, forming a plurality of monolayers 90B directly on the plurality of monolayers 90C, and forming a plurality of monolayers 90A directly on the plurality of monolayers 90B are shown. FIG. 9C to FIG. 9F The specific number and pattern of monolayers 90A, 90B, and 90C are shown for illustration purposes only. In other embodiments, other patterns and / or other numbers of monolayers 90A, 90B, and 90C may be formed.

[0042] In some embodiments, the respective amounts of each of the monolayers 90A, 90B, and 90C may be selected so that the FE material 90 is within the composition range of its orthorhombic phase (e.g., in some embodiments, Fig.33 The range 304 of ). For example, the molar percentage of zirconium in the FE layer 90 may be in the range of about 40% to about 70%, and the molar percentage of the rare earth metal in the FE layer 90 may be in the range of about 1% to about 10%. The molar percentage of the elements in the FE layer 90 may be controlled by forming an appropriate amount of each of the monolayers 90A, 90B, or 90C. By forming the FE material 90 having the above-mentioned composition, the FE material 90 may have an orthorhombic lattice structure after annealing. It has been observed that when the amount of various elements (e.g., rare earth, zirconium and / or rare earth metal) is outside the above-mentioned range, the FE material 90 may not have an orthorhombic lattice structure after annealing.

[0043] The annealing process may be performed after depositing various monolayers (eg, monolayers 90A, 90B, and 90C). Due to the annealing process, the FE material 90 may have a crystal structure with an orthorhombic lattice. Figure 9G A ferroelectric phase hafnium zirconium rare earth metal oxide produced by an annealing process is shown. The annealing temperature can be performed at about 400°C or lower. By including a rare earth metal (e.g., having a larger ionic radius than hafnium) in the FE material 90, an orthorhombic lattice structure can still be obtained in the FE material 90 annealed at a relatively low temperature. Therefore, the BEOL integration of the memory array 200 can be improved. In addition, it has been observed that by including a rare earth metal in the FE material 90, the durability of the FE material 90 can be improved by ten times or more. For example, a 10 8 or more polarization cycles without significant degradation of the FE material 90.

[0044] exist Fig. 10A and Fig. 10B In the embodiment, the OS layer 92 is conformally deposited in the trench 86 on the FE material 90. The OS layer 92 includes a substrate suitable for a TFT (e.g., TFT 204, see Figure 1A ) provides a material for the channel region, such as zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium tin oxide (ITO), combinations thereof, etc. The OS layer 92 may be deposited by CVD, PVD, ALD, PECVD, etc. The OS layer 92 may extend along the sidewalls and bottom surface of the trench 86 on the FE layer 90. After depositing the OS layer 92, an annealing step in an oxygen-related environment (e.g., in a temperature range of about 300° C. to about 450° C.) may be performed to activate charge carriers of the OS layer 92.

[0045] exist Fig.11In the embodiment of the present invention, a dielectric layer 98A is deposited in trench 86 above OS layer 92. Dielectric layer 98A may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. Dielectric layer 98A may extend along the sidewalls and bottom surface of trench 86 above OS layer 92.

[0046] exist Fig.12 In the embodiment of the present invention, the bottom of the dielectric layer 98A in the trench 86 is removed, for example, using a combination of photolithography and etching. The etching can be any feasible etching process, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching can be anisotropic.

[0047] Then, as Fig.12 As shown, dielectric layer 98A may be used as an etching mask to etch through the bottom of OS layer 92 in trench 86. Etching may be any feasible etching process, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching may be anisotropic. Etching OS layer 92 may expose portions of FE material 90 on the bottom surface of trench 86. Thus, portions of OS layer 92 on opposite sidewalls of trench 86 may be separated from each other, which improves isolation between memory cells 202 of memory array 200 (see Figure 1A ).

[0048] exist Fig.13 In the embodiment of the present invention, additional dielectric material 98B may be deposited to fill the remaining portion of trench 86. Dielectric material 98B may have the same material composition as dielectric layer 98A and may be formed using the same process as dielectric layer 98A. Dielectric material 98B and dielectric layer 98A may be collectively referred to as dielectric material 98 hereinafter.

[0049] exist FIG. 14A to FIG. 14C In the embodiment of the present invention, a removal process is then applied to the dielectric material 98, the OS layer 92, and the FE material 90 to remove excess material on the multilayer stack 58. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch back process, or a combination thereof may be used. The planarization process exposes the multilayer stack 58 so that after the planarization process is completed, the top surface of the multilayer stack 58 is flat. Fig. 14C Shown Fig.14A Corresponding top view of the structure shown.

[0050] FIG. 15A to FIG. 18C An intermediate step is shown in fabricating conductive lines 106 and 108 (eg, source lines and bit lines) in memory array 200. Conductive lines 106 and 108 may extend in a direction perpendicular to conductive lines 72 so that individual cells of memory array 200 may be selected for read and write operations. FIG. 15A to FIG. 18C, the figures ending with "A" show the 3D view. Figures 15A to 18C In the diagram, the diagram ending with "B" shows the top-down view, and the diagram ending with "C" shows the top-down view. Figure 1A Corresponding cross-sectional view of line CC'.

[0051] exist Fig.15A , Fig. 15B and Fig. 15C In the embodiment, trenches 100 are patterned through the OS layer 92 and the dielectric material 98 . Fig. 15C Shown Fig. 15B The trench 100 may be patterned by, for example, a combination of photolithography and etching. The trench 100 may be disposed between opposing sidewalls of the FE material 90, and the trench 100 may physically separate adjacent stacks of memory cells in the memory array 200 (see Figure 1A ).

[0052] exist Fig.16A , 16B In 16C , a dielectric material 102 is deposited in the trench 100 and fills the trench 100 . Fig. 16C Shown Fig. 16B . The dielectric layer 102 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. The dielectric layer 102 may extend along the sidewalls and bottom surface of the trench 86 above the OS layer 92. After deposition, a planarization process (e.g., CMP, etch back, etc.) may be performed to remove excess portions of the dielectric material 102. In the resulting structure, the top surfaces of the multilayer stack 58, the FE material 90, the OS layer 92, and the dielectric material 102 may be substantially flush (e.g., within process variations). In some embodiments, the materials of the dielectric materials 98 and 102 may be selected so that they may be selectively etched relative to each other. For example, in some embodiments, the dielectric material 98 is an oxide and the dielectric material 102 is a nitride. In some embodiments, the dielectric material 98 is a nitride and the dielectric material 102 is an oxide. Other materials are also possible.

[0053] exist Fig.17A , 17B and 17C , trenches 104 are patterned for conductive lines 106 and 108 . Fig. 17C Shown Fig. 17B The trenches 104 are patterned by patterning the dielectric material 98 using a combination of photolithography and etching, for example.

[0054] For example, a photoresist 118 may be deposited on the multilayer stack 58, the dielectric material 98, the dielectric material 102, the OS layer 92, and the FE material 90. For example, the photoresist 118 may be formed by using a spin coating technique. The photoresist 82 is patterned to define openings 120. Each opening 120 may overlap a corresponding region of the dielectric material 102, and each opening 120 may also partially expose two separate regions of the dielectric material 98. For example, each opening 120 may expose a region of the dielectric material 102; partially expose a first region of the dielectric material 98; and partially expose a second region of the dielectric material 98, which is separated from the first region of the dielectric material 98 by the dielectric material region 102. In this way, each of the openings 120 may define the patterning of the conductive lines 106 and adjacent conductive lines 108 separated by the dielectric material 102. These photoresists may be patterned using acceptable photolithography techniques. For example, the photoresist 82 is exposed to light for patterning. After the exposure process, the photoresist 82 may be developed to remove exposed or unexposed portions of the photoresist, depending on whether a negative or positive tone resist is used, thereby defining the pattern that forms the opening 120 .

[0055] Subsequently, the portion of dielectric material 98 exposed by opening 120 may be removed, for example, by etching. The etching may be any feasible etching process, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching may be anisotropic. The etching process may use an etchant that etches dielectric material 98 without significantly etching dielectric material 102. As a result, even though opening 120 exposes dielectric material 102, dielectric material 102 is not significantly removed. The pattern of trench 104 may correspond to conductive lines 106 and 108 (see FIG. 1 ). Fig.18A , 18B 18C). For example, a portion of dielectric material 98 may remain between each pair of trenches 104, and dielectric material 102 may be disposed between adjacent pairs of trenches 104. After patterning trenches 104, photoresist 118 may be removed by, for example, ashing.

[0056] exist Fig.18A , Fig.18B and Fig.18C In the embodiment of the present invention, trench 104 is filled with a conductive material to form conductive lines 106 and 108 . Fig.18C Shown Fig.18B. Conductive lines 106 and 108 may each include a conductive material, such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, or the like, each of which may be formed using, for example, CVD, ALD, PVD, PECVD, or the like. After depositing conductive line 106 and the conductive material, planarization (e.g., CMP, etch back, etc.) may be performed to remove excess portions of the conductive material, thereby forming conductive lines 106 and 108. In the resulting structure, the top surfaces of multilayer stack 58, FE material 90, OS layer 92, conductive line 106, and conductive line 108 may be substantially horizontal (e.g., within process variations). Conductive line 106 may correspond to a bit line in a memory array, and conductive line 108 may correspond to a source line in memory array 200. In addition, conductive lines 106 and 108 may provide source / drain electrodes for TFTs in memory array 200. Although Fig.18C A cross-sectional view showing only conductive line 106 is illustrated, but a cross-sectional view of conductive line 108 may also be similar.

[0057] Figures 19 to 28B is a diagram of an intermediate stage in the fabrication of a staircase structure of memory array 200 according to some embodiments. Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26B , Fig. 27 and Fig.28B It is shown along the reference section BB' shown in FIG. 1 . Fig.26A and Fig.28A It is displayed in a three-dimensional view.

[0058] exist Fig.19 In the embodiment of the present invention, a photoresist 56 is formed over the multilayer stack 58. As described above, the multilayer stack 58 may include alternating layers of conductive lines 72 (labeled 72A, 72B, 72C, and 72D) and dielectric layers 52 (labeled 52A, 52B, and 52C). The photoresist 56 may be formed using a spin coating technique and may be patterned using available photolithography techniques.

[0059] exist Fig. 20In the embodiment of the present invention, photoresist 56 is patterned to expose multilayer stack 58 in region 60 while masking the remaining portion of multilayer stack 58 (e.g., the portion including FE material 90, OS layer 92, conductive line 106, and conductive line 108). For example, the uppermost layer of multilayer stack 58 (e.g., conductive line 72D) may be exposed in region 60. The photoresist may mask and protect the portion of multilayer stack 58 including FE material 90, OS layer 92, conductive line 106, and conductive line 108 until photoresist 56 is removed (see FIG. 1 ). Fig.26A and 26B ).

[0060] exist Fig.21 In the embodiment of the present invention, the exposed portion of the multilayer stack 58 in the region 60 is etched using the photoresist 56 as a mask. The etching may be any feasible etching process, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching may be anisotropic. The etching may remove the conductive line 72D and the portion of the dielectric layer 52C in the region 60 and define the opening 61. Because the conductive line 72D and the dielectric layer 52C have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, the dielectric layer 52C acts as an etch stop layer while etching the conductive line 72D, and the conductive line 72C acts as an etch stop layer while etching the dielectric layer 52C. Therefore, the conductive layer 54E and the portion of the conductive line 72D may be selectively removed without removing the remaining layers of the multilayer stack 58, and the opening 61 may extend to a desired depth. Alternatively, a timed etching process may be used to stop etching the opening 61 after the opening 61 reaches a desired depth. In the resulting structure, the conductive line 72C is exposed in the region 60.

[0061] exist Fig. 22 In the embodiment of the present invention, photoresist 56 is cut to expose additional portions of multilayer stack 58. Photoresist can be cut using feasible photolithography techniques. Due to the cutting, the width of photoresist 56 is reduced, and portions of multilayer stack 58 in regions 60 and 62 can be exposed. For example, the top surface of conductive line 72C can be exposed in region 60, while the top surface of conductive line 72D can be exposed in region 62.

[0062] exist Fig.23In the embodiment of the present invention, portions of conductive line 72D, dielectric layer 52C, conductive line 72C, and dielectric layer 52B in regions 60 and 62 are removed by an acceptable etching process using photoresist 56 as a mask. Etching can be any feasible etching process, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. Etching can be anisotropic. Etching can extend opening 61 also into multilayer stack 58. Because conductive line 72D / 72C and dielectric layer 52C / 52B have different material compositions, the etchants used to remove exposed portions of these layers can be different. In some embodiments, dielectric layer 52C acts as an etch stop layer while etching conductive line 72D; conductive line 72C acts as an etch stop layer while etching dielectric layer 52C; dielectric layer 52B acts as an etch stop layer while etching conductive line 72C; conductive line 72B acts as an etch stop layer while etching dielectric layer 52B. As a result, portions of conductive lines 72D / 72C and dielectric layers 52C / 52B can be selectively removed without removing the remaining layers of multilayer stack 58, and opening 61 can extend to a desired depth. In addition, during the etching process, the unetched portions of conductive lines 72 and dielectric layer 52 act as a mask for the underlying layers, and as a result, the previous pattern of conductive lines 72D and dielectric layer 52C (see FIG. 5 ) is removed. Fig. 22 ) may be transferred to underlying conductive line 72C and dielectric layer 52B. In the resulting structure, conductive line 72B is exposed in region 60, while conductive line 72C is exposed in region 62.

[0063] exist Fig.24 In the embodiment of the present invention, photoresist 56 is cut to expose additional portions of multilayer stack 58. Photoresist can be cut using available photolithography techniques. As a result of the cutting, the width of photoresist 56 is reduced, and portions of multilayer stack 58 in regions 60, 62, and 64 can be exposed. For example, the upper surface of conductive line 72B can be exposed in region 60; the upper surface of conductive line 72C can be exposed in region 62; and the upper surface of conductive line 72D can be exposed in region 64.

[0064] exist Fig.25In the embodiment of the present invention, portions of the conductive lines 72D, 72C and 72B in the regions 60, 62 and 64 are removed by a feasible etching process using the photoresist 56 as a mask. The etching may be any feasible etching process, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching may be anisotropic. The etching may extend the opening 61 also into the multilayer stack 58. In some embodiments, the dielectric layer 52C acts as an etch stop layer while etching the conductive line 72D; the dielectric layer 52B acts as an etch stop layer while etching the conductive line 72C; and the dielectric layer 52A acts as an etch stop layer for etching the conductive line 72B. As a result, portions of the conductive lines 72D, 72C and 72B may be selectively removed without removing the remaining layers of the multilayer stack 58, and the opening 61 may be extended to a desired depth. In addition, during the etching process, each of the dielectric layers 52 acts as a mask for the underlying layers, and as a result, the previous pattern of the dielectric layers 52C / 52B (see Fig.24 ) can be transferred to the underlying conductive lines 72C / 72B. In the resulting structure, dielectric layer 52A is exposed in region 60; dielectric layer 52B is exposed in region 62; and dielectric layer 52C is exposed in region 64.

[0065] exist Fig.26A and Fig.26B In the embodiment of the present invention, the photoresist 56 can be removed, such as by a possible ashing or wet stripping process. Thus, a stair structure 68 is formed. The stair structure includes a stack of alternating conductive lines in the dielectric layer 52 and conductive lines 72. The lower conductive lines 72 are wider and extend laterally beyond the upper conductive lines 72, and the width of each conductive layer 72 increases in a direction toward the substrate 50. For example, conductive line 72A can be longer than conductive line 72B; conductive line 72B can be longer than conductive line 72C; conductive line 72C can be longer than conductive line 72D. As a result, in subsequent processing steps, a conductive contact can be formed from above the stair structure 68 to each conductive line 72.

[0066] exist Fig. 27 In the embodiment of the present invention, an intermetallic dielectric (IMD) 70 is deposited on the multilayer stack 58. The first IMD 70 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), FCVD, etc. The dielectric material may include phospho-silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any feasible process may also be used. The IMD 70 extends along the sidewalls of the conductive line 72 and the sidewalls of the dielectric layer 52. In addition, the IMD 70 may contact the top surface of each dielectric layer 52.

[0067] Also like Fig. 27As shown, a removal process is then applied to IMD 70 to remove excess dielectric material on multilayer stack 58. In some embodiments, a planarization process may be used, such as chemical mechanical polishing (CMP), an etch back process, or a combination thereof. The planarization process exposes multilayer stack 58 so that the top surface of multilayer stack 58 and IMD 70 is flat after the planarization process is completed.

[0068] exist Fig.28A , Fig.28B , Fig.28C and Fig.28D In the embodiment of the present invention, contacts 110 are formed to conductive lines 72 , 106 , and 108 . Fig.28A A perspective view of a memory array 200 is shown; Fig.28B A top view of the memory array 200 is shown; and Fig.28C Shows a single Fig.28A A cross-sectional view of the device and the underlying substrate taken along line 30C-30C'; and Fig.28D Shown along Figure 1A 5. A cross-sectional view of a device along line B-B' of FIG. 5. In some embodiments, the stepped shape of conductive line 72 can provide a surface for landing conductive contact 110 on each conductive line 72. Forming contact 110 can include, for example, patterning openings in IMD 70 and dielectric layer 52 using a combination of photolithography and etching to expose portions of conductive layer 54. A liner (not shown) such as a diffusion barrier layer, an adhesion layer, etc. and a conductive material are formed in the opening. The liner may contain titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of IMD 70. The remaining liner and conductive material form contact 110 in the opening.

[0069] like Fig.28A , conductive contacts 112 and 114 may also be formed to conductive lines 106 and 108, respectively, as shown in the perspective view of FIG. 1 . Conductive contacts 110, 112, and 114 may be electrically connected to conductive lines 116A, 116B, and 116C, respectively, which connect the memory array to underlying / upper volt circuitry (e.g., control circuitry) and / or signal, power, and ground lines in the semiconductor die. For example, conductive via 118 may extend through IMD 70 to electrically connect conductive line 116C to underlying circuitry of interconnect structure 220 and active devices on substrate 50, such as Fig.28COther conductive vias may be formed through IMD 70 to electrically connect conductive lines 116A and 116B to underlying circuitry of interconnect structure 220. In alternative embodiments, routing and / or power lines to and from the memory array may be provided by an interconnect structure formed on memory array 200 in addition to or in lieu of interconnect structure 220. Thus, memory array 200 may be completed.

[0070] although Figures 2 to 28B The embodiments of the present invention show specific patterns for conductive lines 106 and 108, but other configurations are also possible. For example, in these embodiments, conductive lines 106 and 108 have a staggered pattern. In some embodiments, conductive lines 106 and 108 in the same row array are aligned with each other. Fig.29 shows a top view, and Fig.30 A cross-sectional view along line CC' of FIG. 28 is shown. Fig.31 Shown along Fig.29 A cross-sectional view of the line D-D'. Fig.29 , 30 and 31, the same reference numerals denote Figures 2 to 28B The same components are formed by the same process.

[0071] Various embodiments provide a 3D-type memory array with vertically stacked memory cells. The memory cell includes a TFT having a FE gate dielectric material and an oxide semiconductor channel region. In some embodiments, the FE material 90 may be a hafnium-based compound including a rare earth metal. The rare earth metal may have an ionic radius greater than that of hafnium. For example, the rare earth metal may be lanthanum, yttrium, gadolinium, cerium, strontium, etc. The inclusion of a rare earth metal may allow the FE material 90 to achieve an orthorhombic crystal structure with a relatively low temperature annealing process (e.g., at a temperature of about 400°C or less). For example, the rare earth dopant in the FE material 90 may expand the composition range of the stable orthorhombic phase of the FE layer 90. Therefore, the FE layer 90 including the embodiment rare earth metal provides an improved low thermal budget BEOL integration for the memory array 200. In addition, by including a rare earth metal in the FE material 90, the inherent fatigue performance and durability of the FE material 90 may be improved. For example, in experimental data, the durability of the FE material 90 can be improved by at least ten times compared to the FE material without the embodiment rare earth metal, and the FE material 90 can allow at least 10 8 poling cycles without significant degradation of the FE material 90. Thus, various embodiments improve the reliability and ease of manufacturability of the resulting device.

[0072] In some embodiments, a memory cell includes a thin film transistor on a semiconductor substrate. The thin film transistor includes: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-containing compound, the hafnium compound containing a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. Optionally, in some embodiments, the ionic radius of the rare earth metal is greater than the ionic radius of hafnium. Optionally, in some embodiments, the rare earth metal is lanthanum, yttrium, gadolinium, cerium or strontium. Optionally, in some embodiments, the hafnium-containing compound is an oxide. Optionally, in some embodiments, the hafnium-containing compound further contains zirconium. Optionally, in some embodiments, the hafnium-containing compound has an orthorhombic lattice crystal structure. Optionally, in some embodiments, the longitudinal axis of the word line extends parallel to the main surface of the semiconductor substrate, the longitudinal axis of the source line extends vertically to the main surface of the semiconductor substrate, and the longitudinal axis of the bit line extends vertically to the main surface of the semiconductor substrate.

[0073] In some embodiments, a device includes a semiconductor substrate; a first memory cell above the semiconductor substrate, the first memory cell including a first thin film transistor, wherein the first thin film transistor includes: a first portion of a ferroelectric material, the first portion of the ferroelectric material is on a sidewall of a first word line, and the ferroelectric material includes a rare earth metal; and a first channel region on the sidewall of the ferroelectric material, the first channel region including an oxide semiconductor material; and a second memory cell above the first memory cell. Optionally, in some embodiments, the ferroelectric material includes HfLaO, HfCeO, HfGdO, HfZrLaO, HfZrGdO, HfZrYO, HfZrCeO, HfZrSrO, or a combination thereof. Optionally, in some embodiments, the ferroelectric material has a crystal structure with an orthorhombic lattice. Optionally, in some embodiments, the oxide semiconductor material extends continuously from the sidewall of the bit line to the sidewall of the source line, and wherein the source line and the bit line each extend in a direction perpendicular to the main surface of the semiconductor substrate. Optionally, in some embodiments, the second memory cell comprises a second thin film transistor, the second thin film transistor comprising: a second portion of a ferroelectric material, the second portion of the ferroelectric material contacts a second word line above the first word line, and the second word line is separated from the first word line by a dielectric layer; and a second channel region. Optionally, in some embodiments, the first word line is longer than the second word line. Optionally, in some embodiments, the oxide semiconductor material comprises ZnO, InWO, InGaZnO, InZnO, ITO, or a combination thereof.

[0074] In some embodiments, a method includes patterning a first trench extending through a first conductive line; depositing a ferroelectric (FE) material along the sidewalls and bottom surface of the first trench, wherein depositing the FE material includes an atomic layer deposition (ALD) process to deposit a hafnium-containing compound, and wherein the hafnium-containing compound further includes a rare earth metal; and depositing an oxide semiconductor (OS) layer on the FE material, the OS layer extending along the sidewalls and bottom surface of the first trench. Optionally, in some embodiments, the ALD process includes: forming a first monolayer of hafnium oxide; and forming a second monolayer of a rare earth metal oxide on the first monolayer. Optionally, in some embodiments, the ALD process also includes: forming a third monolayer of zirconium oxide between the first monolayer and the second monolayer. Optionally, in some embodiments, the ALD process also includes: forming a third monolayer of zirconium oxide on the second monolayer. Optionally, in some embodiments, the ALD process also includes: forming a fourth monolayer of hafnium oxide in contact with the first monolayer; and forming a fifth monolayer of a rare earth metal oxide in direct contact with the second monolayer. Optionally, in some embodiments, the method further includes performing an annealing process on the FE material at a temperature of 400° C. or lower after depositing the FE material, wherein, as a result of the annealing process, the FE material has an orthorhombic lattice structure.

[0075] In some embodiments, a memory cell comprises: a thin film transistor located above a semiconductor substrate, the thin film transistor comprising: a ferroelectric (FE) material, contacting a word line, the FE material being a hafnium-containing compound, and the hafnium-containing compound comprising a rare earth metal; and an oxide semiconductor (OS) layer, contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. In some embodiments, the ionic radius of the rare earth metal is greater than the ionic radius of hafnium. In some embodiments, the rare earth metal is lanthanum, yttrium, gadolinium, cerium, or strontium. In some embodiments, the hafnium-containing compound is an oxide. In some embodiments, the hafnium-containing compound further comprises zirconium. In some embodiments, the hafnium-containing compound has an orthorhombic lattice crystal structure. In some embodiments, the longitudinal axis of the word line extends parallel to the main surface of the semiconductor substrate, the longitudinal axis of the source line extends perpendicular to the main surface of the semiconductor substrate, and the longitudinal axis of the bit line extends perpendicular to the main surface of the semiconductor substrate.

[0076] In some embodiments, a device includes: a semiconductor substrate; a first memory cell located above the semiconductor substrate, the first memory cell including a first thin film transistor, wherein the first thin film transistor includes: a first portion of a ferroelectric material, the first portion of the ferroelectric material is on a sidewall of a first word line, and the ferroelectric material includes a rare earth metal; and a first channel region located on the sidewall of the ferroelectric material, the first channel region includes an oxide semiconductor material; and a second memory cell located above the first memory cell. In some embodiments, the ferroelectric material includes HfLaO, HfCeO, HfGdO, HfZrLaO, HfZrGdO, HfZrYO, HfZrCeO, HfZrSrO, or a combination thereof. In some embodiments, the ferroelectric material has a crystal structure with an orthorhombic lattice. In some embodiments, the oxide semiconductor material extends continuously from the sidewall of the bit line to the sidewall of the source line, and wherein the source line and the bit line each extend in a direction perpendicular to the main surface of the semiconductor substrate. In some embodiments, the second memory cell includes a second thin film transistor, the second thin film transistor including: a second portion of the ferroelectric material, the second portion of the ferroelectric material contacts a second word line above the first word line, the second word line and the first word line are separated by a dielectric layer; and a second channel region. In some embodiments, the first word line is longer than the second word line. In some embodiments, the oxide semiconductor material includes ZnO, InWO, InGaZnO, InZnO, ITO, or a combination thereof.

[0077] In some embodiments, a method includes: patterning a first trench extending through a first conductive line; depositing a ferroelectric (FE) material along the sidewalls and bottom surface of the first trench, wherein depositing the FE material includes an atomic layer deposition (ALD) process to deposit a hafnium-containing compound, and wherein the hafnium-containing compound also includes a rare earth metal; and depositing an oxide semiconductor (OS) layer over the FE material, the OS layer extending along the sidewalls and bottom surface of the first trench. In some embodiments, the ALD process includes: forming a first monolayer of hafnium oxide; and forming a second monolayer of a rare earth metal oxide over the first monolayer. In some embodiments, the ALD process also includes: forming a third monolayer of zirconium oxide between the first monolayer and the second monolayer. In some embodiments, the ALD process also includes: forming a third monolayer of zirconium oxide over the second monolayer. In some embodiments, the ALD process also includes: forming a fourth monolayer of hafnium oxide in contact with the first monolayer; and forming a fifth monolayer of a rare earth metal oxide in direct contact with the second monolayer. In some embodiments, the method further includes performing an annealing process on the FE material at a temperature of 400° C. or lower after depositing the FE material, wherein the FE material has an orthorhombic lattice structure due to the annealing process.

[0078] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A memory cell, comprising: A thin film transistor is located above a semiconductor substrate, and the thin film transistor comprises: a ferroelectric material contacting a word line, the ferroelectric material being a hafnium-containing compound and the hafnium-containing compound including a rare earth metal, wherein the word line is one of a plurality of vertically stacked word lines, the ferroelectric material continuously extending and directly contacting a sidewall of each of the plurality of vertically stacked word lines; and An oxide semiconductor layer contacts a source line and a bit line, wherein the ferroelectric material is disposed between the oxide semiconductor layer and the word line, and the ferroelectric material directly contacts the oxide semiconductor layer.

2. The memory cell according to claim 1, wherein: The ionic radius of the rare earth metal is larger than that of hafnium.

3. The memory cell according to claim 1, wherein: The rare earth metal is lanthanum, yttrium, gadolinium, cerium or strontium.

4. The memory cell according to claim 1, wherein: The hafnium-containing compound is an oxide.

5. The memory cell according to claim 1, wherein: The hafnium-containing compound also includes zirconium.

6. The memory cell according to claim 1, wherein: The hafnium-containing compound has an orthorhombic lattice crystal structure.

7. The memory cell according to claim 1, wherein the longitudinal axis of the word line extends parallel to the main surface of the semiconductor substrate, the longitudinal axis of the source line extends perpendicular to the main surface of the semiconductor substrate, and the longitudinal axis of the bit line extends perpendicular to the main surface of the semiconductor substrate.

8. A semiconductor device comprising: Semiconductor substrate; A first memory unit is located above the semiconductor substrate, wherein the first memory unit includes a first thin film transistor, wherein the first thin film transistor includes: a first portion of a ferroelectric material, the first portion of the ferroelectric material being on a sidewall of the first word line, and the ferroelectric material comprising a rare earth metal; and a first channel region located on a sidewall of the ferroelectric material, the first channel region comprising an oxide semiconductor material; and A second memory unit is located above the first memory unit, wherein the second memory unit includes a second thin film transistor, and the second thin film transistor includes: a second portion of the ferroelectric material, the second portion of the ferroelectric material contacts a second word line above the first word line, the second word line and the first word line are separated by a dielectric layer, and the ferroelectric material extends continuously from a top surface of the second word line to a bottom surface of the first word line, the ferroelectric material directly contacts a sidewall of the first word line and a sidewall of the second word line; and a second channel region, the second channel region comprising the oxide semiconductor material; Wherein, the oxide semiconductor material is in direct contact with the ferroelectric material.

9. The semiconductor device according to claim 8, wherein: The ferroelectric material includes HfLaO, HfCeO, HfGdO, HfZrLaO, HfZrGdO, HfZrYO, HfZrCeO, HfZrSrO or a combination thereof.

10. The semiconductor device according to claim 8, wherein The ferroelectric material has a crystal structure with an orthorhombic lattice.

11. The semiconductor device according to claim 8, wherein The oxide semiconductor material continuously extends from a side wall of the bit line to a side wall of the source line, and wherein the source line and the bit line each extend in a direction perpendicular to a main surface of the semiconductor substrate.

12. The semiconductor device according to claim 8, wherein The mole percentage of zirconium in the ferroelectric material is in the range of 40% to 70%, and the mole percentage of rare earth metal in the ferroelectric material is in the range of 1% to 10%.

13. The semiconductor device according to claim 8, wherein: The first word line is longer than the second word line.

14. The semiconductor device according to claim 8, wherein: The oxide semiconductor material includes ZnO, InWO, InGaZnO, InZnO, ITO or a combination thereof.

15. A method of forming a semiconductor device, comprising: patterning a first trench extending through a first conductive line; Depositing a ferroelectric material along the sidewalls and bottom of the first trench, wherein depositing the ferroelectric material comprises an atomic layer deposition process to deposit a hafnium-containing compound, and wherein the hafnium-containing compound further comprises a rare earth metal; and An oxide semiconductor layer is deposited over the ferroelectric material, the oxide semiconductor layer extending along the sidewalls and the bottom surface of the first trench.

16. The method according to claim 15, wherein: The atomic layer deposition process comprises: forming a first monomolecular layer of hafnium oxide; and A second monolayer of a rare earth metal oxide is formed over the first monolayer.

17. The method according to claim 16, wherein: The atomic layer deposition process further comprises: A third monomolecular layer of zirconium oxide is formed between the first monomolecular layer and the second monomolecular layer.

18. The method according to claim 16, wherein: The atomic layer deposition process further comprises: A third monolayer of zirconium oxide is formed over the second monolayer.

19. The method according to claim 17, wherein: The atomic layer deposition process also includes forming a fourth monolayer of hafnium oxide in contact with the first monolayer; and A fifth monolayer of a rare earth metal oxide is formed in direct contact with the second monolayer.

20. The method according to claim 15, further comprising performing an annealing process on the ferroelectric material at a temperature of 400°C or less after depositing the ferroelectric material, wherein As a result of the annealing process, the ferroelectric material has an orthorhombic lattice structure.

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