Memory cell, memory device and method for forming the same

Abstract

A memory cell includes a transistor located above a semiconductor substrate. The transistor includes a ferroelectric layer arranged along the sidewall of a word line. The ferroelectric layer includes a substance having a valence of 5, a valence of 7, or a combination thereof. The oxide semiconductor layer is electrically connected to a source line and a bit line. The ferroelectric layer is arranged between the oxide semiconductor layer and the word line. Embodiments of the present application provide a memory cell, a memory device, and a method for forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to memory cells, memory devices, and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate; patterning the various material layers using photolithography and etching techniques to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the invention

[0004] An embodiment of the present application provides a memory cell, comprising: a transistor located above a semiconductor substrate, the transistor comprising: a ferroelectric layer arranged along the side wall of a word line, the ferroelectric layer comprising a substance having a valence of 5, a valence of 7, or a combination thereof; and an oxide semiconductor layer electrically connected to a source line and a bit line, wherein the ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

[0005] An embodiment of the present application provides a device, comprising: a semiconductor substrate; a first memory cell located above the semiconductor substrate, the first memory cell comprising a first transistor, wherein the first transistor comprises: a first portion of a ferroelectric layer, the first portion of the ferroelectric layer being located on a side wall of a first word line, and the ferroelectric layer comprising a substance having a valence of 5, a valence of 7, or a combination thereof; and a first channel region located on the side wall of the ferroelectric layer, the first channel region comprising an oxide semiconductor layer, wherein a substance at a first interface between the first channel region and the first portion of the ferroelectric layer has a valence of 5, a valence of 7, or a combination thereof; and a second memory cell located above the first memory cell.

[0006] An embodiment of the present application provides a method comprising: forming a groove extending through a conductive line; depositing a ferroelectric layer along the sidewalls and bottom of the groove; depositing an oxide semiconductor layer above the ferroelectric layer, the oxide semiconductor layer extending along the sidewalls and bottom of the groove; and performing a process to introduce a substance having a valence of 5, a valence of 7, or a combination thereof into the ferroelectric layer.

[0007] Embodiments of the present application provide a ferroelectric memory device and a method for forming the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0009] Figure 1A , Figure 1B ,and Figure 1C shows simplified perspective, circuit, and top views of a ferroelectric memory device according to some embodiments;

[0010] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 Figure 12 Fig.13 , Fig.14 , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.18C , Fig.18D , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B Figure 20C Fig. 22 , Fig.23 , Fig.24 , Fig.25A , Fig.25B , Fig.26A , Fig.26B , Fig.27A , Fig.27B , Fig.28A , Fig.28B , Fig.29A , Fig.29B , Fig. 30A , Fig. 30B , Fig. 30C , FIG. 30D , and Fig.30E shows different views of manufacturing a ferroelectric memory device according to some embodiments;

[0011] Fig.20DA graph showing species concentration and oxygen concentration versus depth of a channel layer, a ferroelectric layer, and a conductive line according to some embodiments;

[0012] Fig.21 Methods of forming ferroelectric layers and channel layers of a ferroelectric memory device according to some embodiments are shown;

[0013] Fig.31 shows a simplified perspective view of a ferroelectric memory device according to an alternative embodiment;

[0014] Fig.32A , Fig.32B , Fig.33A , Fig.33B , Fig.34A , Fig.34B , Fig.34C , and FIG. 36 show different views of an intermediate stage in the manufacture of a ferroelectric memory device according to yet another alternative embodiment;

[0015] Fig.34D A graph showing species concentration and oxygen concentration versus depth of a channel layer, a ferroelectric layer, and a conductive line according to some embodiments;

[0016] Fig.35 A method of forming a ferroelectric layer and a channel layer of a ferroelectric memory device according to some embodiments is shown;

[0017] Fig.37 Methods of forming a ferroelectric memory device according to some embodiments are shown. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or structures discussed.

[0019] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0020] Various embodiments provide memory devices such as 3D memory arrays. In some embodiments, the 3D memory array is a ferroelectric field effect transistor (FeFET) memory circuit comprising a plurality of vertically stacked memory cells. In some embodiments, the corresponding memory cell can be considered as a FeFET, which includes a word line region used as a gate electrode, a bit line region used as a first source / drain electrode, and a source line region used as a second source / drain electrode, a ferroelectric material as a gate dielectric, and an oxide semiconductor (OS) as a channel region. In some embodiments, the corresponding memory cell can be considered as a thin film transistor (TFT).

[0021] Figure 1A , Figure 1B ,and Figure 1C An example of a memory array according to some embodiments is shown. Figure 1A An example of a portion of a simplified memory array 200 is shown in a partial three-dimensional diagram; Figure 1B shows a circuit diagram of a memory array 200; Figure 1C A top view of a memory array 200 according to some embodiments is shown. The memory array 200 includes a plurality of memory cells 202, which may be arranged in a grid of rows and columns. The memory cells 202 may be further stacked vertically to provide a three-dimensional memory array, thereby increasing device density. The memory array 200 may be disposed in the back end of line (BEOL) of a semiconductor die. For example, the memory array may be disposed in an interconnect layer of a semiconductor die, such as above one or more active devices (e.g., transistors) formed on a semiconductor substrate.

[0022] In some embodiments, the memory array 200 is a memory array such as a NOR memory array. In some embodiments, the gate of each memory cell 202 is electrically connected to a corresponding word line (e.g., conductive line 72), the first source / drain region of each memory cell 202 is electrically connected to a corresponding bit line (e.g., conductive line 116B), and the second source / drain region of each memory cell 202 is electrically connected to a corresponding source line (e.g., conductive line 116A), which electrically connects the second source / drain region to ground. The memory cells 202 in the same horizontal row of the memory array 200 can share a common word line, and the memory cells 202 in the same vertical column of the memory array 200 can share a common source line and a common bit line.

[0023] The memory array 200 includes a plurality of vertically stacked conductive lines 72 (eg, word lines) with a dielectric layer 52 disposed between adjacent conductive lines 72. The conductive lines 72 extend parallel to the underlying substrate (in FIGS. 1A and 1B ). Figure 1B The conductor 72 may have a stepped structure such that the lower conductor 72 is longer than the upper conductor 72 and extends laterally beyond the end point of the upper conductor 72. Figure 1A , multiple stacked layers of conductors 72 are shown, wherein the topmost conductor 72 is the shortest conductor and the bottommost conductor 72 is the longest conductor. The respective lengths of the conductors 72 may increase in a direction toward the underlying substrate. In this manner, portions of each conductor 72 may be accessed from above the memory array 200, and the exposed portions of the conductors 72 may be individually contacted.

[0024] The memory array 200 further includes alternating conductive pillars 106 (e.g., electrically connected to the bit lines) and conductive pillars 108 (e.g., electrically connected to the source lines). The conductive pillars 106 and 108 may each extend in a direction perpendicular to the conductive lines 72. The dielectric material 98 is disposed between and isolates adjacent conductive pillars 106 and 108.

[0025] The pairs of conductive pillars 106 and 108 and the intersecting conductive lines 72 define the boundaries of each memory cell 202, and the isolation pillars 102 are disposed between and isolate adjacent pairs of conductive pillars 106 and 108. In some embodiments, the conductive pillars 108 are electrically connected to ground. Figure 1A A particular arrangement of conductive pillars 106 relative to conductive pillars 108 is shown, but it should be understood that the arrangements of conductive pillars 106 and 108 may be swapped in other embodiments.

[0026] In some embodiments, the memory array 200 may further include an oxide semiconductor (OS) material as a channel layer 92. The channel layer 92 may provide a channel region for the memory cell 202. For example, when an appropriate voltage (e.g., higher than a corresponding threshold voltage (Vth) of the corresponding memory cell 202) is applied through the corresponding conductive line 72, then the region of the channel layer 92 intersecting the conductive line 72 may allow current to flow from the conductive pillar 106 to the conductive pillar 108 (e.g., in the direction indicated by the arrow 206).

[0027] In some embodiments, the ferroelectric layer 90' is disposed between the channel layer 92 and each conductive line 72 and the dielectric layer 52, and the ferroelectric layer 90' can be used as a gate dielectric for each memory cell 202. In some embodiments, the ferroelectric layer 90' includes a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, etc.

[0028] The ferroelectric layer 90' can be polarized in one of two different directions, and the polarization direction can be changed by applying an appropriate voltage difference on the ferroelectric layer 90' and generating an appropriate electric field. The polarization can be relatively local (e.g., typically contained within each boundary of the memory cell 202), and a continuous region of the ferroelectric layer 90' can extend across multiple memory cells 202. Depending on the polarization direction of a particular region of the ferroelectric layer 90', the threshold voltage of the corresponding memory cell 202 can change, and a digital value (e.g., 0 or 1) can be stored. For example, when a region of the ferroelectric layer 90' has a first polarization direction, the corresponding memory cell 202 can have a relatively low threshold voltage, and when a region of the ferroelectric layer 90' has a second polarization direction, the corresponding memory cell 202 can have a relatively high threshold voltage. The difference between the two threshold voltages can be referred to as a threshold voltage shift. A larger threshold voltage shift can make it easier (e.g., less prone to error) to read the digital value stored in the corresponding memory cell 202.

[0029] In some embodiments, the ferroelectric layer 90' contains a substance having a valence of 5 (e.g., nitrogen (N)), or having a valence of 7 (e.g., fluorine (F)), or a combination thereof (e.g., an additional substance) to eliminate or block traps or defects in the interface IF2 between the ferroelectric layer 90' / 190' and the channel layer 92 / 192', and / or occupy oxygen vacancies in the ferroelectric layer 90' / 190' to play a passivation role to inhibit the mutual diffusion of oxygen, hydrogen, and vacancies, thereby improving the inherent fatigue performance and durability of the ferroelectric layer 90' / 190'.

[0030] In such an embodiment, in order to implement a write operation on the memory cell 202, a write voltage can be applied to the portion of the ferroelectric layer 90' corresponding to the memory cell 202. In some embodiments, the write voltage is applied, for example, by applying appropriate voltages to the corresponding conductive wire 72 (e.g., word line) and the corresponding conductive pillar 106 / 108 (e.g., bit line / source line). By applying the write voltage to the portion of the ferroelectric layer 90', the polarization direction of the region of the ferroelectric layer 90' can be changed. As a result, the corresponding threshold voltage of the corresponding memory cell 202 can also be switched from a low threshold voltage to a high threshold voltage, and vice versa, and a digital value can be stored in the memory cell 202. Since the conductive wire 72 intersects the conductive pillar 106 and the conductive pillar 108, an individual memory cell 202 can be selected for a write operation.

[0031] In such an embodiment, to perform a read operation on a memory cell 202, a read voltage (a voltage between a low threshold voltage and a high threshold voltage) may be applied to a corresponding conductive line 72 (e.g., a word line). Depending on the polarization direction of the corresponding region of the ferroelectric layer 90', the memory cell 202 may or may not be turned on. As a result, the conductive pillar 106 may or may not be discharged through the conductive pillar 108 (e.g., a source line connected to ground), and the digital value stored in the memory cell 202 may be determined. Because the conductive line 72 intersects the conductive pillars 106 and 108, an individual memory cell 202 may be selected for a read operation.

[0032] Figure 1A The partial three-dimensional view of FIG. 2 further illustrates lines corresponding to reference cross sections of the memory array 200 used in subsequent figures. Section BB′ is along the longitudinal axis of the conductive line 72 and along a direction parallel to, for example, the current flow direction of the memory cell 202. Section CC′ is perpendicular to section BB′ and extends through the dielectric material 98 and the isolation pillar 102. Section DD′ is perpendicular to section BB′ and extends through the dielectric material 98 and the conductive pillar 106. For clarity, subsequent figures refer to these reference cross sections.

[0033] exist Figure 2In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be an integrated circuit die, such as a logic die, a memory die, an ASIC die, etc. The substrate 50 may be a complementary metal oxide semiconductor (CMOS) die, and may be referred to as a CMOS under array (CUA). The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates, such as a multilayer substrate or a gradient substrate, may also be used. In some embodiments, the semiconductor material of substrate 50 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0034] Figure 2 Further shown is a circuit that can be formed above the substrate 50. The circuit includes a transistor located on the top surface of the substrate 50. The transistor may include a gate dielectric layer 302 located above the top surface of the substrate 50, and a gate electrode 304 located above the gate dielectric layer 302. Source / drain regions 306 are disposed on opposite sides of the gate dielectric layer 302 and the gate electrode 304 in the substrate 50. Gate spacers 308 are formed along the sidewalls of the gate dielectric layer 302 and separate the source / drain regions 306 and the gate electrode 302 at an appropriate lateral distance. The transistor may include a fin field effect transistor (FinFET), a nanostructure (e.g., nanosheet, nanowire, all-around gate, etc.) FET (NanoFET), a planar FET, etc., or a combination thereof, and may be formed by a gate-first process or a gate-last process.

[0035] A first interlayer dielectric (ILD) 310 surrounds and isolates the source / drain region 306, the gate dielectric layer 302, and the gate electrode 304, and a second ILD 312 is located above the first ILD 310. A source / drain contact 314 extends through the second ILD 312 and the first ILD 310 and is electrically connected to the source / drain region 306; a gate contact 316 extends through the second ILD 312 and is electrically connected to the gate electrode 304. An interconnect structure 320 is located above the second ILD 312, the source / drain contact 314, and the gate contact 316. The interconnect structure 320 includes, for example, one or more stacked dielectric layers 324, and a conductive feature 322 formed in the one or more dielectric layers 324. The interconnect structure 320 may be electrically connected to the gate contact 316 and the source / drain contact 314 to form a functional circuit. In some embodiments, the functional circuits formed by the interconnect structure 320 may include logic circuits, memory circuits, sense amplifiers, controllers, input / output circuits, image sensor circuits, etc., or combinations thereof. Figure 2 Transistors formed over substrate 50 are discussed, but other active devices (eg, diodes, etc.) and / or passive devices (eg, capacitors, resistors, etc.) may also be formed as part of the functional circuits.

[0036] exist Figure 3 In the embodiment, the multilayer stack 58 is formed in Figure 2 For the purpose of simplicity and clarity, substrate 50, transistors, ILDs 310 and 312, and interconnect structure 320 may be omitted from subsequent figures. Although multilayer stack 58 is shown as being in contact with dielectric layer 324 of interconnect structure 320, any number of intermediate layers may be disposed between substrate 50 and multilayer stack 58. For example, one or more interconnect layers including conductive features in an insulating layer (e.g., a low-k dielectric layer) may be disposed between substrate 50 and multilayer stack 58. In some embodiments, the conductive features may be patterned to provide electrical conductivity to active devices on substrate 50 and / or memory array 200 (see Figure 1A 1B ) provide power, ground, and / or signal lines. In some embodiments, one or more interconnect layers including conductive features in an insulating layer (eg, a low-k dielectric layer) may be disposed over the multilayer stack 58 .

[0037] exist Figure 3In the embodiment of the present invention, the multilayer stack 58 includes alternating layers of sacrificial layers 53A-53D (collectively referred to as sacrificial layers 53) and dielectric layers 52A-52E (collectively referred to as dielectric layers 52). The sacrificial layers 53 may be patterned and replaced in subsequent steps to define conductive lines 72 (e.g., word lines). The sacrificial layers 53 may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, and the like. The dielectric layers 52 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, and the like. The sacrificial layers 53 and the dielectric layers 52 include different materials having different etching selectivities. In some embodiments, the sacrificial layers 53 include silicon nitride, and the dielectric layers 52 include silicon oxide. Each of the sacrificial layers 53 and the dielectric layers 52 may be formed using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), and the like.

[0038] Although Figure 3 A specific number of sacrificial layers 53 and dielectric layers 52 are shown, but other embodiments may include different numbers of sacrificial layers 53 and dielectric layers 52. Additionally, while the multilayer stack 58 is shown with dielectric layers as the topmost and bottommost layers, the disclosure is not limited thereto. In some embodiments, at least one of the topmost and bottommost layers of the multilayer stack 58 is a sacrificial layer.

[0039] Figures 4 to 12 is a diagram of an intermediate stage in the fabrication of a staircase structure of a memory array 200 according to some embodiments. Figures 4 to 12 Along Figure 1A Reference section BB' is shown.

[0040] exist Figure 4 In the embodiment of the present invention, a photoresist 56 is formed over the multilayer stack 58. In some embodiments, the photoresist 56 is formed by a spin coating technique and patterned by an acceptable photolithography technique. Patterning the photoresist 56 can expose the multilayer stack 58 in the region 60 while masking the rest of the multilayer stack 58. For example, the topmost layer of the multilayer stack 58 (e.g., the dielectric layer 52E) can be exposed in the region 60.

[0041] exist Figure 5In the embodiment of the present invention, the exposed portion of the multilayer stack 58 in the region 60 is etched using the photoresist 56 as a mask. The etching may be any acceptable etching process, such as dry etching (e.g., reactive ion etching (RIE), neutral beam etching (NBE), etc.), wet etching, etc., or a combination thereof. The etching may be anisotropic. The etching may remove portions of the dielectric layer 52E and the sacrificial layer 53D in the region 60 and define the opening 61. Since the dielectric layer 52E and the sacrificial layer 53D have different material compositions, the etchants used to remove the exposed portions of these layers may be different. In some embodiments, when etching the dielectric layer 52E, the sacrificial layer 53D is used as an etching stop layer, and when etching the sacrificial layer 53D, the dielectric layer 52D is used as an etching stop layer. As a result, portions of the dielectric layer 52E and the sacrificial layer 53D may be selectively removed without removing the remaining layers of the multilayer stack 58, and the opening 61 may extend to a desired depth. Alternatively, after the opening 61 reaches the desired depth, a time mode etching process may be used to stop the etching of the opening 61. In the resulting structure, dielectric layer 52D is exposed in region 60 .

[0042] exist Figure 6 In some embodiments, photoresist 56 is trimmed to expose other portions of multilayer stack 58. In some embodiments, photoresist 56 is trimmed using an acceptable removal technique such as lateral etching. As a result of the trimming, the width of photoresist 56 is reduced, and portions of multilayer stack 58 in regions 60 and 62 may be exposed. For example, the top surface of dielectric layer 52D may be exposed in region 60, and the top surface of dielectric layer 52E may be exposed in region 62.

[0043] exist Figure 7In the embodiment of the present invention, the dielectric layer 52E, the sacrificial layer 53D, the dielectric layer 52D, and the sacrificial layer 53C in the region 60 and the region 62 are removed by an acceptable etching process using the photoresist 56 as a mask. The etching can be any acceptable etching process, such as dry etching (e.g., RIE, NBE, etc.), wet etching, etc., or a combination thereof. The etching can be anisotropic. The etching can extend the opening 61 further into the multilayer stack 58. Since the sacrificial layers 53D and 53C and the dielectric layers 52E and 52D have different material compositions, the etchants used to remove the exposed portions of these layers can be different. In some embodiments, the portions of the dielectric layers 52E and 52D in the regions 62 and 60 are removed by using the photoresist 56 as a mask and using the underlying sacrificial layers 53D and 53C as etching stop layers. Thereafter, the exposed portions of sacrificial layers 53D and 53C in regions 62 and 60 are removed using photoresist 56 as a mask and using underlying dielectric layers 52D and 52C as etch stops. In the resulting structure, dielectric layer 52C is exposed in region 60 and dielectric layer 52D is exposed in region 62.

[0044] exist Figure 8 In some embodiments, photoresist 56 is trimmed using an acceptable removal technique such as lateral etching. As a result of the trimming, the width of photoresist 56 is reduced, and portions of multilayer stack 58 in regions 60, 62, and 64 may be exposed. For example, the top surface of dielectric layer 52C may be exposed in region 60; the top surface of dielectric layer 52D may be exposed in region 62; and the top surface of dielectric layer 52E may be exposed in region 64.

[0045] exist Fig. 9In the embodiment of the present invention, the dielectric layers 52E, 52D, and 52C and the sacrificial layers 53D, 53C, and 53B in regions 60, 62, and 64 are removed by an acceptable etching process using photoresist 56 as a mask. The etching may be any acceptable etching process, such as dry etching (e.g., RIE, NBE, etc.), wet etching, etc., or a combination thereof. The etching may be anisotropic. The etching may extend the opening 61 further into the multilayer stack 58. Since the dielectric layers 52C-52E and the sacrificial layers 53B-53D have different material compositions, the etchants used to remove the exposed portions of these layers may be different. In some embodiments, the dielectric layers 52E, 52D, and 52C in regions 64, 62, and 60 are removed by using photoresist 56 as a mask and using the sacrificial layers 53D, 53C, and 53B below as etching stop layers. Thereafter, the exposed portions of sacrificial layers 53D, 53C, and 53B in regions 64, 62, and 60 are removed by using photoresist 56 as a mask and using underlying dielectric layers 52D, 52C, and 52B as an etch stop layer. In the resulting structure, dielectric layer 52B is exposed in region 60; dielectric layer 52C is exposed in region 62; and dielectric layer 52D is exposed in region 64.

[0046] exist Fig.10 In some embodiments, photoresist 56 is trimmed using an acceptable removal technique such as lateral etching. As a result of the trimming, the width of photoresist 56 is reduced, and portions of multilayer stack 58 in regions 60, 62, 64, and 66 may be exposed. For example, the top surface of dielectric layer 52B may be exposed in region 60; the top surface of dielectric layer 52C may be exposed in region 62; and the top surface of dielectric layer 52D may be exposed in region 64; and the top surface of dielectric layer 52E may be exposed in region 66.

[0047] exist Fig.11In some embodiments, portions of dielectric layers 52E, 52D, 52C, and 52B in regions 60, 62, 64, and 66 are removed by an acceptable etching process using photoresist 56 as a mask. The etching may be any acceptable etching process, such as dry etching (e.g., RIE, NBE, etc.), wet etching, etc., or a combination thereof. The etching may be anisotropic. The etching may extend opening 61 further into multilayer stack 58. In some embodiments, portions of dielectric layers 52E, 52D, 52C, and 52B in regions 66, 64, 62, and 60 are removed by using photoresist 56 as a mask and using underlying sacrificial layers 53D, 53C, 53B, and 53A as an etch stop layer. In the resulting structure, sacrificial layer 53A is exposed in region 60; sacrificial layer 53B is exposed in region 62; sacrificial layer 53C is exposed in region 64; and sacrificial layer 53D is exposed in region 66. Thereafter, the photoresist 56 may be removed by an acceptable ashing or wet stripping process.

[0048] exist Fig.12 In the embodiment, an intermetallic dielectric (IMD) 70 is formed above the multilayer stack 58. The IMD 70 may be formed by a dielectric material and may be deposited by any suitable method such as CVD, PECVD, flowable CVD (FCVD), etc. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. In some embodiments, the IMD 70 may include an oxide (e.g., silicon oxide, etc.), a nitride (e.g., silicon nitride, etc.), a combination thereof, etc. Other dielectric materials formed by any acceptable process may be used. Afterwards, a removal process is performed to remove excess dielectric material above the multilayer stack 58. In some embodiments, the removal process may be a planarization process, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. The planarization process exposes the multilayer stack 58 so that after the planarization process is completed, the top surfaces of the multilayer stack 58 and the IMD 70 are flush. IMD 70 extends along the sidewalls of sacrificial layers 53B-53D and the sidewalls of dielectric layers 52B-52E. In addition, IMD 70 may contact the top surfaces of sacrificial layers 53A-53D and dielectric layer 52E.

[0049] like Fig.12 As shown, an intermediate and overall staircase structure is thus formed. The intermediate staircase structure includes alternating layers of sacrificial layers 53 and dielectric layers 52. The sacrificial layers 53 are subsequently replaced with conductive lines 72, which will be Fig.16A and Fig. 16BThe lower conductor 72 is longer and extends laterally beyond the upper conductor 72, and the width of each conductor 72 increases in a direction toward the substrate 50 (see Figure 1A and Fig.30E ).

[0050] Figures 13 to 16B is a diagram of an intermediate stage in the fabrication of a memory region of memory array 200 according to some embodiments. Figures 13 to 16B In the embodiment of the present invention, the overall multilayer stack 58 is patterned to form trenches 86 therethrough, and the sacrificial layer 53 is replaced with a conductive material to define conductive lines 72. The conductive lines 72 may correspond to word lines in the memory array 200, and the conductive lines 72 may further provide gate electrodes for memory cells of the resulting memory array 200. Fig.13 , Fig.14 , Fig. 15B ,and Fig. 16B Along Figure 1A The reference section CC' is shown. Fig.15A and Fig.16A It is shown in a local three-dimensional diagram, which is respectively composed of Fig. 15B and Fig. 16B A three-dimensional diagram of the portion surrounded by the dotted line 30 in FIG.

[0051] exist Fig.13 In the embodiment of the present invention, a photoresist pattern 82 and an underlying hard mask pattern 80 are formed over the multilayer stack 58. In some embodiments, a hard mask layer and a photoresist layer are sequentially formed over the multilayer stack 58. The hard mask layer may include, for example, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. The photoresist layer is formed, for example, by a spin coating technique.

[0052] Thereafter, the photoresist layer is patterned to form the photoresist pattern 82 and the groove 86 between the photoresist pattern 82. The photoresist can be patterned, for example, by an acceptable photolithography technique. Then, the pattern of the photoresist pattern 82 is transferred to the hard mask layer by using an acceptable etching process, for example, by dry etching (e.g., RIE, NBE, etc.), wet etching, etc., or a combination thereof, to form the hard mask pattern 80. The etching can be anisotropic. Thus, a groove 86 extending through the hard mask layer is formed. Thereafter, the photoresist pattern 82 can be optionally removed, for example, by an ashing process.

[0053] exist Fig.14 , Fig.15A ,and Fig. 15BIn the embodiment of the present invention, the hard mask pattern 80 is transferred to the multilayer stack 58 using one or more acceptable etching processes, such as dry etching (e.g., RIE, NBE, etc.), wet etching, etc., or a combination thereof. The etching process can be anisotropic. Therefore, the groove 86 extends through the overall multilayer stack 58 and defines the strip-shaped sacrificial layer 53 and the strip-shaped dielectric layer 52 accordingly. In some embodiments, the groove 86 extends through the overall stepped structure and defines the strip-shaped stepped structure accordingly. The hard mask pattern 80 can then be removed by an acceptable process such as a wet etching process, a dry etching process, a planarization process, a combination thereof, etc.

[0054] exist Fig.15A , Fig. 15B , Fig.16A ,and Fig. 16B In some embodiments, portions of sacrificial layer 53A-53D (collectively referred to as sacrificial layer 53) are replaced with conductive lines 72A-72D (collectively referred to as conductive lines 72). In some embodiments, portions of sacrificial layer 53 are removed by an acceptable process such as a wet etching process, a dry etching process, or both. In some embodiments, a peripheral region surrounding an array region having a memory array has portions of some sacrificial layer 53 that are not removed by the replacement process. Therefore, portions of some sacrificial layer 53 in the peripheral region also provide further support to prevent dielectric layer 52 in the array region from collapsing.

[0055] Afterwards, the wire 72 is filled into the space between two adjacent dielectric layers 52. As shown in the partial enlarged view, each wire 72 includes two barrier layers 71 and 75, and a metal layer 73 located between the barrier layers 71 and 75. Specifically, the barrier layer 71 or 75 is arranged between the metal layer 73 and the adjacent dielectric layer 52. The barrier layers 71 and 75 can prevent the metal layer from diffusing to the adjacent dielectric layer 52. The barrier layers 71 and 75 can also provide the function of increasing the adhesion between the metal layer 73 and the adjacent dielectric layer 52, and can be called a glue layer in some examples. In some embodiments, both barrier layers and glue layers with different materials are provided. The barrier layers 71 and 75 are formed by a first conductive material such as a metal nitride (e.g., titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, hafnium nitride, etc.). The metal layer 73 can be formed by a second conductive material such as a metal (e.g., tungsten, ruthenium, molybdenum, cobalt, aluminum, nickel, copper, silver, gold, alloys thereof, etc.). The barrier layers 71, 75, and the metal layer 73 can all be formed by an acceptable deposition process such as CVD, PVD, ALD, PECVD, etc. The first conductive material of the barrier layers 71 and 75 and the second conductive material of the metal layer 73 are also deposited on the sidewalls of the multilayer stack 58 and fill in the trench 86. Thereafter, the first conductive material of the barrier layers 71 and 75 and the second conductive material of the metal layer 73 in the trench 86 are removed by an etch-back process. An acceptable etch-back process can be implemented to remove excess material from the sidewalls of the dielectric layer 52 and the bottom surface of the trench 86. Acceptable etch-back processes include dry etching (e.g., RIE, NBE, etc.), wet etching, etc., or a combination thereof. The acceptable etch-back process can be anisotropic.

[0056] In some embodiments, in a replacement process, the sacrificial layer 53 of the strip-shaped stepped structure is subsequently replaced with a conductive line 72 (see Figure 1A )replace.

[0057] In an alternative embodiment, before forming the conductive pillars 106 and 108 (shown in FIG. Fig.29A 29B), portions of sacrificial layer 53 are replaced with conductive lines 72. In addition to conductive pillars 106 and 108, dielectric material 98, channel layer 92, and isolation pillars 102, portions of sacrificial layer 53 in the peripheral region provide further support to prevent dielectric layer 52 in the array region from collapsing.

[0058] FIG. 17A to FIG. 21 The formation of a ferroelectric layer 90 ′ and a channel layer 92 in the trench 86 is shown. Fig.17A , Fig.18A , Fig.19A ,and Fig. 20A It is shown in a local three-dimensional diagram, which is respectively composed of Fig. 17B , Fig.18B , Fig.19B ,and Fig. 20B A three-dimensional view of the portion surrounded by the dotted line 30 in FIG. Fig. 17B , Fig.18B , Fig.19B ,and Fig. 20B In the cross-section, the Figure 1A The line C-C' is provided.

[0059] Fig.18C and Fig.18D Shows Fig.18B A local enlarged view of area R1. Fig. 20C Shows Fig. 20B A local enlarged view of area R1. Fig.20D Graphs showing species (eg, additional species) concentration and oxygen concentration versus depth of channel layer 92, ferroelectric layer 90', and conductive line 72 are shown. Fig.21 A method of forming the ferroelectric layer 90 ′ and the channel layer 92 of the memory array 200 is shown in accordance with some embodiments.

[0060] exist Fig.17A , Fig. 17B in, and in Fig.21 At action S100, the ferroelectric layer 90 can be conformally deposited in the groove 86 along the sidewalls of the conductive line 72 and the top surface of the dielectric layer 52E, and along the bottom surface of the groove 86. In some embodiments, the ferroelectric layer 90 can be further deposited on the IMD70 and deposited along the sidewalls of each step of the step structure in the step region. The ferroelectric layer 90 can include a material that can be switched between two different polarization directions by applying an appropriate voltage difference on the ferroelectric layer 90. For example, the ferroelectric layer 90 includes a high-k dielectric material, such as a dielectric material based on hafnium (Hf), etc. In some embodiments, the ferroelectric layer 90 includes hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, etc.

[0061] In some embodiments, the ferroelectric layer 90 may include barium titanium oxide (BaTiO3), lead titanium oxide (PbTiO3), lead zirconium oxide (PbZrO3), lithium niobium oxide (LiNbO3), sodium niobium oxide (NaNbO3), potassium niobium oxide (KNbO3), potassium tantalum oxide (KTaO3), bismuth scandium oxide (BiScO3), bismuth iron oxide (BiFeO3), hafnium erbium oxide (HfO3), 1-x Er x O), hafnium lanthanum oxide (Hf 1-x La x O), hafnium yttrium oxide (Hf 1-x Y x O), hafnium gadolinium oxide (Hf 1-x G xO), Hafnium Aluminum Oxide (Hf 1- x Al x O), hafnium zirconium oxide (Hf 1-x Zr x O, HZO), hafnium titanium oxide (Hf 1-x Ti x O), hafnium tantalum oxide (Hf 1-x Ta x O), or a combination thereof, etc. In some embodiments, the ferroelectric layer 90 may include different ferroelectric materials or different types of memory materials. In some embodiments, the method of forming the ferroelectric layer 90 includes implementing an appropriate deposition technique, such as CVD, PECVD, metal oxide chemical vapor deposition (MOCVD), ALD, RPALD, PEALD, MBD, etc.

[0062] In some embodiments, the ferroelectric layer 90 has a thickness of about 1 nm-20 nm, such as 5 nm-10 nm. Other thickness ranges (e.g., greater than 20 nm or 5-15 nm) may be applicable. In some embodiments, the ferroelectric layer 90 is formed in a completely amorphous state. In an alternative embodiment, the ferroelectric layer 90 is formed in a partially crystalline state; that is, the ferroelectric layer 90 is formed in a mixed crystalline-amorphous state and has a certain degree of structural order. In another alternative embodiment, the ferroelectric layer 90 is formed in a completely crystalline state. In some embodiments, the ferroelectric layer 90 is a single layer. In an alternative embodiment, the ferroelectric layer 90 is a multilayer structure.

[0063] exist Fig.21 At action S102, a first annealing process is performed on the ferroelectric layer 90. In an N2, O2 or N2 / O2 environment, the temperature range of the annealing process is in the range of about 250°C to about 550°C, so as to achieve a desired lattice structure for the ferroelectric layer 90. In some embodiments, during the annealing process, the ferroelectric layer 90 is transformed from an amorphous state to a partially or completely crystalline state. In an alternative embodiment, during the annealing, the ferroelectric layer 90 is transformed from a partially crystalline state to a completely crystalline state.

[0064] exist FIG. 20A to FIG. 20D in, and in Fig.21 At action S104, treatment 88 is performed on ferroelectric layer 90 to form ferroelectric layer 90'. In some embodiments, treatment 88 is performed on ferroelectric layer 90 to transform at least a portion of ferroelectric layer 90 into treated ferroelectric portion 90A. Treated ferroelectric portion 90A is used to enhance the durability of the device. In some embodiments, as Fig.18C As shown, the processed ferroelectric portion 90A is a portion of the ferroelectric layer 90'. In another embodiment, as shown in FIG. Fig.18DAs shown, the processed ferroelectric portion 90A is the entire ferroelectric layer 90'.

[0065] In some embodiments, treatment 88 introduces a substance (e.g., an additional substance) into ferroelectric layer 90 through an energy source. The energy source of treatment 88 may be provided by an ion implantation process, a plasma process, or other suitable processes including thermal diffusion, an electron beam, ultraviolet (UV), or a combination thereof. Treatment 88 may be a nitridation process or a halogen treatment process. In some embodiments, treatment 88 introduces a substance (e.g., an additional substance) having a valence of 5 (e.g., nitrogen (N)), having a valence of 7 (e.g., fluorine (F)), or a combination thereof to eliminate or block traps or defects in the interface IF2 between ferroelectric layer 90' and a channel layer 92 to be formed later, and / or to occupy oxygen vacancies in ferroelectric layer 90' and / or a channel layer 92 to be formed later and play a passivation role to inhibit the mutual diffusion of oxygen, hydrogen, and vacancies, thereby improving the inherent fatigue performance and durability of ferroelectric layer 90'. In some embodiments, ferroelectric layer 90' may be referred to as a ferroelectric layer containing a substance (e.g., nitrogen or halogen). In alternative embodiments, the ferroelectric layer 90 ′ may also be referred to as a ferroelectric layer doped with a passivating substance (eg, nitrogen or halogen).

[0066] Thus, the treated ferroelectric portion 90A is a portion of the ferroelectric layer 90' of a substance having a valence of 5, a valence of 7, or a combination thereof. In some embodiments, the ion implantation process or the plasma process is performed at a relatively low energy to prevent damage to the ferroelectric layer 90 and to improve the neutralization efficiency. For example, the ion implantation process is performed at an energy of about 10 KeV to 50 KeV and at a temperature of about 1 atoms / cm 2 To about 1000atoms / cm 2 For example, the plasma process is performed in a plasma chamber with a gas (e.g., N2, NH3, CF4, or CFH3) flow rate of about 1000 sccm to about 10000 sccm, a power of about 15 Watts to about 500 Watts, and a pressure of about 1 Torr to about 760 Torr for a time of about 1 second to about 360 seconds, and at a temperature of less than about 400° C.

[0067] like Fig.18C As shown, the substance concentration of the ferroelectric layer 90' can be about 1E17 / cm 3 to about 1E20 / cm 3In some embodiments, the ferroelectric layer 90' has a varying concentration of a substance (e.g., fluorine, nitrogen, etc.), and the substance concentration may decrease in a direction toward the conductive line 72. For example, the ferroelectric layer 90' may have a three-part structure, including a bottom ferroelectric part 90B, a middle ferroelectric part 90M, and a top ferroelectric part 90T. The bottom ferroelectric part 90B contacts the conductive line 72, and the middle ferroelectric part 90M is located between the bottom ferroelectric part 90B and the top ferroelectric part 90T. The middle ferroelectric part 90M and the top ferroelectric part 90T are collectively referred to as a processed ferroelectric part 90A.

[0068] In some embodiments, the top ferroelectric portion 90T has the maximum material concentration of the ferroelectric layer 90'. The maximum material concentration of the ferroelectric layer 90' is located at the center of the top ferroelectric portion 90T. In one embodiment, the material concentration of the top ferroelectric portion 90T can be in the range of about 50% to about 100% of the maximum material concentration of the ferroelectric layer 90'; the material concentration of the middle ferroelectric portion 90M can be in the range of about 1% to about 40% of the maximum material concentration of the ferroelectric layer 90'; and the material concentration of the bottom ferroelectric portion 90B can be less than 1% of the maximum material concentration of the ferroelectric layer 90'. In some embodiments, the maximum material concentration of the ferroelectric layer 90' can be about 1E17 / cm 3 to about 1E20 / cm 3 within the range.

[0069] In some embodiments, the top ferroelectric portion 90T has a thickness T3; the middle ferroelectric portion 90M has a thickness T2; and the bottom ferroelectric portion 90B has a thickness T1. In some embodiments, the thicknesses T1, T2, and T3 can be in a range between about 5 angstroms and about 10 nm, between about 1 nm and about 50 nm, or other similar values. In addition, the thickness ratio of the thickness T1 to the combined thickness (e.g., the thickness T3 plus the thickness T2) is in a range of about 1:2 to 1:10.

[0070] like Fig.18D As shown, in an alternative embodiment, the treated ferroelectric portion 90A occupies the entire ferroelectric layer 90'. The entire ferroelectric layer 90' includes the substance (e.g., fluorine, nitrogen, etc.). In some embodiments, the ferroelectric layer 90' has a uniformly distributed substance concentration. The substance concentration of the ferroelectric layer 90' can be about 1E17 / cm 3 to about 1E20 / cm 3 within the range.

[0071] like Fig.19A and Fig.19B As shown, and in Fig.21At action S106, a second annealing process 89 is performed on the ferroelectric layer 90'. In some embodiments, the second annealing process 89 includes a spike annealing process. The spike annealing process can be implemented using the following process parameters or conditions: the peak annealing temperature is maintained in the range between about 380°C and about 420°C, the annealing time (or duration) (during the peak temperature maintenance) is in the range between about 1 second and about 60 seconds, and the annealing pressure is in the range between about 50 Torr and about 760 Torr. These process parameters of the annealing process are not arbitrarily selected, but are carefully adjusted to activate the substances in the ferroelectric layer 90'.

[0072] exist Fig. 20A , Fig. 20B in, and in Fig.21 At action S108, a channel layer 92 is conformally deposited in the trench 86 above the ferroelectric layer 90'. The channel layer 92 includes a suitable Figure 1A ) provides a material for the channel region. For example, the channel layer 92 includes an oxide semiconductor (OS), such as zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO, IGZO), indium zinc oxide (InZnO), indium tin oxide (ITO), combinations thereof, and the like. In some embodiments, the channel layer 92 includes polycrystalline silicon (poly-Si), amorphous silicon (a-Si), and the like. The channel layer 92 may be deposited by CVD, PVD, ALD, PECVD, and the like. The channel layer 92 may extend along the sidewalls and bottom surface of the trench 86 above the ferroelectric layer 90. In some embodiments, the channel layer 92 may be further deposited on the IMD 70 and deposited along the sidewalls of each step of the stepped structure in the stepped region. Fig.21 In action S110 , after depositing the channel layer 92 , a third annealing step may be performed in an oxygen-related environment (eg, in a temperature range of about 300° C. to about 450° C.) to activate charge carriers of the channel layer 92 .

[0073] exist Fig. 20CIn some embodiments, after the third annealing process is performed, some of the substance diffuses into the channel layer 92. In some embodiments, some of the substance diffuses into the bottom channel portion 92B of the channel layer 92 in contact with the top ferroelectric portion 90T, while the middle channel portion 92M and the top channel portion of the channel layer 92 have little or no said substance. The top channel portion 92T has a thickness T6; the middle channel portion 92M has a thickness T5; and the bottom channel portion 92B has a thickness T4. Other thickness ranges may apply. In some embodiments, the thickness ratio of the combined thickness T3 to the combined thickness (e.g., thickness T3 plus thickness T2 and thickness T1) is in the range of about 5% to about 50%, about 10% to about 60%, or other similar values. In some embodiments, the thickness ratio of the combined thickness T4 to the combined thickness (e.g., thickness T6 plus thickness T5 and thickness T4) is in the range of about 5% to 50%, about 10% to about 60%, or other similar values.

[0074] exist Fig.20D , a graph showing the relationship between the substance concentration and the oxygen concentration and the depth of the channel layer 92, the ferroelectric layer 90', and the conductive line 72 is shown. The y-axis represents the substance concentration and the oxygen concentration. The x-axis represents the depth of the channel layer 92, the ferroelectric layer 90', and the conductive line 72. Curve

[012] represents the distribution of the oxygen concentration of the channel layer 92; curve

[011] represents the oxygen concentration of the ferroelectric layer 90'; and curve [S1] represents the substance concentration.

[0075] In some embodiments, curve

[012] shows that the middle channel portion 92M of the channel layer 92 has the maximum oxygen concentration. The oxygen concentration increases from the portion of the top channel portion 92T close to the dielectric material 98A to be formed later to the center of the middle channel portion 92M. The oxygen concentration decreases from the center of the middle channel portion 92M to the interface IF2 between the bottom channel portion 92B and the top ferroelectric portion 90T. The top channel portion 92T and the bottom channel portion 92B of the channel layer 92 have an oxygen concentration lower than the oxygen concentration of the middle channel portion 92M of the channel layer 92.

[0076] Curve

[011] shows that the portion of the intermediate ferroelectric portion 90M near the bottom ferroelectric portion 90B has the maximum oxygen concentration. The maximum oxygen concentration of the ferroelectric layer 90' is higher than the maximum oxygen concentration of the channel layer 92. The oxygen concentration increases from the interface IF2 between the top ferroelectric portion 90T and the bottom channel portion 92B to the portion of the intermediate ferroelectric portion 90M near the bottom ferroelectric portion 90B. The oxygen concentration decreases from the portion of the intermediate ferroelectric portion 90M near the bottom ferroelectric portion 90B to the interface IF1 between the bottom ferroelectric portion 90B and the wire 72. The top ferroelectric portion 90T has an oxygen concentration lower than the oxygen concentrations of the intermediate ferroelectric portion 90M and the bottom ferroelectric portion 90B.

[0077] Curve [S1] shows that the ferroelectric layer 90' has the maximum material concentration. The maximum material concentration of the ferroelectric layer 90' is between the maximum oxygen concentration of the channel layer 92 and the maximum oxygen concentration of the ferroelectric layer 90'. The top ferroelectric portion 90T has the maximum material concentration. The material concentration of the middle ferroelectric portion 90M is also lower than the material concentration of the top ferroelectric portion 90T, but greater than the material concentration of the bottom ferroelectric portion 90B.

[0078] The bottom channel portion 92B has a substance concentration that is lower than the substance concentration of the top ferroelectric portion 90T, but greater than the substance concentrations of the middle channel portion 92M and the top channel portion 92T. In one embodiment, the substance concentration of the bottom channel portion 92B may be in the range of about 1% to about 60% of the maximum substance concentration of the ferroelectric layer 90'. The middle channel portion 92M and the top channel portion 92T may have little or no substance, so the substance concentration of the middle channel portion 92M or the top channel portion 92T may be less than 1% of the maximum substance concentration of the ferroelectric layer 90' or zero. The ratio of the distribution range of the substance in the ferroelectric layer 90' to the distribution range of oxygen is greater than the ratio of the distribution range of the substance in the channel layer 92 (e.g., the oxide semiconductor layer) to the distribution range of oxygen.

[0079] The top ferroelectric portion 90T has a substance concentration higher than its oxygen concentration. The interface IF2 between the bottom channel portion 92B and the top ferroelectric portion 190T also has a substance concentration higher than its oxygen concentration. The interface IF2 between the bottom channel portion 92B and the top ferroelectric portion 190T has a substance concentration higher than the substance concentration of the interface IF1 between the bottom ferroelectric portion 90B and the wire 72.

[0080] Figures 22 to 25B The formation of dielectric material 98 and patterned channel layer 92 for memory cell 202 (see FIG. 1A ) in trench 86 is shown. Fig.25A It is shown in a local three-dimensional diagram, which is Fig.25B A three-dimensional view of the portion surrounded by the dotted line 30. Fig. 22 , Fig.23 , Fig.24 , and FIG. 25B , the cross-sectional view is along Figure 1A The line C-C' is provided.

[0081] exist Fig. 22In the embodiment of the present invention, dielectric material 98A is deposited in trench 86 above channel layer 92. In some embodiments, dielectric material 98A includes silicon oxide, silicon nitride, silicon oxynitride, etc., which can be deposited by CVD, PVD, ALD, PECVD, etc. Dielectric material 98A can extend along the sidewalls and bottom surface of trench 86 above channel layer 92. In some embodiments, dielectric material 98A is optional and can be omitted.

[0082] exist Fig.23 In the embodiment of the present invention, the dielectric material 98A and the bottom of the channel layer 92 are removed in the trench 86. The removal process includes an acceptable etching process, such as dry etching (e.g., RIE, NBE, etc.), wet etching, etc., or a combination thereof. The etching can be anisotropic. In some embodiments, the dielectric material 98A and the top of the channel layer 92 are removed from the multilayer stack 58. In some embodiments, the removal process includes a combination of photolithography and etching.

[0083] Accordingly, the remaining dielectric material 98A and the channel layer 92 may expose a portion of the ferroelectric layer 90' on the bottom surface of the trench 86. Thus, portions of the channel layer 92 on opposite sidewalls of the trench 86 may be separated from each other, thereby improving the memory array 200 (see Figure 1A ) between memory cells 202.

[0084] exist Fig.24 In the embodiment of the present invention, dielectric material 98B is deposited to completely fill trench 86. Dielectric material 98B may be formed of one or more materials and may be formed by the same or similar process as dielectric material 98A. In some embodiments, dielectric material 98B and dielectric material 98A include different materials.

[0085] exist Fig.25A and Fig.25B In the embodiment of the present invention, a removal process is applied to dielectric material 98A / 98B, channel layer 92, and ferroelectric layer 90' to remove excess material above multilayer stack 58. In some embodiments, a planarization process such as CMP, an etch-back process, a combination thereof, etc. may be utilized. The planarization process exposes multilayer stack 58 so that after the planarization process is completed, the top surfaces of multilayer stack 58 (e.g., dielectric layer 52E), ferroelectric layer 90', channel layer 92, dielectric material 98A / 98B (collectively referred to as dielectric material 98), and IMD 70 are flush.

[0086] FIG. 26A to FIG. 29BAn intermediate step is shown in fabricating conductive pillars 106 and 108 (eg, source / drain pillars) in memory array 200. Conductive pillars 106 and 108 may extend in a direction perpendicular to conductive lines 72 so that individual cells of memory array 200 may be selected for read and write operations. Fig.26A , Fig.27A , Fig.28A ,and Fig.29A It is shown in a local three-dimensional diagram, which is respectively composed of Fig.26B , Fig.27B , Fig.28B ,and Fig.29B A three-dimensional view of the portion surrounded by the dotted line 30 in FIG. Fig.26B and Fig.27B In the cross-section, the Figure 1A The line C-C' is provided. Fig.28B and 29B In the cross-section, the Figure 1A The line D-D' is provided.

[0087] exist Fig.26A and Fig.26B In some embodiments, the trench 100 is patterned through the channel layer 92 and the dielectric material 98. In an alternative embodiment, the trench 100 is patterned through the channel layer 92, the dielectric material 98, and the ferroelectric layer 90' (not shown). For example, the patterning of the trench 100 can be performed by a combination of photolithography and etching. The trench 100 can be disposed between the opposite sidewalls of the ferroelectric layer 90', and the trench 100 can be disposed between the memory array 200 (see Figure 1A ) in a stack of adjacent memory cells that are physically separated.

[0088] exist Fig.27A and Fig.27BIn the embodiment of the present invention, the isolation column 102 is formed in the trench 100. In some embodiments, the isolation layer is deposited above the multilayer stack 58 and filled in the trench 100. The isolation layer may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. The isolation layer may extend along the sidewalls and bottom surface of the trench 100 above the channel layer 92. After deposition, a planarization process (e.g., CMP, etch back, etc.) may be implemented to remove excess portions of the isolation layer. In the resulting structure, the top surfaces of the multilayer stack 58 (e.g., dielectric layer 52E), the ferroelectric layer 90', the channel layer 92, and the isolation column 102 may be substantially flush (e.g., within process variations). In some embodiments, the materials of the dielectric material 98 and the isolation column 102 may be selected so that they may be selectively etched relative to each other. For example, in some embodiments, the dielectric material 98 includes an oxide, and the isolation column 102 includes a nitride. In some embodiments, dielectric material 98 comprises nitride and spacer 102 comprises oxide. Other materials are also possible.

[0089] exist Fig.28A and Fig.28B In the embodiment, trench 104 is defined for subsequently formed conductive pillars 106 and 108. For example, trench 104 is formed by patterning dielectric material 98 using a combination of photolithography and etching. Fig.28A As shown, photoresist 118 is formed over multilayer stack 58, dielectric material 98, isolation pillar 102, channel layer 92, and ferroelectric layer 90′. In some embodiments, photoresist 118 is patterned by acceptable photolithography techniques to define openings 120. Each opening 120 can expose a corresponding isolation pillar 102 and two separated regions of dielectric material 98 beside isolation pillar 102. In this way, each opening 120 can define a pattern of conductive pillars 106 and adjacent conductive pillars 108 separated by isolation pillars 102.

[0090] Subsequently, the portion of dielectric material 98 exposed by opening 120 may be removed by an acceptable etching process, such as by dry etching (e.g., RIE, NBE, etc.), wet etching, etc., or a combination thereof. The etching may be anisotropic. The etching process may use an etchant that etches dielectric material 98 without significantly etching isolation pillar 102. As a result, even though opening 120 exposes isolation pillar 102, isolation pillar 102 is not significantly removed. The pattern of trench 104 may correspond to conductive pillars 106 and 108 (see FIG. 1 ). Fig.29A and Fig.29B ). After the trenches 104 are patterned, the photoresist 118 may be removed, for example, by ashing.

[0091] exist Fig.29A and 29B , the trench 104 is filled with a conductive material to form conductive pillars 106 and 108. The conductive material may include copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, and the like, which may be formed using, for example, CVD, ALD, PVD, PECVD, and the like. After the conductive material is deposited, planarization (e.g., CMP, etch back, and the like) may be performed to remove excess portions of the conductive material, thereby forming conductive pillars 106 and 108. In the resulting structure, the top surfaces of the multilayer stack 58 (e.g., dielectric layer 52E), ferroelectric layer 90″, channel layer 92, conductive pillars 106, and conductive pillars 108 may be substantially flush (e.g., within process variations). In some embodiments, conductive pillars 106 correspond to and are electrically connected to bit lines in a memory array, and conductive pillars 108 correspond to and are electrically connected to source lines in the memory array 200.

[0092] Therefore, if Fig.29A As shown, stacked memory cells 202 can be formed in the memory array 200. Each memory cell 202 includes a gate electrode (e.g., a portion corresponding to the conductive line 72), a gate dielectric (e.g., a portion corresponding to the ferroelectric layer 90'), a channel region (e.g., a portion corresponding to the channel layer 92), and a source / drain pillar (e.g., a portion corresponding to the conductive pillars 106 and 108). The isolation pillars 102 isolate adjacent memory cells 202 in the same column and at the same vertical level. The memory cells 202 can be arranged in an array of vertically stacked rows and columns.

[0093] exist Fig. 30A , Fig. 30B , Fig. 30C , Fig.30D ,and Fig.30E In the embodiment, IMD 74 is formed on the top surface of multilayer stack 58 (e.g., dielectric layer 52E), ferroelectric layer 90', channel layer 92, conductive pillar 106, conductive pillar 108, and IMD 70. Conductive contacts 110, 112, and 114 are formed on conductive line 72, conductive pillar 106, and conductive pillar 108, respectively. Fig. 30A A perspective view of a memory array 200 is shown, which is also composed of Fig. 30B A three-dimensional diagram of the portion surrounded by the dotted line 30; Fig. 30B Shown along Figure 1A A cross-sectional view of the device along line D-D'; Fig. 30C shows a top view of the memory array 200; Fig.30D Shown along Fig. 30A The cross-sectional view of the line E-E'; Fig.30E Shown along Figure 1A Cross-sectional view of the device along line BB'.

[0094] IMD74 may be formed of a dielectric material and may be deposited by any suitable method such as CVD, PECVD, flowable CVD (FCVD), etc. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), low-k dielectric material, etc. In some embodiments, IMD74 may include an oxide (e.g., silicon oxide, etc.), a nitride (e.g., silicon nitride, etc.), a combination thereof, etc. Other dielectric materials formed by any acceptable process may be used. Thereafter, a removal process is applied to IMD74 to remove excess dielectric material above the multilayer stack 58 and IMD70. In some embodiments, the removal process may be a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc.

[0095] In some embodiments, the stepped shape of the conductors 72 can provide a surface on each conductor 72 for the conductive contact 110 to fall on. In some embodiments, forming the conductive contact 110 can include, for example, patterning openings in the IMD 74 and IMD 70 using a combination of photolithography and etching to expose portions of the conductive line 72. A liner (not shown) such as a diffusion barrier layer, an adhesion layer, etc. and a conductive material are formed in the opening. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can include copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be implemented to remove excess material from the surface of the IMD 74. The liner and conductive material remaining in the opening form the conductive contact 110.

[0096] Also by Fig. 30A As shown in the perspective view of FIG. 1 , conductive contacts 112 and 114 may also be formed on conductive pillars 106 and 108, respectively. Conductive contacts 112, 114, and 110 may be electrically connected to conductive wires 116A, 116B, and 116C, respectively, which connect the memory array to the circuits below / above (e.g., control circuits) and / or signals, power, and ground lines in the semiconductor die. For example, Fig.30D As shown, conductive contact 110 may extend through IMD 74 and IMD 70 to electrically connect wire 116C to wire 72. Other conductive contacts or vias may be formed through IMD 74 to electrically connect wires 116A and 116B to active devices on the substrate below. In alternative embodiments, in addition to or in lieu of interconnect structure 320, wiring and / or power lines to and from the memory array may be provided by an interconnect structure formed above memory array 200. Accordingly, memory array 200 may be completed.

[0097] Although Figures 1A to 30B The embodiments of FIG. 32 show specific patterns for conductive pillars 106 and 108, but other configurations are possible. For example, in these embodiments, conductive pillars 106 and 108 have a staggered pattern. However, in other embodiments, as shown in the ferroelectric memory 200A of FIG. 32, conductive pillars 106 and 108 in the same row of the array are aligned with each other.

[0098] Figures 1A to 30B The process 88 shown in the embodiments of the present invention is shown as being performed at a specific timing, and other suitable timings are also possible. For example, in these embodiments, the process 88 is performed before forming the channel layer 92. However, in other embodiments, such as Fig.32A , Fig.32B , Fig.33A , Fig.33B , Fig.34A , Fig.34B , Fig.34C , Fig.34D , Fig.35 ,and Fig.36 As shown in the memory array 200', process 88 is replaced by process 188 performed after forming the channel layer 192.

[0099] FIG. 32A to FIG. 36 FIG. 32A shows the formation of a ferroelectric layer 190' and a channel layer 192' in the trench 86. Fig.33A , Fig.34A ,and Fig.36 Shown in a partial 3D view. Fig.32A , Fig.33A , and Fig.34A Also by Fig.32B , Fig.33B ,and Fig.34B A three-dimensional view of the portion surrounded by the dotted line 30 in FIG. Fig.32B , Fig.33B ,and Fig.34B In the cross-section, the Fig.36 The line C-C' is provided. Fig.34C Shows Fig.34B A local enlarged view of area R2. Fig.34D A graph showing species concentration and oxygen concentration versus depth of channel layer 192', ferroelectric layer 190', and conductive line 72 is shown. Fig.35 A method of forming a ferroelectric layer 190 ′ and a channel layer 192 ′ is shown according to some embodiments.

[0100] exist Fig.32A , Fig.32B in, and in Fig.35At action S200, after the overall multilayer stack 58 is patterned to form a groove 86 therethrough, the sacrificial layer 53 is replaced with a conductive material to define the conductive line 72, and the ferroelectric layer 190 can be conformally deposited in the groove 86 along the sidewalls of the conductive line 72 and the top surface of the dielectric layer 52E, and along the bottom surface of the groove 86. In some embodiments, the ferroelectric layer 190 can be further deposited on the IMD 70 and deposited along the sidewalls of each step of the step structure in the step region. The ferroelectric layer 190 may include a material that can be switched between two different polarization directions by applying an appropriate voltage difference across the ferroelectric layer 190. The ferroelectric layer 190 can be Fig.17A The ferroelectric layer 90 is the same or similar. Fig.35 At action S202, a first annealing process is performed on the ferroelectric layer 190 to achieve a desired lattice structure for the ferroelectric layer 190. In these embodiments, the first annealing process may be performed at the same time as in Fig.21 The third annealing process in action S102 is the same as or similar to that in step S104.

[0101] exist Fig.32A , Fig.32B in, and in Fig.35 At action S204, a channel layer 192 is conformally deposited in the trench 86 above the ferroelectric layer 190. The channel layer 192 includes a plurality of channels suitable for providing a plurality of channels to the memory cell 202' (see Fig.36 ) provides the material of the channel region. The channel layer 192 may be Fig. 20A The channel layer 92 is the same or similar. Fig.35 At action S206, a second annealing process is performed on the channel layer 192 to activate the charge carriers of the channel layer 192. In these embodiments, the second annealing process may be performed at the same time as the Fig.21 The third annealing process in action S110 is the same as or similar to that in step S111 .

[0102] exist Fig.33A , Fig.33B in, and in Fig.35 At action S208, after forming the ferroelectric layer 190 and the channel layer 192, the process 188 is performed on the channel layer 192 and the ferroelectric layer 190 to form the channel layer 192' and the ferroelectric layer 190' to enhance the durability of the device. In some embodiments, the process 188 introduces substances into the channel layer 192 and the ferroelectric layer 190 through an energy source. The energy source of the process 188 can be provided by an ion implantation process, a plasma process, or other suitable processes including thermal diffusion, electron beam, ultraviolet (UV), or a combination thereof.

[0103] Treatment 188 may be a nitridation treatment process or a halogen treatment process. In some embodiments, treatment 188 introduces a substance having a valence of 5 (e.g., nitrogen (N)) or a valence of 7 (e.g., fluorine (F)) to eliminate or block traps or defects in the interface IF4 between the ferroelectric layer 190 and the channel layer 192, and / or to occupy oxygen vacancies in the interface IF4, the channel layer 192, and / or the ferroelectric layer 190 to play a passivation role to inhibit the mutual diffusion of oxygen, hydrogen, and vacancies, thereby improving the inherent fatigue performance and durability of the ferroelectric layer 190'. In some embodiments, the channel layer 192' may also be referred to as a channel layer containing a substance (e.g., nitrogen or halogen), and the ferroelectric layer 190' may also be referred to as a ferroelectric layer containing a substance (e.g., nitrogen or halogen). In an alternative embodiment, the channel layer 192 ′ may also be referred to as a channel layer doped with a passivating substance (eg, nitrogen or halogen), and the ferroelectric layer 190 ′ may also be referred to as a ferroelectric layer doped with a passivating substance (eg, nitrogen or halogen).

[0104] Therefore, the channel layer 192' and the ferroelectric layer 190' have a valence of 5, a valence of 7, or a combination thereof. In some embodiments, the ion implantation process or the plasma process is performed at a relatively low energy to prevent damage to the channel layer 192 and the ferroelectric layer 190 and to improve the neutralization efficiency. For example, the ion implantation process is performed at an energy of about 1 KeV to 50 KeV and at a temperature of about 1 atoms / cm 2 Up to 1000atoms / cm 2 For example, the plasma process is performed in a plasma chamber at a flow rate of about 10 sccm to about 1000 sccm of a gas (e.g., N2, NH3, CF4, or CFH3), a power of 15 Watts to 500 Watts, and a pressure of about 1 Torr to about 760 Torr for a period of about 1 second to about 30 seconds, and a temperature of less than 250° C. to 400° C. In other embodiments, the plasma process is performed in a plasma chamber at a flow rate of about 1000 sccm to about 10000 sccm of a gas (e.g., N2, NH3, CF4, or CFH3), a power of 10 Watts to 1000 Watts, and a pressure of about 1 Torr to about 1000 Torr for a period of about 1 second to about 360 seconds, and a temperature of less than 500° C.

[0105] exist Fig.35At action S210, a third annealing process 189 is performed on the channel layer 192' and the ferroelectric layer 190'. In some embodiments, the third annealing process 189 includes a spike annealing process. The spike annealing process can be implemented using the following process parameters or conditions: the peak annealing temperature is maintained in the range between about 380°C and about 420°C, the annealing time (or duration) (during the peak temperature maintenance) is in the range between about 1 second and about 60 seconds, and the annealing pressure is in the range between about 50 Torr and about 760 Torr. These process parameters of the annealing process above are not arbitrarily selected, but are carefully adjusted to activate the substances in the channel layer 192' and the ferroelectric layer 190'. As a result, for example, the substance concentration of the channel layer 192' can be about 1E17 / cm 3 to about 1E20 / cm 3 The concentration of the ferroelectric layer 190' may be about 1E17 / cm 3 to about 1E20 / cm 3 within the range.

[0106] like Fig.34C and Fig.34D As shown, in some embodiments, the ferroelectric layer 190' and the channel layer 192' have different concentrations of substances (e.g., fluorine, nitrogen, etc.). For example, the ferroelectric layer 190' can have a three-part structure, including a bottom ferroelectric portion 190B having a thickness T11, a middle ferroelectric portion 190M having a thickness T12, and a top ferroelectric portion 190T having a thickness T13. The bottom ferroelectric portion 190B contacts the conductive line 172, and the middle ferroelectric portion 190M is located between the bottom ferroelectric portion 190B and the top ferroelectric portion 190T. The channel layer 192' can have a three-part structure, including a bottom channel portion 192B having a thickness T14, a middle channel portion 192M having a thickness T15, and a top channel portion 192T having a thickness T16. The bottom channel portion 192B contacts the conductive line 172, and the middle channel portion 192M is located between the bottom channel portion 192B and the top channel portion 192T. These portions of the channel layer 192' and the ferroelectric layer 190' have different substance concentrations and oxygen concentrations.

[0107] exist Fig.34D , a graph showing the relationship between the concentration of a substance and the position of the channel layer 192', the ferroelectric layer 190', and the conductive line 72 is shown. The y-axis represents the concentration of the substance and the oxygen concentration. The x-axis represents the depth of the channel layer 192', the ferroelectric layer 190', and the conductive line 72. Curve

[022] represents the oxygen concentration of the channel layer 192'; Curve

[021] represents the oxygen concentration of the ferroelectric layer 190', and curve [S2] represents the concentration of the substance.

[0108] In some embodiments, curve

[022] shows that the middle channel portion 192M of the channel layer 192' has the largest oxygen concentration, and the top channel portion 192T and the bottom channel portion 192B of the channel layer 192' have lower oxygen concentrations than the middle channel portion 192M of the channel layer 192'.

[0109] Curve

[021] shows that the portion of the middle ferroelectric portion 190M near the bottom ferroelectric portion 190B has the maximum oxygen concentration. The maximum oxygen concentration of the ferroelectric layer 190' is higher than the maximum oxygen concentration of the channel layer 192'. The top ferroelectric portion 190T has an oxygen concentration lower than the oxygen concentrations of the bottom ferroelectric portion 190B and the middle ferroelectric portion 190M.

[0110] Curve [S2] shows that the top channel portion 192T, the middle channel portion 192M, and the bottom channel portion 192B, the top ferroelectric portion 190T, the middle ferroelectric portion 190M, and the bottom ferroelectric portion 190B have the substance. The channel layer 192' has the maximum substance concentration. The ratio of the distribution range of the substance in the channel layer 192' (e.g., the oxide semiconductor layer) to the distribution range of oxygen is greater than the ratio of the distribution range of the substance in the ferroelectric layer 190' to the distribution range of oxygen.

[0111] The maximum substance concentration is between the maximum oxygen concentration of the channel layer 192' and the maximum oxygen concentration of the ferroelectric layer 190'. The bottom channel portion 192B has the maximum substance concentration. The substance concentration increases from the top channel portion 192T of the channel layer 192' to the bottom channel portion 192B. The substance concentration decreases from the bottom channel portion 192B of the channel layer 192' to the bottom ferroelectric portion 190B of the ferroelectric layer 190'. The interface IF4 between the bottom channel portion 192B and the top ferroelectric portion 190T has a higher substance concentration than the interface IF3 between the bottom ferroelectric portion 190B and the conductor 72.

[0112] The interface IF4 between the bottom channel portion 192B and the top ferroelectric portion 190T has a substance concentration higher than its oxygen concentration. The substance concentration of the bottom channel portion 192B is higher than its oxygen concentration. The substance concentration of the top ferroelectric portion 190T is higher than its oxygen concentration.

[0113] After the channel layer 192 ′ is formed, the channel layer 192 ′ is patterned, and subsequent processes are performed according to the above method to form a memory array 200 ′ including a plurality of memory cells 202 ′, as shown in FIG. 36 .

[0114] Fig.362 shows a simplified perspective view of a ferroelectric memory device according to some embodiments. Memory array 200' is similar to memory array 200, and memory cell 202' is similar to Figure 1A The memory cell 202 is formed of a semiconductor layer 192′, but the oxide semiconductor layer 192′ has a wider material distribution range than the channel layer 92 (eg, an oxide semiconductor layer).

[0115] Fig.37 A method for forming a ferroelectric memory device according to some embodiments is shown. Although the method is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions can be performed in an order different from the order shown, and / or can be performed simultaneously. In addition, in some embodiments, the actions or events shown can be subdivided into multiple actions or events, which can be performed at separate times, or performed simultaneously with other actions or sub-actions. In some embodiments, some actions or events shown can be omitted, and other actions or events not shown can also be included.

[0116] In act S300 , a trench is formed extending through the conductive line. FIG. 16A to FIG. 16B Different views corresponding to some embodiments of action S300 are shown.

[0117] In action S302 , a ferroelectric layer is deposited along the sidewalls and bottom surface of the trench. FIG. 17A to FIG. 17B as well as Fig.32A and Fig.32B Different views corresponding to some embodiments of action S302 are shown.

[0118] In action S304, an oxide semiconductor layer is deposited over the ferroelectric layer. The oxide semiconductor layer extends along the sidewalls and bottom surface of the trench. FIG. 20A to FIG. 20B as well as Fig.32A and Fig.32B Different views corresponding to some embodiments of action S304 are shown.

[0119] At action S306, a process is performed to introduce a substance having a valence of 5, a valence of 7, or a combination thereof into the ferroelectric layer. Fig.18A , Fig.18B , Fig.33A ,and Fig.33B Different views corresponding to some embodiments of action S306 are shown. The treatment process is, for example, an ion implantation process, a plasma process, or a combination thereof. In some embodiments, the treatment is performed between the deposition of the ferroelectric layer and the oxide semiconductor layer. In an alternative embodiment, the treatment is performed after the deposition of the oxide semiconductor layer.

[0120] In action S308, an annealing process is performed after the treatment is performed. Fig.19A , Fig.19B , Fig.34A , and Fig.34B Different views corresponding to some embodiments of action S308 are shown.

[0121] Although Figures 1A to 30B and FIG. 32A to FIG. 36 The embodiment of FIG. 8 shows that the staircase structure is formed before forming trench 86 , but other timings are possible. For example, the staircase structure may be formed after forming conductive pillars 106 and 108 and before forming IMD 74 .

[0122] Various embodiments provide a 3D memory array with vertically stacked memory cells. The memory cells each include a TFT having a FE gate dielectric material and an oxide semiconductor channel region. In some embodiments, the ferroelectric layer 90' / 190' and / or the oxide semiconductor layer 92 / 192' may contain a substance having a valence of 5, a valence of 7, or a combination thereof. For example, the substance having a valence of 5 is nitrogen, and the substance having a valence of 7 is fluorine. The inclusion of the substance may allow for the ferroelectric layer 90' to eliminate or block traps or defects in the interface IF2 between the ferroelectric layer 90' / 190' and the channel layer 92 / 192', and / or occupy oxygen vacancies in the interface IF2, the ferroelectric layer 90' / 190', and the channel layer 92 / 192' to play a passivation role to inhibit the mutual diffusion of oxygen, hydrogen, and vacancies, thereby improving the inherent fatigue performance and durability of the ferroelectric layer 90' / 190'. Accordingly, various embodiments improve the reliability of the resulting device and simplify manufacturing.

[0123] According to some embodiments of the present invention, a memory cell includes: a transistor located above a semiconductor substrate, the transistor including: a ferroelectric layer arranged along the side wall of a word line, the ferroelectric layer including a substance having a valence of 5, a valence of 7, or a combination thereof; and an oxide semiconductor layer electrically connected to a source line and a bit line, wherein the ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

[0124] According to an alternative embodiment of the present invention, a device includes: a semiconductor substrate; a first memory cell located above the semiconductor substrate, the first memory cell including a first transistor, wherein the first transistor includes: a first portion of a ferroelectric layer, the first portion of the ferroelectric layer being located on a side wall of a first word line, and the ferroelectric layer including a substance having a valence of 5, a valence of 7, or a combination thereof; and a first channel region located on the side wall of the ferroelectric layer, the first channel region including an oxide semiconductor layer, wherein a substance at a first interface between the first channel region and the first portion of the ferroelectric layer has a valence of 5, a valence of 7, or a combination thereof; and a second memory cell located above the first memory cell.

[0125] According to another alternative embodiment of the present invention, a method includes: forming a trench extending through a conductive line; depositing a ferroelectric layer along the sidewalls and bottom of the trench; depositing an oxide semiconductor layer above the ferroelectric layer, the oxide semiconductor layer extending along the sidewalls and bottom of the trench; and performing a process to introduce a substance having a valence of 5, a valence of 7, or a combination thereof into the ferroelectric layer.

[0126] An embodiment of the present application provides a memory cell, comprising: a transistor located above a semiconductor substrate, the transistor comprising: a ferroelectric layer arranged along the sidewall of a word line, the ferroelectric layer comprising a substance having a valence of 5, a valence of 7, or a combination thereof; and an oxide semiconductor layer electrically connected to a source line and a bit line, wherein the ferroelectric layer is disposed between the oxide semiconductor layer and the word line. In some embodiments, the substance having a valence of 5 is nitrogen, and the substance having a valence of 7 is fluorine. In some embodiments, the ferroelectric layer is in contact with the oxide semiconductor layer. In some embodiments, a first interface between the ferroelectric layer and the oxide semiconductor layer has a first substance concentration that is higher than a second substance concentration at a second interface between the ferroelectric layer and the word line. In some embodiments, the ferroelectric layer has a maximum substance concentration between the first interface and the second interface. In some embodiments, a portion of the oxide semiconductor layer near the first interface has a substance concentration.

[0127] An embodiment of the present application provides a device, comprising: a semiconductor substrate; a first memory cell located above the semiconductor substrate, the first memory cell comprising a first transistor, wherein the first transistor comprises: a first portion of a ferroelectric layer, the first portion of the ferroelectric layer being located on a sidewall of a first word line, and the ferroelectric layer comprising a substance having a valence of 5, a valence of 7, or a combination thereof; and a first channel region located on a sidewall of the ferroelectric layer, the first channel region comprising an oxide semiconductor layer, wherein a substance at a first interface between the first channel region and the first portion of the ferroelectric layer has a valence of 5, a valence of 7, or a combination thereof; and a second memory cell located above the first memory cell. In some embodiments, the substance concentration of the first interface is higher than its oxygen concentration. In some embodiments, the ferroelectric layer continuously extends beyond the first word line and beyond a second word line vertically separated from the first word line by a dielectric layer. In some embodiments, further comprising: a third memory device, comprising: a third portion of the ferroelectric layer, located on a second sidewall of the first word line opposite to the sidewall of the first word line; and a second channel region, separated from the second sidewall of the first word line by the third portion of the ferroelectric layer. In some embodiments, the substance also occupies oxygen vacancies in the ferroelectric layer, the oxide semiconductor layer, or a combination thereof. In some embodiments, the ratio of the distribution range of the substance in the ferroelectric layer to the distribution range of oxygen is greater than the ratio of the distribution range of the substance in the oxide semiconductor layer to the distribution range of oxygen. In some embodiments, the ratio of the distribution range of the substance in the oxide semiconductor layer to the distribution range of oxygen is greater than the ratio of the distribution range of the substance in the ferroelectric layer to the distribution range of oxygen. In some embodiments, the second memory cell comprises a second transistor, the second transistor comprising: a second portion of the ferroelectric layer, the second portion of the ferroelectric layer being electrically connected to a second word line located above the first word line, and the second word line and the first word line being separated by a dielectric layer; and a second channel region.

[0128] An embodiment of the present application provides a method, comprising: forming a groove extending through a conductive line; depositing a ferroelectric layer along the sidewalls and bottom surface of the groove; depositing an oxide semiconductor layer located above the ferroelectric layer, the oxide semiconductor layer extending along the sidewalls and the bottom surface of the groove; and performing a treatment to introduce a substance having a valence of 5, a valence of 7, or a combination thereof into the ferroelectric layer. In some embodiments, the substance having a valence of 5 is nitrogen, and the substance having a valence of 7 is fluorine. In some embodiments, the treatment process comprises an ion implantation process, a plasma process, or a combination thereof. In some embodiments, the treatment is performed between the depositing of the ferroelectric layer and the depositing of the oxide semiconductor layer. In some embodiments, the treatment is performed after the depositing of the oxide semiconductor layer. In some embodiments, an annealing process is also performed after the treatment is performed.

[0129] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device comprising a first memory cell and a second memory cell located above the first memory cell, wherein: The first memory cell includes a first transistor, the first transistor is located above a semiconductor substrate, and the first transistor includes: a first portion of a ferroelectric layer disposed along a sidewall of the first word line, the ferroelectric layer comprising a substance having a valence of 5, a valence of 7, or a combination thereof; as well as a first portion of the oxide semiconductor layer electrically connected to a source line and a bit line, wherein the first portion of the ferroelectric layer is disposed between the first portion of the oxide semiconductor layer and the first word line; The second memory cell includes a second transistor, the second transistor is located above the semiconductor substrate, and the second transistor includes: a second portion of the ferroelectric layer, the second portion of the ferroelectric layer being electrically connected to a second word line located above the first word line and disposed along a sidewall of the second word line, the second word line and the first word line being separated by a dielectric layer; and a second portion of the oxide semiconductor layer.

2. The memory device according to claim 1, wherein: The substance having a valence of 5 is nitrogen, and the substance having a valence of 7 is fluorine.

3. The memory device according to claim 1, wherein: The ferroelectric layer is in contact with the oxide semiconductor layer.

4. The memory device according to claim 1, wherein: A first interface between the ferroelectric layer and the oxide semiconductor layer has a first substance concentration that is higher than a second substance concentration at a second interface between the ferroelectric layer and the first word line.

5. The memory device according to claim 4, wherein: The ferroelectric layer has a maximum substance concentration between the first interface and the second interface.

6. The memory device according to claim 4, wherein: A portion of the oxide semiconductor layer close to the first interface has a substance concentration.

7. A memory device comprising: Semiconductor substrate; A first memory cell is located above the semiconductor substrate, wherein the first memory cell comprises a first transistor, wherein the first transistor comprises: a first portion of a ferroelectric layer, the first portion of the ferroelectric layer being located on a sidewall of the first word line, and the ferroelectric layer comprising a substance having a valence of 5, a valence of 7, or a combination thereof; and a first channel region located on a sidewall of the ferroelectric layer, the first channel region comprising an oxide semiconductor layer, wherein a substance at a first interface between the first channel region and the first portion of the ferroelectric layer has a valence of 5, a valence of 7, or a combination thereof; and A second memory cell is located above the first memory cell, the second memory cell includes a second transistor, and the second transistor includes: a second portion of the ferroelectric layer, the second portion of the ferroelectric layer being electrically connected to a second word line located above the first word line, and the second word line and the first word line being separated by a dielectric layer; and The second channel region.

8. The memory device according to claim 7, wherein: The substance concentration of the first interface is higher than the oxygen concentration thereof.

9. The memory device according to claim 7, wherein: The ferroelectric layer extends continuously beyond the first word line and beyond a second word line vertically separated from the first word line by a dielectric layer.

10. The memory device according to claim 7, further comprising: A third memory device comprising: A third portion of the ferroelectric layer is located on a second sidewall of the first word line opposite to the sidewall of the first word line; and A second channel region is separated from the second sidewall of the first word line by the third portion of the ferroelectric layer.

11. The memory device according to claim 7, wherein: The substance also occupies oxygen vacancies in the ferroelectric layer, the oxide semiconductor layer, or a combination thereof.

12. The memory device according to claim 7, wherein: A ratio of a distribution range of the substance to a distribution range of oxygen in the ferroelectric layer is greater than a ratio of a distribution range of the substance to a distribution range of oxygen in the oxide semiconductor layer.

13. The memory device according to claim 7, wherein: A ratio of a distribution range of the substance to a distribution range of oxygen in the oxide semiconductor layer is greater than a ratio of a distribution range of the substance to a distribution range of oxygen in the ferroelectric layer.

14. The memory device according to claim 7, wherein: The substance having a valence of 5 is nitrogen, and the substance having a valence of 7 is fluorine.

15. A method of forming a memory device, comprising: forming a trench extending through a first conductive line, a dielectric layer located on the first conductive line, and a second conductive line located on the dielectric layer; Depositing a ferroelectric layer along the sidewalls and bottom of the trench, wherein a first portion of the ferroelectric layer is along the sidewalls of the first conductive line, and a second portion of the ferroelectric layer is electrically connected to and along the sidewalls of the second conductive line; depositing an oxide semiconductor layer over the ferroelectric layer, the oxide semiconductor layer extending along the sidewalls and the bottom surface of the trench; and Treatment is performed to introduce a substance having a valence of 5, a valence of 7, or a combination thereof into the ferroelectric layer.

16. The method for forming a memory device according to claim 15, wherein: The substance having a valence of 5 is nitrogen, and the substance having a valence of 7 is fluorine.

17. The method for forming a memory device according to claim 15, wherein: The treatment includes an ion implantation process, a plasma process, or a combination thereof.

18. The method for forming a memory device according to claim 15, wherein: The processing is performed between the depositing of the ferroelectric layer and the depositing of the oxide semiconductor layer.

19. The method for forming a memory device according to claim 15, wherein: The processing is performed after the depositing of the oxide semiconductor layer.

20. The method of forming a memory device according to claim 15, further comprising performing an annealing process after performing the treating.

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