Data driver and display device having the same

Abstract

The present application relates to a data driver and a display device having the same. A data driver is provided, including a digital-to-analog converter configured to convert image signal data into a plurality of data voltages, and an output buffer unit including a plurality of channels for outputting the plurality of data voltages. The output buffer unit includes a plurality of output blocks. Each output block includes one or more channels. Data voltages output from a first output block of the plurality of output blocks are delayed to have a first time difference. Data voltages output from a second output block of the plurality of output blocks are delayed to have a second time difference, the second time difference being different from the first time difference.

Description

Technical Field

[0001] This disclosure relates to a data driver and a display device having the data driver, and more specifically, to a data driver and a display device having the data driver capable of improving charging failures caused by signal delay. Background Technology

[0002] The display device includes a display panel for displaying images and a data driver and a gate driver for driving the display panel. The display panel includes multiple gate lines, multiple data lines, and multiple pixels.

[0003] The data driver outputs a data drive signal to the data line, and the gate driver outputs a gate drive signal to drive the gate line. After the gate signal is applied to the pixel connected to the gate line, the display device can display an image using a data voltage corresponding to the image being displayed.

[0004] Recently, with the increase in display panel size and the adoption of high-speed driving methods, signal delay may occur in the transmission path of the gate signal output from the gate driver. In this case, the charging rate of pixels located far from the gate driver may be lower than that of pixels located near the gate driver. Therefore, there is a need to develop a new device and method to improve charging capability. Summary of the Invention

[0005] This disclosure provides a data driver that can improve charging failures caused by signal delay.

[0006] This disclosure also provides a display device having the above-described data driver.

[0007] Embodiments of this disclosure provide a data driver including: a digital-to-analog converter configured to convert image signal data into a plurality of data voltages; and an output buffer unit including a plurality of channels for outputting the plurality of data voltages. The output buffer unit includes a plurality of output blocks, and each of the plurality of output blocks includes at least one channel.

[0008] In one implementation, a first data voltage output from a first output block of a plurality of output blocks is delayed to have a first time difference, and a second data voltage output from a second output block of a plurality of output blocks is delayed to have a second time difference, the second time difference being different from the first time difference.

[0009] In embodiments of this disclosure, the display device includes: a display panel including a plurality of pixels connected to a plurality of gate lines and a plurality of data lines; a gate driver configured to generate a plurality of gate signals and apply the plurality of gate signals to the plurality of gate lines; at least one data integrated circuit configured to generate a plurality of data voltages based on image signal data and apply the plurality of data voltages to the plurality of data lines; and a signal controller configured to control the gate driver and the data integrated circuit and generate image signal data based on the image data.

[0010] In one implementation, the data integrated circuit includes a plurality of output blocks connected to a data line, and each of the plurality of output blocks includes at least one channel.

[0011] In one implementation, a first data voltage output from a first output block of a plurality of output blocks is delayed to have a first time difference, and a second data voltage output from a second output block of a plurality of output blocks is delayed to have a second time difference, the second time difference being different from the first time difference.

[0012] In embodiments of this disclosure, the display device includes: a display panel including a plurality of pixels connected to a plurality of gate lines and a plurality of data lines; a gate driver configured to generate a plurality of gate signals and apply the plurality of gate signals to the plurality of gate lines; and a plurality of data integrated circuits configured to generate a plurality of data voltages based on image signal data and apply the plurality of data voltages to the plurality of data lines.

[0013] In one embodiment, each of the plurality of data integrated circuits includes a plurality of output blocks connected to a plurality of data lines, and a first data voltage output from at least one first output block of a first data integrated circuit in the plurality of data integrated circuits has an equal first delay value. Attached Figure Description

[0014] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0015] Figure 1 This is a block diagram of a display device according to an embodiment of the present disclosure;

[0016] Figure 2 This is a plan view of a display device according to an embodiment of the present disclosure;

[0017] Figure 3 yes Figure 2 A magnified plan view of the first data integrated circuit and display panel of part A1;

[0018] Figure 4 yes Figure 3 The internal block diagram of the first data integrated circuit shown is shown below;

[0019] Figure 5 It is shown in detail Figure 4 The block diagram shown is of the delayed clock generation unit and the output buffer unit.

[0020] Figure 6A It is shown Figure 5 The waveforms of the first reference clock, second reference clock, third reference clock, and fourth reference clock, as well as the first delay clock block, second delay clock block, third delay clock block, and fourth delay clock block shown in the figure;

[0021] Figure 6B It is shown Figure 5 The waveforms of the output data voltages of the first, second, third, and fourth blocks shown in the figure are at the corresponding time points.

[0022] Figure 6C This is a waveform diagram showing the output time points of the data voltage of the first, second, third, and fourth blocks according to another embodiment;

[0023] Figure 7 This is a plan view of a display device according to an embodiment of the present disclosure;

[0024] Figure 8 yes Figure 7 A magnified plan view of the first data integrated circuit and display panel of part A2;

[0025] Figure 9 It shows that it is applied to Figure 8 The waveforms of the output time points of the data lines of the first, second, third, and fourth blocks shown are as follows:

[0026] Figure 10 yes Figure 7 A magnified plan view of the fourth data integrated circuit and display panel of part A3;

[0027] Figure 11 It shows that it is applied to Figure 10 The waveforms of the output time points of the data lines of the first, second, third, and fourth blocks shown are as follows:

[0028] Figure 12 This is a plan view of a display device according to an embodiment of the present disclosure;

[0029] Figure 13 yes Figure 12 Enlarged plan view of the second, third, and fourth data integrated circuits and the display panel in part A4;

[0030] Figure 14 It shows the application set to Figure 13 The waveforms of the output time points of the data voltage of the data lines in the first, second, and third driving regions shown in the figure;

[0031] Figure 15 It is based on Figure 2 An enlarged plan view of the first data integrated circuit and display panel of another embodiment of part A1; and

[0032] Figure 16 It shows that it is applied to Figure 15 The waveforms of the output time points of the data lines of the first, second, third, fourth, fifth, sixth, seventh, and eighth blocks shown are as follows. Detailed Implementation

[0033] In this specification, when a component (or area, layer, part, etc.) is referred to as being “on”, “connected to”, or “combined to” another component, it means that the component may be directly on, connected to, or combined to the other component, or that there may be a third component between them.

[0034] The same reference numerals denote the same elements. Furthermore, for the sake of effective description, the thickness, scale, and dimensions of the parts are exaggerated in the accompanying drawings.

[0035] "And / or" includes all of one or more combinations defined by the relevant component.

[0036] It will be understood that the terms “first” and “second” are used herein to describe various components, but these components should not be limited by these terms. The terms above are used only to distinguish one component from another. For example, without departing from the scope of this disclosure, a first component may be referred to as a second component, and a second component may be referred to as a first component. Unless otherwise stated, singular terms may include plural forms.

[0037] Furthermore, terms such as "below," "lower side," "upper," and "upper side" are used to describe the relationships of the configurations shown in the accompanying drawings. These terms are described as relative concepts based on the directions shown in the accompanying drawings.

[0038] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Generally, terms defined in dictionaries should be assumed to have the same meaning as in the context of the relevant art, and should not be interpreted anomalously or as having an overly formal meaning unless expressly defined herein.

[0039] In various embodiments of this disclosure, the terms “comprising,” “including,” “containing,” or “comprising” specify properties, areas, fixed quantities, steps, processes, elements, and / or components, but do not exclude other properties, areas, fixed quantities, steps, processes, elements, and / or components.

[0040] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0041] Figure 1 This is a block diagram of a display device according to an embodiment of the present disclosure.

[0042] Reference Figure 1 The display device 1000 includes a signal controller 100, a gate driver 200, a data driver 400, and a display panel 500.

[0043] The display panel 500 includes a plurality of pixels PX connected to a plurality of gate lines GL1 to GLm and a plurality of data lines DL1 to DLn, and displays an image based on output image data R'G'B' (also referred to as image data signal R'G'B'). The plurality of gate lines GL1 to GLm extend in a first direction DR1, and the plurality of data lines DL1 to DLn extend in a second direction DR2 intersecting the first direction DR1. The plurality of pixels PX are arranged in a matrix, and each of the plurality of pixels PX can be electrically connected to one of the plurality of gate lines GL1 to GLm and one of the plurality of data lines DL1 to DLn.

[0044] Signal controller 100 controls the operation of gate driver 200 and data driver 400. Signal controller 100 receives input image data RGB and input control signal CONT from an external device (e.g., a host computer). The input image data RGB may include red grayscale data R, green grayscale data G, and blue grayscale data B for each pixel PX. The input control signal CONT may include a master clock signal, a data enable signal, a vertical synchronization signal, and a horizontal synchronization signal.

[0045] The signal controller 100 generates image data signal R'G'B', gate control signal GCS, and data control signal DCS based on the input image data RGB and the input control signal CONT.

[0046] Specifically, the signal controller 100 can generate an image data signal R'G'B' based on the input image data RGB, and provide the generated image data signal R'G'B' to the data driver 400. The image data signal R'G'B' can be corrected image data generated by correcting the input image data RGB. According to the embodiment, the signal controller 100 can perform image quality correction, spot correction, color characteristic compensation, and / or active capacitance compensation on the input image data RGB.

[0047] Furthermore, the signal controller 100 can generate a gate control signal GCS for controlling the operation of the gate driver 200 based on the input control signal CONT, and provide the generated gate control signal GCS to the gate driver 200. The gate control signal GCS may include a vertical start signal and a gate clock signal. The signal controller 100 can also generate a data control signal DCS for controlling the operation of the data driver 400 based on the input control signal CONT, and provide the generated data control signal DCS to the data driver 400. The data control signal DCS may include a horizontal start signal, a data clock signal, a data load signal, a polarity control signal, and an output control signal.

[0048] The gate driver 200 generates gate signals for driving multiple gate lines GL1 to GLm based on the gate control signal GCS. The gate driver 200 can sequentially apply gate signals to the multiple gate lines GL1 to GLm. Therefore, multiple pixels PX can be driven sequentially in units of pixels connected to the same gate line (i.e., pixel row units).

[0049] The data driver 400 receives a data control signal DCS and an image data signal R'G'B' from the signal controller 100. The data driver 400 generates an analog data voltage based on the data control signal DCS and the digital image data signal R'G'B'. The data driver 400 can sequentially apply data voltages to multiple data lines DL1 to DLn.

[0050] According to one embodiment, the gate driver 200 and / or the data driver 400 are mounted on the display panel 500 in the form of a chip, or can be connected to the display panel 500 in the form of a tape-on-a-package (TCP) or chip-on-film (COF). According to this embodiment, the gate driver 200 and / or the data driver 400 can be integrated into the display panel 500.

[0051] The gate driver 200 is disposed on one or both sides of the display panel 500 to sequentially apply gate signals to the gate lines GL1 to GLm. Figure 1The diagram shows a structure in which the gate driver 200 is connected to one end of the gate lines GL1 to GLm on one side of the display panel 500. However, this disclosure is not limited thereto, and the display device 1000 may have a dual-gate structure in which the gate driver 200 is connected to both sides of the gate lines GL1 to GLm.

[0052] Figure 2 This is a plan view of a display device according to an embodiment of the present disclosure.

[0053] Reference Figure 2 In the display device 1000 according to an embodiment of the present disclosure, the gate driver 200 includes a first gate driving circuit 210 and a second gate driving circuit 220. The first gate driving circuit 210 is connected to a first end of each of the gate lines GL1 to GLm, and the second gate driving circuit 220 is connected to a second end of each of the gate lines GL1 to GLm.

[0054] Each of the first gate driving circuit 210 and the second gate driving circuit 220 may include a shift register that sequentially outputs gate signals. The first gate driving circuit 210 and the second gate driving circuit 220 may operate simultaneously to simultaneously output gate signals to the same gate line. Therefore, each of the gate lines GL1 to GLm can receive a gate signal from the first gate driving circuit 210 and the second gate driving circuit 220 through a first terminal and a second terminal.

[0055] Here, the gate signal output from the first gate driving circuit 210 can be delayed towards the center from the first end of each of the gate lines GL1 to GLm, and the gate signal output from the second gate driving circuit 220 can be delayed towards the center from the second end of each of the gate lines GL1 to GLm. Specifically, there is a difference between the time point at which the gate signal reaches the pixel adjacent to the first end of each gate line and the time point at which the gate signal reaches the pixel adjacent to the center (e.g., the (j+1)th pixel PXj+1) (hereinafter, the turn-on time point).

[0056] For example, the time at which a pixel connected to the first gate line GL1 and the first data line DL1 (hereinafter, the first pixel PX1) turns on in response to the first gate signal may differ from the time at which a pixel connected to the first gate line GL1 and the (j+1)th data line DLj+1 (hereinafter, the (j+1)th pixel PXj+1) turns on in response to the first gate signal. That is, the turn-on time of the (j+1)th pixel PXj+1 may be delayed by a predetermined time from the turn-on time of the first pixel PX1. The delay time of the gate signal can vary depending on the line resistance of each gate line.

[0057] As described above, the conduction time between pixels may vary depending on their position, depending on the line resistance of each gate line. Furthermore, when this conduction time variation occurs between pixels included in the same pixel row, a problem may arise where the charging rate of pixels that are turned on relatively slowly decreases.

[0058] To improve the issue of reduced charging rate, the data driver 400 can take into account the line resistance of each gate line to adjust the timing of the output data voltage.

[0059] Reference Figure 2 The data driver 400 may include a first data integrated circuit 410 and a second data integrated circuit 420. Figure 2 The diagram shows a data driver 400 having a structure including two data integrated circuits 410 and 420, but this disclosure is not limited thereto. That is, the data driver 400 may include three or more data integrated circuits or one data integrated circuit.

[0060] According to an embodiment, the display device 1000 may further include flexible circuit boards 310 and 320 and a printed circuit board 370 electrically connected to the flexible circuit boards 310 and 320, wherein data integrated circuits 410 and 420 are mounted in the flexible circuit boards 310 and 320 in a TCP manner. Specifically, the display device 1000 includes a first flexible circuit board 310 on which a first data integrated circuit 410 is mounted and a second flexible circuit board 320 on which a second data integrated circuit 420 is mounted.

[0061] The first flexible circuit board 310 and the second flexible circuit board 320 are electrically connected to the display panel 500 and the printed circuit board 370, and are disposed between the display panel 500 and the printed circuit board 370. Specifically, one end of each of the first flexible circuit board 310 and the second flexible circuit board 320 can be connected to the printed circuit board 370, and the other end of each of the first flexible circuit board 310 and the second flexible circuit board 320 can be connected to the display panel 500.

[0062] The display panel 500 includes a display area DA for displaying images and a non-display area NDA adjacent to the periphery of the display area DA.

[0063] The display panel 500 may include a plurality of pixels PX1 to PXj+1 disposed in the display area DA. Furthermore, the display panel 500 includes gate lines GL1 to GLm and data lines DL1 to DLj and DLj+1 to DLn that are insulated from and intersect with the gate lines GL1 to GLm.

[0064] In this configuration, the first flexible circuit board 310 and the second flexible circuit board 320 can be connected to the portion of the non-display area NDA of the display panel 500 adjacent to the printed circuit board 370. Although not shown in the figures, the data integrated circuits 410 and 420 can be directly mounted on the non-display area NDA of the display panel 500 using a chip-on-glass (COG) method.

[0065] The first data integrated circuit 410 can be connected to the first group of data lines DL1 to DLj and DLj+1 to DLn, and the second data integrated circuit 420 can be connected to the second group of data lines DLj+1 to DLn. Here, j can be a number corresponding to half of n. Here, the display area DA can include a first driving area DDA1 and a second driving area DDA2, with the first group of data lines DL1 to DLj disposed in the first driving area DDA1 and the second group of data lines DLj+1 to DLn disposed in the second driving area DDA2. Pixels disposed in the first driving area DDA1 can be driven by the first data integrated circuit 410, and pixels disposed in the second driving area DDA2 can be driven by the second data integrated circuit 420.

[0066] Figure 3 yes Figure 2 A magnified plan view of the first data integrated circuit and display panel of part A1. Figure 4 yes Figure 3 The diagram shows the internal block diagram of the first data integrated circuit.

[0067] Reference Figure 3 The first driving region DDA1, which is provided with a first group of data lines DL1 to DLj (hereinafter, the first data line group), can be divided into multiple block regions. As an example of this disclosure, the first driving region DDA1 may include four block regions (hereinafter, the first block region BA1, the second block region BA2, the third block region BA3, and the fourth block region BA4). However, the number of block regions included in the first driving region DDA1 is not limited to this. For example, the first driving region DDA1 may include three or more block regions.

[0068] The first data line groups DL1 to DLj can be divided into multiple blocks, each arranged corresponding to a plurality of block regions. As an example of this disclosure, the first data line groups DL1 to DLj include data lines of a first block (hereinafter, first data line blocks DLa1 to DLak), data lines of a second block (hereinafter, second data line blocks DLb1 to DLbk), data lines of a third block (hereinafter, third data line blocks DLc1 to DLck), and data lines of a fourth block (hereinafter, fourth data line blocks DLd1 to DLdk). The first data line blocks DLa1 to DLak are located in the first block region BA1, and the second data line blocks DLb1 to DLbk are located in the second block region BA2. The third data line blocks DLc1 to DLck are located in the third block region BA3, and the fourth data line blocks DLd1 to DLdk are located in the fourth block region BA4.

[0069] The first data line groups DL1 to DLj are connected to the first data integrated circuit 410 via the first fan-out lines FL1 to FLj (hereinafter referred to as the first fan-out line group). As an example of this disclosure, the first fan-out line groups FL1 to FLj may have different line resistances. Therefore, even if the data voltage is simultaneously output from the first data integrated circuit 410, the time points at which the data voltage arrives at the first data line groups DL1 to DLj may differ from one another when passing through the first fan-out line groups FL1 to FLj with different line resistances.

[0070] As described above, when the first fan-out line groups FL1 to FLj have different line resistances, the first data integrated circuit 410 can take into account the line resistance of each gate line and the line resistance of each of the first fan-out line groups FL1 to FLj to adjust the timing of the output data voltage.

[0071] Reference Figure 4 The first data integrated circuit 410 includes a shift register 411, a latch unit 412, a digital-to-analog converter 413, and an output buffer unit 415.

[0072] Shift register 411 sequentially activates multiple latch clock signals CK1 to CKn based on the horizontal start signal STH and the data clock signal DCK. The horizontal start signal STH and the data clock signal DCK can be included in the signal controller 100 ( Figure 1 The data control signal provided by DCS (as shown in the figure) Figure 1 The signal shown in the diagram.

[0073] The latch unit 412 latches the image data signal R'G'B' in response to the latch clock signals CK1 to CKn provided from the shift register 411. According to an embodiment, the latch unit 412 may simultaneously output the latched image data signal R'G'B' to the digital-to-analog converter 413 based on the data load signal TP, or it may provide the latched image data signal R'G'B' to the digital-to-analog converter 413 with a predetermined time difference. The data load signal TP may be a signal included in the data control signal DCS. According to an embodiment, the latched image data signal R'G'B' is defined as digital image signals D_D1 to D_Dn.

[0074] The digital-to-analog converter 413 receives digital image signals D_D1 to D_Dn from the latch unit 412. The converter 413 converts the received digital image signals D_D1 to D_Dn into data voltages D_A1 to D_An in analog form. Furthermore, although not shown in the figures, multiple gamma voltages from an external source can be provided to the converter 413. The converter 413 can output data voltages D_A1 to D_An corresponding to the digital image signals D_D1 to D_Dn based on the gamma voltages. The data voltages D_A1 to D_An can have positive or negative polarity through a polarity control signal POL provided to the converter 413. The polarity control signal POL can be a signal included in the data control signal DCS. Here, a positively polarized data voltage can be a voltage with a level higher than a reference voltage, and a negatively polarized data voltage can be a voltage with a level lower than a reference voltage.

[0075] The data voltages D_A1 to D_An generated from the digital-to-analog converter 413 are provided to the output buffer unit 415. The output buffer unit 415 may be divided into multiple output blocks, each including one or more output buffers. As an example of this disclosure, the output buffer unit 415 may include four output blocks (hereinafter referred to as the first output block 415a, the second output block 415b, the third output block 415c, and the fourth output block 415d). However, the number of output blocks included in the output buffer unit 415 is not limited thereto. For example, the output buffer unit 415 may include fewer or more than four output blocks.

[0076] The first data integrated circuit 410 may further include a delayed clock generation unit 416. The delayed clock generation unit 416 can generate multiple delayed clocks DCLKa, DCLKb, DCLKc, and DCLKd by reflecting the delay information of each of the multiple output blocks 415a, 415b, 415c, and 415d in a preset reference clock RCLK. Here, the multiple delayed clocks DCLKa, DCLKb, DCLKc, and DCLKd include a delayed clock DCLKa (hereinafter referred to as the first delayed clock block) provided to the first output block 415a, a delayed clock DCLKb (hereinafter referred to as the second delayed clock block) provided to the second output block 415b, a delayed clock DCLKc (hereinafter referred to as the third delayed clock block) provided to the third output block 415c, and a delayed clock DCLKd (hereinafter referred to as the fourth delayed clock block) provided to the fourth output block 415d.

[0077] The delay information of each of the first output block 415a, the second output block 415b, the third output block 415c, and the fourth output block 415d can be stored in the delay clock generation unit 416, or can be provided from an external circuit such as the signal controller 100.

[0078] Output buffer unit 415 receives a first delayed clock block DCLKa, a second delayed clock block DCLKb, a third delayed clock block DCLKc, and a fourth delayed clock block DCLKd from delayed clock generation unit 416. Specifically, synchronized with the first delayed clock block DCLKa, the first output block 415a outputs the data voltages Da1 to Dak of the first block to the first data line blocks DLa1 to DLak (see...). Figure 3 Synchronized with the second delayed clock block DCLKb, the second output block 415b outputs the data voltages Db1 to Dbk of the second block to the second data line blocks DLb1 to DLbk (see...). Figure 3 Synchronized with the third delayed clock block DCLKc, the third output block 415c outputs the data voltages Dc1 to Dck from the third block to the third data line blocks DLc1 to DLck (see...). Figure 3 Synchronized with the fourth delayed clock block DCLKd, the fourth output block 415d outputs the data voltages Dd1 to Ddk of the fourth block to the fourth data line blocks DLd1 to DLdk (see...). Figure 3 ).

[0079] Each of the first output blocks 415a to the fourth output blocks 415d includes a first channel CH1 to a k-th channel CHk, and outputs a corresponding data voltage through the first channel CH1 to the k-th channel CHk. That is, each output block 415a to 415d can determine the time point for outputting the data voltage from the first channel CH1 to the k-th channel CHk in response to the corresponding delayed clock block.

[0080] Figure 5 It is shown in detail Figure 4 The block diagram shown is of the delayed clock generation unit and the output buffer unit. Figure 6A It is shown Figure 5 The waveform diagrams shown are for the first reference clock to the fourth reference clock and the first delay clock block to the fourth delay clock block. Figure 6B It is shown Figure 5 The waveform diagram of the output time points of the data voltage of the first to fourth blocks shown.

[0081] Reference Figure 5 Signal controller 100 ( Figure 1 The diagram shown may include a reference clock generation unit 110. The reference clock generation unit 110 reflects the delay information of each output block 415a to 415d in the data clock signal DCK. Figure 4 As shown in the figure, reference clocks RCLK1, RCLK2, RCLK3 and RCLK4 are used to generate the delay values ​​of the data voltages Dd1 to Ddk output from each output block 415a to 415d. Figure 4 The reference clock RCLK shown may include the reference clocks RCLK1, RCLK2, RCLK3 and RCLK4 described above.

[0082] When the first data integrated circuit 410 ( Figure 4 When the output blocks (shown) include a first output block 415a, a second output block 415b, a third output block 415c, and a fourth output block 415d, the reference clock generation unit 110 can generate a first reference clock RCLK1, a second reference clock RCLK2, a third reference clock RCLK3, and a fourth reference clock RCLK4, and provide them to the first data integrated circuit 410. The first data integrated circuit 410 can independently control the delay values ​​of the first output blocks 415a, the second output block 415b, the third output block 415c, and the fourth output block 415d based on the first reference clock RCLK1, the second reference clock RCLK2, the third reference clock RCLK3, and the fourth reference clock RCLK4.

[0083] exist Figure 5The diagram shows the structure of the reference clock generation unit 110 included in the signal controller 100, but this disclosure is not limited thereto. For example, data integrated circuits 410 and 420 disposed in the display device 1000 (…) Figure 2 Each of the units shown in the figure is provided with a reference clock generation unit 110.

[0084] When the first data integrated circuit 410 ( Figure 4 When the output buffer unit 415 (shown) includes a first output block 415a, a second output block 415b, a third output block 415c, and a fourth output block 415d, the delay clock generation unit 416 may include the first delay clock generation unit 416a, the second delay clock generation unit 416b, the third delay clock generation unit 416c, and the fourth delay clock generation unit 416d. The first delay clock generation unit 416a receives a first reference clock RCLK1 from the reference clock generation unit 110. The first delay clock generation unit 416a can generate first delay clock blocks DCLKa_1 to DCLKa_k by reflecting the delay information of each channel of the first output block 415a in the first reference clock RCLK1. The first delay clock blocks DCLKa_1 to DCLKa_k may include first delay clock signals DCLKa_1 to kth delay clock signals DCLKa_k, which respectively reflect the delay information of the first channel CH1 to the kth channel CHk of the first output block 415a.

[0085] like Figure 5 , Figure 6A and Figure 6B As shown, the first reference clock RCLK1 can be activated from the fourth time point t4 to the fifth time point t5, where the fourth time point t4 is delayed by a fourth time from the reference time point t0, and the fifth time point t5 is delayed by a fifth time from the reference time point t0. That is, the first reference clock RCLK1 can be activated at the fourth time point t4 during the first time period 1t. The k-th delayed clock signal DCLKa_k from the first delayed clock signal DCLKa_1 to the k-th delayed clock signal DCLKa_k can be activated first at the rising time point of the first reference clock RCLK1. In other words, the first delayed clock signals DCLKa_1 to the k-th delayed clock signal DCLKa_k can be activated sequentially from the k-th delayed clock signal DCLKa_k to the first delayed clock signal DCLKa_1. The first delayed clock signals DCLKa_1 to the k-th delayed clock signal DCLKa_k can have a first phase difference with each other. Specifically, the k-th delayed clock signal DCLKa_k and the (k-1)-th delayed clock signal DCLKa_k-1, which are adjacent to each other, have a phase difference obtained by dividing the first time period 1t by the number of channels k. That is, "1t / k" can be defined as the first phase difference.

[0086] The first output block 415a receives the first set of data voltages D_Aa1 to D_Aak from the data voltages D_A1 to D_An generated by the digital-to-analog converter 413. The first output block 415a reflects the delay information in the first set of data voltages D_Aa1 to D_Aak based on the first delay clock signal DCLKa_1 to the k-th delay clock signal DCLKa_k, so as to output the first block's data voltages Da1 to Dak.

[0087] Reference Figure 5 , Figure 6A and Figure 6B The second delayed clock generation unit 416b receives the second reference clock RCLK2 from the reference clock generation unit 110. The second delayed clock generation unit 416b can generate second delayed clock blocks DCLKb_1 to DCLKb_k by reflecting the delay information of each channel of the second output block 415b in the second reference clock RCLK2. The second delayed clock blocks DCLKb_1 to DCLKb_k may include first delayed clock signals DCLKb_1 to kth delayed clock signals DCLKb_k, which respectively reflect the delay information of the first channel CH1 to the kth channel CHk of the second output block 415b.

[0088] The second reference clock RCLK2 can be activated from a first time point t1 to a fourth time point t4, where the first time point t1 is delayed by a first time from the reference time point t0. That is, the second reference clock RCLK2 can be activated at the first time point t1 during the second time period 3t. The k-th delayed clock signal DCLKb_k from the first delayed clock signal DCLKb_1 to the k-th delayed clock signal DCLKb_k can be activated first at the rising time point of the second reference clock RCLK2. In other words, the first delayed clock signal DCLKb_1 to the k-th delayed clock signal DCLKb_k can be activated sequentially from the k-th delayed clock signal DCLKb_k to the first delayed clock signal DCLKb_1. The first delayed clock signal DCLKb_1 to the k-th delayed clock signal DCLKb_k can have a second phase difference with each other. Specifically, the k-th delayed clock signal DCLKb_k and the (k-1)-th delayed clock signal DCLKb_k-1, which are adjacent to each other, have a phase difference obtained by dividing the second time period 3t by the number of channels k. In other words, "3t / k" can be defined as the second phase difference.

[0089] The second output block 415b receives the second set of data voltages D_Ab1 to D_Abk from the data voltages D_A1 to D_An generated by the digital-to-analog converter 413. The second output block 415b reflects the delay information in the second set of data voltages D_Ab1 to D_Abk based on the first delay clock signal DCLKb_1 to the k-th delay clock signal DCLKb_k, so as to output the data voltages Db1 to Dbk of the second block.

[0090] Still refer to Figure 5 , Figure 6A and Figure 6B The third delayed clock generation unit 416c receives a third reference clock RCLK3 from the reference clock generation unit 110. The third delayed clock generation unit 416c can generate third delayed clock blocks DCLKc_1 to DCLKc_k by reflecting the delay information of each channel of the third output block 415c in the third reference clock RCLK3. The third delayed clock blocks DCLKc_1 to DCLKc_k may include first delayed clock signals DCLKc_1 to the kth delayed clock signal DCLKc_k, which respectively reflect the delay information of the first channel CH1 to the kth channel CHk of the third output block 415c.

[0091] The third reference clock RCLK3 can be activated from a first time point t1 to a second time point t2, where the second time point t2 is delayed by a second time from the reference time point t0. That is, the third reference clock RCLK3 can be activated at the first time point t1 during the third time period 1t. The first delayed clock signal DCLKc_1 can be activated first at the rising time point of the third reference clock RCLK3. In other words, the first delayed clock signals DCLKc_1 to the kth delayed clock signal DCLKc_k can be activated sequentially from the first delayed clock signal DCLKc_1 to the kth delayed clock signal DCLKc_k. The first delayed clock signals DCLKc_1 to the kth delayed clock signal DCLKc_k can have a third phase difference with each other. Specifically, the first delayed clock signal DCLKc_1 and the second delayed clock signal DCLKc_2, which are adjacent to each other, have a phase difference obtained by dividing the third time period 1t by the number of channels k. In other words, "1t / k" can be defined as the third phase difference.

[0092] The third output block 415c receives the third set of data voltages D_Ac1 to D_Ack from the data voltages D_A1 to D_An generated by the digital-to-analog converter 413. The third output block 415c reflects the delay information in the third set of data voltages D_Ac1 to D_Ack based on the first delay clock signal DCLKc_1 to the k-th delay clock signal DCLKc_k, so as to output the data voltages Dc1 to Dck of the third block.

[0093] Still refer to Figure 5 , Figure 6A and Figure 6B The fourth delayed clock generation unit 416d receives the fourth reference clock RCLK4 from the reference clock generation unit 110. The fourth delayed clock generation unit 416d can generate the fourth delayed clock blocks DCLKd_1 to DCLKd_k by reflecting the delay information of each channel of the fourth output block 415d in the fourth reference clock RCLK4. The fourth delayed clock blocks DCLKd_1 to DCLKd_k may include the first delayed clock signal DCLKd_1 to the kth delayed clock signal DCLKd_k, which respectively reflect the delay information of the first channel CH1 to the kth channel CHk of the fourth output block 415d.

[0094] The fourth reference clock RCLK4 can be activated from the second time point t2 to the fifth time point t5, where the second time point t2 is delayed by a second time from the reference time point t0. That is, the fourth reference clock RCLK4 can be activated at the second time point t2 during the fourth time period 3t. The first delayed clock signal DCLKd_1 from the first delayed clock signal DCLKd_1 to the k-th delayed clock signal DCLKd_k can be activated first at the rising time point of the fourth reference clock RCLK4. In other words, the first delayed clock signal DCLKd_1 to the k-th delayed clock signal DCLKd_k can be activated sequentially from the first delayed clock signal DCLKd_1 to the k-th delayed clock signal DCLKd_k. The first delayed clock signals DCLKd_1 to the k-th delayed clock signal DCLKd_k can have a fourth phase difference with each other. Specifically, the first delayed clock signal DCLKd_1 and the second delayed clock signal DCLKd_2, which are adjacent to each other, have a phase difference obtained by dividing the fourth time period 3t by the number of channels k. In other words, "3t / k" can be defined as the fourth phase difference.

[0095] The fourth output block 415d receives the fourth set of data voltages D_Ad1 to D_Adk from the data voltages D_A1 to D_An generated by the digital-to-analog converter 413. The fourth output block 415d outputs the fourth set of data voltages D_Ad1 to D_Adk based on the delay information in the fourth set of data voltages D_Ad1 to D_Adk reflected by the first delay clock signal DCLKd_1 to the k-th delay clock signal DCLKd_k.

[0096] like Figure 3 , Figure 4 , Figure 6A and Figure 6B As shown, the data voltages Da1 to Dak of the first block, output from the first channel CH1 to the kth channel CHk of the first output block 415a, are provided to the first data line blocks DLa1 to DLak located in the first block region BA1. The data voltages Db1 to Dbk of the second block, output from the first channel CH1 to the kth channel CHk of the second output block 415b, are provided to the second data line blocks DLb1 to DLbk located in the second block region BA2. Here, the data voltages Da1 to Dak of the first block have a first time difference (1t / k) at the fourth time point t4, and the data voltages from the kth data voltage Dak to the first data voltage Da1 are sequentially delayed. On the other hand, the data voltages Db1 to Dbk of the second block have a second time difference (3t / k) at the first time point t1, and the data voltages from the kth data voltage Dbk to the first data voltage Db1 are sequentially delayed.

[0097] Furthermore, the data voltages Dc1 to Dck of the third block output from the first channel CH1 to the kth channel CHk of the third output block 415c are provided to the third data line blocks DLc1 to DLck arranged in the third block region BA3. The data voltages Dd1 to Ddk of the fourth block output from the first channel CH1 to the kth channel CHk of the fourth output block 415d are provided to the fourth data line blocks DLd1 to DLdk arranged in the fourth block region BA4. Here, the data voltages Dc1 to Dck of the third block have a third time difference (1t / k) at the first time point t1, and are sequentially delayed from the first data voltage Dc1 to the kth data voltage Dck. On the other hand, the data voltages Dd1 to Ddk of the fourth block have a fourth time difference (3t / k) at the second time point t2, and are sequentially delayed from the first data voltage Dd1 to the kth data voltage Ddk.

[0098] Thus, the delay value of the data voltage output from a data integrated circuit can be different for each block. That is, the delay value of the data line is not determined by a single variable, but rather by reflecting all relevant design factors (such as the difference in fan-out line length, the distance from the gate drive circuit, and the number and location of the gate drive circuit). Therefore, there may be situations where the delay value of the data voltage must be set differently for each block. As mentioned above, by controlling the delay value of the data voltage on a block-by-block basis, the delay value can be finely adjusted. As a result, the deviation in charging rate between pixels can be effectively reduced.

[0099] Figure 6B The output waveforms of the data voltages from the first block to the fourth block are shown as an example of this disclosure, exhibiting an inverted V-shape. For instance, due to the first fan-out line group FL1 to FLj ( Figure 3 The length difference between the data voltages shown in the diagram indicates a significant delay in the data voltage. When the gate signal delay is relatively small, the delay value of the data voltage output from the data integrated circuits 410 and 420 can be set based on the length difference between the first fan-out line groups FL1 to FLj. In other words, the output waveform of the data voltage from the first block to the fourth block can be set to an inverted V-shape, where the delay value of the data voltage decreases towards the center of the first fan-out line groups FL1 to FLj. However, the shape of the output waveform of the data voltage from the first block to the fourth block is not limited to this. That is, the shape of the output waveform of the data voltage from the first block to the fourth block can vary in various forms depending on the mounting position of the data integrated circuits 410 and 420, the type of the first fan-out line groups FL1 to FLj, or the degree of gate signal delay.

[0100] Figure 6C This is a waveform diagram showing the output time points from the data voltage of the first block to the data voltage of the fourth block according to another embodiment of the present disclosure.

[0101] Reference Figure 3 , Figure 4 , Figure 5 and Figure 6CThe data voltages Da1 to Dak of the first block output from the first channel CH1 to the kth channel CHk of the first output block 415a are provided to the first data line blocks DLa1 to DLak located in the first block region BA1. The data voltages Db1 to Dbk of the second block output from the first channel CH1 to the kth channel CHk of the second output block 415b are provided to the second data line blocks DLb1 to DLbk located in the second block region BA2. Here, the data voltages Da1 to Dak of the first block have a first time difference (1t / k) at the first time point t1, and the data voltages Da1 to Dak of the first block are sequentially delayed. On the other hand, the data voltages Db1 to Dbk of the second block have a second time difference (3t / k) at the second time point t2, and the data voltages Db1 to Dbk of the second block are sequentially delayed.

[0102] Furthermore, the data voltages Dc1 to Dck of the third block output from the first channel CH1 to the kth channel CHk of the third output block 415c are provided to the third data line blocks DLc1 to DLck arranged in the third block region BA3. The data voltages Dd1 to Ddk of the fourth block output from the first channel CH1 to the kth channel CHk of the fourth output block 415d are provided to the fourth data line blocks DLd1 to DLdk arranged in the fourth block region BA4. Here, the data voltages Dc1 to Dck of the third block have a third time difference (1t / k) at the fourth time point t4, and are sequentially delayed from the kth data voltage Dck to the first data voltage Dc1. On the other hand, the data voltages Dd1 to Ddk of the fourth block have a fourth time difference (3t / k) at the first time point t1, and are sequentially delayed from the kth data voltage Ddk to the first data voltage Dd1.

[0103] Figure 6C The output waveforms of the data voltages from the first block to the fourth block are shown as an example of this disclosure, exhibiting a V-shape. For instance, when the first fan-out line group FL1 to FLj ( Figure 3 When the fan-out lines (as shown in the diagram) have the same length, the delay in data voltage caused by the length difference between the fan-out lines can be so small as to be negligible. In this case, if the first gate drive circuit and the second gate drive circuit are respectively located at both ends of the gate line, the output waveform of the data voltage of the first block to the fourth block of any data integrated circuit can be set to a V-shape, wherein the delay value of the data voltage increases as it moves toward the center of the first fan-out line group FL1 to FLj.

[0104] Figure 7 This is a plan view of a display device according to an embodiment of the present disclosure. Figure 8 yes Figure 7A magnified plan view of the first data integrated circuit and display panel shown in part A2, and Figure 9 It shows that it is applied to Figure 8 The waveform diagram of the output time points of the data voltage of the first block to the data voltage of the fourth block is shown in the figure. Figure 10 yes Figure 7 A magnified plan view of the fourth data integrated circuit and display panel shown in part A3, and Figure 11 It shows that it is applied to Figure 10 The waveform diagram of the output time points of the data voltage of the first block to the data voltage of the fourth block is shown in the figure.

[0105] Reference Figure 7 Data drive 400 (reference) Figure 1 It may include a first data integrated circuit 410, a second data integrated circuit 420, a third data integrated circuit 430, and a fourth data integrated circuit 440. Figure 7 The diagram shows a data driver 400 having a structure including four data integrated circuits 410 to 440, but this disclosure is not limited thereto.

[0106] According to an embodiment, the display device 1000 may further include flexible circuit boards 310 to 340 and a printed circuit board 370 electrically connected to the flexible circuit boards 310 to 340, wherein data integrated circuits 410 to 440 are mounted in the flexible circuit boards 310 to 340 in a TCP (bandwidth package) manner. Specifically, the display device 1000 may include a first flexible circuit board 310 on which a first data integrated circuit 410 is mounted, a second flexible circuit board 320 on which a second data integrated circuit 420 is mounted, a third flexible circuit board 330 on which a third data integrated circuit 430 is mounted, and a fourth flexible circuit board 340 on which a fourth data integrated circuit 440 is mounted.

[0107] The first flexible circuit board 310 to the fourth flexible circuit board 340 are electrically connected to the display panel 500 and the printed circuit board 370, and are disposed between the display panel 500 and the printed circuit board 370.

[0108] The first data integrated circuit 410 can be connected to the first group of data lines DL1 to DLn, and the second data integrated circuit 420 can be connected to the second group of data lines DL1 to DLn. The third data integrated circuit 430 can be connected to the third group of data lines DL1 to DLn, and the fourth data integrated circuit 440 can be connected to the fourth group of data lines DL1 to DLn.

[0109] Here, the display area DA may include a first driving area DDA1 to a fourth driving area DDA4, respectively driven by a first data integrated circuit 410 to a fourth data integrated circuit 440. A first set of data lines is disposed in the first driving area DDA1, and a second set of data lines is disposed in the second driving area DDA2. Furthermore, a third set of data lines is disposed in the third driving area DDA3, and a fourth set of data lines is disposed in the fourth driving area DDA4.

[0110] Reference Figure 8 and Figure 9 The first driving region DDA1, which is provided with the first group of data lines DL1 to DLj (hereinafter, the first data line group), can be divided into multiple block regions. As an example of this disclosure, the first driving region DDA1 may include four block regions (hereinafter, the first block region BA1, the second block region BA2, the third block region BA3, and the fourth block region BA4).

[0111] The first data line groups DL1 to DLj can be divided into multiple blocks, each arranged corresponding to a multiple block area. As an example of this disclosure, the first data line groups DL1 to DLj include first data line blocks DL1 to DLak, second data line blocks DLb1 to DLbk, third data line blocks DLc1 to DLck, and fourth data line blocks DLd1 to DLdk. The first data line blocks DL1 to DLak are located in the first block area BA1, and the second data line blocks DLb1 to DLbk are located in the second block area BA2. The third data line blocks DLc1 to DLck are located in the third block area BA3, and the fourth data line blocks DLd1 to DLdk are located in the fourth block area BA4.

[0112] The first data line groups DL1 to DLj are connected to the first data integrated circuit 410 via the first fan-out line groups FL1 to FLj. As an example of this disclosure, the fan-out lines of the first fan-out line groups FL1 to FLj may have different line resistances. Therefore, even if the data voltage is simultaneously output from the first data integrated circuit 410, the time points at which the data voltage arrives at the first data line groups DL1 to DLj may differ from one another when passing through the first fan-out line groups FL1 to FLj with different line resistances.

[0113] As described above, when the first fan-out line groups FL1 to FLj have different line resistances, the timing of the output data voltage can be adjusted by taking into account the line resistance of each of the first fan-out line groups FL1 to FLj.

[0114] Furthermore, the gate signal output from the first gate drive circuit 210 can be from each gate line GL1 to GLm ( Figure 7The first end of the (shown) is oriented towards the center and delayed. Specifically, there is a difference between the time when the gate signal arrives at the pixel connected to the first data line DL1 in the first data line group DL1 to DLj and the time when the gate signal arrives at the pixel connected to the last data line DLj (hereinafter, the turn-on time).

[0115] For example, the time at which a pixel connected to the first gate line GL1 and the first data line DL1 (hereinafter, the first pixel) turns on in response to the first gate signal may differ from the time at which a pixel connected to the first gate line GL1 and the j-th data line DLj (hereinafter, the j-th pixel) turns on in response to the first gate signal. That is, the turn-on time of the j-th pixel may be delayed by a predetermined time compared to the turn-on time of the first pixel. The delay time of the gate signal can vary depending on the line resistance of each gate line.

[0116] As described above, the conduction time between pixels can vary depending on their position, depending on the line resistance of each gate line. Furthermore, when this conduction time varies between pixels included in the same pixel row, a problem may arise where the charging rate of pixels that are turned on relatively slowly decreases.

[0117] To improve the problem of reduced charging rate, the first data integrated circuit 410 can take into account the line resistance of each gate line to adjust the timing of the output data voltage.

[0118] The first data voltages Da1 to Dak are provided to the first data line blocks DLa1 to DLak located in the first region BA1. The second data voltages Db1 to Dbk are provided to the second data line blocks DLb1 to DLbk located in the second region BA2. Here, the first data voltages Da1 to Dak have a first time difference (1t / k) at the first time point t1, and are sequentially delayed from the first data voltage Da1 to the kth data voltage Dak. On the other hand, the second data voltages Db1 to Dbk have a second time difference (2t / k) at the second time point t2, and are sequentially delayed from the first data voltage Db1 to the kth data voltage Dbk.

[0119] Furthermore, the data voltages Dc1 to Dck of the third block are provided to the third data line blocks DLc1 to DLck, which are located in the third block region BA3. The data voltages Dd1 to Ddk of the fourth block are provided to the fourth data line blocks DLd1 to DLdk, which are located in the fourth block region BA4. Here, the data voltages Dc1 to Dck of the third block have a third time difference (0.5t / k) at the fourth time point t4, and are sequentially delayed from the first data voltage Dc1 to the kth data voltage Dck. On the other hand, the data voltages Dd1 to Ddk of the fourth block have a fourth time difference (1.5t / k) at the 4.5 time point t4.5, and are sequentially delayed from the first data voltage Dd1 to the kth data voltage Ddk.

[0120] Reference Figure 10 and Figure 11 The fourth driving region DDA4, which is equipped with the fourth group of data lines DL3j+1 to DLn (hereinafter, the fourth data line group), can be divided into multiple block regions. As an example of this disclosure, the fourth driving region DDA4 may include four block regions (hereinafter, the first block region BA1, the second block region BA2, the third block region BA3, and the fourth block region BA4). Figure 10 The fourth driving region DDA4 is shown to include the same number of block regions as the first driving region DDA1, but this disclosure is not limited thereto. That is, the fourth driving region DDA4 may include a different number of block regions than the number included in the first driving region DDA1. For example, it is also possible for the fourth driving region DDA4 to include three block regions.

[0121] The fourth data line group DL3j+1 to DLn can be divided into multiple blocks, each arranged corresponding to a multiple block area. As an example of this disclosure, the fourth data line group DL3j+1 to DLn includes first data line blocks DLa1 to DLak, second data line blocks DLb1 to DLbk, third data line blocks DLc1 to DLck, and fourth data line blocks DLd1 to DLdk. The first data line blocks DLa1 to DLak are located in the first block area BA1, and the second data line blocks DLb1 to DLbk are located in the second block area BA2. The third data line blocks DLc1 to DLck are located in the third block area BA3, and the fourth data line blocks DLd1 to DLdk are located in the fourth block area BA4.

[0122] Furthermore, the gate signal output from the second gate drive circuit 220 can be from each gate line GL1 to GLm ( Figure 7The second end of the gate signal is delayed toward the center. Specifically, there is a difference between the time when the gate signal arrives at the pixel connected to the (3j+1)th data line DL3j+1 in the fourth data line group DL3j+1 to DLn and the time when the gate signal arrives at the pixel connected to the last data line DLn (hereinafter, the turn-on time).

[0123] For example, the time at which a pixel connected to the first gate line GL1 and the (3j+1)th data line DL3j+1 (hereinafter, the (3j+1)th pixel) turns on in response to the first gate signal may differ from the time at which a pixel connected to the first gate line GL1 and the nth data line DLn (hereinafter, the nth pixel) turns on in response to the first gate signal. That is, the turn-on time of the (3j+1)th pixel can be delayed by a predetermined time from the turn-on time of the nth pixel. The delay time of the gate signal can vary depending on the line resistance of each gate line.

[0124] As described above, the conduction time between pixels can vary depending on their position, depending on the line resistance of each gate line. Furthermore, when this conduction time varies between pixels included in the same pixel row, a problem may arise where the charging rate of pixels that are turned on relatively slowly decreases.

[0125] To improve the issue of reduced charging rate, the fourth data integrated circuit 440 can take into account the line resistance of each gate line to adjust the timing of the output data voltage.

[0126] like Figure 10 and Figure 11 As shown, data voltages Da1 to Dak of the first block are provided to the first data line blocks DLa1 to DLak located in the first block region BA1. Data voltages Db1 to Dbk of the second block are provided to the second data line blocks DLb1 to DLbk located in the second block region BA2. Here, the data voltages Da1 to Dak of the first block have a first time difference (1.5t / k) at time point t4.5, and are sequentially delayed from the k-th data voltage Dak to the first data voltage Da1. On the other hand, the data voltages Db1 to Dbk of the second block have a second time difference (0.5t / k) at time point t4, and are sequentially delayed from the k-th data voltage Dbk to the first data voltage Db1.

[0127] Furthermore, the data voltages Dc1 to Dck of the third block are provided to the third data line blocks DLc1 to DLck, which are located in the third block region BA3. The data voltages Dd1 to Ddk of the fourth block are provided to the fourth data line blocks DLd1 to DLdk, which are located in the fourth block region BA4. Here, the data voltages Dc1 to Dck of the third block have a third time difference (2t / k) at the second time point t2, and are sequentially delayed from the k-th data voltage Dck to the first data voltage Dc1. On the other hand, the data voltages Dd1 to Ddk of the fourth block have a fourth time difference (1t / k) at the first time point t1, and are sequentially delayed from the k-th data voltage Ddk to the first data voltage Dd1.

[0128] As described above, since the first data integrated circuit 410 and the fourth data integrated circuit 440 are located in different positions, the output timing of the data voltage can be controlled using different delay modes. Furthermore, since each of the first data integrated circuit 410 and the fourth data integrated circuit 440 includes multiple output blocks, the delay value of the data voltage can be adjusted on a block-by-block basis.

[0129] Figure 12 This is a plan view of a display device according to an exemplary embodiment of the present disclosure. Figure 13 yes Figure 12 A magnified plan view of the second to fourth data integrated circuits and the display panel shown in part A4. Figure 14 It shows the application set to Figure 13 The waveform diagram of the output time points of the data voltage of the data lines in the second to fourth drive regions shown in the figure.

[0130] Reference Figure 12 Data drive 400 (reference) Figure 1 This may include a first data integrated circuit 410, a second data integrated circuit 420, a third data integrated circuit 430, a fourth data integrated circuit 440, and a fifth data integrated circuit 450. Figure 12 The diagram shows a data driver 400 having a structure including five data integrated circuits 410 to 450, but this disclosure is not limited thereto.

[0131] According to an embodiment, the display device 1000 may further include flexible circuit boards 310 to 350 and a printed circuit board 370 electrically connected to the flexible circuit boards 310 to 350, wherein data integrated circuits 410 to 450 are mounted in the flexible circuit boards 310 to 350 in a TCP manner. Specifically, the display device 1000 may include a first flexible circuit board 310 on which a first data integrated circuit 410 is mounted, a second flexible circuit board 320 on which a second data integrated circuit 420 is mounted, a third flexible circuit board 330 on which a third data integrated circuit 430 is mounted, a fourth flexible circuit board 340 on which a fourth data integrated circuit 440 is mounted, and a fifth flexible circuit board 350 on which a fifth data integrated circuit 450 is mounted.

[0132] The first flexible circuit board 310 to the fifth flexible circuit board 350 are electrically connected to the display panel 500 and the printed circuit board 370, and are disposed between the display panel 500 and the printed circuit board 370.

[0133] The first data integrated circuit 410 can be connected to the first group of data lines DL1 to DLn, and the second data integrated circuit 420 can be connected to the second group of data lines DL1 to DLn. The third data integrated circuit 430 can be connected to the third group of data lines DL1 to DLn, the fourth data integrated circuit 440 can be connected to the fourth group of data lines DL1 to DLn, and the fifth data integrated circuit 450 can be connected to the fifth group of data lines DL1 to DLn.

[0134] Here, the display area DA may include first driving areas DDA1 to fifth driving areas DDA5, respectively driven by first data integrated circuit 410 to fifth data integrated circuit 450. A first set of data lines is disposed in the first driving area DDA1, and a second set of data lines is disposed in the second driving area DDA2. Furthermore, a third set of data lines is disposed in the third driving area DDA3, and a fourth set of data lines is disposed in the fourth driving area DDA4. A fifth set of data lines is disposed in the fifth driving area DDA5.

[0135] Reference Figure 12 and Figure 13The second data integrated circuit 420 is connected to the second set of data lines DL1, DLag, DLah, DLai, and DLaj, which are arranged in the second driving region DDA2. The third data integrated circuit 430 is connected to the third set of data lines DLb1, DLbg, DLbh, DLbi, and DLbj, which are arranged in the third driving region DDA3. The fourth data integrated circuit 440 is connected to the fourth set of data lines DLc1, DLcg, DLch, DLci, and DLcj, which are arranged in the fourth driving region DDA4. The second driving region DDA2 to the fourth driving region DDA4 are located between the first driving region DDA1 and the fifth driving region DDA5.

[0136] Each of the second driving region DDA2, the third driving region DDA3, and the fourth driving region DDA4 can be divided into multiple block regions. As an example of this disclosure, each of the second driving region DDA2, the third driving region DDA3, and the fourth driving region DDA4 may include four block regions. The second driving region DDA2 includes a first block region BA1a, a second block region BA2a, a third block region BA3a, and a fourth block region BA4a; the third driving region DDA3 includes a first block region BA1b, a second block region BA2b, a third block region BA3b, and a fourth block region BA4b; and the fourth driving region DDA4 includes a first block region BA1c, a second block region BA2c, a third block region BA3c, and a fourth block region BA4c. Compared to the first driving region DDA1 and the fifth driving region DDA5, the second driving region DDA2, the third driving region DDA3, and the fourth driving region DDA4 may have a small delay difference for the gate signal of each block region.

[0137] The second data integrated circuit 420 is connected to the second set of data lines DLa1, DLag, DLah, DLai, and DLaj via the second set of fan-out lines FLa_1, FLa_g, FLa_h, FLa_i, and FLa_j. Here, the second set of fan-out lines FLa_1, FLa_g, FLa_h, FLa_i, and FLa_j can have the same line resistance.

[0138] like Figure 14As shown, the second set of fan-out lines FLa_1, FLa_g, FLa_h, FLa_i, and FLa_j have the same line resistance, and the second driving region DDA2 can include a flat period when the delay difference between the gate signals between the block regions in the second driving region DDA2 is small (or the delay is constant). Here, the flat period can be defined as a period in which the delay values ​​of the data voltages are the same. The flat period provided in the second driving region DDA2 can be referred to as the first flat period FMP1. As an example of this disclosure, the first flat period FMP1 can be formed in the second block region BA2a and the third block region BA3a. Here, the case including the flat period is described as an example, in which the fan-out lines have equal resistance structures and the delay difference between the gate signals is small (or the delay is constant), but this disclosure is not limited to this. That is, when the delay values ​​of the gate signals are designed to be the same, a flat period can exist even in the portion where the delay difference caused by the fan-out lines is small (or the delay is constant).

[0139] Furthermore, the third set of fan-out lines FLb_1, FLb_g, FLb_h, FLb_i, and FLb_j have the same line resistance, and the third driving region DDA3 may include a flat period when the delay difference of the gate signals between the block regions in the third driving region DDA3 is small. Here, the flat period provided in the third driving region DDA3 can be referred to as the second flat period FMP2. As an example of this disclosure, the second flat period FMP2 can be formed in the second block region BA2b and the third block region BA3b.

[0140] Finally, the fourth set of fan-out lines FLc_1, FLc_g, FLc_h, FLc_i, and FLc_j have the same line resistance, and the fourth drive region DDA4 may include a flat period when the delay difference of the gate signals between the block regions in the fourth drive region DDA4 is small. Here, the flat period provided in the fourth drive region DDA4 can be referred to as the third flat period FMP3. As an example of this disclosure, the third flat period FMP3 can be formed in the second block region BA2c and the third block region BA3c.

[0141] In the first flat period FMP1, the output time points of data voltages Dag and Dah can be maintained at time point t3.5, while in the second flat period FMP2, the output time points of data voltages Dbg and Dbh can be maintained at time point t4.5. To prevent the appearance of boundaries in the display area due to the delay difference between the first flat period FMP1 and the second flat period FMP2, a non-flat period with different delay values ​​for the data voltages can be provided between the first flat period FMP1 and the second flat period FMP2. The non-flat period between the first flat period FMP1 and the second flat period FMP2 can be provided in the fourth block region BA4a of the second driving region DDA2 and the first block region BA1b of the third driving region DDA3. The data voltages Dai to Daj provided to the fourth block region BA4a of the second driving region DDA2 have a first time difference (0.5t / (ji)) at time point t3.5, and can be sequentially delayed from the i-th data voltage Dai to the j-th data voltage Daj. The data voltages Db1 to Dbg-1 of the first block of the first block region BA1b provided to the third drive region DDA3 can also have a first time difference (0.5t / (ji)) and can be sequentially delayed from the first data voltage Db1 to the (g-1)th data voltage Dbg-1.

[0142] The output time points of the data voltages Dcg and Dch in the third flat period FMP3 can be maintained at time point t3.5. In this case, to prevent the boundary from being seen in the display area due to the delay difference between the second flat period FMP2 and the third flat period FMP3, a non-flat period with different delay values ​​for the data voltages can be provided between the second flat period FMP2 and the third flat period FMP3. The non-flat period between the second flat period FMP2 and the third flat period FMP3 can be provided in the fourth block region BA4b of the third driving region DDA3 and the first block region BA1c of the fourth driving region DDA4. The data voltages Dbi to Dbj of the fourth block provided to the fourth block region BA4b of the third driving region DDA3 have a second time difference (0.5t / (ji)) at time point t4.5, and can be sequentially delayed from the j-th data voltage Dbj to the i-th data voltage Dbi. The data voltages Dc1 to Dcg-1 of the first block of the first region BA1c supplied to the fourth driving region DDA4 also have a second time difference (0.5t / (ji)), and can be sequentially delayed from the (g-1)th data voltage Dcg-1 to the first data voltage Dc1. Furthermore, the data voltages Dci to Dcj of the fourth block of the fourth region BA4c supplied to the fourth driving region DDA4 have a first time difference (0.5t / (ji)) at the third time point t3, and can be sequentially delayed from the j-th data voltage Dcj to the i-th data voltage Dci.

[0143] Thus, when each of the driving regions DDA2, DDA3, and DDA4 includes a flat period FMP1, FMP2, and FMP3, a block region reflecting the delay value corresponding to the delay deviation between the flat periods FMP1, FMP2, and FMP3 can be set between the flat periods FMP1, FMP2, and FMP3. Therefore, the boundary between the flat periods FMP1, FMP2, and FMP3 can be prevented from being identified.

[0144] Figure 15 It is based on Figure 2 An enlarged plan view of the first data integrated circuit and display panel of another embodiment of part A1, and Figure 16 It shows that it is applied to Figure 15 The waveform diagram of the output time points of the data voltage of the first block to the data voltage of the eighth block is shown in the figure.

[0145] Reference Figure 15The first driving region DDA1, which is provided with the first data line groups DL1 to DLj, can be divided into multiple block regions. As an example of this disclosure, the first driving region DDA1 may include eight block regions (hereinafter, the first block region BA1, the second block region BA2, the third block region BA3, the fourth block region BA4, the fifth block region BA5, the sixth block region BA6, the seventh block region BA7, and the eighth block region BA8). However, the number of block regions included in the first driving region DDA1 is not limited to this. For example, the first driving region DDA1 may include 5 to 7 block regions.

[0146] The first data line groups DL1 to DLj can be divided into multiple blocks, each arranged to correspond to a multiple block region. As an example of this disclosure, the first data line groups DL1 to DLj include first data line blocks DL1 to DLak, second data line blocks DLb1 to DLbk, third data line blocks DLc1 to DLck, fourth data line blocks DLd1 to DLdk, fifth data line blocks DLLe1 to DLek, sixth data line blocks DLf1 to DLfk, seventh data line blocks DLg1 to DLgk, and eighth data line blocks DLh1 to DLhk.

[0147] The first data line blocks DL1 to DLak are located in the first area BA1, the second data line blocks DLb1 to DLbk are located in the second area BA2, the third data line blocks DLc1 to DLck are located in the third area BA3, and the fourth data line blocks DLd1 to DLdk are located in the fourth area BA4. The fifth data line blocks DLLe1 to DLek are located in the fifth area BA5, the sixth data line blocks DLf1 to DLfk are located in the sixth area BA6, the seventh data line blocks DLg1 to DLgk are located in the seventh area BA7, and the eighth data line blocks DLh1 to DLhk are located in the eighth area BA8.

[0148] The first data voltages Da1 to Dak are provided to the first data line blocks DLa1 to DLak located in the first region BA1. The second data voltages Db1 to Dbk are provided to the second data line blocks DLb1 to DLbk located in the second region BA2. Here, the first data voltages Da1 to Dak have a first time difference (0.5t / k) at a reference time point t0, and are sequentially delayed from the first data voltage Da1 to the kth data voltage Dak. On the other hand, the second data voltages Db1 to Dbk have a second time difference (2t / k) at a first time point t1, and are sequentially delayed from the first data voltage Db1 to the kth data voltage Dbk.

[0149] Furthermore, the data voltages Dc1 to Dck of the third block are provided to the third data line blocks DLc1 to DLck, which are located in the third block region BA3. The data voltages Dd1 to Ddk of the fourth block are provided to the fourth data line blocks DLd1 to DLdk, which are located in the fourth block region BA4. Here, the data voltages Dc1 to Dck of the third block are delayed by the same delay value during the first flat period FMP1 (i.e., approximately at time 2.5 (t2.5-t0)). On the other hand, the data voltages Dd1 to Ddk of the fourth block have a third time difference (0.5t / k) at time 2.5, and are sequentially delayed from the first data voltage Dd1 to the kth data voltage Ddk.

[0150] The data voltages De1 to Dek of the fifth block are provided to the fifth data line blocks DLe1 to DLek located in the fifth block area BA5. The data voltages Df1 to Dfk of the sixth block are provided to the sixth data line blocks DLf1 to DLfk located in the sixth block area BA6. The data voltages Dg1 to Dgk of the seventh block are provided to the seventh data line blocks DLg1 to DLgk located in the seventh block area BA7. The data voltages Dh1 to Dhk of the eighth block are provided to the eighth data line blocks DLh1 to DLhk located in the eighth block area BA8.

[0151] Here, the data voltages De1 to Dek of the fifth block have a fourth time difference (1t / k) at the third time point t3, and are sequentially delayed from the first data voltage De1 to the kth data voltage Dek. The data voltages Df1 to Dfk of the sixth block and the data voltages Dg1 to Dgk of the seventh block are delayed by the same delay value during the second flat period FMP2 (i.e., delayed by a fourth time (t4-t0)). On the other hand, the data voltages Dh1 to Dhk of the eighth block have a fifth time difference (1t / k) at the fourth time point t4, and are sequentially delayed from the first data voltage Dh1 to the kth data voltage Dhk.

[0152] In this way, a data integrated circuit is divided into a larger number of output blocks, and the delay value of the data voltage output from a data integrated circuit can be controlled on a block-by-block basis. Therefore, the delay value of the data voltage can be fine-tuned, and as a result, the deviation in charging rate between pixels can be further reduced.

[0153] According to the data driver of this disclosure and the display device having the data driver, by controlling the delay value of the data voltage output from a data integrated circuit on a block-by-block basis, fine adjustment of the delay value can be achieved, thereby reducing the deviation of the charging rate between pixels.

[0154] Although exemplary embodiments of this disclosure have been described, it should be understood that this disclosure is not intended to be limited to these exemplary embodiments, but rather that various changes and modifications can be made by those skilled in the art within the spirit and scope of this disclosure as claimed herein.

Claims

1. Data drives, including: A digital-to-analog converter configured to convert image signal data into multiple data voltages; A delayed clock generation unit is configured to receive a first reference clock and a second reference clock, wherein the first reference clock and the second reference clock are activated at different times during different time periods. The output buffer unit includes multiple channels for outputting the multiple data voltages. The output buffer unit includes multiple output blocks connected to the delayed clock generation unit. Each of the plurality of output blocks includes at least one channel. Specifically, the delayed clock generation unit outputs a first delayed clock signal by reflecting the delay information of the first output block among the plurality of output blocks to the first reference clock, and outputs a second delayed clock signal by reflecting the delay information of the second output block among the plurality of output blocks to the second reference clock. Wherein, the first data voltage output from the first output block is delayed to have a first time difference based on the first delayed clock signal, and The second data voltage output from the second output block is delayed to have a second time difference based on the second delayed clock signal, and the second time difference is different from the first time difference.

2. The data driver according to claim 1, wherein the first reference clock determines the time point at which the first output block outputs the first data voltage, and the second reference clock determines the time point at which the second output block outputs the second data voltage.

3. The data driver according to claim 2, wherein, In the first delayed clock signal, two adjacent first delayed clock signals have a first phase difference. Wherein, two adjacent second delayed clock signals in the second delayed clock signal have a second phase difference, and The first phase difference is different from the second phase difference.

4. The data driver according to claim 3, wherein, The first output block outputs a first data voltage with a first time difference based on the first delayed clock signal, wherein the first time difference corresponds to the first phase difference, and The second output block outputs the second data voltage with the second time difference based on the second delayed clock signal, and the second time difference corresponds to the second phase difference.

5. The data driver according to claim 1, wherein, The data voltages output from at least one of the plurality of output blocks have equal delay values.

6. A display device, comprising: The display panel includes multiple pixels connected to multiple gate lines and multiple data lines; A gate driver configured to generate a plurality of gate signals and apply the plurality of gate signals to the plurality of gate lines; At least one data integrated circuit is configured to generate a plurality of data voltages based on image signal data and apply the plurality of data voltages to the plurality of data lines; as well as A signal controller is configured to control the gate driver and the data integrated circuit, and to generate the image signal data based on the image data. The data integrated circuit includes: A delayed clock generation unit, configured to receive a first reference clock and a second reference clock; and Multiple output blocks are connected to the multiple data lines, and each of the multiple output blocks includes at least one channel. Specifically, the delayed clock generation unit outputs a first delayed clock signal by reflecting the delay information of the first output block among the plurality of output blocks to the first reference clock, and outputs a second delayed clock signal by reflecting the delay information of the second output block among the plurality of output blocks to the second reference clock. Wherein, the first data voltage output from the first output block is delayed to have a first time difference based on the first delayed clock signal, and The second data voltage output from the second output block is delayed to have a second time difference based on the second delayed clock signal, and the second time difference is different from the first time difference. The first reference clock and the second reference clock are activated at different times during different time periods.

7. The display device according to claim 6, wherein, The data integrated circuit includes: A digital-to-analog converter, configured to convert the image signal data into the plurality of data voltages; and The output buffer unit outputs the multiple data voltages. The output buffer unit includes the plurality of output blocks.

8. The display device according to claim 7, wherein, The first reference clock determines the time point at which the first output block outputs the first data voltage, and the second reference clock determines the time point at which the second output block outputs the second data voltage.

9. The display device according to claim 8, wherein, In the first delayed clock signal, two adjacent first delayed clock signals have a first phase difference. Wherein, two adjacent second delayed clock signals in the second delayed clock signal have a second phase difference, and The first phase difference is different from the second phase difference.

10. The display device according to claim 9, wherein, The first output block outputs a first data voltage with a first time difference based on the first delayed clock signal, wherein the first time difference corresponds to the first phase difference, and The second output block outputs the second data voltage with the second time difference based on the second delayed clock signal, and the second time difference corresponds to the second phase difference.

11. The display device according to claim 8, wherein, The signal controller includes a reference clock generation unit, which is configured to generate a first reference clock and a second reference clock and provide the generated first reference clock and the generated second reference clock to the delay clock generation unit.

12. The display device according to claim 6, further comprising a plurality of fan-out lines, the plurality of fan-out lines connecting the plurality of data lines to the data integrated circuit. in, The multiple fan-out lines have equal line resistance.

13. The display device according to claim 12, wherein, The data voltages output from at least one of the plurality of output blocks have equal delay values.

14. The display device according to claim 6, wherein, The gate driver includes: A first gate driving circuit is connected to the first end of the plurality of gate lines; and The second gate drive circuit is connected to the second end of the plurality of gate lines.

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