Low-distortion triangle wave generating circuit and method for generating low-distortion triangle wave

Abstract

A low-distortion triangle wave generating circuit and a method for generating a low-distortion triangle wave. The low-distortion triangle wave generating circuit integrates a charging current and a discharging current on an integrating capacitor in a charging period and a discharging period in a switching cycle of an external clock signal to generate a triangle wave signal, wherein the charging period and the discharging period have the same time length; the low-distortion triangle wave generating circuit generates a common-mode related signal according to the triangle wave signal, wherein the common-mode related signal is related to a common-mode characteristic of the triangle wave signal, and generates an adjustment signal in a gain-based manner according to the difference between the common-mode related signal and a preset DC level; wherein the adjustment signal is used to adjust at least one of the charging current or the discharging current in a feedback manner, so that the triangle wave signal is a symmetrical triangle wave, and the average voltage of the triangle wave signal is equal to a target DC level.

Description

Technical Field

[0001] The present invention relates to a triangle wave generating circuit, in particular to a low-distortion triangle wave generating circuit. The present invention also relates to a method for generating a low-distortion triangle wave. Background Art

[0002] Previous cases related to this application include: US9300281B2, US7746130B2, US8044690B2, "A Sub 1-VConstant Gm–C Switched-Capacitor Current Source, IEEE TRANSACTIONS ON CIRCUITSAND SYSTEMS—II: EXPRESS BRIEFS, VOL.54, NO.3, MARCH 2007", "A Low Area, Switched-Resistor Loop Filter Technique for Fractional-N Synthesizers Applied to aMEMS-based Programmable Oscillator, ISSCC 2010, Session13.1”.

[0003] Figure 1A and Figure 1B A prior art triangular wave generating circuit 101 is shown, wherein two comparators are used to compare the triangular wave signal VTR with a target peak level VH and to compare the triangular wave signal VTR with a target valley level VL, respectively, and the charging current and the discharging current are controlled according to the comparison results of the two comparators, so that in a steady state, the peak value and the valley value of the triangular wave signal VTR can be equal to the target peak level VH and the target valley level VL, respectively.

[0004] The disadvantage of the prior art triangular wave generating circuit 101 is that the time period for modifying and controlling the charging current and the discharging current is limited to a part of the charging or discharging time period. Therefore, the rising slope or the falling slope of the triangular wave signal VTR generated by the prior art will have a turning point, resulting in a higher distortion of the triangular wave signal VTR.

[0005] Figure 2A to Figure 2B A triangle wave generating circuit 102 of the prior art is shown. This prior art also uses two comparators to compare the triangle wave signal VTR with a target peak level VH and to compare the triangle wave signal VTR with a target valley level VL, and controls the charging and discharging time according to the comparison results of the two comparators, so that in a steady state, the peak value and valley value of the triangle wave signal VTR can be equal to the target peak level VH and the target valley level VL, respectively.

[0006] The disadvantage of the prior art triangle wave generating circuit 102 is that when the charging current is not equal to the falling current, the rising time and falling time of the triangle wave signal VTR generated by the prior art will also be not equal, thus causing the generated triangle wave signal VTR to be an asymmetric triangle wave and also have a higher distortion.

[0007] Compared to Figure 1A and Figure 2A Compared with the prior art, the triangular wave signal generated by the present invention has the advantages of single slope and symmetry, and therefore has the advantage of low distortion. Summary of the invention

[0008] From one viewpoint, the present invention provides a low-distortion triangle wave generating circuit, comprising: an integrating circuit for receiving an external clock signal, the integrating circuit integrating an integrating capacitor with a charging current and a discharging current during a charging period and a discharging period in a switching cycle of the external clock signal to generate a triangle wave signal, wherein the charging period and the discharging period have the same time length; and an adjusting control circuit for generating a common-mode related signal according to the triangle wave signal, wherein the common-mode related signal is related to a common-mode characteristic of the triangle wave signal, and the adjusting control circuit generates an adjusting signal in a gain-based manner according to the difference between the common-mode related signal and a preset DC level; wherein the adjusting signal is used to adjust at least one of the charging current or the discharging current in a feedback manner, so that the triangle wave signal is a symmetrical triangle wave, and the average voltage of the triangle wave signal is equal to a target DC level.

[0009] In a preferred embodiment, the regulation control circuit does not adjust the other of the charging current or the discharging current.

[0010] In a preferred embodiment, the regulation control circuit includes: a sampling and holding circuit, which is used to periodically sample and maintain the triangular wave signal at a sampling and holding time point in each switching cycle to generate the common-mode related signal; and an error amplifier circuit, which is used to amplify the difference between the common-mode related signal and the preset DC level to generate the regulation signal, wherein the relationship between the preset DC level and the target DC level is determined by the proportional relationship between the sampling and holding time point and the switching cycle.

[0011] In a preferred embodiment, the sampling and holding circuit samples and maintains the triangular wave signal with a phase difference clock signal, wherein the phase difference clock signal is 90 degrees out of phase with the switching cycle, so as to sample and maintain the middle value of a rising slope or the middle value of a falling slope of the triangular wave signal, thereby generating the common-mode related signal; wherein the error amplifier circuit uses the target DC level as the preset DC level.

[0012] In a preferred embodiment, the low-distortion triangle wave generating circuit is characterized by one of the following: (1) wherein the sampling and holding circuit samples and maintains a peak value of the triangle wave signal using the external clock signal, thereby generating the common-mode related signal; wherein the error amplifier circuit uses a target peak level of the triangle wave signal as the preset DC level; or (2) wherein the sampling and holding circuit samples and maintains a valley value of the triangle wave signal using the external clock signal, thereby generating the common-mode related signal; wherein the error amplifier circuit uses a target valley level of the triangle wave signal as the preset DC level.

[0013] In a preferred embodiment, the sample-and-hold circuit samples and holds the triangle wave signal in an interleaved manner to combine into the common-mode related signal.

[0014] In a preferred embodiment, the regulation control circuit includes a filter amplifier circuit, which includes: an error amplifier; and a low-pass filter feedback network, coupled to the error amplifier in a feedback manner, for receiving the triangular wave signal, wherein the error amplifier and the low-pass filter feedback network amplify the difference between the triangular wave signal and the preset DC level in an active low-pass filtering manner, and simultaneously obtain the common-mode related signal and generate the regulation signal, wherein the error amplifier uses the target DC level as the preset DC level.

[0015] In a preferred embodiment, the regulation control circuit includes: a comparison circuit for comparing the triangular wave signal with a reference signal to generate a pulse width modulation signal; and a filter amplifier circuit, which includes: an error amplifier circuit; and a low-pass filter feedback network coupled to the error amplifier circuit in a feedback manner to receive the pulse width modulation signal, wherein the error amplifier circuit and the low-pass filter feedback network amplify the difference between the pulse width modulation signal and the preset DC level in an active low-pass filtering manner, and simultaneously obtain the common-mode related signal and generate the regulation signal, wherein the preset DC level is related to the reference signal, a target peak level of the triangular wave signal, a target valley level of the triangular wave signal and the amplitude of the pulse width modulation signal, wherein the reference signal is between the target peak level and the target valley level.

[0016] In a preferred embodiment, the reference signal corresponds to the target DC level, and the preset DC level corresponds to 1 / 2 of the amplitude of the PWM signal.

[0017] In a preferred embodiment, the regulation control circuit includes: a comparison circuit for comparing the triangular wave signal with the target DC level to generate a pulse width modulation signal; a duty cycle comparison circuit for comparing the pulse width modulation signal with the external clock signal, or for comparing the pulse width modulation signal with a phase difference clock signal to generate a duty cycle error signal, wherein the phase difference clock signal is 90 degrees different from the phase of the switching cycle; and a filtering circuit for filtering the duty cycle error signal to simultaneously obtain the common-mode related signal and generate the regulation signal.

[0018] In a preferred embodiment, the filtering circuit includes: an error amplifier circuit; and a low-pass filter feedback network, which is coupled to the error amplifier circuit in a feedback manner to receive the duty cycle error signal, wherein the error amplifier circuit and the low-pass filter feedback network amplify the difference between the duty cycle error signal and the preset DC level in an active low-pass filtering manner, and simultaneously obtain the common-mode related signal and generate the adjustment signal, wherein the preset DC level corresponds to 1 / 2 of the amplitude of the duty cycle error signal.

[0019] In a preferred embodiment, the duty cycle comparison circuit includes: a logic comparison circuit for comparing the difference between the pulse width modulation signal and the external clock signal, or for comparing the difference between the pulse width modulation signal and a phase difference clock signal, and generating a pull-up signal and a pull-down signal to represent the duty cycle difference of the rising edge and the falling edge respectively; and a switching circuit, configured as one of the following: (1) the switching circuit includes an upper switch and a lower switch connected in series between a supply voltage and a ground potential, the upper switch and the lower switch are switched under the control of the pull-up signal and the pull-down signal respectively, to generate the duty cycle error signal, wherein the supply voltage and the ground potential are connected in series. The voltage difference between the ground potentials corresponds to the amplitude of the duty cycle error signal, wherein the filter circuit filters the duty cycle error signal to simultaneously obtain the common-mode related signal and generate the adjustment signal; or (2) the switching circuit includes an upper current source and a lower current source connected in series between a supply voltage and a ground potential, which are switched under the control of the pull-up signal and the pull-down signal respectively to generate the duty cycle error signal, wherein the voltage difference between the supply voltage and the ground potential corresponds to the amplitude of the duty cycle error signal, wherein the filter circuit integrates and filters the duty cycle error signal to simultaneously obtain the common-mode related signal and generate the adjustment signal.

[0020] In a preferred embodiment, the integration circuit includes: the integration capacitor; a variable current circuit for generating one of the charging current or the discharging current according to the adjustment signal; a first fixed current source for generating the other of the charging current or the discharging current; and a selection circuit for selecting the charging current or the discharging current to integrate the integration capacitor according to the external clock signal to generate the triangular wave signal.

[0021] In a preferred embodiment, the variable current circuit is configured as one of the following: (1) the variable current circuit includes: a voltage-controlled current source for generating one of the charging current or the discharging current according to the adjustment signal and a transconductance coefficient; (2) the variable current circuit includes: a voltage-controlled current source for generating a variable current according to the adjustment signal and a transconductance coefficient; and a second fixed current source, wherein the sum or difference of the variable current and the current of the second fixed current source corresponds to one of the charging current or the discharging current; (3) the variable current circuit includes: a third fixed current source; and a differential transistor pair for receiving and distributing the second fixed current source to each other. A constant current source, wherein one of the differential transistor pairs is biased at a reference voltage, and the other of the differential transistor pairs is controlled by the adjustment signal, wherein the current flowing through the differential transistor pair corresponds to one of the charging current or the discharging current; or (4) the variable current circuit includes: an analog-to-digital converter, which converts the adjustment signal into a digital switching signal; at least one sub-current source; at least one conversion switch, which is respectively coupled to the at least one sub-current source, wherein the at least one conversion switch receives the digital switching signal to switch accordingly and combine the at least one sub-current source to generate one of the charging current or the discharging current corresponding to the adjustment signal.

[0022] In a preferred embodiment, when the variable current circuit is configured as (1), (2) or (3), the selection circuit includes: a main switch for controlling one of the charging current or the discharging current to integrate the integrating capacitor; and a bypass switch for conducting one of the charging current or the discharging current to a reference potential when the one of the charging current or the discharging current is not integrated with the integrating capacitor.

[0023] From another perspective, the present invention also provides a method for generating a low-distortion triangular wave, comprising: integrating an integrating capacitor with a charging current and a discharging current during a charging period and a discharging period in a switching cycle of an external clock signal to generate a triangular wave signal, wherein the charging period and the discharging period have the same time length; generating a common-mode related signal based on the triangular wave signal, wherein the common-mode related signal is related to a common-mode characteristic of the triangular wave signal, and generating an adjustment signal in a gain-based manner based on the difference between the common-mode related signal and a preset DC level; and adjusting at least one of the charging current or the discharging current based on the adjustment signal in a feedback manner, so that the triangular wave signal is a symmetrical triangular wave, and the average voltage of the triangular wave signal is equal to a target DC level.

[0024] In a preferred embodiment, only one of the charging current or the discharging current is adjusted.

[0025] In a preferred embodiment, the step of generating the adjustment signal includes: periodically sampling and maintaining the triangular wave signal at a sampling and maintaining time point in each switching cycle to generate the common-mode related signal; and amplifying the difference between the common-mode related signal and the preset DC level to generate the adjustment signal, wherein the relationship between the preset DC level and the target DC level is determined by the proportional relationship between the sampling and maintaining time point and the switching cycle.

[0026] In a preferred embodiment, the step of generating the common-mode related signal includes: sampling and maintaining the triangular wave signal with a phase difference clock signal, wherein the phase difference clock signal is 90 degrees out of phase with the switching cycle, so as to sample and maintain the middle value of a rising slope or the middle value of a falling slope of the triangular wave signal, thereby generating the common-mode related signal; wherein the target DC level is used as the preset DC level.

[0027] In a preferred embodiment, the method is characterized by one of the following: (1) sampling and maintaining a peak value of the triangular wave signal using the external clock signal to generate the common-mode related signal; and using a target peak level of the triangular wave signal as the preset DC level; or (2) sampling and maintaining a valley value of the triangular wave signal using the external clock signal to generate the common-mode related signal; and using a target valley value level of the triangular wave signal as the preset DC level.

[0028] In a preferred embodiment, in the step of generating the common-mode correlation signal, the triangle wave signal is sampled and maintained in an interleaved manner to be combined into the common-mode correlation signal.

[0029] In a preferred embodiment, the step of generating the adjustment signal includes: amplifying the difference between the triangle wave signal and the preset DC level by active low-pass filtering, and simultaneously obtaining the common-mode related signal and generating the adjustment signal, wherein the target DC level is used as the preset DC level.

[0030] In a preferred embodiment, the step of generating the adjustment signal includes: comparing the triangular wave signal with a reference signal to generate a pulse width modulation signal; and amplifying the difference between the pulse width modulation signal and the preset DC level in an active low-pass filtering manner, and simultaneously obtaining the common-mode related signal and generating the adjustment signal, wherein the preset DC level is related to the reference signal, a target peak level of the triangular wave signal, a target valley level of the triangular wave signal and the amplitude of the pulse width modulation signal, wherein the reference signal is between the target peak level and the target valley level.

[0031] In a preferred embodiment, the reference signal corresponds to the target DC level, and the preset DC level corresponds to 1 / 2 of the amplitude of the PWM signal.

[0032] In a preferred embodiment, the step of generating the adjustment signal includes: comparing the triangular wave signal with the target DC level to generate a pulse width modulation signal; comparing the pulse width modulation signal with the external clock signal, or comparing the pulse width modulation signal with a phase difference clock signal to generate a duty cycle error signal, wherein the phase difference clock signal is 90 degrees different from the phase of the switching cycle; and filtering the duty cycle error signal to simultaneously obtain the common-mode related signal and generate the adjustment signal.

[0033] In a preferred embodiment, the step of filtering the duty cycle error signal includes: amplifying and filtering the difference between the duty cycle error signal and the preset DC level by active low-pass filtering to simultaneously obtain the common-mode related signal and generate the adjustment signal, wherein the preset DC level corresponds to 1 / 2 of the amplitude of the duty cycle error signal.

[0034] The following detailed description is made through specific embodiments, which should make it easier to understand the purpose, technical content, characteristics and effects achieved by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1A to Figure 1B A prior art triangle wave generating circuit and a corresponding operation waveform diagram are shown.

[0036] Figure 2A to Figure 2B A prior art triangle wave generating circuit and a corresponding operation waveform diagram are shown.

[0037] Figure 3 A schematic diagram showing an embodiment of a low-distortion triangle wave generating circuit of the present invention.

[0038] Figure 4 A schematic diagram showing an embodiment of an adjustment control circuit in the low-distortion triangle wave generating circuit of the present invention.

[0039] Figure 5A The schematic diagram shows a specific embodiment of the sampling and holding circuit and the error amplifier circuit in the low-distortion triangle wave generating circuit of the present invention.

[0040] Figure 5B Display corresponds to Figure 5A Operation waveform diagram.

[0041] Fig. 6A The schematic diagram shows a specific embodiment of the sampling and holding circuit and the error amplifier circuit in the low-distortion triangle wave generating circuit of the present invention.

[0042] Figure 6B Display corresponds to Fig. 6A Operation waveform diagram.

[0043] Fig. 7A The schematic diagram shows a specific embodiment of the sampling and holding circuit and the error amplifier circuit in the low-distortion triangle wave generating circuit of the present invention.

[0044] Figure 7B Display corresponds to Fig. 7A Operation waveform diagram.

[0045] Fig. 8A A schematic diagram showing a specific embodiment of a filter amplifier circuit in the low-distortion triangle wave generating circuit of the present invention.

[0046] Figure 8B Display corresponds to Fig. 8A Operation waveform diagram.

[0047] Fig.9A A schematic diagram showing a specific embodiment of the regulation control circuit in the low-distortion triangle wave generating circuit of the present invention.

[0048] Fig. 9B Display corresponds to Fig.9A Operation waveform diagram.

[0049] Fig. 9C A schematic diagram showing a specific embodiment of a voltage generating circuit in the low-distortion triangle wave generating circuit of the present invention.

[0050] Fig. 10A A schematic diagram showing a specific embodiment of the regulation control circuit in the low-distortion triangle wave generating circuit of the present invention.

[0051] Fig. 10B Display corresponds to Fig. 10A Operation waveform diagram.

[0052] Fig.11A A schematic diagram showing a specific embodiment of the regulation control circuit in the low-distortion triangle wave generating circuit of the present invention.

[0053] Fig. 11B Display corresponds to Fig.11A Operation waveform diagram.

[0054] Fig. 12A A schematic diagram showing a specific embodiment of a duty cycle comparison circuit in the low-distortion triangle wave generating circuit of the present invention.

[0055] Fig. 12B A schematic diagram showing a specific embodiment of a filter circuit in the low-distortion triangle wave generating circuit of the present invention.

[0056] Fig.13 A schematic diagram showing a specific embodiment of a switching circuit and a filtering circuit in the low-distortion triangle wave generating circuit of the present invention.

[0057] Figure 14A to Figure 14B A schematic diagram showing a specific embodiment of an integration circuit in the low-distortion triangle wave generating circuit of the present invention.

[0058] Figures 15A to 15D A schematic diagram showing a specific embodiment of a variable current circuit in the low-distortion triangle wave generating circuit of the present invention.

[0059] Fig.16 A schematic diagram showing a specific embodiment of a variable current circuit in the low-distortion triangle wave generating circuit of the present invention.

[0060] Explanation of symbols in the figure

[0061] 100: Integrator Circuit

[0062] 101~104,105A:Triangle wave generating circuit

[0063] 110A~110B, 115A~115D, 116: Current circuit

[0064] 111: Voltage-controlled current source

[0065] 120: Select Circuit

[0066] 130: Differential transistor pair

[0067] 140: Digital Converter

[0068] 21, 21A, 21B: Sample and hold circuit

[0069] 22, 22A, 22B, 22C: Error amplifier circuit

[0070] 23: Filter amplifier circuit

[0071] 200: Adjustment control circuit

[0072] 221: Error Amplifier

[0073] 222: Low-pass filter feedback network

[0074] 231: Error Amplifier

[0075] 232: Low-pass filter feedback network

[0076] 24A, 24B: Comparison circuit

[0077] 25: Duty cycle comparison circuit

[0078] 251: Logic comparison circuit

[0079] 252A, 252B: Switching circuit

[0080] 26: Filter circuit

[0081] 261: Error Amplifier

[0082] 262: Low-pass filter feedback network

[0083] 28, 28': Filter circuit

[0084] ADJ, ADJU, ADJD: conditioning signals

[0085] CIT: Integrating capacitor

[0086] ckm: pulse width modulation signal

[0087] CLK_e, CLK_eb: external clock signal

[0088] CLK_e90, CLK_e90b: Phase difference clock signal

[0089] Cs1, Cs2: Holding capacitors

[0090] Dadj: Digital switching signal

[0091] Derr: Duty cycle error signal

[0092] DN: Pull-down signal

[0093] Gm: transduction coefficient

[0094] Ichg: Charging current

[0095] Idch: discharge current

[0096] Idf: branch current

[0097] Ifx1, Ifx2, Ifx3: Fixed current sources

[0098] Is1~Isx:Sub-current source

[0099] Ivr: variable current

[0100] SAH: Common mode related signal

[0101] Sup: upper switch

[0102] Sdn: Lower switch

[0103] Sd1~Sdx:conversion switch

[0104] SW1: Main switch

[0105] SW2: Bypass switch

[0106] Tchg: Charging period

[0107] Tdch: discharge period

[0108] Tsw: switching cycle

[0109] UP: pull-up signal

[0110] VCM: Target DC level

[0111] Vdc: Default DC level

[0112] Vdm: common mode related signal

[0113] VH: Target peak level

[0114] VL: Target valley level

[0115] VP: Peak value

[0116] Vpp: Amplitude

[0117] Vref: reference signal

[0118] VTR: triangle wave signal

[0119] VV: Valley value

[0120] Z1, Z2: Feedback elements DETAILED DESCRIPTION

[0121] The drawings in the present invention are all schematic, and are mainly intended to show the coupling relationship between various circuits and the relationship between various signal waveforms. The circuits, signal waveforms and frequencies are not drawn according to scale.

[0122] Figure 3A block diagram of an embodiment of a low-distortion triangle wave generating circuit of the present invention (a triangle wave generating circuit 103) is shown. Figure 3 As shown, in this embodiment, the triangle wave generating circuit 103 includes an integrating circuit 100 and a regulating control circuit 200 .

[0123] The integration circuit 100 is used to receive an external clock signal CLK_e, and in a charging period Tchg and a discharging period Tdch in a switching cycle Tsw of the external clock signal CLK_e, the integration circuit 100 integrates the integration capacitor CIT of the integration circuit 100 with the charging current Ichg and the discharging current Idch respectively to generate a triangular wave signal VTR, wherein the charging period Tchg and the discharging period Tdch have the same time length. In one embodiment, the charging period Tchg and the discharging period Tdch each occupy 50% of the switching cycle Tsw.

[0124] The adjustment control circuit 200 is used to generate a common-mode related signal according to the triangle wave signal VTR, wherein the common-mode related signal is related to a common-mode characteristic of the triangle wave signal VTR, and the adjustment control circuit 200 generates the adjustment signal ADJ in a gain manner according to the difference between the common-mode related signal and a preset DC level Vdc.

[0125] It should be noted that the above-mentioned "common mode characteristics" refer to characteristics related to the common mode value of the triangular wave signal. From one point of view, the common mode value of the triangular wave signal is the low-frequency component or DC component of the triangular wave signal. In one embodiment, the "common mode characteristics" may correspond to the common mode value of the triangular wave signal, or the common mode value plus the offset value, or the peak value or the valley value.

[0126] Please continue reading Figure 3 , the adjustment signal ADJ is used to adjust one of the charging current Ichg or the discharging current Idch in a feedback manner, so that the triangular wave signal VTR is a symmetrical triangular wave, and the average voltage of the triangular wave signal VTR is equal to the target DC level VCM. In other words, at this time, the absolute values ​​of the charging current Ichg and the discharging current Idch are adjusted to be equal to each other by the adjustment signal ADJ.

[0127] From one point of view, when the absolute values ​​of the charging current Ichg and the discharging current Idch are not equal, under the premise that the aforementioned charging period Tchg and the discharging period Tdch respectively occupy 50% of the switching period Tsw, the common mode value of the integrated triangular wave signal VTR will continue to rise or continue to fall. Therefore, when the average voltage of the triangular wave signal VTR is equal to a target DC level VCM, it means that the absolute values ​​of the charging current Ichg and the discharging current Idch are equal. At this time, the triangular wave signal VTR is a symmetrical triangular wave.

[0128] Please continue reading Figure 3 In one embodiment, the integration circuit 103 includes an integration capacitor CIT, current circuits 110A-110B, and a selection circuit 120. In one embodiment, the current circuits 110A-110B are respectively used to provide the above-mentioned charging current Ichg or discharging current Idch. In one embodiment, the selection circuit selects the charging current Ichg or the discharging current Idch to integrate the integration capacitor CIT according to the external clock signal CLK_e (and its inverted signal: the external clock signal CLK_eb). Specifically, the external clock signal CLK_eb is used to control the conduction of the charging current Ichg, and the external clock signal CLK_e is used to control the conduction of the discharging current Idch.

[0129] In addition, according to the present invention, at least one of the current circuits 110A-110B is variable. Specifically, in one embodiment, at least one of the current circuits 110A-110B is variable. In this case, the integration circuit 100 controls the current value of the charging current Ichg or the discharging current Idch according to the adjustment signal ADJ. Specifically, the adjustment signal ADJU is used to control the current value of the charging current Ichg, and the adjustment signal ADJD is used to control the current value of the discharging current Idch.

[0130] In one embodiment, according to the present invention, the regulation control circuit 200 does not adjust the other of the charging current Ichg or the discharging current Idch. In other words, in one embodiment, the regulation control circuit 200 only adjusts one of the charging current Ichg or the discharging current Idch through the adjustment signal ADJ, and the other is a fixed current value. Under this configuration, the absolute current values ​​of the charging current Ichg and the discharging current Idch are more easily adjusted to be equal, that is, the triangular wave signal VTR can be more symmetrical.

[0131] Of course, in other embodiments, the charging current Ichg and the discharging current Idch are adjusted according to the adjustment signal ADJ at the same time, which is also in line with the spirit of the present invention.

[0132] Figure 4A schematic diagram of an embodiment of the regulation control circuit in the low-distortion triangle wave generating circuit (104) of the present invention is shown. In this embodiment, the regulation control circuit 200 includes a sampling and holding circuit 21 and an error amplifier circuit 22. The sampling and holding circuit 21 is used to periodically sample and maintain the triangle wave signal VTR at the sampling and holding time point in each switching cycle Tsw to generate a common-mode related signal. The error amplifier circuit 22 is used to amplify the difference between the common-mode related signal and the preset DC level Vdc to generate an adjustment signal ADJ, wherein the relationship between the preset DC level Vdc and the target DC level VCM is determined by the proportional relationship between the sampling and holding time point and the switching cycle Tsw. The feedback elements Z1 and Z2 in the error amplifier circuit 22 can be configured as resistive elements or capacitive elements as required. The specific configuration details of the sampling and holding circuit 21 are described in detail below.

[0133] Figure 5A A schematic diagram showing a specific embodiment of a sampling and holding circuit and an error amplifier circuit in a low-distortion triangle wave generating circuit (105A) of the present invention. Figure 5B Display corresponds to Figure 5A In this embodiment, the sampling and holding circuit 21A samples and maintains the triangular wave signal VTR with the phase difference clock signal CLK_e90, wherein the phase difference clock signal CLK_e90 is 90 degrees different from the switching period Tsw, so as to sample and maintain the middle value of the rising slope or the middle value of the falling slope of the triangular wave signal VTR, thereby generating the aforementioned common mode correlation signal. Figure 5A and Figure 5B As shown, in this embodiment, since the middle value of the rising slope or the middle value of the falling slope of the triangular wave signal VTR is sampled and maintained, the preset DC level Vdc in the error amplifier circuit 22A is configured as the target DC level VCM. In other words, by adjusting at least one of the charging current Ichg or the discharging current Idch as mentioned above, when the middle value of the rising slope or the middle value of the falling slope of the triangular wave signal VTR is adjusted to the target DC level VCM, the triangular wave signal VTR can be made into a symmetrical triangular wave, and the average voltage of the triangular wave signal VTR is equal to the target DC level VCM. In one embodiment, the error amplifier circuit 22A includes an error amplifier 221 and a low-pass filter feedback network 222.

[0134] Specifically, in this embodiment, the sampling and holding circuit 21A includes a holding capacitor Cs1 and a corresponding sampling switch, which is used to perform a sampling and holding operation on the triangular wave signal VTR according to the phase difference clock signals CLK_e90 and CLK_e90b to generate the sampling and holding signals SAH0 and SAH (corresponding to the common mode related signal). In one embodiment, the sampling and holding circuit 21A further includes a holding capacitor Cs2 and a corresponding sampling switch.

[0135] In one embodiment, if Figure 5B As shown, the sampling and holding circuit 21A samples and holds the triangular wave signal VTR in an interleaved manner to combine into the common mode related signal (SAH). Specifically, the holding capacitor Cs2 and the corresponding sampling switch sample and hold the triangular wave signal VTR in an interleaved manner to generate the sampling and holding signal SAH1, and then the sample and holding signal SAH1 and SAH0 are combined into the common mode related signal (SAH) by the switch at the back end.

[0136] Fig. 6A The schematic diagram shows a specific embodiment of the sampling and holding circuit and the error amplifier circuit in the low-distortion triangle wave generating circuit of the present invention. Figure 6B Display corresponds to Fig. 6A In this embodiment, the sampling and holding circuit 21B samples and holds the peak value VP of the triangular wave signal VTR with the external clock signal CLK_e, thereby generating a common-mode correlation signal (SAH). In other words, the common-mode correlation signal SAH in this embodiment corresponds to the peak value VP of the triangular wave signal VTR; Fig. 6A and Figure 6B As shown, in this embodiment, the preset DC level Vdc in the error amplifier circuit 22B is configured as the target peak level VH of the triangular wave signal VTR. In other words, by adjusting at least one of the charging current Ichg or the discharging current Idch as described above, when the peak value of the triangular wave signal VTR is adjusted to the target peak level VH, the triangular wave signal VTR can be made into a symmetrical triangular wave, and the average voltage of the triangular wave signal VTR is equal to the target DC level VCM. In one embodiment, the sampling and holding circuit 21B still has two sets of holding capacitors and corresponding sampling switches, which can offset the interference caused by sampling the triangular wave signal VTR.

[0137] Fig. 7A The schematic diagram shows a specific embodiment of the sampling and holding circuit and the error amplifier circuit in the low-distortion triangle wave generating circuit of the present invention. Figure 7B Display corresponds to Fig. 7A In this embodiment, the sampling and holding circuit 21 samples and holds the valley value VV of the triangular wave signal VTR with the external clock signal CLK_e, thereby generating a common-mode related signal (SAH). In other words, the common-mode related signal SAH in this embodiment corresponds to the valley value VV of the triangular wave signal VTR; Fig. 7A and Figure 7BAs shown, in this embodiment, the preset DC level Vdc in the error amplifier circuit 22C is configured as the target valley level VL of the triangular wave signal VTR. In other words, by adjusting at least one of the charging current Ichg or the discharging current Idch as described above, when the valley value VV of the triangular wave signal VTR is adjusted to the target valley level VL, the triangular wave signal VTR can be made into a symmetrical triangular wave, and the average voltage of the triangular wave signal VTR can be equal to the target DC level VCM.

[0138] Fig. 8A A schematic diagram showing a specific embodiment of a filter amplifier circuit in the low-distortion triangle wave generating circuit of the present invention. Figure 8B Display corresponds to Fig. 8A In this embodiment, as shown in FIG. Fig. 8A As shown, the regulation control circuit 200 includes a filter amplifier circuit 23 . In one embodiment, the filter amplifier circuit 23 includes an error amplifier 231 and a low-pass filter feedback network 232 .

[0139] The error amplifier 231 and the low-pass filter feedback network 232 are coupled to each other in a feedback manner to receive the triangular wave signal VTR, wherein the error amplifier circuit 231 and the low-pass filter feedback network 232 amplify the difference between the triangular wave signal VTR and the preset DC level Vdc, for example, by means of active low-pass filtering, and simultaneously obtain the common-mode related signal and generate the adjustment signal ADJ by means of active low-pass filtering, wherein the error amplifier 231 uses the target DC level VCM as the preset DC level Vdc. In this embodiment, the common-mode related signal may correspond to the voltage Vdm at the negative input terminal of the error amplifier circuit 22. In other words, by adjusting at least one of the charging current Ichg or the discharging current Idch as mentioned above, when the common-mode related signal Vdm of the triangular wave signal VTR is adjusted to the target DC level VCM, the triangular wave signal VTR can be made into a symmetrical triangular wave, and the average voltage of the triangular wave signal VTR is equal to the target DC level VCM.

[0140] Fig.9A A schematic diagram showing a specific embodiment of the regulation control circuit in the low-distortion triangle wave generating circuit of the present invention. Fig. 9B Display corresponds to Fig.9A Operation waveform diagram. Fig. 9C The schematic diagram of a specific embodiment of the voltage generating circuit in the low-distortion triangle wave generating circuit of the present invention is shown. In this embodiment, the regulating control circuit 200 includes a comparison circuit 24A and a filter amplifier circuit 23 .

[0141] The comparison circuit 24A is used to compare the triangular wave signal VTR with the reference signal Vref to generate a pulse width modulation signal ckm. The filter amplifier circuit 23 is similar to the aforementioned filter amplifier circuit 23, and is used to receive the pulse width modulation signal ckm, wherein the error amplifier circuit 231 and the low-pass filter feedback network 232 amplify the difference between the pulse width modulation signal ckm and the preset DC level Vdc in an active low-pass filtering manner, and simultaneously obtain a common mode related signal (Vdm) and generate an adjustment signal ADJ. In this embodiment, the common mode related signal may correspond to the voltage of the negative input terminal of the error amplifier circuit 231 (corresponding to Vdm).

[0142] In this embodiment, the preset DC level Vdc is related to the reference signal Vref, the target peak level VH of the triangle wave signal VTR, the target valley level VL of the triangle wave signal VTR, and the amplitude of the pulse width modulation signal ckm. Fig. 9C Specifically, in one embodiment, if Fig. 9C As shown, the voltage generating circuit 29 obtains a reference signal Vref between a target peak level VH and a target valley level VL by means of a voltage dividing circuit on the left side. In addition, the voltage dividing circuit on the right side divides the amplitude Vpp of the pulse width modulation signal ckm to generate a preset DC level Vdc according to the ratio of the reference signal Vref to the difference between the target peak level VH and the target valley level VL. In other words, by adjusting at least one of the charging current Ichg or the discharging current Idch as mentioned above, when the common mode related signal Vdm of the triangular wave signal VTR is adjusted to the preset DC level Vdc, the triangular wave signal VTR can be made into a symmetrical triangular wave, and the average voltage of the triangular wave signal VTR can be made equal to the target DC level VCM.

[0143] Fig. 10A A schematic diagram showing a specific embodiment of the regulation control circuit in the low-distortion triangle wave generating circuit of the present invention. Fig. 10B Display corresponds to Fig. 10A Operation waveform diagram. Fig. 10A and Fig. 10B Can be regarded as the aforementioned Figure 9A to Figure 9BA specific embodiment of the embodiment of the present invention, in this embodiment, the aforementioned reference signal Vref for comparison corresponds to the target DC level VCM, and the preset DC level Vdc corresponds to 1 / 2 of the amplitude of the pulse width modulation signal ckm, that is, Vpp / 2. In other words, in this embodiment, the comparison circuit 24B is used to compare the triangular wave signal VTR with the target DC level VCM to generate the pulse width modulation signal ckm, and by adjusting at least one of the charging current Ichg or the discharging current Idch, when the common mode related signal Vdm of the triangular wave signal VTR is adjusted to Vpp / 2, the triangular wave signal VTR can be made into a symmetrical triangular wave, and the average voltage of the triangular wave signal VTR is equal to the target DC level VCM.

[0144] Fig.11A A schematic diagram showing a specific embodiment of the regulation control circuit in the low-distortion triangle wave generating circuit of the present invention. Fig. 11B Display corresponds to Fig.11A In this embodiment, the regulation control circuit 200 includes a comparison circuit 24B, a duty cycle comparison circuit 25 and a filter circuit 26.

[0145] The comparison circuit 24B is used to compare the triangular wave signal VTR with the target DC level VCM to generate the pulse width modulation signal ckm. The duty ratio comparison circuit 25 is used to compare the pulse width modulation signal ckm with the external clock signal CLK_e, or to compare the pulse width modulation signal ckm with the phase difference clock signal CLK_e90 to generate the duty ratio error signal Derr, wherein the phase difference clock signal CLK_e90 is 90 degrees different from the switching period Tsw. The filter circuit 26 is used to filter the duty ratio error signal Derr to simultaneously obtain the common mode correlation signal (Vdm) and generate the adjustment signal ADJ.

[0146] In this embodiment, the error amplifier 261 and the low-pass filter feedback network 262 of the filter circuit 26 are coupled to each other in a feedback manner to receive the duty cycle error signal Derr, wherein the error amplifier 261 and the low-pass filter feedback network 262 amplify the difference between the duty cycle error signal Derr and the preset DC level Vdc in an active low-pass filtering manner, and simultaneously obtain the common mode related signal Vdm and generate the adjustment signal ADJ, wherein the preset DC level Vdc corresponds to 1 / 2 of the amplitude of the duty cycle error signal Derr, i.e., Vpp / 2. In other words, in this embodiment, by adjusting at least one of the charging current Ichg or the discharging current Idch as described above, when the common mode value Vdm of the duty cycle error signal Derr (i.e., the common mode related signal of the triangular wave signal VTR in this embodiment) is adjusted to Vpp / 2, the triangular wave signal VTR can be made into a symmetrical triangular wave, and the average voltage of the triangular wave signal VTR can be made equal to the target DC level VCM.

[0147] Please also see Fig. 12A , Fig. 12A A schematic diagram of a specific embodiment of a duty cycle comparison circuit in the low-distortion triangle wave generating circuit of the present invention is shown. In one embodiment, the duty cycle comparison circuit 25 includes a logic comparison circuit 251 and a switching circuit 252A. The logic comparison circuit 251 is used to compare the difference between the pulse width modulation signal ckm and the external clock signal CLK_e, or to compare the difference between the pulse width modulation signal ckm and the phase difference clock signal CLK_e90, and generate a pull-up signal UP and a pull-down signal DN to represent the difference in the duty cycle of the rising edge and the falling edge respectively. In this embodiment, as Fig. 12A As shown, the switching circuit 252A includes an upper switch Sup and a lower switch Sdn which are connected in series between the supply voltage Vpp and the ground potential. The upper switch Sup and the lower switch Sdn are switched under the control of the pull-up signal UP and the pull-down signal DN respectively to generate a duty cycle error signal Derr, wherein the voltage difference between the supply voltage Vpp and the ground potential corresponds to the amplitude (i.e., Vpp) of the duty cycle error signal Derr, wherein the filtering circuit 26 filters the duty cycle error signal Derr to simultaneously obtain a common-mode related signal and generate an adjustment signal ADJ.

[0148] Fig. 12B Another specific embodiment of the filter circuit in the low-distortion triangle wave generating circuit of the present invention is shown in the schematic diagram. In the embodiment of the above-mentioned regulation control circuit 200 including the switching circuit 252A, the filter circuit can also be Fig. 12B The passive filter circuit 28 replaces the aforementioned filter circuit 26 to filter the duty cycle error signal Derr to simultaneously obtain the common-mode correlation signal and generate the adjustment signal ADJ.

[0149] Fig.13 A schematic diagram of a specific embodiment of the switching circuit and the filtering circuit in the low-distortion triangle wave generating circuit of the present invention is shown. In this embodiment, the switching circuit 252B includes an upper current source Iup and a lower current source Idn connected in series between the supply voltage Vpp and the ground potential, which are respectively switched under the control of the pull-up signal UP and the pull-down signal DN to generate a duty cycle error signal Derr, wherein the voltage difference between the supply voltage Vpp and the ground potential corresponds to the amplitude of the duty cycle error signal Derr, wherein the filtering circuit 28' integrates and filters the duty cycle error signal Derr to simultaneously obtain a common-mode related signal and generate an adjustment signal ADJ.

[0150] Figure 14A to Figure 14B A schematic diagram showing a specific embodiment of an integration circuit in a low-distortion triangle wave generating circuit of the present invention. Fig.14AAs shown, the integration circuit 100A includes an integration capacitor CIT, a variable current circuit 110A, a fixed current source Ifx1, and a selection circuit 120. The variable current circuit 110A is used to generate a charging current Ichg according to an adjustment signal ADJ, and the first fixed current source Ifx1 is used to generate a discharge current Idch. The selection circuit 120 is used to select the charging current Ichg or the discharge current Idch to integrate the integration capacitor CIT according to an external clock signal CLK_e to generate a triangular wave signal VTR.

[0151] In one embodiment, if Fig. 14B As shown, the integration circuit 100B includes an integration capacitor CIT, a variable current circuit 110B, a fixed current source Ifx2, and a selection circuit 120. The variable current circuit 110B is used to generate a discharge current Idch according to an adjustment signal ADJ, and the fixed current source Ifx2 is used to generate a charging current Ichg. The selection circuit 120 is used to select the charging current Ichg or the discharging current Idch to integrate the integration capacitor CIT according to an external clock signal CLK_e to generate a triangular wave signal VTR.

[0152] Figures 15A to 15D A schematic diagram showing a specific embodiment of a variable current circuit in the low-distortion triangle wave generating circuit of the present invention.

[0153] In one embodiment, if Fig.15A As shown, the variable current circuit 115A includes a voltage-controlled current source 111, which is used to generate a charging current Ichg according to an adjustment signal ADJ (ADJU in this embodiment) and a transconductance coefficient Gm. In other embodiments, the voltage-controlled current source 111 can also be used to generate a discharging current Idch according to an adjustment signal ADJD and a transconductance coefficient Gm.

[0154] In one embodiment, if Fig. 15B and Fig. 15C As shown, the variable current circuit (115B, 115C) includes a voltage-controlled current source 111 and a fixed current source Ifx2, which is used to generate a variable current Ivr according to an adjustment signal ADJ and a transconductance coefficient Gm, wherein the sum of the variable current Ivr and the current of the fixed current source Ifx2 ( Fig. 15B ) or the current difference ( Fig. 15C ) corresponds to the charging current Ichg. In other embodiments, the sum of the currents ( Fig. 15B ) or the current difference ( Fig. 15C ) can be used to generate a discharge current Idch according to the adjustment signal ADJD and the transduction coefficient Gm.

[0155] In one embodiment, if Fig.15DAs shown, the variable current circuit 115D includes a fixed current source Ifx3 and a differential transistor pair 130. The transistors M1 and M2 of the differential transistor pair 130 receive and share the fixed current source Ifx3. The transistor M1 of the differential transistor pair is biased at a reference voltage (e.g., ground potential), and the transistor M2 of the differential transistor pair is controlled by an adjustment signal ADJ (e.g., Fig.15D ADJU), wherein the current flowing through the transistor M2 of the differential transistor pair corresponds to the charging current Ichg. Specifically, in this embodiment, the charging current Ichg=fixed current source Ifx3-branch current Idf. In other embodiments, the current flowing through one of the differential transistor pairs can be used to generate the discharge current Idch according to the adjustment signal ADJD and the transconductance coefficient Gm.

[0156] Please continue to refer to the figure Figures 15A to 15D In one embodiment, the selection circuit 120 includes a main switch SW1 and a bypass switch SW2. The main switch SW1 is used to control one of the charging current Ichg or the discharging current Idch to integrate the integration capacitor CIT, and the bypass switch SW2 is used to conduct one of the charging current Ichg or the discharging current Idch to the reference potential when one of the charging current Ichg or the discharging current Idch is not integrated with the integration capacitor CIT, thereby reducing interference caused by switching.

[0157] Fig.16 A schematic diagram showing a specific embodiment of a variable current circuit in a low-distortion triangle wave generating circuit of the present invention. Fig.16 As shown, the variable current circuit 116 includes an analog-to-digital converter 140, at least one sub-current source (such as Is1 to Isx in the figure, x is a positive integer) and a corresponding at least one conversion switch (such as Sd1 to Sdx in the figure, x is a positive integer). The analog-to-digital converter 140 converts the adjustment signal ADJ into a digital switching signal Dadj. The at least one sub-current source is coupled to the at least one conversion switch respectively, wherein the at least one conversion switch receives the digital switching signal Dadj to switch accordingly and combine the at least one sub-current source to generate one of the charging current Ichg or the discharging current Idch corresponding to the adjustment signal ADJ.

[0158] The present invention has been described above with respect to the preferred embodiment, but the above is only to make it easy for those skilled in the art to understand the content of the present invention, and is not used to limit the scope of rights of the present invention. The various embodiments described are not limited to individual applications, but can also be used in combination. For example, two or more embodiments can be used in combination, and part of the components in one embodiment can also be used to replace the corresponding components in another embodiment. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the present invention refers to "processing or calculating or generating an output result according to a certain signal", which is not limited to the signal itself, but also includes, when necessary, converting the signal to voltage and current, current and voltage, and / or ratio conversion, and then processing or calculating according to the converted signal to generate an output result. It can be seen from this that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which are not listed one by one here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A low-distortion triangle wave generating circuit, comprising: an integration circuit for receiving an external clock signal, wherein the integration circuit integrates an integration capacitor with a charging current and a discharging current during a charging period and a discharging period in a switching cycle of the external clock signal to generate a triangular wave signal, wherein the charging period and the discharging period have the same time length; as well as a regulating control circuit for generating a common-mode related signal according to the triangular wave signal, wherein the common-mode related signal is related to a common-mode characteristic of the triangular wave signal, and the regulating control circuit generates a regulating signal in a manner having a gain according to a difference between the common-mode related signal and a predetermined DC level; wherein the regulating signal is used to adjust at least one of the charging current or the discharging current in a feedback manner, so that the triangular wave signal is a symmetrical triangular wave, and the average voltage of the triangular wave signal is equal to a target DC level; in, The regulation control circuit comprises: A sampling and holding circuit, used for periodically sampling and holding the voltage of the triangular wave signal at a sampling and holding time point in each switching cycle to generate the common-mode related signal; as well as An error amplifier circuit is used to amplify the difference between the common mode related signal and the preset DC level to generate the adjustment signal, wherein the relationship between the preset DC level and the target DC level is determined by the proportional relationship between the sampling and holding time point and the switching period.

2. The low-distortion triangle wave generating circuit as claimed in claim 1, wherein: The sampling and holding circuit samples and holds the voltage of the triangular wave signal with a phase difference clock signal, wherein the phase difference clock signal is 90 degrees different from the phase of the switching cycle, so as to sample and hold the middle voltage of a rising slope or a falling slope of the triangular wave signal, thereby generating the common-mode related signal; The error amplifier circuit uses the target DC level as the preset DC level.

3. The low-distortion triangle wave generating circuit as claimed in claim 1, wherein: One of the following: (1) wherein the sample-and-hold circuit samples and holds a peak voltage of the triangular wave signal using the external clock signal, thereby generating the common-mode related signal; wherein the error amplifier circuit uses a target peak level of the triangular wave signal as the preset DC level; or (2) The sampling and holding circuit samples and maintains a valley voltage of the triangular wave signal using the external clock signal, thereby generating the common-mode related signal; and the error amplifier circuit uses a target valley level of the triangular wave signal as the preset DC level.

4. The low-distortion triangle wave generating circuit as claimed in claim 2, wherein: The sampling and holding circuit samples and holds the voltage of the triangle wave signal in an interleaved manner to combine into the common-mode related signal.

5. The low-distortion triangle wave generating circuit as claimed in claim 1, wherein: The regulation control circuit only adjusts one of the charging current or the discharging current.

6. A low-distortion triangle wave generating circuit, comprising: an integration circuit for receiving an external clock signal, wherein the integration circuit integrates an integration capacitor with a charging current and a discharging current during a charging period and a discharging period in a switching cycle of the external clock signal to generate a triangular wave signal, wherein the charging period and the discharging period have the same time length; as well as a regulating control circuit for generating a common-mode related signal according to the triangular wave signal, wherein the common-mode related signal is related to a common-mode characteristic of the triangular wave signal, and the regulating control circuit generates a regulating signal in a manner having a gain according to a difference between the common-mode related signal and a predetermined DC level; The regulating signal is used to adjust at least one of the charging current or the discharging current in a feedback manner so that the triangular wave signal is a symmetrical triangular wave and the average voltage of the triangular wave signal is equal to a target DC level. in, The regulation control circuit comprises: a comparison circuit for comparing the triangle wave signal with the target DC level to generate a pulse width modulation signal; a duty cycle comparison circuit for comparing the pulse width modulation signal with the external clock signal, or for comparing the pulse width modulation signal with a phase difference clock signal to generate a duty cycle error signal, wherein the phase difference clock signal is 90 degrees out of phase with the switching cycle; and a filter circuit for filtering the duty cycle error signal to simultaneously obtain the common mode related signal and generate the adjustment signal; Wherein, the duty cycle comparison circuit comprises: a logic comparison circuit for comparing the difference between the pulse width modulation signal and the external clock signal, or for comparing the difference between the pulse width modulation signal and a phase difference clock signal, and generating a pull-up signal and a pull-down signal to represent the duty cycle difference of the rising edge and the falling edge respectively; and A switching circuit configured as one of the following: (1) the switching circuit comprises an upper switch and a lower switch connected in series between a supply voltage and a ground potential, the upper switch and the lower switch are respectively switched under the control of the pull-up signal and the pull-down signal to generate the duty cycle error signal, wherein the voltage difference between the supply voltage and the ground potential corresponds to the amplitude of the duty cycle error signal, wherein the filter circuit filters the duty cycle error signal to simultaneously obtain the common-mode correlation signal and generate the adjustment signal; or (2) The switching circuit includes an upper current source and a lower current source connected in series between a supply voltage and a ground potential, and are switched under the control of the pull-up signal and the pull-down signal respectively to generate the duty cycle error signal, wherein the voltage difference between the supply voltage and the ground potential corresponds to the amplitude of the duty cycle error signal, and wherein the filtering circuit integrates and filters the duty cycle error signal to simultaneously obtain the common-mode related signal and generate the adjustment signal.

7. The low-distortion triangle wave generating circuit as claimed in claim 6, wherein: The filter circuit includes: an error amplifier circuit; and A low-pass filter feedback network is coupled to the error amplifier circuit in a feedback manner to receive the duty cycle error signal, wherein the error amplifier circuit and the low-pass filter feedback network amplify the difference between the duty cycle error signal and the preset DC level in an active low-pass filtering manner, and simultaneously obtain the common-mode related signal and generate the adjustment signal, wherein the preset DC level corresponds to 1 / 2 of the amplitude of the duty cycle error signal.

8. The low-distortion triangle wave generating circuit as claimed in claim 6, wherein: The regulation control circuit only adjusts one of the charging current or the discharging current.

9. A low-distortion triangle wave generating circuit, comprising: an integration circuit for receiving an external clock signal, wherein the integration circuit integrates an integration capacitor with a charging current and a discharging current during a charging period and a discharging period in a switching cycle of the external clock signal to generate a triangular wave signal, wherein the charging period and the discharging period have the same time length; as well as a regulating control circuit for generating a common-mode related signal according to the triangular wave signal, wherein the common-mode related signal is related to a common-mode characteristic of the triangular wave signal, and the regulating control circuit generates a regulating signal in a manner having a gain according to a difference between the common-mode related signal and a predetermined DC level; wherein the regulating signal is used to adjust at least one of the charging current or the discharging current in a feedback manner, so that the triangular wave signal is a symmetrical triangular wave, and the average voltage of the triangular wave signal is equal to a target DC level; in, The integrator circuit comprises: the integrating capacitor; a variable current circuit for generating one of the charging current or the discharging current according to the adjustment signal; a first fixed current source for generating the other of the charging current or the discharging current; and A selection circuit is used for selecting the charging current or the discharging current to integrate the integration capacitor to generate the triangular wave signal according to the external clock signal.

10. The low-distortion triangle wave generating circuit as claimed in claim 9, wherein: The variable current circuit is configured as one of the following: (1) The variable current circuit comprises: a voltage-controlled current source, for generating one of the charging current or the discharging current according to the adjustment signal and a transconductance coefficient; (2) The variable current circuit includes: a voltage-controlled current source for generating a variable current according to the adjustment signal and a transconductance coefficient; as well as a second fixed current source, wherein a sum or a difference between the variable current and the current of the second fixed current source corresponds to one of the charging current or the discharging current; (3) The variable current circuit includes: a third fixed current source; and a differential transistor pair, receiving and distributing the second fixed current source in common, wherein one of the differential transistor pair is biased at a reference voltage, the other of the differential transistor pair is controlled by the adjustment signal, wherein a current flowing through the differential transistor pair corresponds to one of the charging current or the discharging current; or (4) The variable current circuit includes: an analog-to-digital converter, converting the adjustment signal into a digital switching signal; at least one sub-current source; At least one conversion switch is respectively coupled to the at least one sub-current source, wherein the at least one conversion switch receives the digital switching signal to switch and combine the at least one sub-current source to generate one of the charging current or the discharging current corresponding to the adjustment signal.

11. The low-distortion triangle wave generating circuit as claimed in claim 10, wherein: When the variable current circuit is configured as (1), (2) or (3), The selection circuit includes: a main switch for controlling one of the charging current or the discharging current to integrate the integrating capacitor; and A bypass switch is used to conduct the charging current or the discharging current to a reference potential when the charging current or the discharging current is not integrated to the integration capacitor.

12. A method for generating a low-distortion triangle wave, comprising: In a charging period and a discharging period in a switching cycle of an external clock signal, a charging current and a discharging current are respectively integrated on an integrating capacitor to generate a triangular wave signal, wherein the charging period and the discharging period have the same time length; Generating a common-mode related signal according to the triangle wave signal, wherein the common-mode related signal is related to a common-mode characteristic of the triangle wave signal, and generating an adjustment signal in a manner having a gain according to a difference between the common-mode related signal and a predetermined DC level; and In a feedback manner, adjusting at least one of the charging current or the discharging current according to the adjustment signal, so that the triangular wave signal is a symmetrical triangular wave, and the average voltage of the triangular wave signal is equal to a target DC level; in, The steps of generating the adjustment signal include: Periodically sampling and maintaining the voltage of the triangle wave signal at a sampling and maintaining time point in each switching cycle to generate the common-mode related signal; and The difference between the common-mode related signal and the preset DC level is amplified to generate the adjustment signal, wherein the relationship between the preset DC level and the target DC level is determined by the proportional relationship between the sampling and holding time point and the switching period.

13. The method of claim 12, wherein: The step of generating the common-mode related signal includes: sampling and maintaining the voltage of the triangular wave signal with a phase difference clock signal, wherein the phase difference clock signal is 90 degrees different from the phase of the switching cycle, so as to sample and maintain the middle voltage of a rising slope or the middle voltage of a falling slope of the triangular wave signal, thereby generating the common-mode related signal; wherein the target DC level is used as the preset DC level.

14. The method of claim 12, wherein: One of the following: (1) using the external clock signal to sample and maintain a peak voltage of the triangular wave signal, thereby generating the common-mode related signal; and using a target peak level of the triangular wave signal as the preset DC level; or (2) Using the external clock signal to sample and maintain a valley voltage of the triangular wave signal, thereby generating the common-mode related signal; and using a target valley level of the triangular wave signal as the preset DC level.

15. The method of claim 13, wherein: In the step of generating the common-mode correlation signal, the voltage of the triangle wave signal is sampled and maintained in an interlaced manner to be combined into the common-mode correlation signal.

16. The method of claim 12, wherein: Only one of the charging current or the discharging current is adjusted.

17. A method for generating a low-distortion triangle wave, comprising: In a charging period and a discharging period in a switching cycle of an external clock signal, a charging current and a discharging current are respectively integrated on an integrating capacitor to generate a triangular wave signal, wherein the charging period and the discharging period have the same time length; Generating a common-mode related signal according to the triangle wave signal, wherein the common-mode related signal is related to a common-mode characteristic of the triangle wave signal, and generating an adjustment signal in a manner having a gain according to a difference between the common-mode related signal and a predetermined DC level; and In a feedback manner, adjusting at least one of the charging current or the discharging current according to the adjustment signal, so that the triangular wave signal is a symmetrical triangular wave, and the average voltage of the triangular wave signal is equal to a target DC level; in, The steps of generating the adjustment signal include: Comparing the triangle wave signal with the target DC level to generate a pulse width modulation signal; Comparing the pulse width modulation signal with the external clock signal, or comparing the pulse width modulation signal with a phase difference clock signal to generate a duty cycle error signal, wherein the phase difference clock signal is 90 degrees out of phase with the switching cycle; and filtering the duty cycle error signal to simultaneously obtain the common mode related signal and generate the adjustment signal; The step of generating the duty cycle error signal comprises: Comparing the difference between the pulse width modulation signal and the external clock signal, or comparing the difference between the pulse width modulation signal and a phase difference clock signal, and generating a pull-up signal and a pull-down signal to represent the duty cycle difference of the rising edge and the falling edge respectively; When the pull-up signal is enabled, the duty cycle error signal is switched to a supply voltage, and when the pull-down signal is enabled, the duty cycle error signal is switched to a ground potential; and The duty cycle error signal is filtered or integrated and filtered to simultaneously obtain the common mode related signal and generate the adjustment signal.

18. The method of claim 17, wherein: The steps of filtering the duty cycle error signal include: The difference between the duty cycle error signal and the preset DC level is amplified and low-pass filtered to simultaneously obtain the common-mode related signal and generate the adjustment signal, wherein the preset DC level corresponds to 1 / 2 of the amplitude of the duty cycle error signal.

19. The method of claim 17, wherein: Only one of the charging current or the discharging current is adjusted.

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