Transmission of link data on the I2C bus

Abstract

Embodiments of the present disclosure relate to the transmission of linked data on an I2C bus. In one embodiment, a method for transmitting on an I2C bus includes: transmitting first data on a first channel of a data signal of the I2C bus; and transmitting second data on a second channel of the data signal, wherein the first data and the second data are linked to each other.

Description

[0001] This patent application claims the priority benefit of French patent application FR 19 / 01844, which should be considered as part of the present description. Technical Field

[0002] The present disclosure relates generally to electronic circuits, and more particularly to a system in which multiple circuits can communicate over an I2C bus. Background Art

[0003] In addition to a reference signal (usually ground) that represents one of the two states of a binary signal, the I2C protocol uses a data signal (SDA) and a clock or synchronization signal (SCL).

[0004] The I2C protocol is used to communicate between a master device or circuit (which generates a synchronization signal on a clock line and a data signal on a data line) and a slave device or circuit (which responds to the data signal). The slave device (receiver) generates an acknowledge bit that it transmits on the data line. In practice, the bus conductors are in an idle state at a potential different from the reference potential, the second potential representing the other of the two states of the binary signal. Summary of the invention

[0005] It would be desirable to exploit the presence of an I2C bus to allow authentication of accessories or consumables by the equipment.

[0006] Embodiments overcome all or part of the disadvantages of known authentication processes.

[0007] An embodiment provides a method of transmission over an I2C bus, wherein a first channel of a data signal carries first data, and a second channel of the same data signal carries second data, the two data being linked to each other.

[0008] An embodiment provides a circuit for communicating over an I2C bus, comprising circuitry capable of implementing the described method.

[0009] An embodiment provides a computer program product comprising a non-transitory storage support including instructions suitable for implementing the described method.

[0010] An embodiment provides a memory circuit comprising a lookup table between a first data set and a second data set.

[0011] According to an embodiment, the second data is dependent on the first data.

[0012] According to an embodiment, the second data represents an application of a correction code to the first data.

[0013] According to an embodiment, the second data is a mask.

[0014] According to an embodiment, the second data is identical to the first data.

[0015] According to an embodiment, in transmission mode, a transmission function is applied to transmit data:

[0016] The first data corresponds to the transmission data or to the result of applying a transmission function to the transmission data; and

[0017] The second data corresponds to the transmission data or to a result of applying a transfer function to the transmission data or to a mask applied to the transmission data to obtain the first data.

[0018] According to an embodiment, the transmitter transmits data via a first data transmission, and the second data represents information for verification or correction of the first data by the receiver.

[0019] According to an embodiment, the transmitter masks the transmission data and then via the first data transmission result, the second data represents information demasked by the receiver for the first data.

[0020] According to an embodiment, in the receive mode, a receive function is applied to the first data and the second data and provides receive data, which corresponds to the first data or to a result of the application of the receive function.

[0021] According to an embodiment, information representative of the received data is returned to the transmitting circuit.

[0022] An embodiment provides a system for transmitting on an I2C bus, which includes at least two devices, at least one of which:

[0023] capable of carrying out the methods described; and / or

[0024] comprising communications circuitry such as described; and / or

[0025] including a program product such as described; and / or

[0026] A memory circuit such as described is included.

[0027] An embodiment provides a transmitter for such a system.

[0028] An embodiment provides a receiver for such a system.

[0029] An embodiment provides a transceiver for such a system.

[0030] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1An embodiment of a system for transmitting link data using an I2C bus is shown very schematically in block form;

[0032] Figure 2 is a block diagram of another system for transmitting / receiving link data over an I2C bus;

[0033] Figure 3 shows a timing diagram illustrating the operation of the I2C bus;

[0034] Figure 4 shows a timing diagram illustrating multi-channel transmission over an I2C bus;

[0035] Figure 5 is a block diagram of an embodiment of a data transceiver system using an error correction mechanism (ECC);

[0036] Figure 6 is a flow chart of operations associated with implementation of an error correction mechanism between a transmitter and a receiver;

[0037] Figure 7 illustrating examples of connections between electronic circuitry associated with a printer and electronic circuitry associated with an ink cartridge; and

[0038] Figure 8 Embodiments of electronic circuits capable of implementing the described embodiments are shown very schematically in block form. DETAILED DESCRIPTION

[0039] The same reference numerals are used in different drawings to represent the same elements. Specifically, the structural elements and / or functional elements common to different embodiments may be represented by the same reference numerals and may have the same structural characteristics, dimensional characteristics, and material characteristics.

[0040] For the sake of clarity, only those steps and elements that are helpful for understanding the described embodiments are shown and described in detail. In particular, the generation of signals according to the data to be transmitted over the I2C bus and the reception of these signals by the receiving circuit are not described in detail, the described embodiments are compatible with ordinary transmissions between two or more circuits over the I2C bus.

[0041] Unless otherwise stated, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0042] In the following description, when referring to terms defining absolute positions (such as terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc.) or terms defining relative positions (such as terms “above”, “below”, “upper”, “lower”, etc.) or referring to terms defining directions (such as terms “horizontal”, “vertical”, etc.), unless otherwise specified, they refer to the orientation of the drawing.

[0043] Unless otherwise specified, the expressions "about," "substantially," "substantially," and "approximately" mean within 10%, and preferably within 5%.

[0044] Figure 1 An embodiment of a system using an I2C bus to transmit link data is shown very schematically in block form.

[0045] The I2C bus is formed by two wires or conductors 21 and 22 intended to transmit a data signal SDA and a synchronization signal SCL, respectively.

[0046] A plurality of circuits 11, 12, 13 are coupled (preferably connected) to a transmission conductor 21 (terminals 111, 121) of a data signal SDA, to a transmission conductor 22 (terminals 113, 123) of a synchronization or clock signal SCL, and to a conductor or conductor 23 (terminals 115, 125) at a reference potential (usually ground G). The circuits 11, 12, 13 and other circuits connected to the bus I2C or belonging to the same electronic circuit can be powered at the same voltage or at different voltages. For example, the circuits 11, 12 and 13 are connected to a conductor or conductor 24 (terminals 117, 127) at a higher potential VCC than the potential of the ground GND. The conductors 21 and 22 are individually coupled to the conductor 24 through pull-up resistors Rp so that the signals SDA and SCL are idle in a high state.

[0047] For transmission on the I2C bus, one of the circuits (e.g., circuit 11) is used as a master device (MD) and applies a synchronization signal SCL. The other (one or more) circuits 12 and 13 then have a state of a slave device (SD) to receive data transmitted by circuit 11 and respond to circuit 11. These data can be directed to multiple slave circuits or to a single slave circuit therein. The I2C protocol provides for transmitting the device address before the data byte. Depending on the communication direction, the same circuit can have a master state as well as a slave state.

[0048] According to an embodiment, for the transmission of link data over the I2C bus, the circuits 11 and 12 include transmission blocks 112 and 122 (T) and reception blocks 114 and 124 (R) for sending and receiving data via the conductor SDA, respectively. Each transmission block 112, 122 is derived from a function transmission block 116 or 126 (fT ) receives two pieces of information to be transmitted on the conductor SDA. Each block 116, 126 converts the transmission data TDATA to be transmitted on the I2C bus into two link data. In addition, each receiving block 114, 124 coupled (preferably connected) to the conductor SDA includes a receiving function block 118 or 128 (f R ) two output terminals, making it possible to recover the data RDATA from the two link data received on the I2C bus. The circuit 13 and possible other slave circuits (not shown) also contain blocks and connections similar to those of the previously described circuits 11 and 12. The function blocks 116, 126, 118, 128 are not necessarily the same from one circuit to another.

[0049] According to a particular embodiment, the function blocks 116, 126, 118, 128 may be in the form of hardware and / or software and may be indifferently formed by a circuit, by software or by a memory (a device that directly stores all possible results resulting from the application of the function fT or fR implemented by the corresponding block 116, 126 or 118, 128).

[0050] Figure 2 A block diagram of a system for transmission / reception of link data over an I2C bus.

[0051] Only the elements of the master circuit 11 dedicated to data transmission and the elements of the slave circuit 12 dedicated to data reception are shown, the two circuit parts being connected together by the wires or conductors 21 of the I2C bus. Figure 2 , only the part forming the elements of the circuit driving conductor 21 is shown. The other components of the master and the slave are conventional, in particular the elements generating the synchronization signal SCL applied by circuit 11 to terminal 113 connected to conductor 22.

[0052] The data to be transmitted TDATA is first sent to the input of the function block 116 of the circuit 11 to apply the function f T This results in two related (or linked) data TDATA1 and TDATA2 which are then transmitted back over conductor 21 by transmission block 112 of circuit 11. This is similar to the transmission of two time-distinct channels (a first channel transmitting data TDATA1 and a second channel transmitting data TDATA2) on signal SDA.

[0053] Reception block 124 of circuit 12 then makes available as output two data RDATA1 and RDATA2 originating from two channels for transmission, according to terminal 121 coupled to conductor 21. Finally, function block 128 of circuit 12 processes data RDATA1 and RDATA2 to obtain a single data RDATA as output.

[0054] Figure 3 A timing diagram illustrating the operation of the I2C bus is shown.

[0055] Figure 3 The timing diagram of FIG. 1 illustrates an example of the shape of the signal SCL of the data signal DATA to be transmitted to one or more slave devices by the master device, the shape of the signal S / R inside the master device, and the shape of the signal SDA. The signal S / R indicates the stage in which the master circuit is in the transmission mode (S) and applies the signal SDA, and the stage in which it is in the reception mode (R) and detects the state of the signal SDA. Figure 3 In the example of , a periodic synchronization signal with a duty cycle of 1 / 2 is considered, which is not necessary.

[0056] The I2C protocol defines the communication start bit (START) by switching to the low state of the signal SDA (time t10) while the signal SCL remains in the high state. The switch is caused by the switching of the device in the master state for communication. The master device then switches the signal SCL to a low level (time t11). It then applies the state of the signal SDA according to the state of the first bit B0 of the byte (BYTE) to be transmitted. The state of the signal SDA is verified by the period (time t13 to time t14) in the high state of the signal SCL. When the signal SCL returns to the low state, the master circuit continues the operation of the next bit B1, ..., B7 until all bytes are transmitted.

[0057] At the last bit B7 of the first byte (time t 16 ), the master device releases the signal SDA, which thus returns to the high state, and positions its terminal 111 coupled to the conductor 21 in the read mode of the state of the signal SDA (signal S / R in the low state R).

[0058] The different slave circuits detect the start of communication by monitoring the respective states of the signals SCL and SDA. When the signal SDA is pulled to a low state (time t10) while the signal SCL remains in a high state, the slave device knows that the transmission will begin.

[0059] Typically, the first byte sent by the master device includes seven address bits that identify the recipient circuit, followed by bits that indicate the operation (read / write) desired by the master device.

[0060] The different slave circuits detect the transmitted data and determine, in particular from the first byte forming the recipient address, whether the next byte is intended for this slave circuit.

[0061] At the end of the first byte, the slave circuit identified by the address acknowledges (ACK) the transmitted byte by turning the signal SDA bit to the low state. This transition (time t17) is detected by the master circuit, which can then transmit the next byte and so on until the end of the transmission. For this transmission of the next byte(s), the master circuit switches back the state of its port coupled to the conductor 21 to apply this state (signal S / R in the high state S).

[0062] Once the last data bit has been transmitted and the ACK has been received from the slave, the master acknowledges the transfer by switching the signal SDA to a high state (time t 19 ) to apply a stop condition (STOP).

[0063] Figure 4 A timing diagram illustrating multi-channel transfers over an I2C bus is shown.

[0064] Figure 4 The timing diagram of FIG. 1 illustrates an example of the shape of the signals SCL and SDA applied by the master circuit. Figure 4 In the example of , signal SCL has been arbitrarily shown to have a duty cycle different from 1 / 2.

[0065] Figure 4 Four examples 01, 10, 11, 00 of possible combinations between the signals (state 1 or 0) of the primary channel intended to transmit data TDATA1 on the one hand and the signals (state 1 or 0) of the secondary channel intended to transmit link data TDATA2 on the I2C bus on the other hand are illustrated. The data of the secondary channel is transmitted during the validation period of the primary data signal (high state of the signal SLC - time t 23 To time t 21 ) to write the code in the form of a pulse signal generated externally.

[0066] The I2C protocol provides a time window from the falling edge of the synchronization signal SCL. Typically, the duration t (approximately 200 ns for a 400-kHz protocol) HD Set the falling edge of the signal SCL (time t 21 ) and the minimum interval between the writing of the next data, and the minimum interval between the presentation of data (time t 22 ) and the next rising edge of the signal SCL (time t 23 ) between the maximum duration t CLQV (approximately 700-900 ns in the above example). A minimum duration of the low phase of the signal SCL is also set: it is approximately 1.3 μs for a 400-kHz protocol (and approximately 4.7 μs for a 100-kHz protocol). The interval between the occurrence of the write code and the rising edge of the signal SCL (time t 22To time t 23 ) leaves a free interval in the I2C protocol. The secondary channel (TDATA2) is in the low state of the synchronization signal SCL (with a corresponding duration t HD ) is written during a period of . In the example shown, if there is a pulse (continuous low state then high state), then this corresponds to transmitting state 1 on the secondary channel. However, if there is no pulse, then this corresponds to transmitting state 0 on the secondary channel.

[0067] Therefore, the existence of unexploited cycles in the I2C bus is exploited. Typically, in the I2C protocol with a 400-kHz frequency, a cycle of 700–900 ns makes the time t 22 With time t 23 Separation (duration of the state of the signal SDA in which the receiver of the I2C protocol does not take into account). The pulse transmission for the secondary channel for transmitting the link data TDATA2 utilizes this period. The duration of the pulse is in the range of 300ns to 500ns for the 400kHz protocol (and 1.0μs to 2.2μs for the 100-kHz protocol).

[0068] The slave circuit is able to detect such pulse signals.

[0069] Figure 5 is a block diagram of an embodiment of a data transceiver system using an error correction mechanism (ECC).

[0070] According to this embodiment, block 116 (ECC) applies an error correction code (function fT is the error correction code) to the data to be transmitted TDATA. The result of applying the code to the data TDATA forms data TDATA2.

[0071] According to an embodiment, the data TDATA directly forms the data TDATA1 .

[0072] According to another preferred embodiment, circuit 11 comprises block 119 (ERR) applying an error function to data TDATA to provide intentionally erroneous data TDATA1. The number of bits of data TDATA1 altered by error function ERR is selected to be within the range of bits correctable by an error correction code.

[0073] Block 112 of circuit 11 transmits two data to block 124 of circuit 12 : TDATA2 on the one hand and TDATA1 on the other hand, which represents the data to be transmitted TDATA in the absence of optional block 119 or erroneous data in the presence of optional block 119 .

[0074] The two data RDATA1 and RDATA2 obtained at the output of the block 124 of the circuit 12 are processed by the block 128 (ECC'). The processing result provides the data RDATA. In the example shown, it is assumed that the block 128 applies the error correction code ECC' corresponding to the code ECC to the received data RDATA1 by using the data RDATA2. In other words, the function f R is an error correction code.

[0075] According to an embodiment (in case the circuit 11 does not comprise the block 119 ), the block 128 corrects possible errors of the reception data RDATA1 with respect to the transmission data TDATA1 and thus ensures that the data RDATA corresponds to the data TDATA.

[0076] According to another embodiment in which an error is introduced into the data TDATA1 by the block 119, the erroneous data changed by the block 119 is corrected by applying the error correction code ECC' by the block 128 to restore the data RDATA corresponding to the data TDATA. Thus, the block 128 corrects the data RDATA1 by means of the data RDATA2. According to this embodiment, the correction of the error intentionally introduced by the transmission circuit 11 by the receiving circuit 12 means that the receiving circuit effectively has the functions of data reception and processing on two channels and the error correction function.

[0077] The data RDATA obtained by block 128 can then be provided for the receiving circuit 12. If the data thus received by the circuit 11 in exchange are identical to the data TDATA transmitted by the circuit 11, this means that the circuit 12 effectively implements the functions of data reception and processing on both channels and the error correction function. The circuit 12 thus reproduces the functionality of the described embodiment.

[0078] However, if the receiving circuit does not have the functions of data reception and processing on two channels and the error correction function, the verification by the transmission circuit 11 of the data RDATA received by the receiving circuit shows received data RDATA different from the transmitted data TDATA. The circuit 12 therefore does not reproduce the functionality of the described embodiment.

[0079] According to another embodiment, the data TDATA2 represents the result of applying a cryptographic function (eg a signature) to the data TDATA (function f T is the signature calculation function). The data RDATA1 is therefore equal to the data TDATA and is transmitted with the signature carried by the data TDATA2. On the receiving side, the circuit 11 decodes the received signal and, if it comprises the functionality of this embodiment, is able to process the data of the two channels RDATA1 and RDATA2 and to verify its calculation (which therefore has the function f applied with the circuit 11). TThe function f of the same signature calculation algorithm R ) corresponds to the signature received on the data RDATA2. Assuming a response mechanism according to which the transmitter circuit 11 waits for an acknowledgement representing the signature obtained by the receiver, the fact that the circuit 12 returns an acknowledgement therefore means that the circuit 12 reproduces the functionality of the described embodiment.

[0080] According to yet another embodiment, data TDATA1 and TDATA2 are identical and correspond to data TDATA. Function f T Therefore, it is a function of the replica of the data TDATA. On the receiving side, the function f R is a function of a bit-by-bit combination of the XOR type, the expected result of which is an empty word (all bits in state 0). The detection of the fact that the slave circuit has the functionality of this embodiment can be performed by a swapping procedure according to which the master circuit waits for the function f as a swap R If it receives an empty word, this means that the circuit 12 reproduces the functionality of the described embodiment.

[0081] According to yet another embodiment, data RDATA2 forms a mask that is supposed to be applied to a receiving circuit of data RDATA1 that receives data RDATA1 to return an expected result.

[0082] The data TDATA2, whose generation by block 116 is intended to enable verification or correction of data RDATA1 received by circuit 12, may possibly comprise a smaller number of bits than the data TDATA. In the case of an error correction code, the length of the code determines the number of bits that can be corrected.

[0083] Figure 6 is a flow chart of operations associated with implementation of error correction principles between a transmitter and a receiver.

[0084] The operations described above are generally intended to verify that the receiver is able to use multi-channel transmission and to correct possible errors affecting the data sent by the transmitter.

[0085] In a first step (step 1), the transmitter (sender) sends (sends) a control signal (set configuration) for configuring the communication to the receiver (receiver). The consideration (execution) of the control signal by the receiver causes it to be informed that the transmission on the I2C bus will be performed on both channels and that the error correction function should be active (configuration on).

[0086] In a second step (step 2), the transmitter asks (requests) the receiver for a status request (status request). Consideration (execution) of the request by the receiver enables it to send (RESP) the status (status) to the transmitter. Verification (checking) of the status by the transmitter enables verification that the transmission is properly established (status OK).

[0087] In a third step (step 3), the transmitter asks (requests) the receiver for a handshake request (handshake request). The handshake request is preferably generated by introducing intentional errors in the data to be transmitted, such as Figure 5 In the case where the receiver is provided with the blocks required for multi-channel communication and error correction, the request is considered (executed) by the receiver so that it can send back (RESP) the response expected by the transmitter (handshake response). The response is verified (checked) by the transmitter so that it can verify whether the receiver is able to implement the error correction function (handshake OK).

[0088] Figure 7 An example of the connection between the electronic circuitry of a printer and the electronic circuitry associated with an ink cartridge is described.

[0089] exist Figure 7 In the example of , the printer 31 comprises a main circuit 312, which is particularly dedicated to driving electromechanical components. The printer 31 is equipped with one or more ink cartridges, for example three ink cartridges 33, 35 and 37. Each ink cartridge 33, 35, 37 supports a circuit, respectively 332, 352 and 372. The four circuits 312, 332, 352 and 372 are coupled together by a conductor represented by a cable 320, compatible with transmissions complying with the I2C protocol. Preferably, the circuit 312 of the printer 31 acts as a master circuit, while the circuits 332, 352 and 372 act as slave circuits. In this case, the dual-channel transmission can be set only in the master-slave direction, implementing ordinary I2C transmission and special functions f T and f R The response of the ink cartridge is therefore only provided on the printer side and on the ink cartridge side, respectively.

[0090] Figure 8 An embodiment of an electronic circuit 8 capable of implementing the described embodiments is shown very schematically in block form.

[0091] The electronic circuit 8 comprises:

[0092] One or more digital processing units (PU) 81, such as state machines, microprocessors, programmable logic circuit types, etc.; and / or

[0093] one or more memories of volatile storage devices (RAM) 82, 83 and / or non-volatile storage devices (NVM) for data and programs;

[0094] one or more data, address and / or control buses 84 between different elements within circuit 8; and

[0095] Communications external to the circuit over an I2C bus and other one or more input / output interfaces (I / O) 85; and

[0096] Depending on the application of various other circuits, Figure 8 denoted by block 86 (FCT).

[0097] Assume that the function f R By implementing the circuit 8 of the cartridge, the actual function f can be provided. R not included in the circuit but in its memory (preferably non-volatile memory) to contain a lookup table between the set of data RDATA1 and the set of data RDATA2, reproducing the function f of all or part of the possible values T This therefore enables the cartridge to carry out the described method.

[0098] In case of a partial or total software implementation, the storage support of the relevant device or equipment may store instructions of the computer program product which, when executed by a processor of the equipped device or equipment, causes the processor to implement all or part of the described method.

[0099] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and other variations will occur to those skilled in the art. Specifically, what is discussed in more detail with respect to examples applied to printer-cartridge authentication applies more generally to any accessory or consumable authentication performed by an equipment part.

[0100] Ultimately, based on the functional indications given above, actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art. Specifically, in the error correction embodiments, the selection of the length and nature of the error correction code may vary depending on the application. Furthermore, although the described embodiments more specifically refer to a system that sets up master (printer) functions and slave (ink cartridge) functions, all circuits therein may function as either a master or a slave ( Figure 1 ) to a system is within the capabilities of a person skilled in the art based on the above description.

Claims

1. A method for transmitting on an I2C bus, the method comprising: Transmitting first data on a first channel of a data signal of the I2C bus; as well as transmitting second data over a second channel of the data signal, wherein the first data and the second data are linked to each other; The second data is coded in the form of a pulse signal generated outside a verification period of the first data. The method according to claim 1 , wherein the second data is dependent on the first data. The method according to claim 1 , wherein the second data represents application of a correction code to the first data.

4. The method according to claim 3, further comprising: An error is intentionally generated on the first data. The method according to claim 1 , wherein the second data is a mask. The method according to claim 1 , wherein the second data is the same as the first data.

7. The method according to claim 1, further comprising: A transfer function is applied to the transfer data to generate result data, wherein the first data corresponds to the transfer data or the result data, and wherein the second data corresponds to the transfer data, or the result data, or a mask applied to the transfer data to obtain the first data.

8. The method according to claim 7, wherein a transmitter transmits the transmission data via the first data, and wherein the second data represents information of verification or correction performed on the first data by a receiver.

9. The method according to claim 7, wherein a transmitter masks the transmission data and then transmits the masked result via the first data, and wherein the second data represents information of demasking of the first data by a receiver.

10. The method according to claim 1, further comprising: receiving the first data by a receiver; receiving the second data by the receiver; as well as A receive function is applied to the received first data and the second data to generate receive data corresponding to the first data or to a result of applying the receive function.

11. The method according to claim 10, further comprising: Information representing the received data is returned to the transmission circuit.

12. The method according to claim 11, further comprising: The receiver is authenticated based on the information returned.

13. The method of claim 1, wherein the memory circuit comprises a lookup table between the set of first data and the set of second data.

14. A circuit for communicating over an I2C bus, comprising circuitry capable of implementing the method according to claim 1.

15. A computer program product comprising a non-transitory storage support including instructions capable of implementing the method according to claim 1.

16. A system on an I2C bus, comprising: I2C bus; transmitter, coupled to the I2C bus, and configured to: transmitting first data on a first channel of a data signal of the I2C bus, and transmitting second data over a second channel of the data signal, wherein the first data and the second data are linked to each other; wherein the second data is coded in the form of a pulse signal generated outside a verification period of the first data; as well as The receiver is coupled to the I2C bus and is configured to: receiving the first data, receiving the second data, and A receiving function is applied to the received first data and the second data to generate received data.

17. The system of claim 16, further comprising a memory circuit comprising a lookup table between the set of first data and the set of second data.

18. A transmitter, comprising: a function transmission circuit configured to receive transmission data, and generate first data and second data based on the received transmission data; as well as The transmission circuit is configured as: transmitting the first data on a first channel of a data signal of an I2C bus, and transmitting the second data over a second channel of the data signal, wherein the first data and the second data are linked to each other; The second data is coded in the form of a pulse signal generated outside a verification period of the first data.

19. The transmitter according to claim 18, further comprising: a receiving circuit configured to receive third data and fourth data from the corresponding first channel and second channel of the I2C bus; as well as The function receiving circuit is configured to apply a receiving function to the received third data and fourth data to generate receiving data corresponding to the third data or corresponding to a result of applying the receiving function.

20. A receiver, comprising: The receiving circuit is configured as follows: receiving first data on a first channel of a data signal of the I2C bus, and receiving second data on a second channel of the data signal; as well as a function receiving circuit configured to apply a receiving function to the received first data and the second data to generate receiving data corresponding to the first data or corresponding to a result of applying the receiving function; The second data is coded in the form of a pulse signal generated outside a verification period of the first data.

21. The receiver of claim 20, wherein the receiver is further configured to return information representing the received data to a transmission circuit.

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