Clock data recovery

Abstract

The present invention relates to a clock data recovery. The clock data recovery of the present invention can include a phase corrector generating a first compensated clock signal and a second compensated clock signal based on an external clock signal; and a transition detector, wherein the transition detector includes a first integrator providing a first integrated signal by integrating a first training pattern signal according to the first compensated clock signal, and a second integrator providing a second integrated signal by integrating the first training pattern signal according to the second compensated clock signal, wherein the transition detector detects an occurrence of a transition of the first training pattern signal when the first integrated signal is greater than a first reference voltage and the second integrated signal is less than the first reference voltage.

Description

Technical Field

[0001] The present invention relates to a conversion detector and a clock data recovery device including the conversion detector. Background Technology

[0002] In a transceiver system where the transmitter and receiver are connected via a single channel, the main noise causing signal quality degradation is inter-symbol interference (ISI).

[0003] In a high-speed parallel link system where the transmitter and receiver are connected through multiple channels, in addition to inter-symbol interference, crosstalk-induced jitter (CIJ) also occurs.

[0004] Because multiple clock data recovery units, each corresponding to multiple channels, are used on the receiver side, the required chip area for the clock data recovery units is larger, and there are issues with increased power consumption and manufacturing costs.

[0005] Clock data recovery devices require transition detectors to recover clock signals, and existing transition detectors utilize digital data for transition detection. Therefore, because existing transition detectors can only detect specific unit intervals (UI) rather than the specific time points where transitions occur, they are limited in recovering clock signals robust to jitter caused by inter-symbol interference and crosstalk. Summary of the Invention

[0006] The technical problem to be solved is to provide a conversion detector that is robust to the jitter caused by inter-symbol interference and crosstalk, and a clock data recovery device including the conversion detector.

[0007] A clock data recovery device according to an embodiment of the present invention includes: a phase corrector that generates a first compensated clock signal and a second compensated clock signal based on an external clock signal; and a conversion detector, wherein the conversion detector includes: a first integrator that integrates a first training pattern signal according to the first compensated clock signal to provide a first integrated signal; and a second integrator that integrates the first training pattern signal according to the second compensated clock signal to provide a second integrated signal, wherein the conversion detector detects the occurrence of a conversion of the first training pattern signal when the first integrated signal is greater than a first reference voltage and the second integrated signal is less than the first reference voltage.

[0008] The phase of the second compensation clock signal may be delayed compared to the phase of the first compensation clock signal.

[0009] The conversion detector may further include: a first comparator that outputs a logic value of 1 when the first integrated signal is greater than the first reference voltage, and outputs a logic value of 0 when the first integrated signal is less than the first reference voltage; and a second comparator that outputs a logic value of 1 when the second integrated signal is greater than the first reference voltage, and outputs a logic value of 0 when the second integrated signal is less than the first reference voltage.

[0010] The conversion detector may further include: a first inverter that receives the output value of the second comparator.

[0011] The conversion detector may further include: a first NAND gate, which outputs a first detection signal based on the output values ​​of the first comparator and the first inverter.

[0012] The conversion detector may further include: a first mode signal holding unit, which provides a first mode signal of the training mode corresponding to an initialization signal of the conduction level, wherein the first mode signal holding unit provides the first mode signal of the normal mode corresponding to the first detection signal of the first conduction level after receiving the initialization signal of the conduction level, and thereafter holds the first mode signal of the normal mode independently of the level variation of the first detection signal.

[0013] The first mode signal holding section may include: a first transistor, whose gate electrode receives the first detection signal, one electrode connected to a first power supply, and the other electrode connected to a first sensing node; a second transistor, whose one electrode is connected to the first power supply, and the other electrode connected to the first sensing node; a third transistor, whose gate electrode receives the initialization signal, one electrode connected to the first sensing node, and the other electrode connected to a second power supply; and a second inverter, whose input terminal is connected to the first sensing node, and whose output terminal is connected to the gate electrode of the second transistor.

[0014] The first mode signal holding unit may further include: a third inverter, the input of which is connected to the first sensing node; and a fourth inverter, the input of which is connected to the output of the third inverter, and which outputs the first mode signal.

[0015] The conversion detector may further include: a third integrator that integrates the second training pattern signal according to a third compensation clock signal to provide a third integrated signal; and a fourth integrator that integrates the second training pattern signal according to a fourth compensation clock signal to provide a fourth integrated signal, wherein the occurrence of a conversion of the second training pattern signal is detected when the third integrated signal is less than the second reference voltage and the fourth integrated signal is greater than the second reference voltage.

[0016] The conversion detector may further include: a third comparator that outputs a logic value of 1 when the third integrated signal is greater than the second reference voltage, and outputs a logic value of 0 when the third integrated signal is less than the second reference voltage; and a fourth comparator that outputs a logic value of 1 when the fourth integrated signal is greater than the second reference voltage, and outputs a logic value of 0 when the fourth integrated signal is less than the second reference voltage.

[0017] The conversion detector may further include: a fifth inverter that receives the output value of the third comparator; and a second NAND gate that outputs a second detection signal based on the output values ​​of the fifth inverter and the fourth comparator.

[0018] The conversion detector may further include: a second mode signal holding unit, which provides a second mode signal for the training mode corresponding to the initialization signal at the conduction level, wherein the second mode signal holding unit provides a second mode signal for the normal mode corresponding to the second detection signal at the first conduction level after receiving the initialization signal at the conduction level, and thereafter holds the second mode signal for the normal mode independently of level variations of the second detection signal.

[0019] The second mode signal holding section may include: a fourth transistor, whose gate electrode receives the second detection signal, one electrode connected to the first power supply, and the other electrode connected to the second sensing node; a fifth transistor, whose one electrode is connected to the first power supply, and the other electrode connected to the second sensing node; a sixth transistor, whose gate electrode receives the initialization signal, one electrode connected to the second sensing node, and the other electrode connected to the second power supply; and a sixth inverter, whose input terminal is connected to the second sensing node, and whose output terminal is connected to the gate electrode of the fifth transistor.

[0020] The second mode signal holding unit may further include: a seventh inverter, the input of which is connected to the second sensing node; and an eighth inverter, the input of which is connected to the output of the seventh inverter, and which outputs the second mode signal.

[0021] The first training pattern signal may include a falling pulse during a 1-unit interval in 1 period, and the second training pattern signal may include a rising pulse during a 1-unit interval in 1 period.

[0022] The first training pattern signal can remain high for the remaining unit intervals in a 1-cycle period, excluding the 1-unit interval, while the second training pattern signal can remain low for the remaining unit intervals in a 1-cycle period, excluding the 1-unit interval.

[0023] A clock data recovery device according to an embodiment of the present invention includes: a phase corrector that generates a first compensated clock signal and a second compensated clock signal based on an external clock signal; and a conversion detector, wherein the conversion detector includes: a first integrator that integrates a first training pattern signal according to the first compensated clock signal to provide a first integrated signal; and a second integrator that integrates the first training pattern signal according to the second compensated clock signal to provide a second integrated signal, wherein the conversion detector detects the occurrence of a conversion of the first training pattern signal when the first integrated signal is less than a first reference voltage and the second integrated signal is greater than the first reference voltage.

[0024] A clock data recovery device according to an embodiment of the present invention includes: a phase corrector that generates a first compensated clock signal and a second compensated clock signal based on an external clock signal; and a conversion detector, wherein the conversion detector includes: a first integrator that integrates a first training pattern signal according to the first compensated clock signal to provide a first integrated signal; and a second integrator that integrates the first training pattern signal according to a second compensated clock signal whose phase is delayed compared to the first compensated clock signal to provide a second integrated signal, wherein when the first integrated signal is greater than a first reference voltage and the second integrated signal is less than the first reference voltage, the phase of the second compensated clock signal is stored as a first phase.

[0025] The conversion detector may further include: a third integrator that integrates the second training pattern signal according to a third compensation clock signal to provide a third integrated signal; and a fourth integrator that integrates the second training pattern signal according to the fourth compensation clock signal to provide a fourth integrated signal, wherein when the third integrated signal is less than the second reference voltage and the fourth integrated signal is greater than the second reference voltage, the phase of the fourth compensation clock signal is stored as a second phase.

[0026] The clock data restorer can provide the second compensated clock signal as the sampling clock signal when the first phase is delayed compared to the second phase, and provide the fourth compensated clock signal as the sampling clock signal when the second phase is delayed compared to the first phase.

[0027] The first training pattern signal may include a falling pulse during a 1-unit interval in 1 cycle and remain high during the remaining 1-unit interval in 1 cycle, while the second training pattern signal may include a rising pulse during a 1-unit interval in 1 cycle and remain low during the remaining 1-unit interval in 1 cycle.

[0028] The conversion detector and clock data recovery unit including the conversion detector according to the present invention can recover clock signals that are robust to jitter caused by inter-symbol interference and crosstalk. Attached Figure Description

[0029] Figure 1 This is a diagram illustrating a receiver and a transceiver including the receiver according to an embodiment of the present invention.

[0030] Figure 2 This is a diagram used to illustrate the received signal in response to a transmitted signal.

[0031] Figure 3 This is a diagram used to illustrate the received signal in response to another transmitted signal.

[0032] Figure 4 This is a diagram illustrating a receiving unit according to an embodiment of the present invention.

[0033] Figure 5 It is a diagram used to illustrate the pattern of the relationship between the received signals of adjacent channels and the received signals of the target channel.

[0034] Figure 6 This is a diagram used to illustrate jitter caused by crosstalk from adjacent received signals.

[0035] Figure 7 This is a diagram illustrating another example of jitter caused by crosstalk from adjacent received signals.

[0036] Figure 8 It is a diagram used to illustrate the jitter caused by crosstalk based on the relationship between the adjacent received signals of two adjacent channels and the received signal of the target channel.

[0037] Figure 9 This diagram illustrates the rationale for receiving a first training pattern signal with the same first conversion direction through a channel in training mode.

[0038] Figure 10 This diagram illustrates the rationale for receiving a second training pattern signal with the same second conversion direction through a channel in training mode.

[0039] Figure 11 and Figure 12 This diagram illustrates the rationale for recovering a clock signal using the first training pattern signal of the sensing channel from the first training pattern signal of the channel.

[0040] Figure 13 and Figure 14 This diagram illustrates the rationale for recovering the clock signal using the second training pattern signal of the sensing channel in the second training pattern signal of the channel.

[0041] Figure 15 This is a diagram illustrating a clock data recovery device according to an embodiment of the present invention.

[0042] Figure 16 This is a diagram illustrating a conversion detector according to an embodiment of the present invention.

[0043] Figure 17 It is used to illustrate what can be used Figure 16 A graph of an exemplary first training style signal for the transformation detector.

[0044] Figures 18 to 20 It is used to illustrate the signal based on the first training pattern. Figure 16 A diagram illustrating the operation of the conversion detector.

[0045] Figure 21 This is a diagram illustrating a conversion detector according to another embodiment of the present invention.

[0046] Figure 22 It is used to illustrate what can be used Figure 21 A diagram of an exemplary second training style signal for the transformation detector. Detailed Implementation

[0047] Hereinafter, several embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art to which this invention pertains can easily implement it. The present invention can be implemented in many different forms and is not limited to the embodiments described herein.

[0048] To clearly illustrate the invention, irrelevant details have been omitted, and the same reference numerals have been used throughout the specification to refer to the same or similar constituent elements. Therefore, the reference numerals described above can also be used in different figures.

[0049] Furthermore, for ease of explanation, the size and thickness of the various components shown in the accompanying drawings are arbitrarily illustrated; therefore, the present invention is not limited to the content shown in the drawings. The thickness is enlarged in the drawings to clearly illustrate the multiple layers and regions.

[0050] Figure 1 This is a diagram illustrating a receiver and a transceiver including the receiver according to an embodiment of the present invention.

[0051] Reference Figure 1 According to an embodiment of the present invention, a transceiver TCS includes a transmitter DV1 and a receiver DV2.

[0052] Transmitter DV1 includes transmission units TX1 to TX(2n-1) connected to the corresponding channels CH1 to CH(2n-1).

[0053] Receiver DV2 includes receiving units RX1 to RX(2n-1) connected to the corresponding channels CH1 to CH(2n-1).

[0054] Furthermore, the receiver DV2 includes a clock data recovery unit (CDR). The clock data recovery unit (CDR) can be connected to the sensing channel CHn among channels CH1 to CH(2n-1) via the sensing line SL, and to the receiving units RX1 to RX(2n-1) via the clock line CL. According to an embodiment, the clock data recovery unit (CDR) can be connected to the transmitting units TX1 to TX(2n-1) via the mode line ML.

[0055] The transceiver (TCS) can operate in either training mode or normal mode. Training mode is used by the clock data recovery unit (CDR) to generate a sampling clock signal, while normal mode is used to sample the data signal using the generated sampling clock signal. During training mode, training pattern signals can be transmitted through channels CH1 to CH(2n-1), while during normal mode, data signals can be transmitted through channels CH1 to CH(2n-1).

[0056] First, let's explain the training mode.

[0057] In one embodiment, the receiving units RX1 to RX(2n-1) can receive training pattern signals with the same transition direction through channels CH1 to CH(2n-1) in training mode.

[0058] At this time, the Clock Data Recovery Unit (CDR) can generate a phase-adjusted sampling clock signal in training mode, so that the transition time point of the training pattern signal of the sensing channel CHn corresponds to the sampling time point. According to an embodiment, when generating the sampling clock signal, the Clock Data Recovery Unit (CDR) can provide a mode signal corresponding to the normal mode via the mode line ML.

[0059] In another embodiment, the receiving units RX1 to RX(2n-1) can receive, in training mode, a first training pattern signal having the same first conversion direction and a second training pattern signal having the same second conversion direction through channels CH1 to CH(2n-1). In this case, the first conversion direction and the second conversion direction can be different from each other.

[0060] At this time, the Clock Data Recovery Unit (CDR) can generate a sampling clock signal in training mode, such that the generated sampling clock signal corresponds to a more delayed phase in the first sampling time point corresponding to the first conversion time point of the first training pattern signal of the sensing channel CHn and the second sampling time point corresponding to the second conversion time point of the second training pattern signal.

[0061] The normal mode will be explained below.

[0062] The transmitting units TX1 to TX(2n-1) can provide various data signals through the corresponding channels CH1 to CH(2n-1) when they receive the mode signal corresponding to the normal mode.

[0063] The clock data recovery unit (CDR) can supply the sampled clock signal to the receiving units RX1 to RX(2n-1) via the clock line CL in normal mode.

[0064] The receiving units RX1 to RX(2n-1) can sample the data signals received through the corresponding channels CH1 to CH(2n-1) using the sampling clock signal in normal mode.

[0065] According to this embodiment, no clock data recovery unit is required for each of the multiple channels CH1 to CH(2n-1), only one clock data recovery unit (CDR) is needed for the sensing channel CHn, thus reducing the chip area and power consumption.

[0066] The following text will refer to Figures 11 to 14 The following points should be noted: Even if sampling clock signals for multiple channels CH1 to CH(2n-1) are generated based on a single sensing channel CHn, there will be no problem in data sampling.

[0067] At this point, it is important to determine the sensing channel CHn among the multiple channels CH1 to CH(2n-1). According to one embodiment, the sensing channel CHn can be the channel among channels CH1 to CH(2n-1) that receives the slowest phase signal for the same transmitted signal. According to another embodiment, the sensing channel CHn can be the middle channel among channels CH1 to CH(2n-1).

[0068] Here, n can be a positive integer greater than 2. However, in Figure 1 In the diagram, the last channel CH(2n-1) is illustrated as the (2n-1)th channel, i.e., an odd-numbered channel. However, this embodiment can also be applied to the case where the last channel is an even-numbered channel. For example, the last channel could also be the 2nth channel. For instance, if the sensing channel CHn is the fourth channel, the last channel could be the eighth channel. Furthermore, if the last channel is the eighth channel, the sensing channel CHn could also be the fifth channel.

[0069] That is, for determining the sensing channel CHn in this embodiment, what is important is not which channel CHn is, but rather determining the channel among channels CH1 to CH(2n-1) that receives the slowest phase signal for the same transmitted signal as the sensing channel CHn.

[0070] When the physical structure of channels CH1 to CH(2n-1) is simply arranged parallel to each other on a plane, the sensing channel CHn can be the middle channel among channels CH1 to CH(2n-1). However, when channels CH1 to CH(2n-1) are provided in a three-dimensional structure (e.g., when multiple channels are bundled together inside the wiring sheath), the manufacturer can identify the channel receiving the slowest phase signal by pre-transmitting sample training signals and designate that channel as the sensing channel CHn. That is, the sensing channel CHn can be determined differently for each product.

[0071] Furthermore, the following text will refer to Figures 6 to 14 This demonstrates that the jitter problem caused by crosstalk can be effectively solved according to this embodiment, and will be further explained below. Figure 17 and Figure 22 This demonstrates that it can effectively solve the problem of inter-symbol interference.

[0072] Figure 2 This is a diagram used to illustrate the received signal in response to a transmitted signal. Figure 3 This is a diagram used to illustrate the received signal in response to another transmitted signal.

[0073] exist Figure 2 and Figure 3In this case, it is assumed that there is no jitter caused by crosstalk. Figure 2 and Figure 3 In this context, the interval between adjacent sampling time points is one unit interval (UI).

[0074] exist Figure 2 and Figure 3 In this context, the variable level of the received signal can be either above the lowest level LL1 or below the highest level HL1. An intermediate level IL1 exists between the lowest level LL1 and the highest level HL1. In this case, it is assumed that the channel through which the received signal passes is ideal. Regarding the difference between an ideal channel and a real channel, refer to... Figure 17 and Figure 22 Related explanations.

[0075] Reference Figure 2 The illustration exemplarily depicts the received signal fr_a via receiver DV2 when a binary level signal of 0, 1, or 0 is transmitted from transmitter DV1 through any channel. Assume... Figure 2 The remaining data of the transmitted signal (not shown in the diagram) is binary level 0.

[0076] It is possible to obtain such results when the channel is designed as a low-pass filter. Figure 2 The shape of the received signal fr_a is shown. Therefore, according to one embodiment, each of the multiple channels CH1 to CH(2n-1) connecting the transmitter DV1 and the receiver DV2 can be designed as a low-pass filter.

[0077] Follow as Figure 2 The received signal in the response pattern shown can be referred to as a duo-binary signal. Besides the case where the channel is designed as a low-pass filter, a similar response can also occur when the transmitter DV1 has an encoder for duo-binary signaling. Figure 2 The response pattern is shown.

[0078] Although various binary signaling methods exist, in Figure 2 In the case of the received signal fr_a, typically, the sampling time point sp1_a is marked as the pre-cursor, the sampling time point sp2_a is marked as the main-cursor, the sampling time point sp3_a is marked as the first post-cursor, and the sampling time point sp4_a is marked as the second post-cursor. To properly apply dual binary signaling, various known methods can be used to ensure that the levels (magnitudes) of the main and first post-cursors are identical.

[0079] Reference Figure 3 The illustration exemplarily depicts the received signal spr_b of receiver DV2 when a transmit signal with binary levels of 0, 1, 1, 0 is transmitted from transmitter DV1 through any channel. Assume... Figure 3 The remaining data of the transmitted signal (not shown in the diagram) is binary level 0.

[0080] exist Figure 3 In this context, the received signal spr_b can be considered as an overlapping signal of the response signal fr_b corresponding to the first binary level 1 and the response signal sr_b corresponding to the second binary level 1. In the case of the response signal fr_b, typically, the sampling time point sp1_b is marked as the pre-mark, the sampling time point sp2_b as the main mark, the sampling time point sp3_b as the first post-mark, and the sampling time point sp4_b as the second post-mark. Similarly, in the case of the response signal sr_b, typically, the sampling time point sp2_b is marked as the pre-mark, the sampling time point sp3_b as the main mark, the sampling time point sp4b as the first post-mark, and the sampling time point sp5_b as the second post-mark.

[0081] The following is for reference Figure 2 and Figure 3 The decoding method for dual binary signals is explained.

[0082] When performing decoding for a dual binary signal, a determined value of the previous 1UI data may be required. If the determined value of the previous 1UI data is 1, a first reference voltage VH1 can be used to determine the current data. And, if the determined value of the previous 1UI data is 0, a second reference voltage VL1 can be used to determine the current data. The first reference voltage VH1 may have an intermediate value between the highest level HL1 and the intermediate level IL1 of the variable levels of the received signal. The second reference voltage VL1 may have an intermediate value between the lowest level LL1 and the intermediate level IL1 of the variable levels of the received signal.

[0083] For example, refer to Figure 2 At sampling time point sp2_a, the previously determined value of 1UI data is 0, so the binary level of the current data can be determined based on the second reference voltage VL1. Since the level of the received signal sampled at sampling time point sp2_a is the intermediate level IL1 and it is higher than the second reference voltage VL1, the binary level can be determined to be 1.

[0084] Next, refer to Figure 2At sampling time point sp3_a, the previously determined value of 1UI data is 1, so the binary level of the current data can be determined based on the first reference voltage VH1. Since the level of the received signal sampled at sampling time point sp3_a is the intermediate level IL1 and it is lower than the first reference voltage VH1, the binary level can be determined to be 0.

[0085] For example, refer to Figure 3 At sampling time point sp2_b, the previously determined value of 1UI data is 0, so the binary level of the current data can be determined based on the second reference voltage VL1. Since the level of the received signal sampled at sampling time point sp2_b is the intermediate level IL1 and it is higher than the second reference voltage VL1, the binary level can be determined to be 1.

[0086] Next, refer to Figure 3 At sampling time point sp3_b, the previously determined value of 1UI data is 1, so the binary level of the current data can be determined based on the first reference voltage VH1. Since the level of the received signal sampled at sampling time point sp3_b is the highest level HL1 and it is higher than the first reference voltage VH1, the binary level can be determined to be 1.

[0087] Next, refer to Figure 3 At sampling time point sp4_b, the previously determined value of 1UI data is 1, so the binary level of the current data can be determined based on the first reference voltage VH1. Since the level of the received signal sampled at sampling time point sp4_b is the intermediate level IL1 and it is lower than the first reference voltage VH1, the binary level can be determined to be 0.

[0088] The above determination method is specified based on Figure 4 The receiving unit RXI.

[0089] Figure 4 This is a diagram illustrating a receiving unit according to an embodiment of the present invention.

[0090] Although Figure 4 The receiving unit RXI is illustrated with the i-th channel Chi as a reference, but the same concept can be applied to other channels and receiving units. i can be a positive integer. If the i-th channel CHi is a sensing channel CHn, the receiving unit RXI can also be connected to the sensing line SL.

[0091] refer to Figure 4 The receiving unit RXI may include a first comparator CMP1, a second comparator CMP2, and a multiplexer MUX.

[0092] The first comparator CMP1 provides a logic value by comparing the received signal with a first reference voltage VH1 based on a sampling clock signal supplied via clock line CL. The received signal can be received via channel CHi. The first comparator CMP1 operates based on the rising or falling transition of the sampling clock signal, sampling the magnitude of the received signal at that sampling time point and comparing it with the first reference voltage VH1. In another embodiment, the first comparator CMP1 can compare the magnitude of the received signal integrated over a high-level period or a low-level period of the sampling clock signal with the first reference voltage VH1. If the received signal is greater than the first reference voltage VH1, the first comparator CMP1 can provide a high logic value, and if the received signal is less than the first reference voltage VH1, the first comparator CMP1 can provide a low logic value.

[0093] The second comparator CMP2 provides a logic value by comparing the received signal and the second reference voltage VL1 based on the sampling clock signal. The received signal can be received through the channel CHi. The second comparator CMP2 operates according to the rising or falling transition of the sampling clock signal, sampling the magnitude of the received signal at that sampling time point and comparing it with the second reference voltage VL1. In another embodiment, the second comparator CMP2 can compare the magnitude of the received signal integrated over a high-level or low-level period of the sampling clock signal with the second reference voltage VL1. If the received signal is greater than the second reference voltage VL1, the second comparator CMP2 can provide a high-level logic value, and if the received signal is less than the second reference voltage VL1, the second comparator CMP2 can provide a low-level logic value.

[0094] The multiplexer MUX can output one of the output values ​​of the first comparator CMP1 and the second comparator CMP2 as the current data D[m]. The multiplexer MUX can also select one of the output values ​​of the first comparator CMP1 and the second comparator CMP2 as the current data D[m] based on the past data D[m-1] up to 1 UI. Specifically, if the past data D[m-1] is at a binary level of 1, the output value of the first comparator CMP1 can be output as the current data D[m]. Conversely, if the past data D[m-1] is at a binary level of 0, the output value of the second comparator CMP2 can be output as the current data D[m]. When the output value of the multiplexer MUX is a high logic value, the binary level of the current data D[m] can be 1, and when the output value of the multiplexer MUX is a low logic value, the binary level of the current data D[m] can be 0.

[0095] Figure 5 It is a diagram used to illustrate the pattern of the relationship between the received signals of adjacent channels and the received signals of the target channel.

[0096] When describing jitter caused by crosstalk, the target channel is called the victim channel, and the adjacent channel that adversely affects the victim channel is called the aggressor channel. In this description, we assume that the target channel, which is the victim channel, is channel CH2, and the aggressor channel is channel CH1.

[0097] On the other hand, the jitter caused by crosstalk in channel CH2 has an adverse effect on channel CH1. This adverse effect may return to channel CH2, but in this case, the effect is relatively weak and the explanation would be too complicated, so the explanation is omitted.

[0098] The case where the conversion directions of the sacrificial channel CH2 and the harmful channel CH1 are different is called odd mode. For example... Figure 5 As shown, there are two possible scenarios.

[0099] The case where the conversion directions of the sacrificial channel CH2 and the harmful channel CH1 are the same is called even mode. For example... Figure 5 As shown, there are two possible scenarios.

[0100] Conversely, the situation where no conversion occurs in the channel is called static mode. Figure 5 In this case, regardless of the conversion direction of the sacrificial channel CH2, there is no conversion in the harmful channel CH1. As... Figure 5 As shown, there are two possible scenarios.

[0101] Figure 6 This is a diagram used to illustrate the jitter caused by crosstalk from adjacent received signals. Figure 7 This is a diagram illustrating another example of jitter caused by crosstalk from adjacent received signals.

[0102] refer to Figure 6 The diagram illustrates the even-numbered pattern of all ascending transitions of the sacrificial channel CH2 and the harmful channel CH1.

[0103] If an upward transition occurs in the offending channel CH1, the mutual inductance between the two channels CH1 and CH2 causes a voltage drop in the sacrificial channel CH2 in the opposite direction downwards.

[0104] Therefore, it takes some time for the voltage of the sacrifice channel CH2 to rise again, and this delay becomes the jitter caused by crosstalk in even mode.

[0105] refer to Figure 7 The diagram illustrates the even-numbered pattern where both the sacrificial channel CH2 and the harmful channel CH1 undergo a complete downswing transition.

[0106] If a down-conversion occurs in the offending channel CH1, the mutual inductance between the two channels CH1 and CH2 causes a voltage rise in the sacrificial channel CH2 in the opposite direction.

[0107] Therefore, it takes some time for the voltage of the sacrifice channel CH2 to drop again, and this delay becomes the jitter caused by crosstalk in even mode.

[0108] As a result, in even-numbered modes, jitter occurs due to crosstalk caused by the delay of the received signal in the sacrificial channel CH2, regardless of the conversion direction.

[0109] In odd-numbered mode, jitter caused by crosstalk may occur in the opposite direction to that in even-numbered mode; this is omitted from the description. For reference, in static mode, jitter caused by crosstalk may not occur.

[0110] Figure 8 It is a diagram used to illustrate the jitter caused by crosstalk based on the relationship between the adjacent received signals of two adjacent channels and the received signal of the target channel.

[0111] In this description, it is assumed that the target channel as the sacrifice channel is channel CH2, and the harmful channels are channels CH1 and CH3.

[0112] On the other hand, the jitter caused by crosstalk in channel CH2 has an adverse effect on channels CH1 and CH3. This adverse effect may return to channel CH2, but in this case, the effect is relatively weak and the explanation would be too complicated, so the explanation is omitted.

[0113] The case where the switching directions of the sacrificial channel CH2 and the two harmful channels CH1 and CH3 are the same is called 2-even mode. For example... Figure 8 As shown, there may be two scenarios: case 2em_a where all signals in channels CH1, CH2, and CH3 have an up-conversion and case 2em_b where all signals in channels CH1, CH2, and CH3 have a down-conversion.

[0114] Reference Figure 8 As shown, the following can be confirmed: when two harmful channels CH1 and CH3 switch in the same direction, the jitter caused by the largest crosstalk occurs; when only one harmful channel switches, the jitter caused by the smaller crosstalk occurs; when two harmful channels CH1 and CH3 switch in opposite directions, they cancel each other out and no jitter caused by crosstalk occurs.

[0115] The situation where the switching directions of two adjacent harmful channels CH1 and CH3 are the same but opposite to the switching direction of the sacrificial channel CH2 is called 2-odd mode. (See reference...) Figure 8 The diagram illustrates two scenarios (2om_a, 2om_b). In these scenarios, the jitter caused by crosstalk is in the opposite direction to that of the 2-even pattern.

[0116] The static mode occurs when no switching occurs between the two adjacent harm channels CH1 and CH3.

[0117] Figure 9 This diagram illustrates the rationale for receiving a first training pattern signal with the same first conversion direction through a channel in training mode.

[0118] Hereinafter, the first conversion direction can represent the downward conversion direction. And the second conversion direction can represent the upward conversion direction.

[0119] To illustrate this, refer again... Figure 2 and Figure 3 From this, we can see the following characteristics of dual binary signaling. In the case of a rising transition from 0 to 1 and a falling transition from 1 to 0, the level of the sampled received signal is always the intermediate level IL1.

[0120] For example, refer to Figure 2The transmitted signal transitions from a binary level of 0 to 1, then immediately falls back from 1 to 0. At this time, reference... Figure 2 The received signal fr_a, when sampled at the sampling time points sp2_a and sp3_a corresponding to each conversion, all have the intermediate level IL1.

[0121] And, for example, refer to Figure 3 The transmitted signal, a binary level, rises from 0 to 1, remains 1 during 1UI, and then falls back to 0. At this time, referencing... Figure 3 The received signal spr_b, sampled at the sampling time points sp2_b and sp4_b corresponding to each conversion, all have an intermediate level IL1.

[0122] In this embodiment, compensation for jitter caused by crosstalk can be performed based on the characteristics of dual binary signaling.

[0123] Refer again Figure 9 This conceptually illustrates the case where the 1UI signal was previously at binary level 1 and is currently at binary level 0. That is, the case of a descent transition. Figure 9 The signals shown are not actual signals; for ease of understanding, the responses to individual binary data have been conceptually separated and exaggerated. For example, Figure 9 The sampling time point sp_fs can correspond to Figure 2 The sampling time point sp3_a, Figure 9 The signal that overlaps with the previous signal prv_s_a and the current signal curr_s_a can be Figure 2 The received signal fr_a at sampling time point sp3_a.

[0124] Figure 9 The previous signals prv_o_a, prv_s_a, and prv_e_a are the single bit responses to binary level 1 in odd mode, static mode, and even mode, respectively. To clearly illustrate the signals, it is assumed that the preceding and following binary data are at level 0.

[0125] Figure 9 The current signals curr_o_a, curr_s_a, and curr_e_a are the single-bit responses to binary level 0 in odd mode, static mode, and even mode, respectively, and are assumed to be the case where the preceding and following binary data are at level 1.

[0126] The sampling time point sp_fs is the sampling time point of the sampling clock signal CLK_fs with phase adjusted based on the static mode, and the sampling time point sp_fe is the sampling time point of the sampling clock signal CLK_fe with phase adjusted based on the even mode.

[0127] When the received signal is in static mode and sampling is performed at sampling time point sp_fs using the sampling clock signal CLK_fs, the sum of the first post-mark of the previous signal prv_s_a and the main mark of the current signal curr_s_a is the intermediate level IL1. Since the binary level of the previous signal prv_s_a is 1, the first reference voltage VH1 is used when determining the current signal curr_s_a. Because the sum of the first post-mark of the previous signal prv_s_a and the main mark of the current signal curr_s_a is the intermediate level IL1 and is lower than the first reference voltage VH1, the current signal curr_s_a can be determined as binary level 0.

[0128] Conversely, when the received signal is in even-number mode and sampling is performed at sampling time point sp_fs using the sampling clock signal CLK_fs, the sum of the first post-mark of the previous signal prv_e_a and the main mark of the current signal curr_e_a is higher than the intermediate level IL1. Since the binary level of the previous signal prv_e_a is 1, the first reference voltage VH1 is used when determining the current signal curr_e_a. Because the sum of the first post-mark of the previous signal prv_e_a and the main mark of the current signal curr_e_a is lower than the first reference voltage VH1, the current signal curr_e_a should be determined to be a binary level of 0, but there is a problem that the margin fm1 is too small. Depending on the communication environment, an error occurs during decoding when the sum of the first post-mark of the previous signal prv_e_a and the main mark of the current signal curr_e_a exceeds the first reference voltage VH1.

[0129] When the received signal is in odd-number mode and sampling is performed at sampling time point sp_fs using the sampling clock signal CLK_fs, the sum of the first post-mark of the previous signal prv_o_a and the main mark of the current signal curr_o_a is lower than the intermediate level IL1. Since the binary level of the previous signal prv_o_a is 1, the first reference voltage VH1 is used when determining the current signal curr_o_a. Because the sum of the first post-mark of the previous signal prv_o_a and the main mark of the current signal curr_o_a is sufficiently lower than the first reference voltage VH1, it is not problematic to determine the binary level of the current signal curr_o_a as 0. In this case, there is actually a greater margin than in the static mode.

[0130] As mentioned above, in the case of descent transition, the worst case for compensation is the even-numbered pattern.

[0131] According to this embodiment, in training mode, a "first training pattern signal with the same first conversion direction" can be received through channels CH1 to CH(2n-1), that is, "a first training pattern signal with a descent conversion direction in an even-numbered mode".

[0132] According to this embodiment, a phase-adjusted sampling clock signal CLK_fe can be generated such that the transition time point of the first training pattern signal corresponds to the sampling time point sp_fe. It can be confirmed that at the phase-adjusted sampling time point sp_fe, there is sufficient margin fm2 in the even-numbered mode. There is even greater margin in the static and odd-numbered modes, therefore there are no problems. Accordingly, while following the sampling clock signal CLK_fe, the probability of decoding errors due to jitter caused by crosstalk is reduced in all modes.

[0133] Figure 10 This diagram illustrates the rationale for receiving a second training pattern signal with the same second conversion direction through a channel in training mode.

[0134] Reference Figure 10 This conceptually illustrates the case where the 1UI signal was previously at binary level 0 and is currently at binary level 1. That is, the case of an up-conversion. Figure 10 The signals shown are not actual signals; for ease of understanding, the responses to individual binary data have been conceptually separated and exaggerated. For example, Figure 10 The sampling time point sp_rs can correspond to Figure 2 The sampling time point sp2_a, Figure 10 The signal that overlaps with the previous signal prv_s_b and the current signal curr_s_b can be Figure 2 The received signal fr_a at sampling time point sp2_a.

[0135] Figure 10 The previous signals prv_o_b, prv_s_b, and prv_e_b are the single-bit responses to binary level 0 in odd mode, static mode, and even mode, respectively. To clearly illustrate the signals, it is assumed that the preceding and following binary data are at level 1.

[0136] Figure 10The current signals curr_o_b, curr_s_b, and curr_e_b are the single-bit responses to binary level 1 in odd mode, static mode, and even mode, respectively. For clarity, it is assumed that the preceding and following binary data are at level 0.

[0137] The sampling time point sp_rs is the sampling time point of the sampling clock signal CLK_rs with the phase adjusted based on the static mode, and the sampling time point sp_re is the sampling time point of the sampling clock signal CLK_re with the phase adjusted based on the even mode.

[0138] When the received signal is in static mode and sampling is performed using the sampling clock signal CLK_rs at sampling time point sp_rs, the sum of the first post-mark of the previous signal prv_s_b and the main mark of the current signal curr_s_b is the intermediate level IL1. Since the binary level of the previous signal prv_s_b is 0, the second reference voltage VL1 is used when determining the current signal curr_s_b. Because the sum of the first post-mark of the previous signal prv_s_b and the main mark of the current signal curr_s_b is the intermediate level IL1 and is higher than the second reference voltage VL1, the current signal curr_s_b can be determined to be a binary level 1.

[0139] Conversely, when the received signal is in even-number mode and sampling is performed using the sampling clock signal CLK_rs at sampling time point sp_rs, the sum of the first post-mark of the previous signal prv_e_b and the main mark of the current signal curr_e_b is lower than the intermediate level IL1. Since the binary level of the previous signal prv_e_b is 0, the second reference voltage VL1 is used when determining the current signal curr_e_b. Because the sum of the first post-mark of the previous signal prv_e_b and the main mark of the current signal curr_e_b is higher than the second reference voltage VL1, the current signal curr_e_b should be determined to be a binary level 1, but there is a problem that the margin rm1 is too small. Depending on the communication environment, an error occurs during decoding when the sum of the first post-mark of the previous signal prv_e_b and the main mark of the current signal curr_e_b is less than the second reference voltage VL1.

[0140] When the received signal is in odd-number mode and sampling is performed using the sampling clock signal CLK_rs at sampling time point sp_rs, the sum of the first post-mark of the previous signal prv_o_b and the main mark of the current signal curr_o_b is higher than the intermediate level IL1. Since the binary level of the previous signal prv_o_b is 0, the second reference voltage VL1 is used when determining the current signal curr_o_b. Because the sum of the first post-mark of the previous signal prv_o_b and the main mark of the current signal curr_o_b is sufficiently higher than the second reference voltage VL1, it is not problematic to determine the binary level of the current signal curr_o_b as 1. In this case, there is actually a greater margin than in the static mode.

[0141] As mentioned above, in the case of an ascending transition, the worst-case scenario requiring compensation is the odd-numbered pattern.

[0142] According to this embodiment, in training mode, a "second training pattern signal with the same second conversion direction" can be received through channels CH1 to CH(2n-1), that is, "a second training pattern signal with an upward conversion direction in odd-numbered modes".

[0143] According to this embodiment, a phase-adjusted sampling clock signal CLK_re can be generated such that the transition time point of the second training pattern signal corresponds to the sampling time point sp_re. It can be confirmed that at the phase-adjusted sampling time point sp_re, there is a sufficient margin rm2 in the even-numbered mode. There is an even greater margin in the static and odd-numbered modes, therefore there are no problems. Accordingly, while following the sampling clock signal CLK_re, the probability of decoding errors caused by jitter due to crosstalk is reduced in all modes.

[0144] exist Figure 9 The situation of the descent transition and Figure 10 In all cases of rising transitions, the phase of the sampling clock signals CLK_fe and CLK_re, set based on even mode, is delayed compared to the phase of the sampling clock signals CLK_fs and CLK_rs, set based on static mode.

[0145] Therefore, according to an embodiment of the present invention, even if only one of the first training pattern signal and the second training pattern signal is trained in the training mode, margins fm2 and rm2 can be ensured.

[0146] According to another embodiment of the invention, both the first training pattern signal and the second training pattern signal can be trained in training mode. In this case, the Clock Data Recovery Unit (CDR) can generate the sampled clock signal with a more delayed phase corresponding to a first sampling time point sp_fe corresponding to a first transition time point of the first training pattern signal and a second sampling time point sp_re corresponding to a second transition time point of the second training pattern signal. In this case, with the transition corresponding to the faster phase, there is no problem in resolving decoding errors because a margin is further ensured from the corresponding reference voltage.

[0147] Although Figure 9 and Figure 10 The document describes the case where sampling is performed based on the rising transition of the sampling clock signal; however, according to the product, sampling can also be performed based on the falling transition of the sampling clock signal. Furthermore, according to the product, when using current integral sampling, to ensure acquisition time, the transition points of the clock signals CLK_fs, CLK_fe, CLK_rs, and CLK_re can be before the sampling points sp_fs, sp_fe, sp_rs, and sp_re. For ease of explanation, the case where sampling is performed at the rising transition of the sampling clock signal will be described below.

[0148] Figure 11 and Figure 12 This diagram illustrates the rationale for recovering a clock signal using the first training pattern signal of the sensing channel from the first training pattern signal of the channel.

[0149] The following assumes that the training pattern signal is provided in an even-numbered pattern.

[0150] Even if the transmitting units TX1 to TX(2n-1) transmit the same first training pattern signal, the phase of the first training pattern signal CHns may be delayed to the maximum extent because the sensing channel CHn, located in the middle, is most affected by jitter caused by crosstalk. The sampling clock signal CLK_f3 can be a signal whose phase is adjusted so that the transition time point of the first training pattern signal CHns corresponds to the sampling time point sp_f3.

[0151] The phases of the first training pattern signals CH(n-1)s and CH(n+1)s received through channels CH(n-1) and CH(n+1) can be delayed compared to the phases of other first training pattern signals and faster than the phase of the first training pattern signal CHns. The sampling clock signal CLK_f2 can be a signal whose phase is adjusted so that the transition time of the first training pattern signals CH(n-1)s and CH(n+1)s corresponds to the sampling time point sp_f2.

[0152] The outermost channels CH1 and CH(2n-1) are least affected by jitter caused by crosstalk. Therefore, the phase of the first training pattern signals CH1s and CH(2n-1)s received through channels CH1 and CH(2n-1) can be faster than the phase of other first training pattern signals. The sampling clock signal CLK_f1 can be a signal whose phase is adjusted so that the transition time of the first training pattern signals CH1s and CH(2n-1)s corresponds to the sampling time sp_f1.

[0153] When sampling is performed at sampling time point sp_f1 using sampling clock signal CLK_f1, the sum of the first post-mark of the previous signals prv_CH1s and prv_CH(2n-1)s of channels CH1 and CH(2n-1) and the main mark of the current signals curr_CH1s and curr_CH(2n-1)s is the intermediate level IL1, which has sufficient margin with the first reference voltage VH1. Therefore, decoding to binary level 0 is not a problem.

[0154] However, the sum of the first post-mark of the previous signals prv_CH(n-1)s and prv_CH(n+1)s of channels CH(n-1) and CH(n+1) and the main mark of the current signals curr_CH(n-1)s and curr_CH(n+1)s, as well as the sum of the first post-mark of the previous signal prv_CHns of sensing channel CHn and the main mark of the current signal curr_CHns, exceeds the first reference voltage VH1, thus incorrectly decoding it into binary level 1 and causing an error.

[0155] When sampling is performed at sampling time point sp_f2 using sampling clock signal CLK_f2, the sum of the first post-mark of the previous signals prv_CH(n-1)s and prv_CH(n+1)s of channels CH(n-1) and CH(n+1) and the main mark of the current signals curr_CH(n-1)s and curr_CH(n+1)s is the intermediate level IL1, which has sufficient margin with the first reference voltage VH1. Therefore, decoding to binary level 0 is not a problem.

[0156] Furthermore, the sum of the first post-mark of the previous signals prv_CH1s and prv_CH(2n-1)s of channels CH1 and CH(2n-1) and the main mark of the current signals curr_CH1s and curr_CH(2n-1)s is below the intermediate level IL1. Therefore, the margin with the first reference voltage VH1 is sufficient, so there is no problem in decoding it to binary level 0.

[0157] However, the sum of the first post-mark of the previous signal prv_CHns and the main mark of the current signal curr_CHns in the sensing channel CHn is insufficient with the margin f2m of the first reference voltage VH1, so there is a possibility of incorrect decoding to binary level 1.

[0158] When sampling is performed using the sampling clock signal CLK_f3 at sampling time point sp_f3, the sum of the first post-mark of the previous signal prv_CHns and the main mark of the current signal curr_CHns of the sensing channel CHn is the intermediate level IL1, which has a sufficient margin f3m with the first reference voltage VH1. Therefore, decoding to binary level 0 is not a problem. For other channels CH1, CH(n-1), CH(n+1), and CH(2n-1), there is a larger margin with respect to the first reference voltage VH1, so decoding to binary level 0 is not a problem.

[0159] Therefore, it can be confirmed that even if the sampling clock signal CLK_f3 is generated using the first training pattern signal of the sensing channel CHn, which has the strongest effect of jitter caused by crosstalk, it is not a problem to accurately sample the data signals of other channels CH1, CH(n-1), CH(n+1), and CH(2n-1).

[0160] Figure 13 and Figure 14 This diagram illustrates the rationale for recovering the clock signal using the second training pattern signal of the sensing channel in the second training pattern signal of the channel.

[0161] The following assumes that the training pattern signal is provided in an even-numbered pattern.

[0162] Even if the transmitting units TX1 to TX(2n-1) transmit the same second training pattern signal, the phase of the second training pattern signal CHns' may be delayed to the maximum extent because the sensing channel CHn, located in the middle, is most affected by jitter caused by crosstalk. The sampling clock signal CLK_r3 can be a signal whose phase is adjusted so that the transition time point of the second training pattern signal CHns' corresponds to the sampling time point sp_r3.

[0163] The phases of the second training pattern signals CH(n-1)s' and CH(n+1)s' received through channels CH(n-1) and CH(n+1) can be delayed compared to the phases of other second training pattern signals and faster than the phase of the second training pattern signal CHns'. The sampling clock signal CLK_r2 can be a signal whose phase is adjusted so that the transition time of the second training pattern signals CH(n-1)s' and CH(n+1)s' corresponds to the sampling time sp_r2.

[0164] The outermost channels CH1 and CH(2n-1) are least affected by jitter caused by crosstalk. Therefore, the phases of the second training pattern signals CH1s' and CH(2n-1)s' received through channels CH1 and CH(2n-1) can be faster than the phases of other second training pattern signals. The sampling clock signal CLK_r1 can be a signal whose phase is adjusted so that the transition time of the second training pattern signals CH1s' and CH(2n-1)s' corresponds to the sampling time sp_r1.

[0165] When sampling is performed at sampling time point sp_r1 using sampling clock signal CLK_r1, the sum of the first post-mark of the previous signals prv_CH1s' and prv_CH(2n-1)s' of channels CH1 and CH(2n-1) and the main mark of the current signals curr_CH1s' and curr_CH(2n-1)s' is the intermediate level IL1, which has sufficient margin with the second reference voltage VL1. Therefore, there is no problem in decoding it into binary level 1.

[0166] However, the sum of the first post-mark of the previous signals prv_CH(n-1)s' and prv_CH(n+1)s' of channels CH(n-1) and CH(n+1) and the main mark of the current signals curr_CH(n-1)s' and curr_CH(n+1)s' is insufficient with respect to the second reference voltage VL1, which may lead to incorrect decoding as binary level 0. Furthermore, the sum of the first post-mark of the previous signal prv_CHns' of channel CHn and the main mark of the current signal curr_CHns' is less than the second reference voltage VL1, thus resulting in incorrect decoding as binary level 0.

[0167] When sampling is performed at sampling time point sp_r2 using sampling clock signal CLK_r2, the sum of the first post-mark of the previous signals prv_CH(n-1)s' and prv_CH(n+1)s' of channels CH(n-1) and CH(n+1) and the main mark of the current signals curr_CH(n-1)s' and curr_CH(n+1)s' is the intermediate level IL1, which has sufficient margin with the second reference voltage VL1. Therefore, decoding to binary level 1 is not a problem.

[0168] Furthermore, the sum of the first post-mark of the previous signals prv_CH1s' and prv_CH(2n-1)s' of channels CH1 and CH(2n-1) and the main mark of the current signals curr_CH1s' and curr_CH(2n-1)s' is above the intermediate level IL1, which provides a more sufficient margin with the second reference voltage VL1. Therefore, the second reference voltage VL1 and the margin are more sufficient, so decoding to binary level 1 is not a problem.

[0169] However, the sum of the first post-mark of the previous signal prv_CHns' and the main mark of the current signal curr_CHns' in the sensing channel CHn is insufficient with the margin r2m of the second reference voltage VL1, so there is a possibility of incorrect decoding to binary level 0.

[0170] When sampling is performed using the sampling clock signal CLK_r3 at sampling time point sp_r3, the sum of the first post-mark of the previous signal prv_CHns' and the main mark of the current signal curr_CHns' of the sensing channel CHn is the intermediate level IL1, which has sufficient margin r3m with the second reference voltage VL1. Therefore, decoding to binary level 1 is not a problem. Other channels CH1, CH(n-1), CH(n+1), and CH(2n-1) have a larger margin with the second reference voltage VL1, so decoding to binary level 1 is not a problem.

[0171] Therefore, it can be confirmed that even if the sampling clock signal CLK_r3 is generated using the second training pattern signal of the sensing channel CHn, which has the strongest jitter caused by crosstalk, it is not a problem to accurately sample the data signals of other channels CH1, CH(n-1), CH(n+1), and CH(2n-1).

[0172] Figure 15 This is a diagram illustrating a clock data recovery device according to an embodiment of the present invention.

[0173] Reference Figure 15 The clock data recovery unit (CDR) may include a conversion detector (TDU) and a phase corrector (PCU).

[0174] The transition detector (TDU) can provide a mode signal corresponding to either the training mode or the normal mode based on the training pattern signal and the compensation clock signal Comp_CLK. The training pattern signal can be either a first training pattern signal or a second training pattern signal, and can be received via the sensing line SL. The mode signal can be provided via the mode line ML.

[0175] The phase corrector (PCU) can generate at least one of a compensation clock signal (Comp_CLK) and a sampling clock signal based on the mode signal and the external clock signal (Ext_CLK). The PCU can also generate a first compensation clock signal and a second compensation clock signal based on the external clock signal (Ext_CLK). The compensation clock signal (Comp_CLK) can be provided to the conversion detector (TDU), and the sampling clock signal can be provided to the clock line (CL).

[0176] First, the Transformer Detector (TDU) provides a pattern signal corresponding to the training pattern when input with the training pattern signal. The Phase Corrector (PCU) corrects the phase of the external clock signal Ext_CLK to generate a compensation clock signal Comp_CLK when input with the pattern signal corresponding to the training pattern.

[0177] Next, when the transition time point of the training pattern signal is successfully detected based on the compensation clock signal Comp_CLK in training mode, the transition detector TDU can provide the pattern signal corresponding to the normal mode. Conversely, when the transition time point of the training pattern signal is not detected based on the compensation clock signal Comp_CLK in training mode, the transition detector TDU can continuously provide the pattern signal corresponding to the training mode.

[0178] At this point, while the training mode is maintained, the phase corrector PCU can re-correct the phase of the external clock signal Ext_CLK, thereby regenerating the compensation clock signal Comp_CLK. Furthermore, when the training mode ends and the normal mode begins, the phase corrector PCU can generate a sampling clock signal with the same phase as the current compensation clock signal Comp_CLK.

[0179] Figure 16 This is a diagram illustrating a conversion detector according to an embodiment of the present invention.

[0180] Reference Figure 16 According to an embodiment of the present invention, the conversion detector F_TDU may include integrators INT1 and INT2, comparators CP1 and CP2, a first NAND gate NAND1, a first inverter INV1 and a first mode signal holding unit MISU1.

[0181] The conversion detector F_TDU can receive the first compensation clock signal CCK1 and the second compensation clock signal CCK2, which are used as the aforementioned compensation clock signal Comp_CLK. The phase of the second compensation clock signal CCK2 can be delayed compared to the phase of the first compensation clock signal CCK1.

[0182] Furthermore, the conversion detector F_TDU can receive the first training pattern signal through the sensing line SL.

[0183] The first integrator INT1 can provide a first integrated signal by integrating the first training pattern signal according to the first compensation clock signal CCK1. For example, during the period when the first compensation clock signal CCK1 is high, the first integrator INT1 can integrate the first training pattern signal to provide the first integrated signal.

[0184] The second integrator INT2 can integrate the first training pattern signal based on the second compensation clock signal CCK2 to provide a second integrated signal. For example, during the period when the second compensation clock signal CCK2 is high, the second integrator INT2 can integrate the first training pattern signal to provide a second integrated signal.

[0185] According to the embodiment, integrators INT1 and INT2 can receive the first mode signal through the mode line ML, and can operate under the first mode signal in the training mode and stop operating under the first mode signal in the normal mode.

[0186] The first comparator CP1 can output a logic value of 1 when the first integrated signal is greater than the first reference voltage VH2, and output a logic value of 0 when the first integrated signal is less than the first reference voltage VH2. For example, the first comparator CP1 can operate when the inverted signal CCK1B of the first compensation clock signal CCK1 is high to compare the first integrated signal with the first reference voltage VH2.

[0187] The second comparator CP2 can output a logic value of 1 when the second integrated signal is greater than the first reference voltage VH2, and output a logic value of 0 when the second integrated signal is less than the first reference voltage VH2. For example, the second comparator CP2 can operate when the inverted signal CCK2B of the second compensation clock signal CCK2 is high to compare the second integrated signal with the first reference voltage VH2.

[0188] According to an embodiment, each of the first comparator CP1 and the second comparator CP2 may include a latch at the back end and hold the respective output value for a certain period of time.

[0189] The first inverter INV1 can receive the output value of the second comparator CP2. The first inverter INV1 can output a logic value that inverts the output value of the second comparator CP2.

[0190] The first NAND gate NAND1 can output a first detection signal based on the output values ​​of the first comparator CP1 and the first inverter INV1. For example, the first NAND gate NAND1 can output a logic value of 0 as the first detection signal only when the output values ​​of the first comparator CP1 and the first inverter INV1 are both logic values ​​of 1, and output a logic value of 1 as the first detection signal in other cases. The first detection signal can be applied to the first detection node DN1.

[0191] The first mode signal holding unit MISU1 can provide a first mode signal for the training mode in response to an initialization signal with a conduction level. The first mode signal holding unit MISU1 can receive an initialization signal via the initialization line RSL and provide the first mode signal via the mode line ML.

[0192] According to an embodiment, the first mode signal holding unit MISU1 can provide a first mode signal in normal mode corresponding to a first detection signal of the first conduction level after receiving an initialization signal of the conduction level, and then maintain the first mode signal in normal mode regardless of changes in the level of the first detection signal.

[0193] That is, if the first mode signal holding unit MISU1 starts providing the first mode signal of the normal mode based on the first detection signal, then the first mode signal of the normal mode can be continuously provided regardless of the level fluctuation of the first detection signal. In this embodiment, in order for the first mode signal holding unit MISU1 to provide the first mode signal of the training mode, it is necessary to receive an initialization signal with a conduction level through the initialization line RSL.

[0194] Here, "on level" refers to the level of a signal that enables the transistor to conduct when the corresponding signal is applied. For example, since the first transistor T1 to which the first detection signal is applied is a P-type transistor (e.g., PMOS), the on level of the first detection signal can be low. Furthermore, since the third transistors T3-1 and T3-2 to which the initialization signal is applied are N-type transistors (e.g., NMOS), the on level of the initialization signal can be high.

[0195] According to an embodiment, the first mode signal holding unit MISU1 may include transistors T1, T2, T3-1, T3-2 and inverters INV2, INV3, INV4.

[0196] For the first transistor T1, its gate electrode can receive a first detection signal, one electrode is connected to the first power supply VDD, and the other electrode is connected to the first sensing node SN1. The first transistor T1 can be a P-type transistor. The gate electrode of the first transistor T1 can be connected to the first sensing node DN1.

[0197] For the second transistor T2, its gate electrode can be connected to the output of the second inverter INV2, one electrode is connected to the first power supply VDD, and the other electrode is connected to the first sensing node SN1. The second transistor T2 can be a P-type transistor.

[0198] For the third transistors T3-1 and T3-2, their gate electrodes can receive an initialization signal. One electrode is connected to the first sensing node SN1, and the other electrode is connected to the second power supply VSS. The third transistors T3-1 and T3-2 can be N-type transistors. The gate electrodes of the third transistors T3-1 and T3-2 can be connected to the initialization line RSL. For example... Figure 16 As shown, the third transistors T3-1 and T3-2 may include two sub-transistors T3-1 and T3-2. The voltage level of the second power supply VSS may be lower than the voltage level of the first power supply VDD.

[0199] For the second inverter INV2, the input terminal can be connected to the first sensing node SN1, and the output terminal can be connected to the gate electrode of the second transistor T2.

[0200] The input of the third inverter INV3 can be connected to the first sensing node SN1.

[0201] For the fourth inverter INV4, its input can be connected to the output of the third inverter INV3, and it outputs the first mode signal. For example, the output of the fourth inverter INV4 can be connected to the mode line ML.

[0202] Figure 17 It is used to illustrate what can be used Figure 16 A graph of an exemplary first training style signal for the transformation detector.

[0203] Figure 17 The dashed waveform represents the waveform of the first training pattern signal F_TRP under ideal channel conditions. Figure 17 The solid line waveform represents the waveform of the first training pattern signal F_TRP under actual channel conditions.

[0204] One period of the first training pattern signal F_TRP can be (j+k)-UI, and the binary level during j-UI can be different from the binary level during k-UI. In this case, j and k can be integers greater than 0.

[0205] According to one embodiment, k can be 1. For example, the first training pattern signal F_TRP can include a falling pulse during 1 UI of 1 cycle and remain high during the remaining UI of 1 cycle.

[0206] In this scenario, since no transition occurs during the j-UI period and the voltage is charged to the channel, the first transition (fall-down transition) may not occur sufficiently during the short k-UI period. That is, Figure 17 The first training pattern signal F_TRP is likely the worst-case scenario for inter-symbol interference during descent transition.

[0207] Therefore, by simultaneously sending the first training pattern signal F_TRP (even pattern) as the worst-case scenario to all channels, and by determining the phase of the sampling clock signal in a way that the first transition can be detected in the sensing channel, a sampling clock signal phase that is robust to both jitter caused by crosstalk and inter-symbol interference can be obtained.

[0208] According to this embodiment, since it is not necessary to apply pre-emphasis technology to the transmission units TX1 to TX(2n-1), the construction cost can be saved.

[0209] Figures 18 to 20 It is used to illustrate the signal based on the first training pattern. Figure 16 A diagram illustrating the operation of the conversion detector.

[0210] Specifically, Figure 18 It is used for explanation Figure 17 A graph showing the operation of the switching detector F_TDU during the time period t1f to t2f. Figure 19 and Figure 20 It is used for explanation Figure 17 The diagram shows the operation of the switching detector F_TDU during the time period t2f to t3f.

[0211] The first reference voltage VH2 can be the intermediate value between the highest level HL2 and the intermediate level IL2 of the variable levels of the integral signals INT1s and INT2s. The second reference voltage VL2 can be the intermediate value between the lowest level LL2 and the intermediate level IL2 of the variable levels of the integral signals INT1s and INT2s. Voltages HL2, VH2, IL2, VL2, and LL2 can be compared with reference... Figure 2 and Figure 3 The voltages HL1, VH1, IL1, VL1, and LL1 may be the same or different.

[0212] When the first integral signal INT1s is greater than the first reference voltage VH2 and the second integral signal INT2s is less than the first reference voltage VH2, the conversion detector F_TDU can detect the occurrence of the conversion of the first training pattern signal F_TRP.

[0213] For example, the first integrator INT1 can integrate the first training pattern signal F_TRP during the period when the first compensation clock signal CCK1 is high to generate the first integrated signal INT1s. Furthermore, the second integrator INT2 can integrate the first training pattern signal F_TRP during the period when the second compensation clock signal CCK2 is high to generate the second integrated signal INT2s.

[0214] According to the embodiment, when the corresponding compensation clock signals CCK1 and CCK2 are low, the integrators INT1 and INT2 can be initialized, thereby initializing the output value to the intermediate level IL2.

[0215] for Figure 18 In the case where no transition occurs during the period t1f to t2f, the magnitudes of the first integral signal INT1s and the second integral signal INT2s can be the same.

[0216] exist Figure 18 In this case, the first integral signal INT1s and the second integral signal INT2s are greater than the first reference voltage VH2, therefore the first comparator CP1 and the second comparator CP2 both output a logic value of 1. Accordingly, the first inverter INV1 outputs a logic value of 0, and the first NAND gate NAND1 outputs a logic value of 1. The first detection signal has a logic value of 1, and the first transistor T1 remains in the off state. Therefore, in Figure 18 In this case, the first mode signal of the training mode can be continuously output, and the phase of the first compensation clock signal CCK1 and the second compensation clock signal CCK2 can be changed and adjusted by the phase corrector PCU.

[0217] for Figure 19 and Figure 20 In this case, during the transition period t2f to t3f, the magnitudes of the first integral signal INT1s and the second integral signal INT2s can be different from each other. For example, the second integral signal INT2s can be smaller than the first integral signal INT1s.

[0218] Nevertheless, in Figure 19 In this case, since the first integral signal INT1s and the second integral signal INT2s are greater than the first reference voltage VH2, the first detection signal has a logic value of 1. Therefore, in Figure 19 In this case, the first mode signal of the training mode can be continuously output, and the phase of the first compensation clock signal CCK1 and the second compensation clock signal CCK2 can be changed and adjusted by the phase corrector PCU.

[0219] exist Figure 20 In this case, the first integral signal INT1s is greater than the first reference voltage VH2, and the second integral signal INT2s is less than the first reference voltage VH2. Therefore, the first comparator CP1 outputs a logic value of 1, and the second comparator CP2 outputs a logic value of 0. Therefore, the first inverter INV1 outputs a logic value of 1, and the first NAND gate NAND1 outputs a logic value of 0. The first detection signal has a logic value of 0, and the first transistor T1 is turned on.

[0220] Therefore, the voltage of the first power supply VDD is charged to the first sensing node SN1, and the logic value 1 is output as the first mode signal through the third inverter INV3 and the fourth inverter INV4. The logic value 1 of the first mode signal can represent the normal mode, and the logic value 0 can represent the training mode. Therefore, the phase corrector PCU can generate a sampling clock signal with the same phase as the second compensation clock signal CCK2.

[0221] Subsequently, even if the logic value of the first detection signal changes and the first transistor T1 turns on or off, the second transistor T2 remains on through the second inverter INV2, thus maintaining the voltage of the first sensing node SN1. Therefore, regardless of changes in the logic value of the first detection signal, the first mode signal in normal mode continues to be output.

[0222] Figure 21 This is a diagram illustrating a conversion detector according to another embodiment of the present invention.

[0223] Reference Figure 21 According to an embodiment of the present invention, the conversion detector R_TDU may include integrators INT3 and INT4, comparators CP3 and CP4, a fifth inverter INV5, a second NAND gate NAND2, and a second mode signal holding section MISU2.

[0224] The conversion detector R_TDU can receive the third compensation clock signal CCK3 and the fourth compensation clock signal CCK4, which are used as the compensation clock signal Comp_CLK mentioned above. The phase of the fourth compensation clock signal CCK4 can be delayed compared to the phase of the third compensation clock signal CCK3.

[0225] Furthermore, the conversion detector R_TDU can receive the second training pattern signal through the sensing line SL.

[0226] The third integrator INT3 can provide a third integrated signal by integrating the second training pattern signal based on the third compensation clock signal CCK3. For example, during the period when the third compensation clock signal CCK3 is high, the third integrator INT3 can integrate the second training pattern signal to provide a third integrated signal.

[0227] The fourth integrator INT4 can provide a fourth integrated signal by integrating the second training pattern signal based on the fourth compensation clock signal CCK4. For example, during the period when the fourth compensation clock signal CCK4 is high, the fourth integrator INT4 can provide a fourth integrated signal by integrating the second training pattern signal.

[0228] According to the embodiment, integrators INT3 and INT4 can receive the second mode signal through the mode line ML, and can operate under the second mode signal in training mode and stop operating under the second mode signal in normal mode.

[0229] The third comparator CP3 can output a logic value of 1 when the third integral signal is greater than the second reference voltage VL2, and output a logic value of 0 when the third integral signal is less than the second reference voltage VL2. For example, the third comparator CP3 can operate when the inverted signal CCK3B of the third compensation clock signal CCK3 is high, and compare the third integral signal with the second reference voltage VL2.

[0230] The fourth comparator CP4 can output a logic value of 1 when the fourth integral signal is greater than the second reference voltage VL2, and output a logic value of 0 when the fourth integral signal is less than the second reference voltage VL2. For example, the fourth comparator CP4 can operate when the inverted signal CCK4B of the fourth compensation clock signal CCK4 is high to compare the fourth integral signal with the second reference voltage VL2.

[0231] According to an embodiment, each of the third comparator CP3 and the fourth comparator CP4 may include a latch at the back end and hold the respective output value for a certain period of time.

[0232] The fifth inverter, INV5, can receive the output value of the third comparator, CP3. The fifth inverter, INV5, can output a logic value that inverts the output value of the third comparator, CP3.

[0233] The second NAND gate NAND2 can output a second detection signal based on the output values ​​of the fifth inverter INV5 and the fourth comparator CP4. For example, the second NAND gate NAND2 can output a logic value of 0 as the second detection signal only when the output values ​​of the fifth inverter INV5 and the fourth comparator CP4 are both logic values ​​of 1, and output a logic value of 1 as the second detection signal in other cases. The second detection signal can be applied to the second detection node DN2.

[0234] The second mode signal holding unit MISU2 can provide a second mode signal for the training mode in response to an initialization signal with a conduction level. The second mode signal holding unit MISU2 can receive an initialization signal via the initialization line RSL and provide the second mode signal via the mode line ML.

[0235] According to an embodiment, the second mode signal holding unit MISU2 can provide a normal mode second mode signal corresponding to the second detection signal of the first conduction level after receiving the initialization signal of the conduction level, and then maintain the normal mode second mode signal regardless of the level change of the second detection signal.

[0236] That is, if the second mode signal holding unit MISU2 starts providing the second mode signal of the normal mode based on the second detection signal, it can then continuously provide the second mode signal of the normal mode regardless of the level fluctuation of the second detection signal. In this embodiment, in order for the second mode signal holding unit MISU2 to provide the second mode signal of the training mode, it is necessary to receive an initialization signal with a conduction level through the initialization line RSL.

[0237] According to an embodiment, the second mode signal holding section MISU2 may include transistors T4, T5, T6-1, T6-2 and inverters INV6, INV7, INV8.

[0238] For the fourth transistor T4, its gate electrode can receive the second detection signal, one electrode is connected to the first power supply VDD, and the other electrode is connected to the second sensing node SN2. The fourth transistor T4 can be a P-type transistor. The gate electrode of the fourth transistor T4 can be connected to the second sensing node DN2.

[0239] For the fifth transistor T5, its gate electrode can be connected to the output of the sixth inverter INV6, one electrode is connected to the first power supply VDD, and the other electrode is connected to the second sensing node SN2. The fifth transistor T5 can be a P-type transistor.

[0240] For the sixth transistors T6-1 and T6-2, their gate electrodes can receive an initialization signal, one electrode is connected to the second sensing node SN2, and the other electrode is connected to the second power supply VSS. The sixth transistors T6-1 and T6-2 can be N-type transistors. The gate electrodes of the sixth transistors T6-1 and T6-2 can be connected to the initialization line RSL. For example... Figure 21 As shown, the sixth transistors T6-1 and T6-2 may include two sub-transistors T6-1 and T6-2.

[0241] The input of the sixth inverter INV6 can be connected to the second sensing node SN2, and the output can be connected to the gate electrode of the fifth transistor T5.

[0242] The input of the seventh inverter INV7 can be connected to the second sensing node SN2.

[0243] For the eighth inverter INV8, its input can be connected to the output of the seventh inverter INV7, and it outputs a second mode signal. For example, the output of the eighth inverter INV8 can be connected to the mode line ML.

[0244] Figure 22 It is used to illustrate what can be used Figure 21 A diagram of an exemplary second training style signal for the transformation detector.

[0245] Figure 22 The dashed waveform represents the waveform of the second training pattern signal R_TRP under ideal channel conditions. Figure 22 The solid line waveform represents the waveform of the second training pattern signal R_TRP under actual channel conditions.

[0246] One period of the second training pattern signal R_TRP can be (j+k)-UI, and the binary level during j-UI can be different from the binary level during k-UI. In this case, j and k can be integers greater than 0.

[0247] According to one embodiment, k can be 1. For example, the second training pattern signal R_TRP can include a rising pulse during 1 UI of 1 cycle and remain low during the remaining UI of 1 cycle.

[0248] In this scenario, since no transition occurs during the j-UI period and the voltage is charged to the channel, the second transition (ascending transition) may not occur sufficiently during the short k-UI period. That is, Figure 22 The second training pattern signal R_TRP is likely the worst-case scenario for inter-symbol interference during the rising transition.

[0249] Therefore, by simultaneously sending the second training pattern signal R_TRP (even pattern) as the worst-case scenario to all channels, and by determining the phase of the sampling clock signal in a way that the second transition can be detected in the sensing channel, a sampling clock signal phase that is robust to both jitter caused by crosstalk and inter-symbol interference can be obtained.

[0250] According to this embodiment, since pre-enhancement technology is not required in the transmission units TX1 to TX(2n-1), the construction cost can be saved.

[0251] for Figure 21 For the transition detector R_TDU, when the third integral signal is less than the second reference voltage VL2 and the fourth integral signal is greater than the second reference voltage VL2, the transition of the second training pattern signal R_TRP can be detected. Detailed operation of the transition detector R_TDU and... Figure 16 The detailed operation of the transition detector F_TDU is similar, so repeated descriptions will be omitted. For reference, since the first training pattern signal F_TRP is held high for a relatively long time, the transition detector F_TDU can operate with reference to the first reference voltage VH2, while since the second training pattern signal R_TRP is held low for a relatively long time, the transition detector R_TDU can operate with reference to the second reference voltage VL2.

[0252] Based on the above, Figure 15The transition detector TDU can be configured as Figure 16 The conversion detector F_TDU and Figure 22 One of the conversion detectors R_TDU.

[0253] For example, in the transition detector TDU only includes Figure 16 In the case of a transition detector F_TDU, the clock data recovery unit DR can provide a second compensated clock signal CCK2 with the phase when a transition is detected as the sampling clock signal. For example, in the case where the transition detector TDU only includes Figure 22 In the case of the transition detector R_TDU, the clock data restorer CDR can provide a fourth compensated clock signal CCK4 with the phase when a transition is detected as the sampling clock signal.

[0254] According to another embodiment, Figure 15 The transition detector TDU can include all transition detectors F_TDU and R_TDU.

[0255] For example, the clock data recovery unit (CDR) can send the first mode signal of the training mode to the mode line ML. Upon receiving the first mode signal of the training mode, the transmitting units TX1 to TX(2n-1) can transmit the first training pattern signal F_TRP.

[0256] Therefore, the Clock Data Recovery Unit (CDR) can activate the Conversion Detector (F_TDU) and output the first mode signal of normal mode to the mode line ML. At this time, the Clock Data Recovery Unit (CDR) can store the phase of the second compensated clock signal CCK2 as the first phase.

[0257] Next, the clock data recovery unit (CDR) can send the second mode signal of the training mode to the mode line ML. Upon receiving the second mode signal of the training mode, the transmitting units TX1 to TX(2n-1) can send the second training pattern signal R_TRP.

[0258] Therefore, the Clock Data Recovery Unit (CDR) can enable the Transition Detector (R_TDU) to operate and output a second mode signal in normal mode to the mode line (ML). At this time, the CDR can store the phase of the fourth compensation clock signal (CCK4) as the second phase.

[0259] The Clock Data Recovery (CDR) can provide a compensated clock signal with a more delayed phase, either the first or second phase, as the sampling clock signal. For example, if the first phase is delayed compared to the second phase, a second compensated clock signal CCK2 is provided as the sampling clock signal; conversely, if the second phase is delayed compared to the first phase, a fourth compensated clock signal CCK4 is provided. The reason for choosing the more delayed phase can be found in the section on... Figure 12 and Figure 14 The explanation is as follows. According to this embodiment, the phase of the sampling clock signal that is robust to both descent and scalar transitions can be obtained.

[0260] The accompanying drawings and detailed description of the invention described so far are merely illustrative of the invention and are used for purposes of explanation only, not to limit the meaning or scope of the invention as set forth in the claims. Therefore, it will be understood by those skilled in the art that various modifications and equivalent embodiments can be implemented. Thus, the true scope of protection of this invention should be determined based on the technical concept of the stated claims.

Claims

1. A clock data recovery device, comprising: A phase corrector generates a first compensation clock signal and a second compensation clock signal based on an external clock signal; as well as Conversion detector, The conversion detector includes: A first integrator integrates a first training pattern signal based on the first compensation clock signal to provide a first integrated signal; and The second integrator integrates the first training pattern signal according to the second compensation clock signal to provide a second integrated signal. Specifically, when the first integral signal is greater than the first reference voltage and the second integral signal is less than the first reference voltage, the conversion detector detects the occurrence of a conversion in the first training pattern signal.

2. The clock data recovery device according to claim 1, wherein, The phase of the second compensation clock signal is delayed compared to the phase of the first compensation clock signal.

3. The clock data recovery device according to claim 2, wherein, The conversion detector also includes: The first comparator outputs a logic value of 1 when the first integrated signal is greater than the first reference voltage, and outputs a logic value of 0 when the first integrated signal is less than the first reference voltage; and The second comparator outputs a logic value of 1 when the second integrated signal is greater than the first reference voltage, and outputs a logic value of 0 when the second integrated signal is less than the first reference voltage.

4. The clock data recovery device according to claim 3, wherein, The conversion detector also includes: The first inverter receives the output value of the second comparator.

5. The clock data recovery device according to claim 4, wherein, The conversion detector also includes: The first NAND gate outputs a first detection signal based on the output values ​​of the first comparator and the first inverter.

6. The clock data recovery device according to claim 5, wherein, The conversion detector also includes: The first mode signal holding unit provides the first mode signal for the training mode in response to the initialization signal of the conduction level. The first mode signal holding unit provides a first mode signal in normal mode corresponding to the first detection signal at the first conduction level after receiving the initialization signal at the conduction level, and thereafter holds the first mode signal in normal mode regardless of level changes of the first detection signal.

7. The clock data recovery device according to claim 6, wherein, The first mode signal holding unit includes: The first transistor has a gate electrode that receives the first detection signal, one electrode that is connected to a first power supply, and the other electrode that is connected to a first sensing node. The second transistor has one electrode connected to the first power supply and the other electrode connected to the first sensing node; The third transistor has a gate electrode that receives the initialization signal, one electrode connected to the first sensing node, and the other electrode connected to the second power supply; and The second inverter has its input connected to the first sensing node and its output connected to the gate electrode of the second transistor.

8. The clock data recovery device according to claim 7, wherein, The first mode signal holding unit further includes: A third inverter, the input of which is connected to the first sensing node; and The fourth inverter has its input terminal connected to the output terminal of the third inverter and outputs the first mode signal.

9. The clock data recovery device according to claim 8, wherein, The conversion detector also includes: A third integrator integrates the second training pattern signal according to a third compensation clock signal to provide a third integrated signal; and The fourth integrator integrates the second training pattern signal according to the fourth compensation clock signal to provide a fourth integrated signal. Specifically, when the third integral signal is less than the second reference voltage and the fourth integral signal is greater than the second reference voltage, the occurrence of the transition of the second training pattern signal is detected.

10. The clock data recovery device according to claim 9, wherein, The conversion detector also includes: The third comparator outputs a logic value of 1 when the third integrated signal is greater than the second reference voltage, and outputs a logic value of 0 when the third integrated signal is less than the second reference voltage; and The fourth comparator outputs a logic value of 1 when the fourth integrated signal is greater than the second reference voltage, and outputs a logic value of 0 when the fourth integrated signal is less than the second reference voltage.

11. The clock data recovery device according to claim 10, wherein, The conversion detector also includes: The fifth inverter receives the output value of the third comparator; and The second NAND gate outputs a second detection signal based on the output values ​​of the fifth inverter and the fourth comparator.

12. The clock data recovery device according to claim 11, wherein, The conversion detector also includes: The second mode signal holding unit provides a second mode signal for the training mode in accordance with the initialization signal corresponding to the conduction level. The second mode signal holding unit provides a normal mode second mode signal corresponding to the second detection signal at the first conduction level after receiving the initialization signal at the conduction level, and thereafter holds the normal mode second mode signal regardless of level fluctuations of the second detection signal.

13. The clock data recovery device according to claim 12, wherein, The second mode signal holding unit includes: The fourth transistor has a gate electrode that receives the second detection signal, one electrode that is connected to the first power supply, and the other electrode that is connected to the second sensing node. The fifth transistor has one electrode connected to the first power supply and the other electrode connected to the second sensing node; The sixth transistor has a gate electrode that receives the initialization signal, one electrode that is connected to the second sensing node, and the other electrode that is connected to the second power supply. The sixth inverter has its input connected to the second sensing node and its output connected to the gate electrode of the fifth transistor. The seventh inverter, with its input connected to the second sensing node; and The eighth inverter has its input terminal connected to the output terminal of the seventh inverter and outputs the second mode signal.

14. The clock data recovery device according to claim 13, wherein, The first training pattern signal includes a falling pulse during a 1-unit interval within a 1-cycle period. The second training pattern signal includes a rising pulse during a 1-unit interval within a 1-cycle period.

15. The clock data recovery device according to claim 14, wherein, The first training pattern signal remains high during the remaining unit intervals in one cycle, excluding the one-unit interval. The second training pattern signal remains at a low level during the remaining unit intervals in a 1-cycle, excluding the 1-unit interval.

16. A clock data recovery device, comprising: A phase corrector generates a first compensation clock signal and a second compensation clock signal based on an external clock signal; as well as Conversion detector, The conversion detector includes: A first integrator integrates a first training pattern signal based on the first compensation clock signal to provide a first integrated signal; and The second integrator integrates the first training pattern signal according to the second compensation clock signal to provide a second integrated signal. Specifically, when the first integral signal is less than the first reference voltage and the second integral signal is greater than the first reference voltage, the conversion detector detects the occurrence of a conversion in the first training pattern signal.

17. A clock data recovery device, comprising: A phase corrector generates a first compensation clock signal and a second compensation clock signal based on an external clock signal; as well as Conversion detector, The conversion detector includes: a first integrator, which integrates the first training pattern signal according to the first compensation clock signal to provide a first integrated signal; and The second integrator integrates the first training pattern signal based on a second compensated clock signal whose phase is delayed compared to the first compensated clock signal to provide a second integrated signal. Specifically, when the first integral signal is greater than the first reference voltage and the second integral signal is less than the first reference voltage, the phase of the second compensation clock signal is stored as the first phase.

18. The clock data recovery device according to claim 17, wherein, The conversion detector also includes: A third integrator integrates the second training pattern signal according to a third compensation clock signal to provide a third integrated signal; and The fourth integrator integrates the second training pattern signal according to the fourth compensation clock signal to provide a fourth integrated signal. Specifically, when the third integral signal is less than the second reference voltage and the fourth integral signal is greater than the second reference voltage, the phase of the fourth compensation clock signal is stored as the second phase.

19. The clock data recovery device according to claim 18, wherein, When the first phase is delayed compared to the second phase, the second compensation clock signal is provided as the sampling clock signal. When the second phase is delayed compared to the first phase, the fourth compensated clock signal is provided as the sampling clock signal.

20. The clock data recovery device according to claim 19, wherein, The first training pattern signal includes a falling pulse during one unit interval of one cycle and remains high during the remaining unit intervals of one cycle. The second training pattern signal includes a rising pulse during a 1-unit interval in 1 cycle and remains low during the remaining 1-unit interval in 1 cycle.

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