Light-emitting display device and its pixel

Abstract

The present invention relates to a light-emitting display device and a pixel thereof. The pixel of the light-emitting display device includes: a capacitor; a first transistor; a second transistor including a gate for receiving a gate write signal; a third transistor including a gate for receiving a scan signal; a fourth transistor including a gate for receiving a gate initialization signal; a fifth transistor including a gate for receiving a first emission signal; a sixth transistor including a gate for receiving a second emission signal; and a light-emitting diode. The scan signal and the gate write signal may be provided at a first frequency, and the first emission signal, the second emission signal, and the gate initialization signal may be provided at a second frequency higher than the first frequency.

Description

Technical Field

[0001] The inventive concept relates to a display device, and more particularly, to a light-emitting display device and a pixel thereof. Background Art

[0002] A display device such as an organic light-emitting diode (OLED) display device may display an image at a constant frame rate (or constant frame frequency) of about 60 Hz or higher. However, the frame rate of a rendering process in which frame data is provided from a host processor (e.g., a graphics processing unit (GPU) and / or a graphics card) to the OLED display device may be different from the frame rate (or refresh rate) of the OLED display device. Specifically, when the host processor provides frame data for a game image (game image), etc., which requires complex rendering, to the OLED display device, the frame rate mismatch may be exacerbated, and a tearing phenomenon may occur in a case where a boundary line is caused by the frame rate mismatch in an image of the OLED display device.

[0003] To prevent or reduce the tearing phenomenon, a variable frame mode (e.g., FreeSync, G-Sync, etc.) may be used, in which the host processor provides frame data to the OLED display device at a variable frame rate (or variable frame frequency) by changing the time length (or duration) of a blank period in each frame period. The OLED display device supporting the variable frame mode may display an image in synchronization with the variable frame rate, thereby reducing or preventing the tearing phenomenon.

[0004] However, in an OLED display device operating in the variable frame mode, even if the input image data represents a constant gray level, the brightness of the OLED display device may not remain constant as the time length of the blank period changes. Summary of the Invention

[0005] An exemplary embodiment provides a pixel of a light-emitting display device having substantially constant brightness even when a driving frequency changes.

[0006] An exemplary embodiment provides an organic light-emitting diode (OLED) display device capable of having substantially constant brightness even when a driving frequency changes.

[0007] According to an exemplary embodiment, a pixel of a light-emitting display device is provided. The pixel includes: a capacitor having a first electrode coupled to a line of a first power supply voltage and a second electrode coupled to a gate node; a first transistor having a first terminal, a second terminal, and a gate coupled to the gate node; a second transistor having a gate receiving a gate write signal, a first terminal coupled to a data line, and a second terminal coupled to the first terminal of the first transistor; a third transistor having a gate receiving a scan signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the gate node; a fourth transistor having a gate receiving a gate initialization signal, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to an anode of a light-emitting diode; a fifth transistor having a gate receiving a first emission signal, a first terminal coupled to a line of the first power supply voltage, and a second terminal coupled to the first terminal of the first transistor; a sixth transistor having a gate receiving a second emission signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the light-emitting diode; and a light-emitting diode having an anode and a cathode coupled to a line of a second power supply voltage. The scan signal and the gate write signal are provided at a first frequency, and the first emission signal, the second emission signal, and the gate initialization signal are provided at a second frequency higher than the first frequency.

[0008] In an exemplary embodiment, the first transistor, the second transistor, the fourth transistor, and the fifth transistor may be P-type metal-oxide-semiconductor (PMOS) transistors, and the third transistor and the sixth transistor may be N-type metal-oxide-semiconductor (NMOS) transistors.

[0009] In an exemplary embodiment, the first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor may be PMOS transistors, and the third transistor may be an NMOS transistor.

[0010] In an exemplary embodiment, the second frequency may be a fixed frequency, and the first frequency may be a variable frequency.

[0011] In an exemplary embodiment, the light-emitting diode is an organic light-emitting diode (OLED), the light-emitting display device is an OLED display device, the second frequency may correspond to twice the maximum frequency of the variable input frame frequency of the OLED display device, and the first frequency may correspond to the second frequency divided by N, where N is an integer greater than 1 and less than or equal to the maximum frequency.

[0012] In an exemplary embodiment, the light-emitting diode is an organic light-emitting diode (OLED), the light-emitting display device is an OLED display device, and the frame period of the OLED display device may include: a gate and anode initialization period in which a gate node and an anode are initialized; a data writing period in which a data voltage of a data line is written into a capacitor; a first bias period in which a bias is applied to a first transistor; a first emission period in which the organic light-emitting diode emits light; an anode initialization period in which the anode is initialized; a second bias period in which a bias is applied to the first transistor; and a second emission period in which the organic light-emitting diode emits light.

[0013] In an exemplary embodiment, during the gate and anode initialization period, the first emission signal may have a cut-off level, the second emission signal may have a conduction level, the gate initialization signal may have a conduction level, the scan signal may have a conduction level, the gate write signal may have a cut-off level, the third transistor, the fourth transistor, and the sixth transistor may be turned on, an initialization voltage may be applied to the anode through the fourth transistor, and the initialization voltage may be applied to the gate node through the fourth transistor, the sixth transistor, and the third transistor.

[0014] In an exemplary embodiment, during the data writing period, the first emission signal may have a cut-off level, the second emission signal may have a cut-off level, the gate initialization signal may have a cut-off level, the scan signal may have a conduction level, the gate write signal may have a conduction level, the second transistor and the third transistor may be turned on, the third transistor may diode-connect the first transistor, and the data voltage may be applied to a second electrode of the capacitor through the second transistor and the diode-connected first transistor.

[0015] In an exemplary embodiment, during the first bias period, the first emission signal may have a conduction level, the second emission signal may have a cut-off level, the gate initialization signal may have a cut-off level, the scan signal may have a cut-off level, the gate write signal may have a cut-off level, the fifth transistor may be turned on, and a first power supply voltage may be applied to a first terminal of the first transistor through the fifth transistor.

[0016] In an exemplary embodiment, in each of the first emission period and the second emission period, the first emission signal may have a conduction level, the second emission signal may have a conduction level, the gate initialization signal may have a cut-off level, the scan signal may have a cut-off level, the gate write signal may have a cut-off level, the fifth transistor and the sixth transistor may be turned on, and a drive current generated by the first transistor may be provided to the organic light-emitting diode.

[0017] In an exemplary embodiment, during an anode initialization period, the first emission signal may have a cut-off level, the second emission signal may have a conduction level, the gate initialization signal may have a conduction level, the scan signal may have a cut-off level, the gate write signal may have a cut-off level, the fourth transistor and the sixth transistor may be turned on, and an initialization voltage may be applied to the anode through the fourth transistor.

[0018] In an exemplary embodiment, during a second bias period, the first emission signal may have a conduction level, the second emission signal may have a cut-off level, the gate initialization signal may have a cut-off level, the scan signal may have a cut-off level, the gate write signal may have a cut-off level, the fifth transistor may be turned on, and a first power supply voltage may be applied to a first terminal of the first transistor through the fifth transistor.

[0019] According to an exemplary embodiment, an OLED display device is provided, including: a display panel having a plurality of pixels; a scan driver configured to provide a scan signal, a gate write signal, and a gate initialization signal to the plurality of pixels; an emission driver configured to provide a first emission signal and a second emission signal to the plurality of pixels; and a controller configured to control the scan driver and the emission driver. Each pixel among the plurality of pixels includes: a capacitor having a first electrode coupled to a line of a first power supply voltage and a second electrode coupled to a gate node; a first transistor having a first terminal, a second terminal, and a gate coupled to the gate node; a second transistor having a gate receiving the gate write signal, a first terminal coupled to a data line, and a second terminal coupled to the first terminal of the first transistor; a third transistor having a gate receiving the scan signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the gate node; a fourth transistor having a gate receiving the gate initialization signal, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to an anode of an organic light-emitting diode; a fifth transistor having a gate receiving the first emission signal, a first terminal coupled to a line of the first power supply voltage, and a second terminal coupled to the first terminal of the first transistor; a sixth transistor having a gate receiving the second emission signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the organic light-emitting diode; and an organic light-emitting diode having an anode and a cathode coupled to a line of a second power supply voltage. The scan driver provides the scan signal and the gate write signal to the plurality of pixels at a first frequency, and provides the gate initialization signal to the plurality of pixels at a second frequency higher than the first frequency. The emission driver provides the first emission signal and the second emission signal to the plurality of pixels at the second frequency.

[0020] In an exemplary embodiment, the OLED display device further includes: a data driver configured to provide data voltages to a plurality of pixels. The controller can control the data driver, can provide a scan start pulse and a gate write start pulse to the scan driver at a first frequency such that the scan signal and the gate write signal are provided at the first frequency; can provide a gate initialization start pulse to the scan driver at a second frequency such that the gate initialization signal is provided at the second frequency; and can provide a first emission start pulse and a second emission start pulse to the emission driver at the second frequency such that the first emission signal and the second emission signal are provided at the second frequency.

[0021] In an exemplary embodiment, within each frame period, the controller can provide one scan start pulse, one gate write start pulse, and at least two gate initialization start pulses to the scan driver, and can provide at least two first emission start pulses and at least two second emission start pulses to the emission driver.

[0022] In an exemplary embodiment, the second frequency can be a fixed frequency, and the first frequency can be a variable frequency.

[0023] In an exemplary embodiment, the controller can receive input image data from an external host processor at a variable input frame frequency, the second frequency can correspond to twice the maximum frequency of the variable input frame frequency, and the first frequency can correspond to the second frequency divided by N, where N is an integer greater than 1 and less than or equal to the maximum frequency.

[0024] In an exemplary embodiment, the first transistor, the second transistor, the fourth transistor, and the fifth transistor can be PMOS transistors, and the third transistor and the sixth transistor can be NMOS transistors.

[0025] In an exemplary embodiment, the first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor can be PMOS transistors, and the third transistor can be an NMOS transistor.

[0026] In an exemplary embodiment, the frame period of the OLED display device can include: a gate and anode initialization period during which the gate node and the anode are initialized; a data write period during which the data voltage of the data line is written to the capacitor; a first bias period during which a bias is applied to the first transistor; a first emission period during which the organic light-emitting diode emits light; an anode initialization period during which the anode is initialized; a second bias period during which a bias is applied to the first transistor; and a second emission period during which the organic light-emitting diode emits light.

[0027] According to an exemplary embodiment, a display device includes: a display panel having a plurality of pixels; a scan driver configured to provide a scan signal to the plurality of pixels; and an emission driver configured to provide an emission signal to the plurality of pixels; wherein each of the plurality of pixels includes: a first transistor including a first terminal, a second terminal, and a gate coupled to a capacitor; a second transistor including a gate coupled to the scan driver, a first terminal coupled to a data line, and a second terminal coupled to the first terminal of the first transistor; a third transistor including a gate coupled to the scan driver, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the gate of the first transistor; a fifth transistor including a gate coupled to the emission driver, a first terminal coupled to a line of a first power voltage, and a second terminal coupled to the first terminal of the first transistor; and a sixth transistor including a gate coupled to the emission driver, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a first terminal of an emission device, wherein the scan driver provides a signal to the plurality of pixels at a first frequency; wherein the emission driver provides a signal to the plurality of pixels at a second frequency greater than the first frequency.

[0028] In an exemplary embodiment, the display device may include: a fourth transistor including a gate receiving a signal at the second frequency, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to the first terminal of the emission device.

[0029] In an exemplary embodiment, the first transistor, the second transistor, the fourth transistor, and the fifth transistor are PMOS transistors, and at least one of the third transistor and the sixth transistor is an NMOS transistor.

[0030] In an exemplary embodiment, the second frequency is a fixed frequency, and the first frequency is a variable frequency.

[0031] In an exemplary embodiment, the emission device is an organic light-emitting diode (OLED), and the second frequency corresponds to a non-zero multiple of the first frequency.

[0032] As described above, in the pixel of the OLED display device and the OLED display device according to an exemplary embodiment, the pixel may include: a capacitor; a first transistor; a second transistor having a gate receiving a gate write signal; a third transistor having a gate receiving a scan signal; a fourth transistor having a gate receiving a gate initialization signal; a fifth transistor having a gate receiving a first emission signal; a sixth transistor having a gate receiving a second emission signal; and an OLED. The scan signal and the gate write signal may be provided at a first frequency, and the first emission signal, the second emission signal, and the gate initialization signal may be provided at a second frequency higher than the first frequency. Accordingly, in the pixel according to the exemplary embodiment, the bias may be applied to the first transistor at the (constant) second frequency, and thus, even if the first frequency (e.g., the driving frequency or the display scan frequency) changes, an image may be displayed at substantially constant brightness with the same gray level. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The illustrative, non - limiting exemplary embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0034] Figure 1 is a circuit diagram illustrating a pixel of an organic light - emitting diode (OLED) display device according to an exemplary embodiment;

[0035] Figure 2 is a diagram illustrating an example of driving characteristics of the first transistor;

[0036] Figure 3 is a diagram illustrating an example of brightness of a display panel driven at different driving frequencies;

[0037] Figure 4 is a timing diagram for describing an example of an operation of a pixel according to an exemplary embodiment;

[0038] Figure 5 is a circuit diagram for describing an example of an operation of a pixel during a gate and anode initialization period;

[0039] Figure 6 is a circuit diagram for describing an example of an operation of a pixel during a data write period;

[0040] Figure 7 is a circuit diagram for describing an example of an operation of a pixel during a first bias period or a second bias period;

[0041] Figure 8 is a circuit diagram for describing an example of an operation of a pixel during a first emission period or a second emission period;

[0042] Figure 9A circuit diagram for describing an example of the operation of a pixel during an anode initialization period;

[0043] Figure 10 A timing diagram for describing another example of the operation of a pixel according to an exemplary embodiment;

[0044] Figure 11 A circuit diagram of a pixel of an OLED display device according to an exemplary embodiment;

[0045] Figure 12 A timing diagram for describing an example of the operation of a pixel according to an exemplary embodiment;

[0046] Figure 13 A block diagram of an OLED display device according to an exemplary embodiment;

[0047] Figure 14 A timing diagram for describing an example of input image data provided to an OLED display device according to an exemplary embodiment;

[0048] Figure 15 A diagram for describing an example of a display scanning operation performed at a variable frequency and a self-scanning operation performed at a fixed frequency;

[0049] Figure 16 A timing diagram for describing an example of the operation of an OLED display device in which the driving frequency changes according to an exemplary embodiment; and

[0050] Figure 17 A block diagram of an electronic device including an OLED display device according to an exemplary embodiment. DETAILED DESCRIPTION

[0051] Hereinafter, embodiments of the inventive concept will be explained in detail with reference to the accompanying drawings.

[0052] Figure 1 Illustrating a pixel of an organic light emitting diode (OLED) display device according to an exemplary embodiment, Figure 2 illustrating an example of the driving characteristics of a first transistor, and Figure 3 illustrating an example of the luminance of a display panel driven at different driving frequencies.

[0053] Referring to Figure 1 , a pixel PX according to an exemplary embodiment may include a capacitor CST, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and an organic light emitting diode EL.

[0054] Although the OLED emitting device has been shown and described, it should be understood that alternative embodiments may employ alternative emitting devices instead of and / or in addition to the OLED emitting device, such as, for example, an inorganic light emitting diode emitting device. The exemplary embodiments provided herein are for ease of understanding and are not limited thereto.

[0055] The capacitor CST may store the data voltage transmitted through the second transistor T2 and the first transistor T1 diode-connected by the third transistor T3. For example, the capacitor CST may be referred to as a storage capacitor for storing the data voltage. In an exemplary embodiment, the capacitor CST may include a first electrode coupled to a line of the first power supply voltage ELVDD and a second electrode coupled to the gate node NG.

[0056] The first transistor T1 may generate a driving current based on the voltage of the gate node NG or the voltage of the second electrode of the capacitor CST. For example, the first transistor T1 may be referred to as a driving transistor for generating the driving current. In an exemplary embodiment, the first transistor T1 may include a gate coupled to the gate node NG, a first terminal coupled to the second transistor T2 and the fifth transistor T5, and a second terminal coupled to the third transistor T3 and the sixth transistor T6.

[0057] The second transistor T2 may transmit the data voltage of the data line DL to the first terminal of the first transistor T1 in response to the gate write signal GW. For example, the second transistor T2 may be referred to as a switching transistor for transmitting the data voltage of the data line DL. In an exemplary embodiment, the second transistor T2 may include a gate receiving the gate write signal GW, a first terminal coupled to the data line DL, and a second terminal coupled to the first terminal of the first transistor T1.

[0058] The third transistor T3 may operate as a diode-connected transistor (such as a metal oxide semiconductor field effect transistor (MOSFET) in the saturation region) in response to the scan signal SCAN to diode-connect the first transistor T1. For example, the third transistor T3 may be referred to as a compensation transistor for compensating the threshold voltage of the first transistor T1. In an exemplary embodiment, the third transistor T3 may include a gate receiving the scan signal SCAN, a first terminal coupled to the second terminal of the first transistor T1, and a second terminal coupled to the gate node NG.

[0059] The fourth transistor T4 may apply an initialization voltage VINT to the anode of the organic light-emitting diode EL in response to a gate initialization signal GI. For example, the fourth transistor T4 may be referred to as an initialization transistor for initializing the anode and / or the gate node NG. In an exemplary embodiment, the fourth transistor T4 may include a gate receiving the gate initialization signal GI, a first terminal coupled to a line of the initialization voltage VINT, and a second terminal coupled to the anode of the organic light-emitting diode EL.

[0060] The fifth transistor T5 may connect a line of the first power supply voltage ELVDD to the first terminal of the first transistor T1 in response to a first emission signal EM1. For example, the fifth transistor T5 may be referred to as a first emission transistor for generating a current path from the line of the first power supply voltage ELVDD to the line of the second power supply voltage ELVSS. In an exemplary embodiment, the fifth transistor T5 may include a gate receiving the first emission signal EM1, a first terminal coupled to the line of the first power supply voltage ELVDD, and a second terminal coupled to the first terminal of the first transistor T1.

[0061] The sixth transistor T6 may connect the second terminal of the first transistor T1 to the line of the second power supply voltage ELVSS in response to a second emission signal EM2. For example, the sixth transistor T6 may be referred to as a second emission transistor for generating a current path from the line of the first power supply voltage ELVDD to the line of the second power supply voltage ELVSS. In an exemplary embodiment, the sixth transistor T6 may include: a gate receiving the second emission signal EM2, a first terminal coupled to the second terminal of the first transistor T1, and a second terminal coupled to the anode of the organic light-emitting diode EL.

[0062] When the fifth transistor T5 and the sixth transistor T6 are turned on, the organic light-emitting diode EL may emit light based on the driving current generated by the first transistor T1. In an exemplary embodiment, the organic light-emitting diode EL may include an anode coupled to the second terminal of the sixth transistor T6 and a cathode coupled to the line of the second power supply voltage ELVSS.

[0063] In an OLED display device that supports a variable frame mode (e.g., FreeSync mode, G-Sync mode, Q-Sync mode, etc.) in which input image data is provided at a variable input frame frequency (or variable frame rate), the driving frequency of a display panel including a plurality of pixels PX or the display scanning frequency (or display refresh rate) at which data voltages are written to the plurality of pixels PX can be changed according to the variable input frame frequency, and the time length of each frame period can be changed according to the driving frequency (or display scanning frequency). When the driving frequency of the display panel is changed, even if the input image data represents the same gray level, as the time length of each frame period increases, the luminance of the pixel PX or the display panel (especially at high gray levels) may decrease due to the leakage current of the first transistor T1 to the sixth transistor T6 of the pixel PX, or specifically, due to the leakage current of the third transistor T3 and the sixth transistor T6 directly or indirectly connected to the capacitor CST. For example, as illustrated in Figure 3 if the driving frequency of the display panel is changed from approximately 120 Hz to approximately 60 Hz, the time length of each frame period can be doubled. In this case, even if the input image data represents the same gray level of 255 (255G), there may be a luminance difference 230 between the luminance 210 of the display panel driven at approximately 120 Hz and the luminance 220 of the display panel driven at approximately 60 Hz. That is, compared with the luminance 210 of the display panel driven at approximately 120 Hz, the luminance 220 of the display panel driven at approximately 60 Hz in which the time length of each frame period is increased can be reduced.

[0064] However, in the pixel PX of an OLED display device according to an exemplary embodiment as illustrated in Figure 1 the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 can be implemented using P-type metal oxide semiconductor (PMOS) transistors, and the third transistor T3 and the sixth transistor T6 can be implemented using N-type metal oxide semiconductor (NMOS) transistors having relatively low leakage current. In this case, since the third transistor T3 and the sixth transistor T6 directly or indirectly connected to the capacitor CST are implemented using NMOS transistors, the leakage current from the capacitor CST through the third transistor T3 and the sixth transistor T6 can be reduced. Therefore, even if the driving frequency or the display scanning frequency of the display panel is changed, the pixel PX or the display panel can display an image with substantially constant luminance at the same gray level. Therefore, the pixel PX according to the exemplary embodiment can be applied to an OLED display device that supports a variable frame mode in which the driving frequency or the display scanning frequency of the display panel is changed.

[0065] However, even if the third transistor T3 and the sixth transistor T6 are implemented using NMOS transistors, when the driving frequency of the display panel changes, the driving characteristics of the first transistor T1 (i.e., the driving transistor) may also change. Therefore, as the time length of each frame period increases, the luminance of the pixel PX or the display panel (especially at low gray levels) may increase at the same gray level. For example, as Figure 2 illustrated in Figure 3 , when performing a display scanning operation of writing a data voltage to the pixel PX in each frame period, a bias (e.g., a turn-on bias) may be applied to the first transistor T1, and the first transistor T1 may have a first driving characteristic 110 of a drain-source current IDS according to a gate-source voltage VGS initialized by the bias. After that, until the bias is applied to the first transistor T1 again in the next frame period, the driving characteristics of the first transistor T1 may gradually change from the first driving characteristic 110 to a second driving characteristic 130. Due to the change in the driving characteristics of the first transistor T1, the luminance of the pixel PX or the display panel may change according to the driving frequency of the display panel. For example, as

[0066] illustrated in

[0067] , even if the input image data represents the same 11 gray level 11G, the luminance 260 of a display panel driven at approximately 120 Hz and the luminance 270 of a display panel driven at approximately 60 Hz may have a luminance difference 280. That is, compared with the luminance 260 of a display panel driven at approximately 120 Hz, the luminance 270 of a display panel driven at approximately 60 Hz, in which the time length of each frame period is increased, may be increased. It should be understood that this is contrary to the effect for the higher gray level 255G described previously, and compared with the luminance 210 of a display panel driven at approximately 120 Hz, the luminance 220 of a display panel driven at approximately 60 Hz may be decreased rather than increased.

[0066] However, in the OLED display device according to the exemplary embodiment, in each frame period, a display scanning operation of writing a data voltage to a plurality of pixels PX may be performed once, and a self-scanning operation of applying a bias to the first transistor T1 of the plurality of pixels PX may be performed two or more times. In the exemplary embodiment, in each frame period, a display scanning operation and a self-scanning operation may be performed substantially simultaneously, and then a self-scanning operation may be additionally performed one or more times. For example, when the display scanning operation and the self-scanning operation are performed substantially simultaneously, the gate node NG and the anode of the organic light-emitting diode EL may be initialized, the data voltage may be written to the capacitor CST, and a bias may be applied to the first transistor T1. Further, when the self-scanning operation is additionally performed, the anode of the organic light-emitting diode EL may be initialized, and a bias may be applied to the first transistor T1.

[0067] To perform one display scan operation and two or more self-scan operations, the scan signal SCAN and the gate write signal GW may be provided to each pixel PX at a first frequency FF1, and the first emission signal EM1, the second emission signal EM2, and the gate initialization signal GI may be provided to each pixel PX at a second frequency FF2 higher than the first frequency FF1. For example, the first emission signal EM1, the second emission signal EM2, the gate initialization signal GI, the scan signal SCAN, and the gate write signal GW may be provided to each pixel PX such that the display scan operation and the self-scan operation can be performed substantially simultaneously, and then, the first emission signal EM1, the second emission signal EM2, and the gate initialization signal GI may be provided to each pixel PX such that the self-scan operation can be additionally performed. Therefore, the self-scan operation can be performed at a second frequency FF2 higher than the first frequency FF1 which is the frequency of the display scan operation or the display scan frequency.

[0068] In an exemplary embodiment, the first frequency FF1 may be a variable frequency, and the second frequency FF2 may be a fixed frequency. Therefore, the first frequency FF1 can be changed according to the variable input frame frequency, but even if the variable input frame frequency is changed, the second frequency FF2 may be substantially constant. Thus, since the second frequency FF2 which is the frequency of the self-scan operation or the self-scan frequency is substantially constant even if the first frequency FF1 which is the frequency of the display scan operation or the display scan frequency is changed, the bias can be applied to the first transistor T1 of each pixel PX at the substantially constant second frequency FF2, and thus, the first transistor T1 of each pixel PX can have substantially constant driving characteristics at any driving frequency.

[0069] In an exemplary embodiment, the second frequency FF2 may correspond to twice the maximum frequency of the variable input frame frequency, and the first frequency FF1 may be determined as the second frequency FF2 divided by N, where N is an integer greater than 1 and less than or equal to the maximum frequency. For example, in the case where the variable input frame frequency is in the range from about 1 Hz to about 120 Hz, the second frequency FF2 may be determined to be about 240 Hz which is twice the maximum frequency of about 120 Hz. Further, the first frequency FF1 may be determined corresponding to the variable input frame frequency among the values calculated by dividing the second frequency FF2 by N (e.g., about 120 Hz (when N is 2), about 80 Hz (when N is 3), about 60 Hz (when N is 4), …, about 1 Hz (when N is 240), etc.) in the current frame period.

[0070] As described above, in the pixel PX according to the exemplary embodiment, since the third transistor T3 and the sixth transistor T6 directly or indirectly connected to the capacitor CST are implemented using NMOS transistors, the leakage current from the capacitor CST through the third transistor T3 and the sixth transistor T6 can be reduced. Further, in the OLED display device including the pixel PX according to the exemplary embodiment, the frequency of the self-scanning operation of the first transistor T1 to which the bias is applied to each pixel PX or the second frequency FF2 may be a fixed frequency higher than the first frequency FF1. Therefore, even if the driving frequency or the display scanning frequency of the display panel changes, the pixel PX and the OLED display device according to the exemplary embodiment can display an image having a substantially constant brightness at the same gray level.

[0071] In an alternative embodiment, the first transistor to the fifth transistor T1, T2, T3', T4, and T5 may be implemented using PMOS transistors, and the sixth transistor T6 may be implemented using an NMOS transistor having a relatively low leakage current. In this case, since the sixth transistor T6 indirectly connected to the capacitor CST is implemented using an NMOS transistor, the leakage current from the capacitor CST through the sixth transistor T6 can be reduced.

[0072] Figure 4 An example of the operation of a pixel according to an exemplary embodiment is illustrated. Figure 5 An example of the operation of a pixel during the gate and anode initialization periods is illustrated. Figure 6 An example of the operation of a pixel during the data write period is illustrated. Figure 7 An example of the operation of a pixel during the first bias period or the second bias period is illustrated. Figure 8 An example of the operation of a pixel during the first emission period or the second emission period is illustrated. Figure 9 An example of the operation of a pixel during the anode initialization period is illustrated, and Figure 10 Another example of the operation of a pixel according to an exemplary embodiment is illustrated.

[0073] Referring to Figure 1 and Figure 4 , the frame period of the OLED display device including the pixel PX according to the exemplary embodiment may include a gate and anode initialization period GAIP, a data write period DWP, a first bias period BP1, a first emission period EP1, at least one anode initialization period AIP, at least one second bias period BP2, and at least one second emission period EP2. As Figure 4As illustrated, when the first frequency FF1, which is the driving frequency or the display scanning frequency, is approximately 120 Hz and the second frequency FF2, which is the self-scanning frequency, is approximately 240 Hz, the frame period FP may include an anode initialization period AIP, a second bias period BP2, and a second emission period EP2. Further, during the gate and anode initialization period GAIP, the data write period DWP, and the first bias period BP1, the operation of the pixel PX may correspond to the display scanning operation and the self-scanning operation that are basically simultaneously executed, and during the anode initialization period AIP and the second bias period BP2, the operation of the pixel PX may correspond to the self-scanning operation additionally executed.

[0074] During the gate and anode initialization period GAIP, the gate node NG and the anode of the organic light-emitting diode EL may be initialized. As Figure 4 illustrated, during the gate and anode initialization period GAIP, the first emission signal EM1 may have a cut-off level, the second emission signal EM2 may have a conduction level, the gate initialization signal GI may have a conduction level, the scan signal SCAN may have a conduction level, and the gate write signal GW may have a cut-off level. As Figure 4 illustrated, at the start time point of the gate and anode initialization period GAIP, the first emission signal EM1, the scan signal SCAN, and the gate initialization signal GI may be respectively changed to the cut-off level, the conduction level, and the conduction level basically simultaneously. However, the time points at which the first emission signal EM1, the scan signal SCAN, and the gate initialization signal GI change may not be limited thereto. For example, Figure 4 different from that illustrated, the first emission signal EM1 may be changed to the cut-off level, then the scan signal SCAN may be changed to the conduction level, and then the gate initialization signal GI may be changed to the conduction level. In an exemplary embodiment, the time length of the gate and anode initialization period GAIP may correspond to but not be limited to one horizontal time (1H time). Further, in an exemplary embodiment, one horizontal time of the OLED display device may be determined based on the maximum frequency of the variable input frame frequency.

[0075] In an exemplary embodiment, as Figure 1 and Figure 4As shown in the figure, the first emission signal EM1, the gate initialization signal GI, and the gate write signal GW may be low-level active signals having a low level as the conduction level, and the second emission signal EM2 and the scan signal SCAN may be high-level active signals having a high level as the conduction level. For example, the high level of the first emission signal EM1, the second emission signal EM2, the gate initialization signal GI, the scan signal SCAN, and the gate write signal GW may be, but are not limited to, approximately 7V, and the low level of the first emission signal EM1, the second emission signal EM2, the gate initialization signal GI, the scan signal SCAN, and the gate write signal GW may be, but are not limited to, approximately -8V.

[0076] As Figure 5 As shown in the figure, during the gate and anode initialization period GAIP, the fifth transistor T5 may be turned off in response to the first emission signal EM1 having a cut-off level, the sixth transistor T6 may be turned on in response to the second emission signal EM2 having a conduction level, the fourth transistor T4 may be turned on in response to the gate initialization signal GI having a conduction level, the third transistor T3 may be turned on in response to the scan signal SCAN having a conduction level, and the second transistor T2 may be turned off in response to the gate write signal GW having a cut-off level. Therefore, during the gate and anode initialization period GAIP, the initialization voltage VINT may be applied to the anode of the organic light-emitting diode EL through the fourth transistor T4, and thus, the voltage of the anode of the organic light-emitting diode EL or the parasitic capacitor of the organic light-emitting diode EL may be initialized. Further, the initialization voltage VINT may be applied to the gate node NG through the fourth transistor T4, the sixth transistor T6, and the third transistor T3, and thus, the voltage of the gate node NG or the capacitor CST may be initialized.

[0077] During the data write period DWP, the data voltage of the data line DL may be written into the capacitor CST. As Figure 4 As shown in the figure, during the data write period DWP, the first emission signal EM1 may have a cut-off level, the second emission signal EM2 may have a cut-off level, the gate initialization signal GI may have a cut-off level, the scan signal SCAN may have a conduction level, and the gate write signal GW may have a conduction level. As Figure 4 As shown in the figure, at the start time point of the data write period DWP, the gate initialization signal GI, the second emission signal EM2, and the gate write signal GW may be changed to the cut-off level, the cut-off level, and the conduction level, respectively, substantially simultaneously, but the time points at which the gate initialization signal GI, the second emission signal EM2, and the gate write signal GW change are not limited thereto. For example, Figure 4Different from that illustrated, the gate initialization signal GI may be changed to a cut-off level, then the second emission signal EM2 may be changed to a cut-off level, and then the gate write signal GW may be changed to a conduction level. In an exemplary embodiment, the time length of the data write period DWP may correspond to but not be limited to one horizontal time (1H time).

[0078] As Figure 6 As illustrated, during the data write period DWP, the fifth transistor T5 may be cut off in response to the first emission signal EM1 having a cut-off level, the sixth transistor T6 may be cut off in response to the second emission signal EM2 having a cut-off level, the fourth transistor T4 may be cut off in response to the gate initialization signal GI having a cut-off level, the third transistor T3 may be turned on in response to the scan signal SCAN having a conduction level, and the second transistor T2 may be turned on in response to the gate write signal GW having a conduction level. Therefore, during the data write period DWP, the third transistor T3 may diode-connect the first transistor T1, and the data voltage VDAT may be applied to the gate node NG or the second electrode of the capacitor CST through the second transistor T2 and the diode-connected first transistor T1. Since the data voltage VDAT is transmitted through the diode-connected first transistor T1, the second electrode of the capacitor CST or the gate node NG may have a voltage VDAT - VTH obtained by subtracting the threshold voltage VTH of the first transistor T1 from the data voltage VDAT.

[0079] During the first bias period BP1, a bias (e.g., conduction bias) may be applied to the first transistor T1. As Figure 4 As illustrated, during the first bias period BP1, the first emission signal EM1 may have a conduction level, the second emission signal EM2 may have a cut-off level, the gate initialization signal GI may have a cut-off level, the scan signal SCAN may have a cut-off level, and the gate write signal GW may have a cut-off level. As Figure 4 As illustrated, at the start time point of the first bias period BP1, the gate write signal GW, the scan signal SCAN, and the first emission signal EM1 may be respectively changed to a cut-off level, a cut-off level, and a conduction level substantially simultaneously. However, the time points at which the gate write signal GW, the scan signal SCAN, and the first emission signal EM1 change are not limited thereto. For example, Figure 4 Different from that illustrated, the gate write signal GW may be changed to a cut-off level, then the scan signal SCAN may be changed to a cut-off level, and then the first emission signal EM1 may be changed to a conduction level. In an exemplary embodiment, the time length of the first bias period BP1 may be in the range of but not limited to from two horizontal times (2H time) to eight horizontal times (8H time).

[0080] AsFigure 7 As illustrated, during the first bias period BP1, the fifth transistor T5 can be turned on in response to a first emission signal EM1 having a conductive level, the sixth transistor T6 can be turned off in response to a second emission signal EM2 having a cut-off level, the fourth transistor T4 can be turned off in response to a gate initialization signal GI having a cut-off level, the third transistor T3 can be turned off in response to a scan signal SCAN having a cut-off level, and the second transistor T2 can be turned off in response to a gate write signal GW having a cut-off level. Therefore, during the first bias period BP1, the first power supply voltage ELVDD can be applied to the first terminal (e.g., source) of the first transistor T1 through the fifth transistor T5. Thus, since the voltage of the gate node NG or the voltage VDAT - VTH obtained by subtracting the threshold voltage VTH from the data voltage VDAT is applied to the gate of the first transistor T1, and the first power supply voltage ELVDD is applied to the first terminal (e.g., source) of the first transistor T1, a bias corresponding to the on-state or an on-bias using the first power supply voltage ELVDD can be applied to the first transistor T1.

[0081] During the first emission period EP1, the organic light-emitting diode EL can emit light. As Figure 4 illustrated, during the first emission period EP1, the first emission signal EM1 can have a conductive level, the second emission signal EM2 can have a conductive level, the gate initialization signal GI can have a cut-off level, the scan signal SCAN can have a cut-off level, and the gate write signal GW can have a cut-off level.

[0082] As Figure 8 illustrated, during the first emission period EP1, the fifth transistor T5 can be turned on in response to a first emission signal EM1 having a conductive level, the sixth transistor T6 can be turned on in response to a second emission signal EM2 having a conductive level, the fourth transistor T4 can be turned off in response to a gate initialization signal GI having a cut-off level, the third transistor T3 can be turned off in response to a scan signal SCAN having a cut-off level, and the second transistor T2 can be turned off in response to a gate write signal GW having a cut-off level. Therefore, during the first emission period EP1, the first transistor T1 can generate a driving current corresponding to the voltage of the gate node NG or the voltage VDAT - VTH obtained by subtracting the threshold voltage VTH from the data voltage VDAT, the fifth transistor T5 and the sixth transistor T6 can form a current path from the line of the first power supply voltage ELVDD to the line of the second power supply voltage ELVSS, and the driving current generated by the first transistor T1 can be supplied to the organic light-emitting diode EL. Thus, the organic light-emitting diode EL can emit light based on the driving current corresponding to the data voltage VDAT.

[0083] During the anode initialization period AIP, the anode of the organic light emitting diode EL can be initialized. As Figure 4 illustrated, during the anode initialization period AIP, the first emission signal EM1 can have a cut-off level, the second emission signal EM2 can have a conduction level, the gate initialization signal GI can have a conduction level, the scan signal SCAN can have a cut-off level, and the gate write signal GW can have a cut-off level. During the first bias period BP1, the first emission period EP1, the anode initialization period AIP, the second bias period BP2, and a second emission period EP2, the scan signal SCAN and the gate write signal GW can be maintained at the cut-off level. As Figure 4 illustrated, at the start time point of the anode initialization period AIP, the first emission signal EM1 and the gate initialization signal GI can be changed to the cut-off level and the conduction level respectively substantially simultaneously, however, the time points at which the first emission signal EM1 and the gate initialization signal GI are changed can be not limited thereto. For example, different from Figure 4 illustrated, the first emission signal EM1 can be changed to the cut-off level, and then the gate initialization signal GI can be changed to the conduction level.

[0084] As Figure 9 illustrated, during the anode initialization period AIP, the fifth transistor T5 can be turned off in response to the first emission signal EM1 having a cut-off level, the sixth transistor T6 can be turned on in response to the second emission signal EM2 having a conduction level, the fourth transistor T4 can be turned on in response to the gate initialization signal GI having a conduction level, the third transistor T3 can be turned off in response to the scan signal SCAN having a cut-off level, and the second transistor T2 can be turned off in response to the gate write signal GW having a cut-off level. Therefore, during the anode initialization period AIP, the initialization voltage VINT can be applied to the anode of the organic light emitting diode EL through the fourth transistor T4, and thus, the voltage of the anode of the organic light emitting diode EL or the parasitic capacitor of the organic light emitting diode EL can be initialized.

[0085] During the second bias period BP2, a bias (e.g., a turn-on bias) can be applied to the first transistor T1. In an exemplary embodiment, the time length of the second bias period BP2 can be in the range of but not limited to from two horizontal times (2H times) to eight horizontal times (8H times). The first emission signal EM1, the second emission signal EM2, the gate initialization signal GI, the scan signal SCAN, and the gate write signal GW in the second bias period BP2 can be substantially the same as the first emission signal EM1, the second emission signal EM2, the gate initialization signal GI, the scan signal SCAN, and the gate write signal GW in the first bias period BP1, and the operation of the pixel PX in the second bias period BP2 can be substantially the same as the operation of the pixel PX in the first bias period BP1. That is, the voltage of the gate node NG or the voltage VDAT - VTH obtained by subtracting the threshold voltage VTH from the data voltage VDAT can be applied to the gate of the first transistor T1, and the first power supply voltage ELVDD can be applied to the first terminal (e.g., the source) of the first transistor T1, and thus, a bias corresponding to the on state or a turn-on bias using the first power supply voltage ELVDD can be applied to the first transistor T1. Therefore, even if the first frequency FF1, which is the driving frequency or the display scan frequency, changes, the bias can be applied to the first transistor T1 at the second frequency FF2, which is the self-scan frequency.

[0086] During the second emission period EP2, the organic light-emitting diode EL can emit light. The operation of the pixel PX in the second emission period EP2 can be substantially the same as the operation of the pixel PX in the first emission period EP1. That is, during the second emission period EP2, the organic light-emitting diode EL can emit light based on the driving current corresponding to the data voltage VDAT.

[0087] In an exemplary embodiment, the second frequency FF2 can be determined as a fixed frequency (e.g., approximately 240 Hz) corresponding to twice the maximum frequency of the variable input frame frequency (e.g., approximately 120 Hz), and the first frequency FF1 can be determined as the second frequency FF2 divided by N according to the variable input frame frequency in each frame period, where N is an integer greater than 1 and less than or equal to the maximum frequency. Figure 4 An example where N is 2 is illustrated, or an example where the first frequency FF1 is determined as approximately 120 Hz by dividing the second frequency FF2 of approximately 240 Hz by 2. Further, Figure 10 An example where N is 3 is illustrated, or an example where the first frequency FF1 is determined as approximately 80 Hz by dividing the second frequency FF2 of approximately 240 Hz by 3. As Figure 10As illustrated, in the case where the first frequency FF1, which is a driving frequency or a display scanning frequency, is approximately 80 Hz and the second frequency FF2, which is a self-scanning frequency, is approximately 240 Hz, the frame period FP may include two anode initialization periods AIP, two second bias periods BP2, and two second emission periods EP2. As Figure 4 and Figure 10 illustrated, even if the first frequency FF1, which is a driving frequency or a display scanning frequency, changes, the bias may be applied to the first transistor T1 of each pixel PX at a fixed or constant second frequency FF2, and the OLED display device may display an image having a substantially constant luminance at the same gray level. The fixed or constant second frequency FF2 is the self-scanning frequency in the first bias period BP1 and the second bias period BP2.

[0088] Figure 11 illustrates a pixel of an OLED display device according to an exemplary embodiment, and Figure 12 illustrates an example of the operation of a pixel according to an exemplary embodiment.

[0089] Referring to Figure 11 and Figure 12 , a pixel PX' according to an exemplary embodiment may include a capacitor CST, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6', and an organic light-emitting diode EL. Except that the sixth transistor T6' is implemented using a PMOS transistor, Figure 11 the pixel PX' of Figure 1 may have substantially the same configuration as the pixel PX of Figure 12 Further, except that the second emission signal EM2 is a low-level effective signal having a low level as a conduction level, Figure 4 the signals EM1, GI, SCAN, and GW provided to the pixel PX' illustrated in

[0090] As Figure 11As illustrated, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6' may be implemented using PMOS transistors, and the third transistor T3 may be implemented using an NMOS transistor having a relatively low leakage current. In this case, since the third transistor T3 directly connected to the capacitor CST is implemented using an NMOS transistor, the leakage current from the capacitor CST through the third transistor T3 can be reduced. Further, in the OLED display device including the pixel PX' according to the exemplary embodiment, the frequency of the self-scanning operation of the first transistor T1 to which a bias is applied to each pixel PX' or the second frequency FF2 may be a fixed frequency higher than the first frequency FF1. Therefore, even if the driving frequency or the display scanning frequency of the display panel changes, the pixel PX' and the OLED display device according to the exemplary embodiment can display an image having a substantially constant luminance at the same gray level.

[0091] Figure 13 Illustrates an OLED display device according to an exemplary embodiment, Figure 14 Illustrates an example of input image data provided to the OLED display device according to an exemplary embodiment, Figure 15 Illustrates an example of a display scanning operation performed at a variable frequency and a self-scanning operation performed at a fixed frequency, and Figure 16 Illustrates an example of the operation of an OLED display device in which the driving frequency changes according to an exemplary embodiment.

[0092] Referring to Figure 13 , the OLED display device 300 according to the exemplary embodiment may include a display panel 310, a data driver 320, a scan driver 330, an emission driver 340, and a controller 350.

[0093] The display panel 310 may include a plurality of pixels PX. Each pixel PX of the display panel 310 may be Figure 1 the pixel PX, Figure 11 the pixel PX' or any other suitable pixel.

[0094] The data driver 320 may provide a data voltage VDAT to a plurality of pixels PX based on output image data ODAT and a data control signal DCTRL received from the controller 350. In an exemplary embodiment, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a horizontal start signal, and a load signal. The data driver 320 may receive frame data as the output image data ODAT at a first frequency FF1 that is the driving frequency of the display panel 310 or at a display scan frequency from the controller 350. In an exemplary embodiment, the data driver 320 and the controller 350 may be implemented using a single integrated circuit, and the single integrated circuit may be referred to as a timing controller embedded data driver (TED). In other exemplary embodiments, the data driver 320 and the controller 350 may be implemented using separate integrated circuits.

[0095] The scan driver 330 may provide a scan signal SCAN, a gate write signal GW, and a gate initialization signal GI to a plurality of pixels PX based on a scan control signal received from the controller 350. In an exemplary embodiment, the scan control signal may include a scan start pulse SCAN_SP, a gate write start pulse GW_SP, and a gate initialization start pulse GI_SP. The scan driver 330 may sequentially provide the scan signal SCAN to the plurality of pixels PX row by row in response to the scan start pulse SCAN_SP, may sequentially provide the gate write signal GW to the plurality of pixels PX row by row in response to the gate write start pulse GW_SP, and may sequentially provide the gate initialization signal GI to the plurality of pixels PX row by row in response to the gate initialization start pulse GI_SP. In an exemplary embodiment, the scan driver 330 may receive the scan start pulse SCAN_SP and the gate write start pulse GW_SP at the first frequency FF1, and may receive the gate initialization start pulse GI_SP at a second frequency FF2 that is the self-scan frequency. Further, in an exemplary embodiment, the scan control signal may further include, but is not limited to, a scan clock signal, a gate write clock signal, and a gate initialization clock signal. In an exemplary embodiment, the scan driver 330 may be integrated or formed in a peripheral portion of the display panel 310. In other exemplary embodiments, the scan driver 330 may be implemented using one or more integrated circuits.

[0096] The emission driver 340 may provide a first emission signal EM1 and a second emission signal EM2 to a plurality of pixels PX based on an emission control signal received from the controller 350. The emission control signal may include a first emission start pulse EM1_SP and a second emission start pulse EM2_SP. The emission driver 340 may sequentially provide the first emission signal EM1 to the plurality of pixels PX row by row in response to the first emission start pulse EM1_SP, and may sequentially provide the second emission signal EM2 to the plurality of pixels PX row by row in response to the second emission start pulse EM2_SP. In an exemplary embodiment, the emission driver 340 may receive the first emission start pulse EM1_SP and the second emission start pulse EM2_SP at a second frequency FF2. Further, in an exemplary embodiment, the emission control signal may further include, but is not limited to, a first emission clock signal and a second emission clock signal. In an exemplary embodiment, the emission driver 340 may be integrated or formed in a peripheral portion of the display panel 310. In other exemplary embodiments, the emission driver 340 may be implemented using one or more integrated circuits.

[0097] The controller 350 (e.g., a timing controller) may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit (GPU), an application processor (AP), or a graphics card). In an exemplary embodiment, the input image data IDAT may be RGB image data including red image data, green image data, and blue image data. In an exemplary embodiment, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a main clock signal, etc. The controller 350 may generate output image data ODAT, a data control signal DCTRL, a scan control signal, and an emission control signal based on the input image data IDAT and the control signal CTRL. The controller 350 may control the operation of the data driver 320 by providing the output image data ODAT and the data control signal DCTRL to the data driver 320, may control the operation of the scan driver 330 by providing the scan control signal to the scan driver 330, and may control the operation of the emission driver 340 by providing the emission control signal to the emission driver 340.

[0098] According to an exemplary embodiment, the OLED display device 300 includes: a display panel 310 having a plurality of pixels PX; a scan driver 330 configured to provide a scan signal to the plurality of pixels; and an emission driver 340 configured to provide an emission signal to the plurality of pixels; wherein each of the plurality of pixels includes: a capacitor CST including a first electrode and a second electrode of a line coupled to a first power supply voltage ELVDD; a first transistor T1 including a first terminal, a second terminal, and a gate coupled to the second electrode of the capacitor CST; a second transistor T2 including a gate coupled to the scan driver, a first terminal coupled to a data line DL, and a second terminal coupled to the first terminal of the first transistor T1; a third transistor T3 including a gate coupled to the scan driver, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the gate of the first transistor; a fifth transistor T5 including a gate coupled to the emission driver, a first terminal of a line coupled to the first power supply voltage ELVDD, and a second terminal coupled to the first terminal of the first transistor; and a sixth transistor T6 including a gate coupled to the emission driver, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the first terminal of the emission device, wherein the scan driver provides a signal to the plurality of pixels PX at a first frequency FF1; wherein the emission driver provides a signal to the plurality of pixels PX at a second frequency FF2 greater than the first frequency FF1.

[0099] In an exemplary embodiment, the OLED display device may include: a fourth transistor T4 including a gate receiving a signal at a second frequency FF2, a first terminal of a line coupled to an initialization voltage Vint, and a second terminal coupled to the first terminal of the emission device. The first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 may be PMOS transistors, and at least one of the third transistor T3 and the sixth transistor T6 may be an NMOS transistor. The second frequency may be a fixed frequency, and the first frequency may be a variable frequency. The emission device may be an OLED, and the second frequency may correspond to a non-zero multiple of the first frequency.

[0100] A controller 350 of the OLED display device 300 according to an exemplary embodiment may receive input image data IDAT from a host processor at a variable input frame frequency VIFF in a variable frame mode (e.g., FreeSync mode, G-Sync mode, Q-Sync mode, etc.). For example, as Figure 14As illustrated, the periods of each of the renderings 410, 420, and 430 of the host processor may not be constant (especially in the case of rendering game image data), and in the variable frame mode, the host processor may provide the input image data IDAT or the frame data FD1, FD2, FD3, and FD4 to the OLED display device 300 synchronously with these irregular periods of the renderings 410, 420, and 430, respectively. For example, in the variable frame mode, each frame period FP1, FP2, and FP3 may include constant active periods AP1, AP2, and AP3 having a constant time length, and the host processor may provide the frame data FD1, FD2, and FD3 to the OLED display device 300 at a variable input frame frequency VIFF by changing the time lengths of the variable blank periods BP1, BP2, and BP3 of the frame periods FP1, FP2, and FP3. For example, the variable input frame frequency VIFF may change in the range from about 1 Hz to about 120 Hz in each frame period FP1, FP2, and FP3.

[0101] In an exemplary embodiment, the second frequency FF2 as the self-scan frequency may be a fixed frequency (e.g., about 240 Hz) corresponding to twice the maximum frequency (e.g., about 120 Hz) of the variable input frame frequency VIFF. Further, the first frequency FF1 as the driving frequency or the display scan frequency of the display panel 310 may be determined as the second frequency FF2 divided by N according to the variable input frame frequency VIFF in each frame period, where N is an integer greater than 1 and less than or equal to the maximum frequency. Thus, the OLED display device 300 according to the exemplary embodiment may perform a display scan operation that writes a data voltage VDAT corresponding to the output image data ODAT to a plurality of pixels PX at the first frequency FF1 as a variable frequency, and may perform a self-scan operation that applies a bias to the driving transistors of the plurality of pixels PX at the second frequency FF2 as a fixed frequency. In the exemplary embodiment, in each frame period, the OLED display device 300 may perform a display scan operation and a self-scan operation basically simultaneously once, and then may additionally perform one or more self-scan operations.

[0102] For example, as Figure 15 illustrated, in the case where the maximum frequency of the variable input frame frequency VIFF is about 120 Hz, even if the variable input frame frequency VIFF changes, the OLED display device 300 may perform a self-scan operation at a fixed second frequency FF2 of about 240 Hz. Further, in the case where the variable input frame frequency VIFF is about 120 Hz, as Figure 15As shown in 510, the OLED display device 300 may perform a display scanning operation at a first frequency FF1 of approximately 120 Hz. Accordingly, in each frame period FP, one display scanning operation may be performed, and two self-scanning operations may be performed. Further, in the case where the variable input frame frequency VIFF is approximately 80 Hz, as Figure 15 As shown in 520, the OLED display device 300 may perform a display scanning operation at a first frequency FF1 of approximately 80 Hz. Accordingly, in each frame period FP, one display scanning operation may be performed, and three self-scanning operations may be performed. Further, in the case where the variable input frame frequency VIFF is approximately 60 Hz, as Figure 15 As shown in 530, the OLED display device 300 may perform a display scanning operation at a first frequency FF1 of approximately 60 Hz. Accordingly, in each frame period FP, one display scanning operation may be performed, and four self-scanning operations may be performed. Further, in the case where the variable input frame frequency VIFF is approximately 48 Hz, as Figure 15 As shown in 540, the OLED display device 300 may perform a display scanning operation at a first frequency FF1 of approximately 48 Hz. Accordingly, in each frame period FP, one display scanning operation may be performed, and five self-scanning operations may be performed. Further, in the case where the variable input frame frequency VIFF is approximately 30 Hz, as Figure 15 As shown in 550, the OLED display device 300 may perform a display scanning operation at a first frequency FF1 of approximately 30 Hz. Accordingly, in each frame period FP, one display scanning operation may be performed, and eight self-scanning operations may be performed. Further, in the case where the variable input frame frequency VIFF is approximately 24 Hz, as Figure 15 As shown in 560, the OLED display device 300 may perform a display scanning operation at a first frequency FF1 of approximately 24 Hz. Accordingly, in each frame period FP, one display scanning operation may be performed, and ten self-scanning operations may be performed.

[0103] To perform a display scan operation at a first frequency FF1 of variable frequency and a self-scan operation at a second frequency FF2, the controller 350 may provide a scan start pulse SCAN_SP and a gate write start pulse GW_SP to the scan driver 330 at the first frequency FF1, may provide a gate initialization start pulse GI_SP to the scan driver 330 at the second frequency FF2, and may provide a first emission start pulse EM1_SP and a second emission start pulse EM2_SP to the emission driver 340 at the second frequency FF2. Further, the time length of each frame period FP may correspond to the first frequency FF1. Thus, in each frame period FP, the controller 350 may provide one scan start pulse SCAN_SP, one gate write start pulse GW_SP, and at least two gate initialization start pulses GI_SP to the scan driver 330, and may provide at least two first emission start pulses EM1_SP and at least two second emission start pulses EM2_SP to the emission driver 340.

[0104] For example, as Figure 16As shown in the figure, when the first frequency FF1 is approximately 120 Hz and the second frequency FF2 is approximately 240 Hz, in each frame period FP, the controller 350 can provide one scan start pulse SCAN_SP, one gate write start pulse GW_SP, and two gate initialization start pulses GI_SP to the scan driver 330, and can provide two first emission start pulses EM1_SP and two second emission start pulses EM2_SP to the emission driver 340. Therefore, in each frame period FP, the scan driver 330 can provide the scan signal SCAN to the plurality of pixels PX at the first frequency FF1 of approximately 120 Hz in response to one scan start pulse SCAN_SP, such that the scan signal SCAN is provided to each pixel PX once, can provide the gate write signal GW to the plurality of pixels PX at the first frequency FF1 of approximately 120 Hz in response to one gate write start pulse GW_SP, such that the gate write signal GW is provided to each pixel PX once, and can provide the gate initialization signal GI to the plurality of pixels PX at the second frequency FF2 of approximately 240 Hz in response to two gate initialization start pulses GI_SP, such that the gate initialization signal GI is provided to each pixel PX twice. For example, the scan driver 330 can sequentially provide the gate initialization signal GI from the first row to the last row of the display panel 310 in response to the current gate initialization start pulse GI_SP, and at the time point when the scan driver 330 provides the gate initialization signal GI to the middle row of the display panel 310 in response to the current gate initialization start pulse GI_SP, the controller 350 can provide the next gate initialization start pulse GI_SP to the scan driver 330. Further, in each frame period FP, the emission driver 340 can provide the first emission signal EM1 to the plurality of pixels PX at the second frequency FF2 of approximately 240 Hz in response to two first emission start pulses EM1_SP, such that the first emission signal EM1 is provided to each pixel PX twice, and can provide the second emission signal EM2 to the plurality of pixels PX at the second frequency FF2 of approximately 240 Hz in response to two second emission start pulses EM2_SP, such that the second emission signal EM2 is provided to each pixel PX twice.For example, the emission driver 340 may sequentially provide a first emission signal EM1 and a second emission signal EM2 from the first row to the last row of the display panel 310 in response to a current first emission start pulse EM1_SP and a current second emission start pulse EM2_SP, and at a time point when the emission driver 340 provides the first emission signal EM1 and the second emission signal EM2 to the middle row of the display panel 310 in response to the current first emission start pulse EM1_SP and the current second emission start pulse EM2_SP, the controller 350 may provide the next first emission start pulse EM1_SP and second emission start pulse EM2_SP to the emission driver 340. Further, the controller 350 may provide frame data FD as output image data ODAT to the data driver 320 at a first frequency FF1 of approximately 120 Hz, such that one frame data FD is provided in each frame period FP. Accordingly, the display scanning operation may be performed at the first frequency FF1 of approximately 120 Hz, and the self-scanning operation may be performed at a second frequency FF2 of approximately 240 Hz.

[0105] Further, as Figure 16As illustrated, when the first frequency FF1 is approximately 60 Hz and the second frequency FF2 is approximately 240 Hz, in each frame period FP, the controller 350 may provide one scan start pulse SCAN_SP, one gate write start pulse GW_SP, and four gate initialization start pulses GI_SP to the scan driver 330, and may provide four first emission start pulses EM1_SP and four second emission start pulses EM2_SP to the emission driver 340. Accordingly, in each frame period FP, the scan driver 330 may provide the scan signal SCAN to the plurality of pixels PX at the first frequency FF1 of approximately 60 Hz in response to one scan start pulse SCAN_SP, such that the scan signal SCAN is provided to each pixel PX once, may provide the gate write signal GW to the plurality of pixels PX at the first frequency FF1 of approximately 60 Hz in response to one gate write start pulse GW_SP, such that the gate write signal GW is provided to each pixel PX once, and may provide the gate initialization signal GI to the plurality of pixels PX at the second frequency FF2 of approximately 240 Hz in response to four gate initialization start pulses GI_SP, such that the gate initialization signal GI is provided to each pixel PX four times. Further, in each frame period FP, the emission driver 340 may provide the first emission signal EM1 to the plurality of pixels PX at the second frequency FF2 of approximately 240 Hz in response to four first emission start pulses EM1_SP, such that the first emission signal EM1 is provided to each pixel PX four times, and may provide the second emission signal EM2 to the plurality of pixels PX at the second frequency FF2 of approximately 240 Hz in response to four second emission start pulses EM2_SP, such that the second emission signal EM2 is provided to each pixel PX four times. Further, the controller 350 may provide the frame data FD as the output image data ODAT to the data driver 320 at the first frequency FF1 of approximately 60 Hz, such that one frame data FD is provided in each frame period FP. Accordingly, the display scan operation may be performed at the first frequency FF1 of approximately 60 Hz, and the self-scan operation may be performed at the second frequency FF2 of approximately 240 Hz.

[0106] As described above, in the OLED display device 300 according to the exemplary embodiment, the self-scan frequency or the second frequency FF2 may be a fixed frequency higher than the first frequency FF1. Accordingly, even when the first frequency FF1, which is the driving frequency or the display scan frequency of the display panel 310, changes, the OLED display device 300 according to the exemplary embodiment may display an image having a substantially constant luminance at the same gray level.

[0107] Although exemplary embodiments have been shown and described in which a higher self-scan frequency is fixed and a potentially lower frame rate of frequency is variable, the embodiments are not limited thereto. For example, the higher self-scan frequency may be the minimum multiple of the variable frame rate to reach or exceed a threshold frequency.

[0108] Figure 17 FIG. illustrates an electronic device including an OLED display device according to an exemplary embodiment.

[0109] Referring to Figure 17 , the electronic device 1100 may include a processor 1110, a storage device 1120, a storage unit 1130, an input / output (I / O) device 1140, a power supply 1150, and an OLED display device 1160. The electronic device 1100 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, etc.

[0110] The processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. The processor 1110 may be coupled to other components via an address bus, a control bus, a data bus, etc. Further, in an exemplary embodiment, the processor 1110 may be further coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0111] The storage device 1120 may store data for operating the electronic device 1100. For example, the storage device 1120 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.), and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.).

[0112] The storage device 1130 can be a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1140 can be an input device such as a keyboard, keypad, mouse, touch screen, etc. and an output device such as a printer, speaker, etc. The power supply 1150 can supply power for operating the electronic device 1100. The OLED display device 1160 can be coupled to other components via a bus or other communication link.

[0113] The OLED display device 1160 can be substantially similar to Figure 13 the OLED display device 300 without limitation. In the OLED display device 1160, each pixel can include: a capacitor; a first transistor; a second transistor including a gate receiving a gate write signal; a third transistor including a gate receiving a scan signal; a fourth transistor including a gate receiving a gate initialization signal; a fifth transistor including a gate receiving a first emission signal; a sixth transistor including a gate receiving a second emission signal; and an OLED. The scan signal and the gate write signal can be provided at a first frequency, and the first emission signal, the second emission signal, and the gate initialization signal can be provided at a second frequency higher than the first frequency. Accordingly, the bias can be applied to the first transistor at the (fixed or constant) second frequency, and thus, even if the first frequency (e.g., the driving frequency or the display scan frequency) changes, the OLED display device 1160 can display an image having a substantially constant brightness at the same gray level.

[0114] The inventive concept can be applied to any OLED display device 1160 supporting a variable frame mode and any electronic device 1100 including the OLED display device 1160. For example, the inventive concept can be applied to a smart phone, a wearable electronic device, a tablet computer, a mobile phone, a television (TV), a digital TV, a three-dimensional (3D) TV, a personal computer (PC), a household appliance, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, etc.

[0115] Although the exemplary embodiments have been described, those of ordinary skill in the relevant art can readily understand that many modifications are possible in the exemplary embodiments without substantially departing from the teachings of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Therefore, it is to be understood that the foregoing is an illustration of the various exemplary embodiments and is not to be construed as a limitation to the particular exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments as well as other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A pixel of a light-emitting display device, the pixel comprising: A capacitor including a first electrode coupled to a line of a first power supply voltage and a second electrode coupled to a gate node; A first transistor including a first terminal, a second terminal, and a gate coupled to the gate node; A second transistor including a gate receiving a gate write signal, a first terminal coupled to a data line, and a second terminal coupled to the first terminal of the first transistor; A third transistor including a gate receiving a scan signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the gate node; A fourth transistor including a gate receiving a gate initialization signal, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to an anode of a light-emitting diode; A fifth transistor including a gate receiving a first emission signal, a first terminal coupled to the line of the first power supply voltage, and a second terminal coupled to the first terminal of the first transistor; A sixth transistor including a gate receiving a second emission signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the light-emitting diode; and The light-emitting diode including the anode and a cathode coupled to a line of a second power supply voltage, Wherein the scan signal and the gate write signal are provided at a first frequency, and the first emission signal, the second emission signal, and the gate initialization signal are provided at a second frequency higher than the first frequency, and Wherein the second frequency is an integer multiple of the first frequency.

2. The pixel according to claim 1, wherein, The first transistor, the second transistor, the fourth transistor, and the fifth transistor are P-type metal oxide semiconductor transistors, and Wherein the third transistor and the sixth transistor are N-type metal oxide semiconductor transistors.

3. The pixel according to claim 1, wherein, The first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are P-type metal oxide semiconductor transistors, and Wherein the third transistor is an N-type metal oxide semiconductor transistor.

4. The pixel according to claim 1, wherein The second frequency is a fixed frequency, and the first frequency is a variable frequency.

5. The pixel according to claim 1, Among them, The light-emitting diode is an organic light-emitting diode, and the light-emitting display device is an organic light-emitting diode display device, Wherein the second frequency corresponds to twice the maximum frequency of a variable input frame frequency of the organic light-emitting diode display device, and Wherein the first frequency corresponds to the second frequency divided by N, where N is an integer greater than 1 and less than or equal to the maximum frequency.

6. The pixel according to claim 1, wherein, The light-emitting diode is an organic light-emitting diode, the light-emitting display device is an organic light-emitting diode display device, and a frame period of the organic light-emitting diode display device includes: A gate and anode initialization period during which the gate node and the anode are initialized; A data write period during which a data voltage of the data line is written into the capacitor; A first bias period in which a bias is applied to the first transistor; A first emission period in which the organic light-emitting diode emits light; An anode initialization period in which the anode is initialized; A second bias period in which the bias is applied to the first transistor; and A second emission period in which the organic light-emitting diode emits light.

7. The pixel according to claim 6, wherein, During the gate and anode initialization periods, the first emission signal has a cut-off level, the second emission signal has a conductive level, the gate initialization signal has the conductive level, the scan signal has the conductive level, the gate write signal has the cut-off level, the third transistor, the fourth transistor, and the sixth transistor are turned on, the initialization voltage is applied to the anode through the fourth transistor, and the initialization voltage is applied to the gate node through the fourth transistor, the sixth transistor, and the third transistor. Wherein, during the data writing period, the first emission signal has the cut-off level, the second emission signal has the cut-off level, the gate initialization signal has the cut-off level, the scan signal has the conductive level, the gate write signal has the conductive level, the second transistor and the third transistor are turned on, the third transistor diode-connected to the first transistor, and the data voltage is applied to the second electrode of the capacitor through the second transistor and the diode-connected first transistor. Wherein, during the first bias period, the first emission signal has the conductive level, the second emission signal has the cut-off level, the gate initialization signal has the cut-off level, the scan signal has the cut-off level, the gate write signal has the cut-off level, the fifth transistor is turned on, and the first power supply voltage is applied to the first terminal of the first transistor through the fifth transistor. Wherein, in each of the first emission period and the second emission period, the first emission signal has the conductive level, the second emission signal has the conductive level, the gate initialization signal has the cut-off level, the scan signal has the cut-off level, the gate write signal has the cut-off level, the fifth transistor and the sixth transistor are turned on, and the drive current generated by the first transistor is provided to the organic light-emitting diode. Wherein, during the anode initialization period, the first emission signal has the cut-off level, the second emission signal has the conductive level, the gate initialization signal has the conductive level, the scan signal has the cut-off level, the gate write signal has the cut-off level, the fourth transistor and the sixth transistor are turned on, and the initialization voltage is applied to the anode through the fourth transistor, and During the second bias period, the first emission signal has the conduction level, the second emission signal has the cut-off level, the gate initialization signal has the cut-off level, the scan signal has the cut-off level, the gate write signal has the cut-off level, the fifth transistor is turned on, and the first power supply voltage is applied to the first terminal of the first transistor through the fifth transistor.

8. An organic light emitting diode display device, comprising: A display panel including a plurality of pixels; A scan driver configured to provide a scan signal, a gate write signal, and a gate initialization signal to the plurality of pixels; An emission driver configured to provide a first emission signal and a second emission signal to the plurality of pixels; And A controller configured to control the scan driver and the emission driver, Wherein each of the plurality of pixels includes: A capacitor including a first electrode coupled to a line of the first power supply voltage and a second electrode coupled to a gate node; A first transistor including a first terminal, a second terminal, and a gate coupled to the gate node; A second transistor including a gate receiving the gate write signal, a first terminal coupled to a data line, and a second terminal coupled to the first terminal of the first transistor; A third transistor including a gate receiving the scan signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the gate node; A fourth transistor including a gate receiving the gate initialization signal, a first terminal coupled to a line of the initialization voltage, and a second terminal coupled to an anode of the organic light emitting diode; A fifth transistor including a gate receiving the first emission signal, a first terminal coupled to the line of the first power supply voltage, and a second terminal coupled to the first terminal of the first transistor; A sixth transistor including a gate receiving the second emission signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the organic light emitting diode; and The organic light emitting diode including the anode and a cathode coupled to a line of the second power supply voltage, wherein the scan driver provides the scan signal and the gate write signal to the plurality of pixels at a first frequency, and provides the gate initialization signal to the plurality of pixels at a second frequency higher than the first frequency, Wherein the emission driver provides the first emission signal and the second emission signal to the plurality of pixels at the second frequency, and Wherein the second frequency is an integer multiple of the first frequency.

9. The organic light emitting diode display device according to claim 8, further comprising: A data driver configured to provide a data voltage to the plurality of pixels; Wherein the controller is further configured to: Control the data driver; Provide a scan start pulse and a gate write start pulse to the scan driver at the first frequency, such that the scan signal and the gate write signal are provided at the first frequency; Provide a gate initialization start pulse to the scan driver at the second frequency, such that the gate initialization signal is provided at the second frequency; and Provide a first emission start pulse and a second emission start pulse to the emission driver at the second frequency, such that the first emission signal and the second emission signal are provided at the second frequency.

10. A display device, comprising: A display panel, the display panel including a plurality of pixels; A scan driver configured to provide a scan signal to the plurality of pixels; And An emission driver configured to provide an emission signal to the plurality of pixels; Wherein each pixel of the plurality of pixels includes: A first transistor, the first transistor including a first terminal, a second terminal, and a gate coupled to a capacitor; A second transistor, the second transistor including a gate coupled to the scan driver, a first terminal coupled to a data line, and a second terminal coupled to the first terminal of the first transistor; A third transistor, the third transistor including a gate coupled to the scan driver, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the gate of the first transistor; A fifth transistor, the fifth transistor including a gate coupled to the emission driver, a first terminal coupled to a line of a first power voltage, and a second terminal coupled to the first terminal of the first transistor; and A sixth transistor, the sixth transistor including a gate coupled to the emission driver, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a first terminal of an emission device, Wherein the scan driver provides the scan signal to the plurality of pixels at a first frequency, Wherein the emission driver provides the emission signal to the plurality of pixels at a second frequency greater than the first frequency, and Wherein the second frequency is an integer multiple of the first frequency.

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