Image sensor and imaging system including the same

Abstract

The present invention relates to an image sensor and to an imaging system comprising the image sensor. In particular, the present invention relates to an X-ray image sensor and an imaging system. The image sensor according to the present invention comprises: a pixel array comprising a plurality of active pixels arranged in a matrix of rows and columns; and a plurality of column lines to which the outputs of pixels in the same column are coupled for the purpose of outputting pixel signals. The image sensor further comprises a readout circuit system comprising a plurality of readout units, each readout unit being configured for reading out a corresponding column line via an input node of the readout unit. The image sensor is characterized in that the image sensor further comprises a capacitive unit, such as a capacitor, for capacitively coupling each input node to its corresponding column line.

Description

Technical Field

[0001] The present invention relates to an image sensor and an imaging system comprising the image sensor. In particular, the present invention relates to an X-ray image sensor and an imaging system. Background Art

[0002] Unless otherwise stated, an image sensor according to the present invention comprises an image sensor configured for capturing electromagnetic radiation. Specifically, this radiation may be in the form of visible light or it may be in the form of X-rays.

[0003] When an image sensor is configured to sense X-rays, it may include a photosensitive element, such as a photodiode, configured to absorb incoming X-ray photons and generate a photocurrent. This type of conversion is known as direct conversion. Other image sensors may include a scintillator layer that converts incoming X-ray photons into visible light photons. These latter photons may be absorbed by a photosensitive element, which in turn generates a photocurrent. This type of conversion is known as indirect conversion. The present invention relates to both types of conversion.

[0004] An image sensor typically includes a pixel array. This array comprises a plurality of pixels arranged in a matrix of rows and columns. The image sensor typically further includes a plurality of column lines, to which the outputs of pixels in the same column are coupled for outputting pixel signals. The image sensor further includes readout circuitry comprising a plurality of readout units, each configured to read out a corresponding column line via an input node of the readout unit.

[0005] exist Figure 1 An example of a known image sensor 1 is shown in . Here, only a single pixel 2 of the matrix is ​​shown for illustrative purposes. Pixel 2 is a passive pixel comprising a photodiode PD coupled between ground and the source terminal of a select FET Ts, the gate of which is connected to a row select line rs. Instead of fixing the anode at ground potential, a different potential, for example -5 V, can be used. The drain terminal of the select FET Ts is connected to a column line cl. A certain parasitic capacitance is associated with this line. Figure 1 In FIG, this parasitic capacitance is represented by capacitor Cp. Typically, each row of the pixel matrix is ​​connected to a corresponding row select line, and each column is connected to a corresponding column line. For the purpose of driving the row select lines, the image sensor 1 includes a row controller (not shown) that ensures that two pixels in the same column are not inadvertently connected to the same column line at the same time.

[0006] The image sensor 1 further comprises a readout circuit system. This circuit system comprises a plurality of readout units 3, typically one unit per column line. Figure 1In FIG. 3 , a single readout unit 3 is shown comprising a charge amplifier 31 , a correlated double sampling 'CDS' unit 32 and an analog to digital converter 'ADC' 33 .

[0007] Charge amplifier 31 includes a differential amplifier 34, such as an operational amplifier, having a non-inverting terminal '+' connected to a reference voltage Vref and an inverting terminal '-' connected to the output of amplifier 34 via a feedback capacitor Cf. Switch s1 is arranged in parallel with feedback capacitor Cf.

[0008] The output of the amplifier 34 is connected to a CDS unit 32 which performs two measurements and feeds the difference between these measurements to an ADC 33 for converting the difference into a digital value.

[0009] exist Figure 1 In a TFT, the pixel array is arranged on a thin film transistor (TFT) panel. More specifically, the thin film transistor on the TFT panel corresponds to the select transistor Ts. The photodiode (PD) is typically implemented by arranging small islands of photosensitive material, such as amorphous silicon, on the TFT panel.

[0010] In addition, Figure 1 In FIG, the readout unit 3 is implemented in an integrated circuit arranged on a semiconductor die. Typically, the readout unit 3 is implemented in complementary metal oxide semiconductor 'CMOS' technology. The division between integration on the semiconductor die and integration on the TFT panel is indicated by dotted line 4.

[0011] During pixel readout, pixel 2 is connected to column line cl through select FET Ts. The column line cl including its parasitic capacitance Cp is initially reset to Vref by closing switch s1 of charge amplifier 31. At this stage, CDS unit 32 samples the output of charge amplifier 31 as the first pixel readout. When pixel 2 is selected via select FET Ts, the internal capacitance of photodiode PD, hereinafter referred to as Cdiode, is also charged to Vref. If the internal capacitance has been previously discharged by the photocurrent, the potential across the internal capacitance will start at Vref−Vsig. This means that there is a negative signal charge Qsig = Cdiode×Vsig on Cdiode. To reset photodiode PD to Vref, this signal charge must move across the column line to the feedback capacitance Cf of charge amplifier 31. It should be noted that at this stage, switch s1 is open. Therefore, the voltage at the output terminal of charge amplifier 31 rises by an amount of dV = Qsig / Cf. This voltage step at the output of charge amplifier 31, that is, from Vref to Vref+Qsig / Cf, is sampled by CDS unit 32 as the second pixel readout. The difference between the sampled first pixel readout and the second pixel readout is then converted to a digital value by ADC 33. In this way, CDS unit 32 cancels the reset noise and charge injection that occur in charge amplifier 31.

[0012] The column line cl has a large parasitic capacitance Cp. This causes a noise problem. Charge amplifier 31 keeps the potential on Cp constant at Vref, which corresponds to the voltage at its non-inverting terminal ‘+’. However, in reality, charge amplifier 31 keeps the voltage on Cp equal to Vref plus its own noise voltage. The latter can be represented by a voltage source connected in series with the non-inverting terminal ‘+’ of amplifier 34. More precisely, amplifier 34 forces current through feedback capacitor Cf into Cp in order to charge Cp to the noise of amplifier 34. This current not only charges Cp but also charges Cf. The noise gain is approximately Cp / Cf. Since usually Cf<<Cp, for example, Cp = 30 pF and Cf = 300 fF, the noise gain can be very high. Because of this high noise gain, the noise of amplifier 34 should be as low as possible.

[0013] Low noise can be achieved by using a high current to bias the input stage of amplifier 34. This significantly increases the power dissipation, thereby causing self-heating in the image sensor. This can become a problem because at high temperatures, the scintillator layer used in an indirect conversion X-ray image sensor can degrade and the leakage current of photodiode PD can increase, resulting in darker noise.

[0014] Another way to achieve low noise is to reduce the bandwidth of the CDS unit 32 used to sample the signal. Typically, a low-pass filter is inserted between the charge amplifier 31 and the CDS unit 32. The lower the bandwidth of this low-pass filter, the lower the noise. Obviously, there is a trade-off between power dissipation (self-heating), speed (bandwidth), and noise. This trade-off is a fundamental limitation of passive pixel TFT panels.

[0015] The noise / speed / power trade-off discussed previously can be avoided by using active pixels. Figure 2 The diagram illustrates a known image sensor 1 in which active pixels 2 are used. Figure 2 The same reference numerals are used to refer to Figure 1 The same or similar components in

[0016] The active pixel 2 is a known three-transistor (3T) pixel, which includes a reset FET Tr, a select FET Ts, and a source follower SF. It is called an active pixel because the source follower SF provides a buffering function within the pixel 2.

[0017] In the active pixel 2, the photodiode PD will charge the storage capacitor, which is a capacitor internal to the photodiode PD or an external capacitor. This charge is reflected in the voltage at the node N. This latter node can be reset to a reference voltage Vres using a reset FET Tr, which is controlled by a row controller (not shown) using a reset line rt. When light is detected, the resulting photocurrent will gradually discharge the storage capacitor, causing the voltage at the node N to decrease.

[0018] The voltage at node N can be read using a select transistor Ts which is controlled by a row controller (not shown) using a row select line rs. When activated, the voltage at node N will be placed on column line cl via source follower SF. This latter transistor is biased using a current source 35 inside readout unit 3. Figure 2 , column line c1 is driven between Vdd and ground. The latter is associated with a current source 35, one terminal of which is connected to column line c1 and the other terminal is grounded.

[0019] Active pixels 2 are typically implemented using CMOS technology. However, increasing the size of a CMOS-based pixel array is more difficult and more expensive than with a TFT panel. Consequently, efforts have been made to implement active pixel arrays on TFT panels. However, the applicant has discovered that implementing active pixel arrays on TFT panels is not without problems. More specifically, the transistors produced in the glass TFT panel manufacturing process have large threshold variations. The threshold voltage of the TFT changes due to process variations, temperature variations, negative or positive bias temperature instabilities, and exposure to X-rays. All of these effects are much greater in TFT technology than in CMOS technology.

[0020] Using standard integrated circuit fabrication processes for implementing the readout circuitry imposes limitations on the supply voltage to be used, e.g., 3.3V or 5V. The voltage at input node M of readout unit 3 should be within the supply rails. Variations in the threshold voltage of the TFTs reduce the headroom available for signal swing. More precisely, the voltage at column line cl and node M equals the voltage at photodiode PD and node N minus the threshold voltage of source follower SF. Therefore, any variation in the TFT threshold will introduce a voltage variation at node M. Furthermore, current source 35, which biases source follower SF, requires some headroom.

[0021] If the threshold variation is 3 V, and if a 3.3 V supply is applied to the readout unit 3, a substantially zero dynamic range will remain for the signal. Thus, the lack of dynamic range complicates the combination of known standard CMOS readout circuitry and a TFT panel. Summary of the Invention

[0022] It is an object of the present invention to provide an image sensor comprising a plurality of active pixels, in which the above-mentioned problems do not occur or at least to a lesser extent.

[0023] According to the present invention, this object is achieved by an image sensor as described in claim 1, comprising a pixel array integrated on a thin film transistor (TFT) panel. The pixel array comprises a plurality of active pixels arranged in a matrix of rows and columns, and comprises a plurality of column lines to which the outputs of pixels in the same column are coupled for the purpose of outputting pixel signals. Each column line is driven between a first voltage and a second voltage lower than the first voltage.

[0024] The image sensor further includes readout circuitry including a plurality of readout units, each readout unit configured to read out a corresponding column line via an input node of the readout unit.

[0025] The image sensor further includes a capacitive unit, such as a capacitor, for capacitively coupling each input node to its corresponding column line.

[0026] The readout circuitry is integrated onto one or more semiconductor dies of a first type, and the capacitor unit is integrated onto one or more semiconductor dies of a second type. The one or more semiconductor dies of the first type have been manufactured using a first semiconductor process and each include low-voltage components for implementing the readout circuitry, wherein the readout circuitry has a first maximum voltage rating. The one or more semiconductor dies of the second type have been manufactured using a second semiconductor process different from the first semiconductor process and each include high-voltage components for implementing the capacitor unit, wherein the capacitor unit has a second maximum voltage rating that is higher than the first maximum voltage rating. The difference between the first voltage and the second voltage is greater than the first maximum voltage rating but less than the second maximum voltage rating. The voltage on the column line is limited to between the first voltage and the second voltage. This voltage range should be large enough to allow for variations due to signal swings during operation, but also large enough to accommodate threshold variations over the life of the sensor.

[0027] In the context of this application, the maximum voltage rating of a component is defined as the maximum potential difference that can exist across the component while having little or no reduction in component life. For example, a two-terminal component may have +A volts at one terminal and -B volts at the other. The voltage difference across this component is then calculated as A + B. In this case, the maximum voltage rating is equal to the sum of A and B, with which there is little or no reduction in life. It should be noted that positive, negative, or zero volts can be applied to the terminals.

[0028] By using capacitive coupling between the input nodes and the column lines, the voltage at the input nodes can be offset to a value that will not damage the readout circuitry. More specifically, the power supply voltage used to operate the pixels and column lines can be prevented from being placed on the input nodes of the readout circuitry. This enables the image sensor of the present invention to be implemented using TFT technology in combination with low-voltage standard CMOS process technology for implementing the readout circuitry. Furthermore, by arranging the capacitive elements on one or more semiconductor dies of the second type, it is possible to use standard, off-the-shelf, low-voltage readout circuitry semiconductor dies in combination with TFT panels that operate using relatively high power supply voltages.

[0029] As light falls on the pixels, the voltage on the column lines changes during operation. This change occurs on a relatively short timescale, related to the sensor's frame rate. However, this voltage also changes due to variations in the threshold voltage of the transistors on the TFT panel. In the case of an X-ray image sensor, these variations occur on a much larger timescale and can be caused by threshold voltage shifts due to radiation damage. Threshold voltages can also shift due to temperature instabilities in negative or positive biasing. Due to process tolerances, threshold voltages can further vary between transistors on the same panel.

[0030] Threshold voltage shift and / or diffusion will impose limits on the voltage levels between which the voltage on the column line will vary during image capture. For example, the voltage on the column line can vary between Va and Va-Vsigmax, where Vsigmax is the maximum change in voltage on the column line due to light falling on the pixel, and Va is a reference level. Typically, Vsigmax is fixed. However, Va may vary due to the threshold voltage shift and / or diffusion described above. For example, the reference Figure 2 , Va can be equal to Vdd minus the threshold voltage of the source follower SF.

[0031] By appropriately selecting the first and second voltages, it is possible to ensure that over time, the voltages Va and Va-Vsigmax can be achieved on each column line of the TFT panel to avoid loss of dynamic range. However, the absolute values ​​of both Va and Va-Vsigmax may be too high or too low for the readout circuitry to process directly. According to the present invention, this problem is alleviated by using a capacitor cell that is manufactured using a different process from the readout circuitry. For example, the capacitor cell is manufactured using a high-voltage CMOS process, and the readout circuitry is manufactured using a low-voltage CMOS process.

[0032] The image sensor may further include a row controller for selecting a pixel to be read out from among a plurality of pixels. For each pixel, the image sensor may further include a source follower for buffering a pixel signal, and a select transistor for outputting the buffered pixel signal to a corresponding column line based on a row select signal output by the row controller. Additionally, the image sensor may include a source follower load, such as a current source or a resistor, for each column line.

[0033] The first voltage may be a voltage applied to the drain of the source follower. Additionally or alternatively, each source follower load is connected between a corresponding column line and a reference node, wherein the second voltage may be a voltage applied to the reference node. Typically, the reference node of the column lines is the same, and the voltage applied to the drain of the source follower is the same.

[0034] In addition, for each pixel, the image sensor may further include a photodiode arranged between the signal node and a node maintained at a first reference voltage, such as ground. Each pixel may further include: a storage capacitor configured to accumulate charge due to photocurrent generated by the photodiode; and a reset transistor coupled between the photodiode and a second reference voltage and configured to set the voltage on the signal node to the second reference voltage based on a reset signal output by the row controller. In some embodiments, the storage capacitor is formed solely by the internal capacitance of the photodiode, while in other embodiments, an additional capacitor is arranged in parallel with the photodiode. Such an additional capacitor may be advantageous if the internal capacitance of the photodiode is too small to achieve the desired full well capacitance.

[0035] The first reference voltage can be ground, and the second voltage can be a negative voltage. In this case, the voltage headroom required to accommodate voltage levels Va and Va-Vsigmax is primarily achieved by appropriately selecting a sufficiently low second voltage. Alternatively, the first reference voltage can be a positive non-zero voltage, and the second voltage can be ground. By using a higher first reference voltage, Va is shifted upward. Assuming the first voltage is sufficiently high, the required voltage headroom can be achieved even when the source-follower load is grounded.

[0036] The source follower loads described above can be integrated onto one or more semiconductor dies of the same second type as the corresponding capacitive cells. This has the advantage that a standard TFT panel can be used instead of the TFT panel on which the source follower loads are implemented. Thus, by using a semiconductor die of the second type on which both the capacitive cells and the source follower loads are integrated, it is possible to combine already available TFT panels operating at relatively high voltages (e.g., 10V or higher) with low-voltage readout integrated circuit dies operating at much lower voltages (e.g., <3V) without risk of damaging the readout circuitry. However, the present invention does not exclude embodiments in which the source follower loads are integrated onto the TFT panel.

[0037] The readout circuit system may be composed of a plurality of first segments, each first segment corresponding to a plurality of column lines and integrated on a corresponding semiconductor die of the first type. The first segments may be identical to each other. The image sensor may further include a plurality of first flexible foils, through which the TFT panel is connected to an external device, wherein the corresponding semiconductor die of the first type is arranged on the corresponding first flexible foil. Preferably, the second type of semiconductor die corresponding to the column line associated with a given first segment of the plurality of first segments is arranged on the same first flexible foil as the first type of semiconductor die corresponding to the given first segment, and the second type of semiconductor die (when applicable) is integrated with a capacitor unit and a source follower load. The external device may, for example, be a device that collects various readout values ​​for the pixel array and constructs an image based on the readout values.

[0038] The row controller may include a plurality of second segments, each of which corresponds to a plurality of rows of the pixel array. These second segments may be identical. Each second segment may further include a driver for outputting row select signals and select signals for the plurality of rows, where applicable, and may be integrated on a corresponding semiconductor die of the third type. The image sensor may further include a plurality of second flexible foils, through which the TFT panel is connected to the rest of the row controller, wherein the corresponding semiconductor die of the third type is arranged on the corresponding second flexible foils.

[0039] The first maximum rated voltage may be between 3 and 6 volts, more preferably between 3.5 and 5.7 volts, and the second maximum rated voltage may be between 10 and 100 volts, more preferably between 10 and 50 volts, and wherein the difference between the first voltage and the second voltage is between 7.5 and 15 volts, more preferably between 8 and 12 volts.

[0040] The first flexible foils can each include n inputs, each connected to a corresponding column line on the TFT panel. Each first flexible foil can include n conductive paths on the flexible substrate. Connection to these paths is possible, for example, using bump technology, thereby allowing semiconductor dies of a first type and a second type to be arranged on the first flexible foil and electrically connected to the first flexible foil. Using multiple first flexible foils and corresponding semiconductor dies, each column line of the pixel array can be read out.

[0041] The TFT panel may be based on amorphous silicon, low temperature polysilicon, or indium gallium zinc oxide. These materials are deposited on a substrate such as a glass panel. The photosensitive element may also be formed by depositing a photosensitive material such as amorphous silicon or amorphous selenium onto the substrate. Additionally or alternatively, the image sensor may further include a scintillator layer arranged above the pixel array. Such a layer may be used to indirectly convert the image sensor. Additionally or alternatively, one or more semiconductor dies of the first, second and / or third types may be based on complementary metal oxide semiconductor 'CMOS' technology. For example, the first semiconductor process may be a 3.3V or 5V digital CMOS process, and the second semiconductor process may be a 16V, 42V or 48V bulk or SOIBCD process, such as a process initially targeted for automotive applications.

[0042] The image sensor can be configured to perform a correlated double sampling (CDS) scheme for each selected pixel based on a first pixel readout and a second pixel readout. For example, the first pixel readout may correspond to a pixel read out a predetermined amount of time after the pixel is reset, and the second pixel readout may correspond to a pixel read out directly after it has been reset. Typically, the predetermined amount of time, also known as the integration time, is sufficient to fully utilize the available voltage swing of the pixel voltage when the pixel array is irradiated at a corresponding maximum dose. Typically, the pixel array is read out and reset row by row. After the entire pixel array has been read out and reset, an X-ray source or other source of electromagnetic radiation generates an exposure flash and the pixels integrate the light. After the predetermined amount of time, the pixels are read out and reset row by row. In this first pixel readout, the sample taken is referred to as the signal level. Immediately thereafter, the pixel is reset and a second sample is obtained. This second sample is referred to as the reference level for the CDS scheme.

[0043] It should be noted that the present invention is not limited to a specific temporal order of the first pixel readout and the second pixel readout. In other words, embodiments are also possible in which the second pixel readout is performed earlier in time than the first pixel readout.

[0044] The readout circuitry may include multiple analog-to-digital converters (ADCs). For example, a single ADC may be provided for each column line. Alternatively, a column-parallel CDS circuit may be used, followed by a multiplexer. This multiplexer directs the inputs received from the CDS circuits associated with multiple column lines to one or more high-speed ADCs. In this case, one ADC can be used to convert signals for more than one column line.

[0045] The readout circuitry may be configured to readout the column lines based on charge-mode readout. For example, each readout unit may be configured to set the voltage at the input node to a third reference voltage during a first pixel readout and a second pixel readout. Each readout unit may be configured to determine an output voltage based on the charge transfer to and from the capacitor unit during the second pixel readout. More specifically, each readout unit may include a charge amplifier comprising an operational amplifier having a non-inverting input connected to the third reference voltage and an inverting input connected to the capacitor unit via a first switch. The output of the operational amplifier may be coupled to the inverting input via a feedback capacitor. Each readout unit may further include a second switch disposed between the output and inverting input of the operational amplifier. Additionally, the readout circuitry may include a plurality of analog-to-digital converters (ADCs) coupled to the outputs of the operational amplifiers of the readout units. The image sensor may include a second controller configured to control the first and second switches such that the voltage at the input node is set to the third reference voltage by closing the first and second switches during the first pixel readout, and to open the second switch when performing the second pixel readout. The second controller may be further configured to control the first switch to be turned off when the output of the operational amplifier is converted by an ADC among the plurality of ADCs.

[0046] Alternatively, the readout circuitry may be configured to readout the column lines based on a voltage-mode readout. For example, each readout unit may be configured to set the voltage on the input node to be equal to a fourth reference voltage during a first pixel readout period, and to determine the output voltage based on a change in the voltage on the input node relative to the fourth reference voltage during a second pixel readout period. More specifically, each readout unit may further include a voltage setting unit for setting the voltage on the input node to the fourth reference voltage during the first pixel readout period, and for providing a high impedance state during the second pixel readout period to allow the voltage on the input node to track the pixel voltage when changing from a value corresponding to the first pixel readout to a value corresponding to the second pixel readout.

[0047] The readout circuitry may include a plurality of analog-to-digital converters (ADCs). An exemplary embodiment of a readout unit based on voltage-mode readout may include a first operational amplifier having a non-inverting input connected to a fourth reference voltage via a third switch and an inverting input connected to an output of the operational amplifier. The readout circuitry may further include a charge amplifier including a second operational amplifier having a non-inverting input connected to a fifth reference voltage and an inverting input connected to the output of the first operational amplifier via a series capacitor and a series fourth switch, and connected to the output of the second operational amplifier via a parallel connection of a feedback capacitor and a fifth switch, wherein the output of the second operational amplifier is connected to an ADC in the plurality of ADCs. The readout circuitry may further include a third controller configured to control the third switch to be closed during a first pixel readout and open during a second pixel readout, to control the fourth switch to be closed during both the first and second pixel readouts and open after the second pixel readout to allow the output of the second operational amplifier to be converted by the connected ADC, and to control the fifth switch to be open during the first pixel readout and closed during the second pixel readout.

[0048] In an embodiment, the timing signals of the readout circuit system are synchronized to the timing of the row controller by a main controller that is typically arranged outside the readout circuit system and the TFT panel. This main controller may correspond to the second or third controller described above. Typically, the main controller is a field programmable gate array 'FPGA' or a microcontroller and may be arranged away from the panel and outside the readout circuit system. The row controller may be implemented as a gate driver containing an offset register to select rows and a number of gates to control the reset and row select lines. The reset and row select line timing of the row to which the offset register points can be controlled by some digital signals provided to the gate driver by the FPGA or microcontroller. The FPGA or microcontroller may also provide clock and data input signals for the offset register. The FPGA may also provide timing synchronization signals to the readout circuit system to ensure that the readout circuit system and the gate driver operate synchronously.

[0049] According to a second aspect, the present invention provides an imaging system comprising an image sensor as described above and a processing unit for constructing an image based on an output from the readout circuitry. The imaging system may be configured to construct an X-ray image of an object. In this case, the imaging system may further comprise an X-ray source positioned such that the object to be imaged can be arranged between the X-ray source and the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Next, the present invention will be described in more detail, wherein:

[0051] Figure 1 An example of a known TFT-based image sensor using passive pixels is shown;

[0052] Figure 2 An example of a known image sensor using active pixels is shown;

[0053] Figure 3A and 3B Schematically illustrating a first example and a second example of a TFT-based image sensor according to the present invention, respectively;

[0054] Figure 4 An embodiment of an image sensor according to the present invention using voltage mode readout is shown;

[0055] Figure 5 Another embodiment of an image sensor according to the present invention using voltage mode readout is shown;

[0056] Figure 6 An embodiment of an image sensor according to the present invention using charge mode readout is shown;

[0057] Figure 7 A third example of a TFT-based image sensor according to the present invention is shown;

[0058] Figure 8 shows a layout of an embodiment of an image sensor according to the present invention;

[0059] Figure 9 Shown in Figure 8 A detailed view of the flexible foil used in the image sensor;

[0060] as well as

[0061] Figure 10 An X-ray imaging system according to the present invention is shown. DETAILED DESCRIPTION

[0062] Figure 3A A first example of a TFT-based image sensor according to the present invention is schematically shown. More specifically, an embodiment of an image sensor 100A according to the present invention is similar to Figure 2 The image sensor includes a pixel array, wherein a single active pixel 102 is shown in FIG3 . The active pixel 102 includes a reset transistor Tr controlled via a reset line rt, a selection transistor Ts controlled via a row selection line rs, and a source follower SF.

[0063] The readout unit 103 having an input node M includes a correlated double sampling unit 132 and an ADC converter 133 .

[0064] Figure 3ADotted line 104 and dotted line 104A are indicated. Components shown to the right of dotted line 104 are implemented on a first type of semiconductor die, for example, based on readily available CMOS technology. Components shown between dotted lines 104 and 104A are implemented on a second type of semiconductor die, for example, based on high-voltage CMOS technology. Finally, components shown to the left of dotted line 104A are implemented on a TFT panel.

[0065] As illustrated, a current source 135 acting as a load for the source follower SF is arranged on the TFT panel.

[0066] Capacitive coupling between input node M and column line c1 is provided by capacitor Cc, which is formed on the second type of semiconductor die. This capacitor provides a voltage level shift between input node M and column line c1. Capacitor Cc can be implemented as a metal-insulator-metal capacitor, a metal oxide semiconductor capacitor, or the like.

[0067] The photodiode PD will generally perform best if it is reset to, for example, 5V between its cathode and anode. Figure 3A In the example, the anode is grounded. This means that Vres should be 5 V. However, the gates of the reset transistor Tr and the select transistor Ts may have to be pulsed to, for example, 10 V or 25 V to obtain a low on-resistance.

[0068] The 5V on photodiode PD defines the reset level. During reference level sampling, column line cl will be at 5V minus Vgs of source follower SF. During signal level sampling, column line cl will be at 5V - Vgs - Vsig. If the threshold level shift is large, column line cl may fall below 0V. This can be problematic for current source 135 if it is connected between column line cl and ground. There are two solutions to this problem.

[0069] As a first solution, the bottom terminal of the current source 135 can be connected to a negative potential. As a second solution, instead of Figure 3A The anode of the photodiode PD is connected to 0 V as shown, but it can be connected to 5 V. This means that the Vres of the pixel must be raised to 10 V. Similarly, Vdd must be raised to at least 10 V. However, these higher voltages on the column line cl are blocked by the capacitor Cc.

[0070] As described above, various voltages are used for the TFT panel, such as the on voltage on the gate (eg, +25V), the off voltage on the gate (eg, -5V), and Vres and Vdd for the pixels.

[0071] During operation, the voltage on the column line c1 of the TFT panel varies in the range of several volts due to the signal and, in addition, varies in the range of several more volts due to threshold variations. In practice, it has been found that a voltage range of about 10 V is sufficient to accommodate threshold variations.

[0072] Capacitor Cc will have to block the aforementioned 10 V range. Therefore, capacitor Cc implemented in the second type of semiconductor die should be able to withstand voltages in this range and should therefore be fabricated in an IC with a rated voltage of, for example, 12 V or higher. However, the first type of semiconductor die can be implemented using a low-voltage semiconductor process.

[0073] In most cases, a negative power supply is either not available or not desirable. It is then necessary to use the second solution described above, where even more importantly, the capacitor Cc prevents a possible high voltage on the column line cl from damaging the readout unit 103.

[0074] According to the present invention, threshold voltage variations are absorbed across coupling capacitor Cc so that these variations do not reduce voltage headroom. In other words, any threshold voltage variations of the TFT panel are stored on capacitor Cc so that the readout unit 103 does not have to sacrifice voltage headroom for TFT threshold variations. A secondary goal is to isolate the low-voltage readout unit (e.g., operating at 3.3V) from the potentially higher voltages (e.g., 10V) on the TFT panel.

[0075] The current source 135 may be implemented as a current mirror, where there is one transistor for each column in the panel.

[0076] Figure 3B A second example of a TFT-based image sensor according to the present invention is schematically shown. Figure 3A In contrast, the current source 135 is now also implemented on the second type of semiconductor.In this way, the TFT panel does not have to be equipped with the current source 135 and the readout unit 103 can be fully realized using standard low voltage CMOS technology.

[0077] Figure 4 An embodiment of an image sensor 200 according to the present invention using voltage mode readout is shown. Figure 4 shows a relatively simple implementation of the CDS unit 132. In addition, in this embodiment, the current source 135 and the capacitor Cc are integrated in a circuit similar to Figure 3B on a second type of semiconductor die.

[0078] As long as the pixel row is selected, the voltage on the column line cl will always stabilize to the defined DC voltage. This stabilization may take some time, but after stabilization, the DC voltage is basically defined as the voltage on the node N minus the threshold Vth of the source follower.

[0079] Will refer to Figure 4 The operation of image sensor 200 is explained using the timing diagram shown in the upper right corner of FIG. Initially, the voltage at node N is Vres - Vsig, where Vres is the original potential after reset and Vsig is the amount of potential drop due to exposure to light. The voltage on the left plate of capacitor Cc is Vres - Vsig - Vth, where Vth is the threshold of source follower SF. Here, it is assumed that the gate-source voltage of source follower SF (which is equal to Vth plus a small overload) can be approximated as Vth. The voltage on the right plate of capacitor Cc is pulled to Vref via switch Sin. This results in the voltage Vcap across capacitor Cc being equal to Vcap = Vres - Vsig - Vth - Vref.

[0080] Some time later, when Vcap has stabilized, switch Sin opens, as indicated by the negative edge of Sin in the timing diagram. From this point forward, the voltage on the right side of Cc tracks any offset on the left side. More precisely, due to the high input impedance associated with input node M, essentially no current flows from the side of capacitor Cc into input node M. Because no current flows through Cc, the voltage across Cc is constant. This means that the voltage on the right side of Cc tracks the voltage on the left side of Cc exactly, with a level offset equal to the Vcap calculated above.

[0081] Shortly after Sin is disconnected, Ssig is disconnected and the signal level on Csig is sampled by CDS unit 132. The voltage on Csig is equal to Vref in the first order. In the second order, it is equal to Vref plus any charge injection that occurs when Sin is disconnected and the charge injection that occurs when Ssig is disconnected.

[0082] After the signal level on Csig is sampled by CDS unit 132, pixel 102 is reset. The voltage on node N then changes from Vres - Vsig to Vres. The voltage on column line cl changes from Vres - Vsig - Vth to Vres - Vth. This means that the column voltage steps upward by the amount Vsig. Therefore, the voltage on Cref moves upward from Vref to Vref + Vsig. After Sref is disconnected, the signal level on Cref is sampled by CDS unit 132. By subtracting the second pixel readout from the first pixel readout, that is, Vref - (Vref + Vsig) = Vsig, the component in the pixel signal associated with the amount of captured light can be extracted. This value can then be converted into a digital value by ADC unit 133.

[0083] Due to the capacitive division between Cc and Cref, there is a capacitive reduction in the signal voltage. However, since Cc>>Cref, this reduction can be ignored. Alternatively, a voltage buffer can be placed between the input node M and the switches Ssig and Sref to avoid capacitive loading caused by Csig and / or Cref.

[0084] Figure 5 Another embodiment of an image sensor 300 according to the present invention using voltage mode readout is shown. Also, in this embodiment, the current source 135 and the capacitor Cc are integrated on a second type of semiconductor die.

[0085] The operation of Cc and Sin is the same as in Figure 4 In addition, the same reference numerals will be used to refer to the same or similar components.

[0086] The CDS unit 132 includes a first operational amplifier 1321 that acts as a voltage buffer to allow accurate tracking of the voltage step that occurs on the right-hand plate of Cc when the pixel 102 is reset. With this embodiment, the capacitive voltage division can be small because only the input capacitance of the buffer loads the column line c1.

[0087] The CDS unit 132 further includes a second operational amplifier 1322, which functions as a charge amplifier. The non-inverting input of amplifier 1322 is connected to a reference voltage Vcm, and the inverting input is connected to the output of amplifier 1321 via a series connection of a switch Ssh and a capacitor Cs. The inverting input is further connected to the output of amplifier 1322 via a feedback capacitor Cf. A switch Srst is arranged in parallel with capacitor Cf, and the output of amplifier 1322 is connected to the ADC unit 133.

[0088] In this embodiment, when switch Sin is open, the readout unit 103 has a high input impedance, allowing the voltage step that occurs on the right-hand plate of Cc when the pixel 102 is reset to be accurately tracked.

[0089] Initially, when column line cl is at Vres - Vsig - Vth, Sin forces the right plate of capacitor Cc to Vref. At this point, because Srst of CDS unit 132 is closed, the voltage on capacitor Cs will be equal to Vref - Vcm. Subsequently, Sin opens, and the voltage on Cc is sampled. After that, Srst opens. This completes the reset of capacitor Cf. Now, if pixel 102 is reset using reset line rt, there will be a voltage step of magnitude Vsig on input node M, which is also reflected at the right plate of Cc and the left plate of Cs. Because the right plate of Cs is fixed at Vcm, this causes the current flowing through Cs to also flow through Cf. As a result, the output of CDS unit 132 will change from the level Vcm during reset to Vcm - Vsig × Cs / Cf. This indicates that CDS unit 132 acquires the pixel signal voltage with a gain that depends on the capacitance ratio and level-shifts the signal voltage to the new reference level Vcm. Vcm may be selected at any convenient voltage level for CDS unit 132 and ADC unit 133 to prevent electrical breakdown of components in these units. For example, Vcm may be set to a voltage level above 0V, which can be easily reached by amplifier 1322 to avoid the need for a negative supply voltage for amplifier 1322.

[0090] When the switch Ssh is open, there can no longer be any current flowing through Cs and therefore no current flowing through Cf. This freezes / samples / stores the signal voltage on the output of the CDS unit 132 for subsequent ADC conversion by the ADC unit 133.

[0091] Figure 6 An embodiment of an image sensor according to the present invention using charge mode readout is shown. In addition, in this embodiment, the current source 135 and the capacitor Cc are integrated on the second type of semiconductor die. Also in this case, the readout unit 103 includes a charge amplifier formed using an operational amplifier 1323, but together with the switches Srst and Sin and the timing signals, the charge amplifier actually implements a CDS operation. This CDS operation is very similar to that combined with Figure 4 and 5 The operation of the CDS unit 132 is described.

[0092] Initially, the left plate of Cc is at Vres - Vsig - Vth. Initially, Sin and Srst are turned on, allowing op amp 1323 to force the voltage on the right plate of Cc to equal Vref, which may correspond to the voltage between the power supply rails of amplifier 1323, for example. Subsequently, Srst is turned off. After that, op amp 1323 can affect only the voltage on input node M by forcing current into feedback capacitor Cf. Pixel 102 is then reset. This shifts the column line voltage from Vres - Vsig - Vth to Vres - Vsig. The inverting input of op amp 1323 remains constant at Vref. Therefore, the voltage on Cc changes by the amount Vsig. This voltage change implies a charge change equal to Cc × Vsig. Therefore, charge should flow through Cf into Cc. This charge causes the potential at the output of op amp 1323 to decrease from Vref to Vref - Vsig × (Cc / Cf). Finally, Sin can be turned off, isolating op amp 1323 from column line c1. From this point forward, no current may flow into the input node M, thereby freezing the output voltage of the operational amplifier 1323. This output voltage may be processed by the ADC unit 133.

[0093] Figures 4 to 6 The ADC unit 133 depicted in FIG. 1 may be a column-parallel ADC or an ADC shared among multiple columns of the pixel array.

[0094] exist Figure 5 and 6 In the embodiment shown, the value of Cc affects the gain of CDS unit 133. The value of Cc can be different between columns. This creates a column gain pattern. The value of Cc is constant over temperature / lifetime, making it easy to remove the gain pattern through calibration, such as flat-field correction.

[0095] Figure 7 A third example of a TFT-based image sensor according to the present invention is shown. Figure 3A and 3B Compared to the example in FIG. 1 , the components to the right of dotted line 104B, namely, capacitor Cc, current source 135, and readout unit 103, are now implemented in a hybrid semiconductor die. The term "hybrid" here refers to the fact that both low-voltage and high-voltage components are available in a single semiconductor technology (e.g., CMOS). High-voltage components, i.e., components that can withstand high voltages, are used to implement current source 135 and capacitor Cs, while low-voltage components are used to implement readout unit 103.

[0096] Figure 8 FIG. 5 shows a layout of an embodiment of an image sensor 500 according to the present invention. Depending on whether the current source 135 is implemented on the TFT panel, this layout may be suitable for Figure 3A or Figure 3BExamples shown.

[0097] On the right, a row driver integrated circuit 501 formed by a third type of semiconductor die is arranged on a flexible foil 502, which is bonded to a TFT panel 503 on which a pixel array and an optional current source 135 are arranged. Circuit 501 controls the row select lines and reset lines. More specifically, each integrated circuit 501 drives the row select lines and reset lines for multiple rows of pixels. These circuits are part of a row controller. In an embodiment, the row controller is essentially formed entirely by circuit 501. In other embodiments, the row controller may include additional circuitry arranged away from the panel 503 and the flexible foil 502. For example, the panel 503 may be mounted to a separate printed circuit board (not shown), wherein the electrical connection between the circuitry on the printed circuit board and the panel 503 is obtained via the flexible foil 502. In this case, the additional circuitry may be implemented on the printed circuit board. It is also possible to split the column lines in the center of the array. If the column lines are each split into an upper half and a lower half, then there should be readout circuitry on both sides of the pixel array to read out the upper half of the pixel array connected to the upper half of the column lines and the lower half of the pixel array connected to the lower half of the column lines. This approach doubles the amount of circuitry and also increases the overall speed of the detector by a factor of two.

[0098] Regardless of the column line split, it is also possible to drive the row select lines from one or both sides of the pixel array. Driving on both sides provides a speed advantage because only half the RC load of the row select line is actually loading the gate drivers on either side of the pixel array.

[0099] The readout circuitry can also be divided into separate integrated circuits 504 mounted on the flexible foil 505. In this case, the readout circuitry can be formed entirely by the integrated circuit, or portions of the readout circuitry can be arranged on a printed circuit board. In addition, each integrated circuit 504 includes readout units for multiple column lines. Similarly, integrated circuit 508 includes capacitor Cc and optional current source 135, which are associated with the same column lines as integrated circuit 504. Figure 9 A more detailed view of the flexible foil 505 is shown in FIG.

[0100] Instead of using semiconductor dies of the first and second types, a single mixed-type semiconductor die could be used. However, this would require the use of expensive high-voltage semiconductor processes. In this case, the image sensor would include:

[0101] a pixel array integrated on a thin film transistor 'TFT' panel and comprising a plurality of active pixels arranged in a matrix of rows and columns, and comprising a plurality of column lines to which the outputs of pixels in the same column are coupled for the purpose of outputting pixel signals, each of said column lines being driven between a first voltage and a second voltage lower than the first voltage;

[0102] a readout circuitry comprising a plurality of readout units, each readout unit configured to read out a corresponding column line via an input node of the readout unit;

[0103] wherein the image sensor further comprises a capacitive unit, such as a capacitor, for capacitively coupling each input node to its corresponding column line;

[0104] wherein the readout circuitry and the capacitive unit are integrated on one or more semiconductor dies of a mixed type, the readout circuitry has a first maximum rated voltage and the capacitive unit has a second maximum rated voltage higher than the first maximum rated voltage;

[0105] The difference between the first voltage and the second voltage is greater than the first maximum rated voltage but less than the second maximum rated voltage.

[0106] Alternatively, both the capacitor unit and the source follower load can be integrated on the TFT panel. In the latter case, the image sensor will include:

[0107] a pixel array integrated on a thin film transistor 'TFT' panel and comprising a plurality of active pixels arranged in a matrix of rows and columns and comprising a plurality of column lines to which the outputs of the pixels in the same column are coupled for the purpose of outputting pixel signals;

[0108] a readout circuitry comprising a plurality of readout units, each readout unit configured to read out a corresponding column line via an input node of the readout unit;

[0109] a capacitive unit, such as a capacitor, for capacitively coupling each input node to its corresponding column line;

[0110] a row controller for selecting a pixel to be read out from a plurality of pixels;

[0111] a source follower load, for each column line, which may be, for example, a current source or a resistor;

[0112] as well as

[0113] For each pixel, a source follower for buffering the pixel signal, and a selection transistor for outputting the buffered pixel signal to the corresponding column line according to a row selection signal output by the row controller;

[0114] The readout circuit system is integrated on one or more semiconductor dies, and the capacitor unit and the source follower load are integrated on a TFT panel.

[0115] like Figure 9 As shown, flexible foil 505 includes a first end 506 connected to the TFT panel and a second end 507 connected to an external device for image processing. Flexible foil 505 includes a plurality 509 of conductive traces or paths for connecting corresponding column lines of the TFT panel to a second type of semiconductor die 508, which includes capacitors Cc and optionally current sources 135. Typically, flexible foil 505 can include n traces to connect to n column lines on the TFT panel. Thus, die 508 includes n capacitors Cc and optionally n current sources 135. From die 508, another set of n traces 510 extend between die 508 and the first type of die 504 on which the readout unit 135 is integrated.

[0116] The flexible foil 505 includes m traces or paths 512 for connecting the readout unit on the die 504 to an external device. Of these m traces or paths, some traces or paths 511 are used to transmit digital data output by the readout unit 135, while other traces or paths 513 are used to provide power supply voltage and reference (ground) voltage to the dies 504, 508.

[0117] like Figure 9 As shown in , it is not necessary for each column line to correspond to a respective conductive path 511 of the contact 507. For example, the semiconductor die 504 can use a serial interface to communicate data with an external device.

[0118] Figure 10 An X-ray imaging system 1000 according to the present invention is shown. It comprises an X-ray source 1100 and an image sensor 1200, between which an object 1300 to be imaged may be provided. A general control and processing unit 1400 may be provided for controlling the X-ray source 1100 and the image sensor 1200 and for constructing an X-ray image based on the output from the image sensor 1200. Figures 4 to 7 Any of the image sensors presented in can be used as image sensor 1200.

[0119] In the above, the present invention has been explained using detailed embodiments of the present invention. However, the present invention is not limited to these embodiments. Various modifications may be made to these embodiments without departing from the scope of the present invention as defined by the appended claims and their equivalents.

[0120] For example, some direct-conversion detectors integrate holes rather than electrons. In such detectors, the voltage at node N increases rather than decreases due to integration. In such pixels, the voltage Vres typically used to reset node N is at a different potential than the voltage Vdd connected to the drain of the source-follower SF. This changes the direction of the voltage step sensed by the correlated double sampling circuitry in the readout circuitry. Those skilled in the art will readily appreciate that the present invention relates equally to such embodiments.

Claims

1. An image sensor, comprising: a pixel array integrated on a thin film transistor 'TFT' panel and comprising a plurality of active pixels arranged in a matrix of rows and columns and comprising a plurality of column lines, wherein outputs of pixels in the same column are coupled to one of the plurality of column lines for the purpose of outputting pixel signals, wherein the image sensor is configured such that during operation the voltage on each column line is limited between a first voltage and a second voltage; a readout circuitry comprising a plurality of readout units, each readout unit configured to read out a corresponding column line via an input node of the readout unit; The image sensor further comprises a capacitor unit for capacitively coupling each input node to its corresponding column line; wherein the readout circuitry is integrated on one or more semiconductor dies of a first type, and wherein the capacitive unit is integrated on one or more semiconductor dies of a second type; wherein the one or more semiconductor dies of the first type have been fabricated using a first semiconductor process and each include low voltage components to implement the readout circuitry, the readout circuitry having a first maximum voltage rating; wherein the one or more semiconductor dies of the second type have been manufactured using a second semiconductor process different from the first semiconductor process and each includes a high-voltage component to implement the capacitor unit, the capacitor unit having a second maximum rated voltage higher than the first maximum rated voltage; and The difference between the first voltage and the second voltage is greater than the first maximum rated voltage but less than the second maximum rated voltage.

2. The image sensor according to claim 1 , further comprising a row controller for selecting a pixel to be read out among the plurality of pixels; wherein for each pixel, the image sensor further comprises a source follower for buffering the pixel signal, and a selection transistor for outputting the buffered pixel signal to the corresponding column line according to a row selection signal output by the row controller; wherein for each column line, the image sensor further comprises a source follower load; wherein the first voltage is a voltage applied to a drain of the source follower, and wherein the source follower load is connected between the column line and a reference node, and wherein the second voltage is a voltage applied to the reference node during operation of the image sensor; in, The source follower load is integrated on one or more semiconductor dies of the same second type as the corresponding capacitor unit.

3. The image sensor of claim 2 , wherein for each pixel, the image sensor further comprises: a photodiode disposed between the signal node and a node maintained at a first reference voltage; a storage capacitor configured to accumulate charge due to a photocurrent generated by the photodiode; as well as a reset transistor coupled between the photodiode and a second reference voltage and configured to set the voltage on the signal node to the second reference voltage according to a reset signal output by the row controller.

4. The image sensor according to claim 3, wherein: The first reference voltage is ground and the second voltage is a negative voltage, or wherein the first reference voltage is a positive non-zero voltage and the second voltage is ground.

5. The image sensor according to claim 2 , wherein the readout circuitry is composed of a plurality of first segments, each first segment corresponding to a plurality of column lines and integrated on a respective semiconductor die of the first type, the image sensor further comprising a plurality of first flexible foils through which a thin film transistor (TFT) panel is connected to an external device, wherein the respective semiconductor die of the first type are arranged on the respective first flexible foils; The semiconductor die of the second type corresponding to the column line associated with a given first segment among the plurality of first segments is arranged on the same first flexible foil as the semiconductor die of the first type corresponding to the given first segment, the capacitor unit and the source follower being integrated thereon.

6. An image sensor according to claim 3, wherein the row controller comprises a plurality of second sections, each second section corresponding to a plurality of rows of the pixel array and comprising a driver for outputting the row select signal and the reset signal for the plurality of rows when applicable and integrated on a respective semiconductor die of a third type, the image sensor further comprising a plurality of second flexible foils, the thin film transistor 'TFT' panel being connected to the rest of the row controller via the plurality of second flexible foils, wherein the respective semiconductor die of the third type are arranged on respective second flexible foils.

7. The image sensor of claim 1, wherein the first maximum rated voltage is between 3 and 6 volts, wherein the second maximum rated voltage is between 10 and 100 volts, and a difference between the first voltage and the second voltage is between 7.5 and 15 volts.

8. The image sensor according to claim 1, wherein the thin film transistor (TFT) panel is based on amorphous silicon, low temperature polysilicon or indium gallium zinc oxide, and / or wherein the image sensor further comprises a scintillator layer arranged above the pixel array, and / or wherein the one or more semiconductor dies of the first type and / or the second type are based on complementary metal oxide semiconductor (CMOS) technology.

9. The image sensor of claim 1 , wherein the image sensor is configured to perform a correlated double sampling measurement scheme based on a first pixel readout and a second pixel readout for each selected pixel; wherein the first pixel readout corresponds to a pixel being read out a predetermined amount of time after resetting the pixel, and Wherein the second pixel readout corresponds to a pixel being read out directly after having been reset.

10. The image sensor of claim 9 , wherein the readout circuitry is configured to readout the column lines based on a charge-mode readout, wherein each readout unit is configured to set the voltage on the input node equal to a third reference voltage during the first pixel readout and the second pixel readout, and wherein each readout unit is configured to determine an output voltage for each pixel based on charge transfer during the second pixel readout to and from the capacitor unit.

11. The image sensor according to claim 10 , wherein each readout unit includes a charge amplifier, the charge amplifier including an operational amplifier having a non-inverting input terminal connected to the third reference voltage and an inverting input terminal connected to the capacitance unit via a first switch, wherein an output terminal of the operational amplifier is coupled to the inverting input terminal via a feedback capacitor, and the readout unit further includes a second switch arranged between the output terminal and the inverting input terminal of the operational amplifier.

12. The image sensor of claim 11, wherein the readout circuitry comprises a plurality of analog-to-digital converters (ADCs) coupled to the outputs of the operational amplifiers of the readout cells; in, The image sensor includes a second controller configured to control the first switch and the second switch so that the voltage at the input node is set to the third reference voltage by closing the first switch and the second switch during the first pixel readout, and so that the second switch is opened when the second pixel readout is performed, and is configured to control the first switch to be opened when the output of the operational amplifier is converted by an ADC among the multiple ADCs.

13. The image sensor of claim 9 , wherein the readout circuit system is configured to read out the column lines based on a voltage mode readout, wherein each readout unit is configured to set the voltage on the input node to be equal to a fourth reference voltage during the first pixel readout, and to determine the output voltage based on a change in the voltage of the input node relative to the fourth reference voltage during the second pixel readout.

14. The image sensor according to claim 13, each readout unit further includes a voltage setting unit for setting the voltage on the input node to the fourth reference voltage during the first pixel readout, and for providing a high impedance state during the second pixel readout to allow the voltage on the input node to track the pixel voltage when the voltage on the input node changes from a value corresponding to the first pixel readout to a value corresponding to the second pixel readout.

15. The image sensor of claim 14, wherein the readout circuitry comprises a plurality of analog-to-digital converters (ADCs), and wherein each readout unit further comprises: a first operational amplifier having a non-inverting input terminal connected to the fourth reference voltage via a third switch and an inverting input terminal connected to an output terminal of the first operational amplifier; a charge amplifier comprising a second operational amplifier having a non-inverting input connected to a fifth reference voltage and an inverting input connected to the output of the first operational amplifier via a series capacitor and a series fourth switch and connected to the output of the second operational amplifier via a parallel connection of a feedback capacitor and a fifth switch, wherein the output of the second operational amplifier is connected to an ADC of the plurality of ADCs; as well as A third controller is configured to: controlling the third switch to be closed during the first pixel readout period and to be open during the second pixel readout period; controlling the fourth switch to be closed during the first pixel readout and the second pixel readout and to be open after the second pixel readout to allow the output of the second operational amplifier to be converted by the connected ADC; The fifth switch is controlled to be open during the first pixel readout period and closed during the second pixel readout period.

16. The image sensor according to claim 1, wherein The capacitance unit is a capacitor.

17. The image sensor according to claim 1, wherein: The voltage range defined by the first voltage and the second voltage is large enough to allow for variations in signal swing during operation, but also large enough to accommodate threshold variations of the thin film transistor 'TFT' panel over the life of the image sensor.

18. The image sensor according to claim 1, wherein The first maximum rated voltage of the readout circuit is defined as the maximum potential difference that can exist across low-voltage components while hardly reducing the life of the readout circuit, and the readout circuit system is implemented using the low-voltage components, and wherein the second maximum rated voltage of the capacitor unit is defined as the maximum potential difference that can exist across the capacitor unit while hardly reducing the life of the capacitor unit.

19. An imaging system comprising: The image sensor according to any one of claims 1 to 18; a processing unit for constructing an image based on output from the readout circuitry; The imaging system is configured to construct an X-ray image of the object.

20. The imaging system of claim 19, wherein: The imaging system further comprises an X-ray source positioned such that the object to be imaged can be arranged between the X-ray source and an image sensor.

Images