Display device and method of manufacturing a display device

Abstract

A display device and a method of manufacturing the display device are provided. The display device can include a first gate electrode, a buffer layer, a first active pattern, a source pattern and a drain pattern, an insulating layer, an oxygen supply pattern, a second active pattern, an insulating pattern, and a second gate electrode, the first gate electrode is positioned on a substrate, the buffer layer is positioned on the first gate electrode, the first active pattern is positioned on the buffer layer, overlaps the first gate electrode, and includes an oxide semiconductor, the source pattern and the drain pattern are respectively positioned on end portions of the first active pattern, the insulating layer overlaps the source pattern and the drain pattern on the buffer layer, the oxygen supply pattern is positioned on the insulating layer, overlaps the first active pattern, and supplies oxygen to the first active pattern, the second active pattern is positioned on the insulating layer and is spaced apart from the oxygen supply pattern, the second active pattern includes a channel region and a source region and a drain region, the insulating pattern is positioned on the channel region of the second active pattern, and the second gate electrode is positioned on the insulating pattern.

Description

Technical Field

[0001] This disclosure relates to display devices, and more specifically, to display devices including transistors. Background Technology

[0002] A display device may include pixels and drivers for driving the pixels. Each of the pixels and drivers may include a transistor.

[0003] The area where transistors are arranged can be reduced as the resolution of the display device increases and the dead zone of the display device decreases. Therefore, the electrical characteristics of transistors arranged in a relatively narrow space can be reduced. Summary of the Invention

[0004] The embodiments provide a display device including transistors with improved electrical characteristics.

[0005] The implementation provides a method for manufacturing a display device to reduce manufacturing costs and manufacturing time.

[0006] The display device according to the embodiments may include a first gate electrode, a buffer layer, a first active pattern, a source pattern and a drain pattern, an insulating layer, an oxygen supply pattern, a second active pattern, an insulating pattern and a second gate electrode, wherein the first gate electrode is disposed on a substrate, the buffer layer is disposed on the first gate electrode, the first active pattern is disposed on the buffer layer, overlaps with the first gate electrode and includes an oxide semiconductor, the source pattern and the drain pattern are respectively disposed on the ends of the first active pattern, the insulating layer overlaps with the source pattern and the drain pattern on the buffer layer, the oxygen supply pattern is disposed on the insulating layer, overlaps with the first active pattern and supplies oxygen to the first active pattern, the second active pattern is disposed on the insulating layer and spaced apart from the oxygen supply pattern, and the second active pattern includes a channel region and a source region and a drain region respectively disposed on the ends of the channel region, the insulating pattern is disposed on the channel region of the second active pattern, and the second gate electrode is disposed on the insulating pattern.

[0007] In an implementation, each of the oxygen supply pattern and the second active pattern may include an oxide semiconductor.

[0008] In an implementation, the oxygen supply pattern, the second active pattern, and the first active pattern may comprise the same material.

[0009] In an implementation, each of the oxygen supply pattern and the second active pattern may include a material different from the material of the first active pattern.

[0010] In an embodiment, the display device may further include an interlayer insulating layer overlapping the oxygen supply pattern and the second gate electrode on the insulating layer, a first source electrode and a first drain electrode disposed on the interlayer insulating layer and electrically connected to the source pattern and the drain pattern, respectively, and a second source electrode and a second drain electrode disposed on the interlayer insulating layer and electrically connected to the source region and the drain region, respectively.

[0011] In an embodiment, the display device may further include a planarization layer disposed on an interlayer insulating layer. The first source electrode may include a first lower source electrode disposed on the interlayer insulating layer and a first upper source electrode disposed on the planarization layer and electrically connected to the first lower source electrode. The first drain electrode may include a first lower drain electrode disposed on the interlayer insulating layer and a first upper drain electrode disposed on the planarization layer and electrically connected to the first lower drain electrode. The second source electrode may include a second lower source electrode disposed on the interlayer insulating layer and a second upper source electrode disposed on the planarization layer and electrically connected to the second lower source electrode. The second drain electrode may include a second lower drain electrode disposed on the interlayer insulating layer and a second upper drain electrode disposed on the planarization layer and electrically connected to the second lower drain electrode.

[0012] In an embodiment, the display device may further include a protective layer disposed between an interlayer insulating layer and a planarization layer, and overlapping with a first lower source electrode, a first lower drain electrode, a second lower source electrode, and a second lower drain electrode.

[0013] In one embodiment, the display device may further include a planarization layer disposed on an interlayer insulating layer. A first source electrode, a first drain electrode, a second source electrode, and a second drain electrode may be disposed on the planarization layer.

[0014] In an embodiment, the display device may further include a conductive pattern disposed between the substrate and the buffer layer and overlapping with the second active pattern.

[0015] In one embodiment, the conductive pattern may be electrically connected to the second source electrode or the second gate electrode.

[0016] In an embodiment, the display device may further include a data line disposed between the substrate and the buffer layer and electrically connected to the first drain electrode.

[0017] In an embodiment, the display device may further include a drive voltage line disposed between the substrate and the buffer layer and electrically connected to the second drain electrode.

[0018] The display device according to an embodiment may include a first transistor, an oxygen supply pattern, and a second transistor, wherein the first transistor is disposed on a substrate and has a bottom gate structure, the first transistor includes a first active pattern comprising an oxide semiconductor, the oxygen supply pattern is disposed on the first active pattern and supplies oxygen to the first active pattern, the second transistor is disposed on the substrate and has a top gate structure, and the second transistor includes a second active pattern. The oxygen supply pattern and the second active pattern may be disposed on the same layer.

[0019] In an embodiment, the display device may further include pixels and a scan driver, wherein the pixel includes a pixel circuit and a light-emitting element electrically connected to the pixel circuit, and the scan driver supplies a scan signal to the pixel circuit.

[0020] In an implementation, the pixel circuit may include a first transistor and a second transistor.

[0021] In one implementation, the second transistor may be electrically connected to the light-emitting element.

[0022] In an implementation, the scan driver may include a first transistor and a second transistor.

[0023] A method for manufacturing a display device according to an embodiment may include forming a first gate electrode on a substrate, forming a buffer layer on the first gate electrode, forming a first active pattern on the buffer layer that overlaps with the first gate electrode and includes an oxide semiconductor, forming a source pattern and a drain pattern at the ends of the first active pattern, forming an insulating layer on the buffer layer that overlaps with the source pattern and the drain pattern, simultaneously forming an oxygen supply pattern that overlaps with the first active pattern and a second active pattern spaced apart from the oxygen supply pattern on the insulating layer, forming an insulating pattern on the second active pattern, and forming a second gate electrode on the insulating pattern.

[0024] In an embodiment, the method may further include heat-treating the oxygen supply pattern after forming the oxygen supply pattern and before forming the insulating pattern to supply oxygen from the oxygen supply pattern to the first active pattern.

[0025] In one implementation, the first active pattern, the source pattern, and the drain pattern can be formed by using a halftone mask photolithography process.

[0026] The display device according to the embodiment may include an oxygen supply pattern disposed on a first active pattern of a first transistor having a bottom gate structure, the oxygen supply pattern and a second active pattern of a second transistor having a bottom gate structure being disposed on the same layer, and the oxygen supply pattern supplying oxygen to the first active pattern. Therefore, the electrical characteristics of the first transistor can be improved.

[0027] In the method for manufacturing a display device according to the embodiment, the oxygen supply pattern and the second active pattern can be formed substantially simultaneously. Therefore, an additional process for forming the oxygen supply pattern is not required, and the manufacturing cost and manufacturing time of the display device can be reduced. Attached Figure Description

[0028] The illustrative and non-limiting embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 This is a schematic plan view showing a display device according to an embodiment.

[0030] Figure 2 This is a schematic circuit diagram showing pixels according to an embodiment.

[0031] Figure 3 This is a schematic cross-sectional view showing pixels according to an embodiment.

[0032] Figure 4 This is a schematic cross-sectional view showing a scan driver according to an embodiment.

[0033] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G , Figure 5H , Figure 5I and Figure 5J This is a schematic cross-sectional view illustrating a method for manufacturing a display device according to an embodiment.

[0034] Figure 6 This is a schematic cross-sectional view showing pixels according to an embodiment.

[0035] Figure 7 This is a schematic cross-sectional view showing pixels according to an embodiment.

[0036] Figure 8 This is a schematic cross-sectional view illustrating a method for manufacturing a display device according to an embodiment.

[0037] Figure 9 This is a schematic cross-sectional view showing pixels according to an embodiment. Detailed Implementation

[0038] The display device and the method of manufacturing the display device according to the embodiments will be explained in detail below with reference to the accompanying drawings.

[0039] Unless otherwise defined or implied herein, all terms used (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless clearly defined in the specification, terms, such as those defined in common dictionaries, shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formal manner.

[0040] Figure 1 This is a schematic plan view showing a display device according to an embodiment.

[0041] Reference Figure 1 The display device may include pixels PX arranged in the display area DA and scan driver SD, driver chip IC and flexible printed circuit FPC arranged in the peripheral area PA.

[0042] Multiple pixels PX can be arranged in a display area DA along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. Each pixel PX can be electrically connected to a scan line SL, a data line DL, and a drive voltage line PL. The scan line SL extends along the first direction DR1 and provides a scan signal to the pixel PX. The data line DL extends along the second direction DR2 and provides a data signal to the pixel PX. The drive voltage line PL extends parallel to the data line DL and provides a drive voltage to the pixel PX. The display area DA can display an image using light emitted from each of the multiple pixels PX.

[0043] The peripheral region PA may be adjacent to the display region DA. In an embodiment, the peripheral region PA may surround the display region DA.

[0044] The scan driver SD can be disposed on the first side of the display area DA and can be electrically connected to the scan line SL. The scan driver SD can provide scan signals to the pixel PX through the scan line SL. The scan driver SD may include transistors.

[0045] The driver chip IC can be arranged on the second side of the display area DA and can be electrically connected to the data line DL. The driver chip IC may include a data driver that generates the data voltage.

[0046] A flexible printed circuit (FPC) can be disposed on the second side of the display area DA, and a driver chip IC is disposed between the FPC and the display area DA. The FPC can be electrically connected to the drive voltage line PL. The FPC may include a power supply device for generating the drive voltage. The power supply device can provide the drive voltage to the pixel PX via the drive voltage line PL.

[0047] Figure 2This is a schematic circuit diagram showing a pixel PX according to an embodiment.

[0048] Reference Figure 2 A pixel PX may include a pixel circuit PC and a light-emitting element EL electrically connected to the pixel circuit PC. In one embodiment, the pixel circuit PC may include a first transistor TR1, a second transistor TR2, and a capacitor CAP. However, the invention is not limited thereto, and in another embodiment, the pixel circuit PC may include three or more transistors and / or two or more capacitors.

[0049] The first transistor TR1 may be electrically connected to the data line DL and the node ND. The first transistor TR1 may include a first drain electrode that receives data voltage from the data line DL, a first source electrode that is electrically connected to the node ND, and a first gate electrode that receives scan signal from the scan line SL. The first transistor TR1 may transmit the data voltage to the node ND based on the scan signal.

[0050] The second transistor TR2 may be electrically connected to the drive voltage line PL and the light-emitting element EL. The second transistor TR2 may include a second drain electrode that receives a drive voltage from the drive voltage line PL, a second source electrode that is electrically connected to the light-emitting element EL, and a second gate electrode that is electrically connected to the node ND. The second transistor TR2 may provide a drive current DC to the light-emitting element EL based on the voltage between the second drain electrode and the second gate electrode.

[0051] A capacitor CAP may be electrically connected between the drive voltage line PL and the node ND. The capacitor CAP may include a first electrode receiving the drive voltage from the drive voltage line PL and a second electrode electrically connected to the node ND. When the first transistor TR1 is off, the capacitor CAP may maintain the voltage between the second drain electrode and the second gate electrode.

[0052] The light-emitting element EL can be electrically connected between the second transistor TR2 and a common power supply. The light-emitting element EL may include a first electrode electrically connected to the second transistor TR2 and a second electrode receiving a common voltage from the common power supply. The light-emitting element EL can emit light based on a drive current DC provided from the second transistor TR2.

[0053] Figure 3 This is a schematic cross-sectional view showing a pixel PX according to an embodiment.

[0054] Reference Figure 3 The pixel PX may include a first transistor TR1, a second transistor TR2, and a light-emitting element EL disposed on the substrate 100.

[0055] The substrate 100 may be a transparent insulating substrate. For example, the substrate 100 may be formed of glass, quartz, plastic, etc.

[0056] A first gate electrode 111 and a conductive pattern 112 may be disposed on the substrate 100. The first gate electrode 111 may be used as the gate electrode of a first transistor TR1. The conductive pattern 112 may be spaced apart from the first gate electrode 111. The conductive pattern 112 may prevent external light, impurities, etc. from flowing into the second transistor TR2 through the substrate 100. The first gate electrode 111 and the conductive pattern 112 may be formed of or include conductive materials such as molybdenum (Mo), copper (Cu), aluminum (Al), and titanium (Ti).

[0057] A buffer layer 120 may be disposed on the first gate electrode 111 and the conductive pattern 112. The buffer layer 120 may cover or overlap the first gate electrode 111 and the conductive pattern 112 on the substrate 100. The buffer layer 120 may prevent impurities from flowing in through the substrate 100. In addition, the buffer layer 120 may provide a planarized surface above the substrate 100. The buffer layer 120 may be formed of or include an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0058] A first active pattern 131 may be disposed on the buffer layer 120. The first active pattern 131 may overlap with the first gate electrode 111. The first active pattern 131 may be formed of an oxide semiconductor. The oxide semiconductor may include at least one oxide selected from indium (In), gallium (Ga), zinc (Zn), tin (Sn), titanium (Ti), zirconium (Zr), and hafnium (Hf).

[0059] An active pattern 141 and a drain pattern 142 may be disposed on the ends (or opposite ends) of the first active pattern 131. Each of the source pattern 141 and the drain pattern 142 may be formed of or include a conductive material such as molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), etc. The first active pattern 131 may be used as the channel region of the first transistor TR1, and the source pattern 141 and the drain pattern 142 may be used as the source region and drain region of the first transistor TR1, respectively.

[0060] The insulating layer 150 may cover or overlap the first active pattern 131, source pattern 141, and drain pattern 142 on the buffer layer 120. The insulating layer 150 may be formed of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0061] An oxygen supply pattern 161 and a second active pattern 162 may be arranged on the insulating layer 150. The oxygen supply pattern 161 may overlap with the first active pattern 131. The second active pattern 162 may be spaced apart from the oxygen supply pattern 161 and may overlap with the conductive pattern 112. The oxygen supply pattern 161 can supply oxygen to the first active pattern 131 through the insulating layer 150. For example, when the oxygen supply pattern 161 is formed on the insulating layer 150, oxygen can be supplied from the oxygen supply pattern 161 to the insulating layer 150. Then, if the oxygen supply pattern 161 is heat-treated, oxygen can be supplied from the insulating layer 150 to the first active pattern 131.

[0062] If the oxygen supply pattern 161 is not arranged on the first active pattern 131, the first active pattern 131 may have oxygen vacancies. In this case, the charge carriers (e.g., holes) in the first active pattern 131 may increase, thereby shifting the initial threshold voltage of the first transistor TR1.

[0063] However, in one embodiment, an oxygen supply pattern 161 disposed on the first active pattern 131 supplies oxygen to the first active pattern 131, thereby reducing oxygen vacancies in the first active pattern 131. Therefore, the initial threshold voltage shift of the first transistor TR1 can be reduced or substantially prevented. Thus, the electrical characteristics of the first transistor TR1 can be improved.

[0064] Each of the oxygen supply pattern 161 and the second active pattern 162 may be formed of an oxide semiconductor. The oxide semiconductor may include at least one oxide selected from indium (In), gallium (Ga), zinc (Zn), tin (Sn), titanium (Ti), zirconium (Zr), and hafnium (Hf). In one embodiment, each of the oxygen supply pattern 161 and the second active pattern 162 may include the same material as the first active pattern 131. In another embodiment, each of the oxygen supply pattern 161 and the second active pattern 162 may include a different material than the first active pattern 131.

[0065] The second active pattern 162 may include a channel region 162C, a source region 162S, and a drain region 162D respectively disposed at one end (or opposite end) of the channel region 162C. The source region 162S and the drain region 162D may be doped with P-type or N-type impurities, and the channel region 162C may be doped with impurities of a different type than those in the source region 162S and the drain region 162D. In an embodiment, the source region 162S and the drain region 162D may be doped with N-type impurities, and the channel region 162C may be doped with P-type impurities.

[0066] An insulating pattern 122 may be arranged on the channel region 162C of the second active pattern 162. The insulating pattern 122 may be formed of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0067] A second gate electrode 172 may be arranged on the insulating pattern 122. The second gate electrode 172 may overlap with the channel region 162C of the second active pattern 162. The second gate electrode 172 may be used as the gate electrode of the second transistor TR2. The second gate electrode 172 may be formed of a conductive material such as molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), etc.

[0068] In one embodiment, the second gate electrode 172 may be electrically connected to the conductive pattern 112. In this embodiment, the second gate electrode 172 may serve as the upper gate electrode of the second transistor TR2, and the conductive pattern 112 may serve as the lower gate electrode of the second transistor TR2. Therefore, the second transistor TR2 may have a dual-gate structure, and the second transistor TR2 may have a relatively high electron mobility.

[0069] The first gate electrode 111, the first active pattern 131, the source pattern 141, and the drain pattern 142 can form a first transistor TR1. The first transistor TR1 may have a bottom gate structure in which the first gate electrode 111 is arranged below the first active pattern 131.

[0070] A second active pattern 162, including a channel region 162C, a source region 162S, and a drain region 162D, and a second gate electrode 172, can form a second transistor TR2. The second transistor TR2 may have a top-gate structure in which the second gate electrode 172 is disposed above or on the second active pattern 162.

[0071] Despite Figure 3 Not shown in the image, but Figure 2 Each of the first and second electrodes of the capacitor CAP, as well as one of the first gate electrode 111, the first active pattern 131, the source pattern 141, the oxygen supply pattern 161, and the second gate electrode 172, may be arranged on the same layer. For example, the first electrode of the capacitor CAP may be arranged on the same layer as the source pattern 141, and the second electrode of the capacitor CAP may be arranged on the same layer as the second gate electrode 172.

[0072] An interlayer insulating layer 180 may be disposed on the oxygen supply pattern 161 and the second gate electrode 172. The interlayer insulating layer 180 may cover or overlap the oxygen supply pattern 161, the second gate electrode 172, and the second active pattern 162 on the insulating layer 150. The interlayer insulating layer 180 may be formed of or include inorganic insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride.

[0073] A first source electrode S1, a first drain electrode D1, a second source electrode S2, and a second drain electrode D2 may be arranged on the interlayer insulating layer 180. The first source electrode S1 may be electrically connected to the source pattern 141, and the first drain electrode D1 may be electrically connected to the drain pattern 142. The second source electrode S2 may be electrically connected to the source region 162S, and the second drain electrode D2 may be electrically connected to the drain region 162D.

[0074] In this embodiment, the second source electrode S2 may be electrically connected to the conductive pattern 112. In this case, the output saturation characteristics of the second transistor TR2 can be improved, and the driving range of the second transistor TR2 can be increased.

[0075] In this embodiment, the first source electrode S1 may include a first lower source electrode 191 and a first upper source electrode 221, and the first drain electrode D1 may include a first lower drain electrode 192 and a first upper drain electrode 222. The second source electrode S2 may include a second lower source electrode 193 and a second upper source electrode 223, and the second drain electrode D2 may include a second lower drain electrode 194 and a second upper drain electrode 224.

[0076] A first lower source electrode 191, a first lower drain electrode 192, a second lower source electrode 193, and a second lower drain electrode 194 may be disposed on the interlayer insulating layer 180. The first lower source electrode 191 may be electrically connected to the source pattern 141 through contact holes formed in the insulating layer 150 and the interlayer insulating layer 180, and the first lower drain electrode 192 may be electrically connected to the drain pattern 142 through contact holes formed in the insulating layer 150 and the interlayer insulating layer 180, or through contact holes formed in the insulating layer 150 and the interlayer insulating layer 180. The second lower source electrode 193 can be electrically connected to the source region 162S through a contact hole formed in the interlayer insulating layer 180 or through a contact hole formed in the interlayer insulating layer 180, and the second lower drain electrode 194 can be electrically connected to the drain region 162D through a contact hole formed in the interlayer insulating layer 180 or through a contact hole formed in the interlayer insulating layer 180. The first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193, and the second lower drain electrode 194 can be formed of conductive materials such as molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), etc.

[0077] A planarization layer 210 may be formed on the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193, and the second lower drain electrode 194. The planarization layer 210 may overlap with the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193, and the second lower drain electrode 194 on the interlayer insulating layer 180. The planarization layer 210 may be formed of an organic insulating material such as polyimide (PI).

[0078] A first upper source electrode 221, a first upper drain electrode 222, a second upper source electrode 223, and a second upper drain electrode 224 may be disposed on the planarization layer 210. The first upper source electrode 221 may be electrically connected to the first lower source electrode 191 through contact holes formed in the planarization layer 210, and the first upper drain electrode 222 may be electrically connected to the first lower drain electrode 192 through contact holes formed in the planarization layer 210. The second upper source electrode 223 may be electrically connected to the second lower source electrode 193 through contact holes formed in the planarization layer 210, and the second upper drain electrode 224 may be electrically connected to the second lower drain electrode 194 through contact holes formed in the planarization layer 210. The first upper source electrode 221, the first upper drain electrode 222, the second upper source electrode 223, and the second upper drain electrode 224 may be formed of or include conductive materials such as metals, alloys, or transparent conductive oxides. For example, the conductive material may include silver (Ag), indium tin oxide (ITO), etc.

[0079] A first electrode 230 may be disposed on the planarization layer 210. A second upper source electrode 223 may extend to form the first electrode 230. In other words, the first electrode 230 and the second upper source electrode 223 may be integral with each other. Therefore, the first electrode 230 may be electrically connected to the second transistor TR2.

[0080] Because the second transistor TR2 continuously supplies the drive current DC to the light-emitting element EL, the reliability of the second transistor TR2 against positive bias is important. Compared to the first transistor TR1 with a bottom-gate structure, the second transistor TR2 with a top-gate structure can have the desired reliability against positive bias. Therefore, it is advantageous for the first electrode 230 to be electrically connected to the second transistor TR2 instead of the first transistor TR1.

[0081] A pixel defining layer 240 may be disposed on the first upper source electrode 221, the first upper drain electrode 222, the second upper source electrode 223, the second upper drain electrode 224, and the first electrode 230. The pixel defining layer 240 may overlap with the first upper source electrode 221, the first upper drain electrode 222, the second upper source electrode 223, the second upper drain electrode 224, and the first electrode 230 on the planarization layer 210. The pixel defining layer 240 may include a pixel opening that exposes at least a portion of the first electrode 230. In an embodiment, the pixel opening may expose a central portion of the first electrode 230, and the pixel defining layer 240 may overlap with a peripheral portion of the first electrode 230. The pixel defining layer 240 may be formed of an organic insulating material such as polyimide (PI).

[0082] An emission layer 250 may be disposed on the first electrode 230. The emission layer 250 may be disposed on the first electrode 230 exposed by the pixel opening. The emission layer 250 may be formed of at least one of organic light-emitting materials and quantum dots.

[0083] In this embodiment, the organic light-emitting material may include low-molecular-weight organic compounds or high-molecular-weight organic compounds. For example, low-molecular-weight organic compounds may include copper phthalocyanine, N,N'-diphenylbenzidine, aluminum trihydroxyquinoline (tri-(8-hydroxyquinoline)aluminum), etc. High-molecular-weight organic compounds may include poly(3,4-ethylenedioxythiophene), polyaniline, poly(p-phenylacetylene), polyfluorene, etc.

[0084] In one embodiment, the quantum dot may include a core comprising group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and combinations thereof. In one embodiment, the quantum dot may have a core-shell structure comprising a core and a shell surrounding the core. The shell prevents chemical denaturation of the core, thereby serving as a protective layer for maintaining semiconductor properties and a charging layer for imparting electrophoretic properties to the quantum dot.

[0085] A second electrode 260 may be disposed on the emitting layer 250. In an embodiment, the second electrode 260 may also be disposed on the pixel defining layer 240. The second electrode 260 may be formed of a conductive material such as a metal, alloy, or transparent conductive oxide. For example, the conductive material may include aluminum (Al), platinum (Pt), silver (Ag), magnesium (Mg), gold (Au), chromium (Cr), tungsten (W), titanium (Ti), etc. The first electrode 230, the emitting layer 250, and the second electrode 260 may form a light-emitting element EL.

[0086] Figure 4 This is a schematic cross-sectional view showing a scan drive SD according to an embodiment.

[0087] Reference Figure 4The scan driver SD may include a first transistor TR1 and a second transistor TR2 disposed on the substrate 100. Except that the pixel defining layer 240 does not include a pixel opening and the scan driver SD does not include a light-emitting element EL, see reference... Figure 4 The described scan drive SD is essentially the same as the reference. Figure 3 The described pixels PX are the same or similar. Therefore, duplicate descriptions will be omitted.

[0088] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G , Figure 5H , Figure 5I and Figure 5J This is a schematic cross-sectional view illustrating a method for manufacturing a display device according to an embodiment.

[0089] Reference Figure 5A The first gate electrode 111 and the conductive pattern 112 may be formed on the substrate 100, and the buffer layer 120 may be formed on the first gate electrode 111 and the conductive pattern 112.

[0090] First, a conductive layer may be formed on the substrate 100, and the conductive layer may be etched to form a first gate electrode 111 and a conductive pattern 112. Then, a buffer layer 120 overlapping the first gate electrode 111 and the conductive pattern 112 may be formed on the substrate 100.

[0091] Reference Figure 5B , Figure 5C and Figure 5D A first active pattern 131, a source pattern 141, and a drain pattern 142 can be formed on the buffer layer 120.

[0092] In one embodiment, the first active pattern 131, the source pattern 141, and the drain pattern 142 can be formed by photolithography using a halftone mask 410.

[0093] First, an active layer 130 and a conductive layer 140 can be sequentially formed on the buffer layer 120. Then, a photoresist layer can be formed on the conductive layer 140, and the photoresist layer can be patterned using a halftone mask 410 to form a photoresist pattern 310.

[0094] The halftone mask 410 may include a light-blocking portion 411, a light-transmitting portion 412, and a semi-transparent portion 413. The light-blocking portion 411 blocks most of the external light, and the light-transmitting portion 412 transmits most of the external light. The semi-transparent portion 413 may have a transmittance greater than that of the light-blocking portion 411 and less than that of the light-transmitting portion 412. The light-blocking portion 411 may be positioned corresponding to the source pattern 141 and the drain pattern 142, and the semi-transparent portion 413 may be positioned corresponding to a portion of the first active pattern 131 located between the source pattern 141 and the drain pattern 142.

[0095] A halftone mask 410 can be used to expose and develop the photoresist layer so as to form a photoresist pattern 310. The photoresist pattern 310 may include a first portion 311 and a second portion 312 protruding from an end (or opposite end) of the first portion 311.

[0096] Then, the photoresist pattern 310 can be used as an etching mask to etch the active layer 130 and the conductive layer 140 to form the first active pattern 131 and the conductive pattern 140a. The photoresist pattern 310 can then be ashed to retain a second portion 312 of the photoresist pattern 310. The second portion 312 of the photoresist pattern 310 can then be used as an etching mask to etch the conductive pattern 140a to form the source pattern 141 and the drain pattern 142. Therefore, the first active pattern 131, the source pattern 141, and the drain pattern 142 can be formed by photolithography.

[0097] Reference Figure 5E An insulating layer 150 may be formed on the first active pattern 131, the source pattern 141, and the drain pattern 142; and an oxide semiconductor layer 160 may be formed on the insulating layer 150. In an embodiment, after the oxide semiconductor layer 160 is formed, it may be heat-treated. During the formation of the oxide semiconductor layer 160 on the insulating layer 150 or the heat treatment of the oxide semiconductor layer 160, oxygen may be supplied from the oxide semiconductor layer 160 to the insulating layer 150.

[0098] Reference Figure 5F An oxygen supply pattern 161 and a second active pattern 162 can be formed on the insulating layer 150.

[0099] First, an etchable oxide semiconductor layer 160 is used to form an oxygen supply pattern 161 and a second active pattern 162. Thus, the oxygen supply pattern 161 and the second active pattern 162 can be formed substantially simultaneously.

[0100] Then, in an embodiment, the oxygen supply pattern 161 may be heat-treated to supply oxygen to the first active pattern 131. The first active pattern 131 may include oxygen vacancies. Oxygen can be supplied from the insulating layer 150 to the first active pattern 131 by heat-treating the oxygen supply pattern 161, thereby reducing the oxygen vacancies in the first active pattern 131.

[0101] Reference Figure 5G and Figure 5H An insulating pattern 122 and a second gate electrode 172 can be formed on the second active pattern 162.

[0102] First, an insulating layer 121 overlapping the oxygen supply pattern 161 and the second active pattern 162 can be formed on the insulating layer 150, and a conductive layer can be formed on the insulating layer 121. Next, the conductive layer can be etched to form a second gate electrode 172. Then, the second gate electrode 172 can be used as an etching mask to etch the insulating layer 121 to form an insulating pattern 122.

[0103] Reference Figure 5I An interlayer insulating layer 180 may be formed on the oxygen supply pattern 161 and the second gate electrode 172; and a first lower source electrode 191, a first lower drain electrode 192, a second lower source electrode 193 and a second lower drain electrode 194 may be formed on the interlayer insulating layer 180.

[0104] First, an interlayer insulating layer 180 may be formed on the insulating layer 150, overlapping the oxygen supply pattern 161, the second gate electrode 172, and the second active pattern 162. The interlayer insulating layer 180 may contact the second active pattern 162 so that impurities may be injected into the ends (or opposite ends) of the second active pattern 162 to form source region 162S and drain region 162D.

[0105] Next, contact holes exposing the source pattern 141 and the drain pattern 142 can be formed in the interlayer insulating layer 180 and the insulating layer 150, respectively; and contact holes exposing the source region 162S and the drain region 162D can be formed in the interlayer insulating layer 180, respectively. Then, a conductive layer filling the contact holes can be formed on the interlayer insulating layer 180; and the conductive layer can be etched to form a first lower source electrode 191, a first lower drain electrode 192, a second lower source electrode 193, and a second lower drain electrode 194.

[0106] Reference Figure 5J A planarization layer 210 may be formed on the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193, and the second lower drain electrode 194; and a first upper source electrode 221, a first upper drain electrode 222, a second upper source electrode 223, and a second upper drain electrode 224 may be formed on the planarization layer 210.

[0107] First, a planarization layer 210 overlapping the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193, and the second lower drain electrode 194 can be formed on the interlayer insulating layer 180. Then, contact holes exposing the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193, and the second lower drain electrode 194 can be formed in the planarization layer 210. Next, a conductive layer filling the contact holes can be formed on the planarization layer 210; and this conductive layer can be etched to form the first upper source electrode 221, the first upper drain electrode 222, the second upper source electrode 223, and the second upper drain electrode 224.

[0108] Figure 6 This is a schematic cross-sectional view showing a pixel PX according to an embodiment.

[0109] In addition to the pixel PX, it also includes a protective layer 200, as shown in the reference. Figure 6 The described pixel PX can be basically compared with the reference. Figure 3 The described pixels PX are the same or similar. Therefore, duplicate descriptions will be omitted.

[0110] Reference Figure 6 In one embodiment, the protective layer 200 may be disposed between the interlayer insulating layer 180 and the planarization layer 210. The protective layer 200 may overlap with the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193, and the second lower drain electrode 194 on the interlayer insulating layer 180. The protective layer 200 may be formed of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. If the planarization layer 210 formed of organic insulating material is directly disposed on the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193, and the second lower drain electrode 194 (in other words, if the planarization layer 210 directly contacts the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193, and the second lower drain electrode 194), then the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193, and the second lower drain electrode 194 formed of copper (Cu) or the like can be corroded by chemical reaction with the planarization layer 210. However, in an embodiment, the protective layer 200 overlapping the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193, and the second lower drain electrode 194 can be arranged between the interlayer insulating layer 180 and the planarization layer 210, so that the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193, and the second lower drain electrode 194 are not corroded.

[0111] Figure 7 This is a schematic cross-sectional view showing a pixel PX according to an embodiment.

[0112] In addition to the structure of the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2, refer to Figure 7 The described pixel PX can be basically compared with the reference. Figure 3 The described pixels PX are the same or similar. Therefore, duplicate descriptions will be omitted.

[0113] Reference Figure 7 In this embodiment, the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 can be arranged on the planarization layer 210. The first source electrode S1 can be electrically connected to the source pattern 141 through contact holes formed in the insulating layer 150, the interlayer insulating layer 180, and the planarization layer 210, or through contact holes formed in the insulating layer 150, the interlayer insulating layer 180, and the planarization layer 210. Similarly, the first drain electrode D1 can be electrically connected to the drain pattern 142 through contact holes formed in the insulating layer 150, the interlayer insulating layer 180, and the planarization layer 210, or through contact holes formed in the insulating layer 150, the interlayer insulating layer 180, and the planarization layer 210. The second source electrode S2 can be electrically connected to the source region 162S through contact holes formed in the interlayer insulating layer 180 and the planarization layer 210, and the second drain electrode D2 can be electrically connected to the drain region 162D through contact holes formed in the interlayer insulating layer 180 and the planarization layer 210. The first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 can be formed (or include) conductive materials such as metals, alloys, transparent conductive oxides, etc. For example, conductive materials may include silver (Ag), indium tin oxide (ITO), etc.

[0114] The first electrode 230 may be disposed on the planarization layer 210. The second source electrode S2 may extend to form the first electrode 230. In other words, the first electrode 230 and the second source electrode S2 may be integral with each other.

[0115] Figure 8 This is a schematic cross-sectional view illustrating a method for manufacturing a display device according to an embodiment.

[0116] In addition to the formation of the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2, refer to Figures 5A to 5H and Figure 8 The method for manufacturing the display device described herein can be referenced. Figures 5A to 5J The methods for manufacturing the display devices are substantially the same or similar. Therefore, repeated descriptions will be omitted.

[0117] Reference Figure 8An interlayer insulating layer 180 and a planarization layer 210 may be formed on the oxygen supply pattern 161 and the second gate electrode 172, and a first source electrode S1, a first drain electrode D1, a second source electrode S2 and a second drain electrode D2 may be formed on the planarization layer 210.

[0118] First, an interlayer insulating layer 180 overlapping the oxygen supply pattern 161, the second gate electrode 172, and the second active pattern 162 can be formed on the insulating layer 150. Next, a planarization layer 210 can be formed on the interlayer insulating layer 180.

[0119] Then, contact holes exposing the source pattern 141 and the drain pattern 142, respectively, can be formed in the insulating layer 150, the interlayer insulating layer 180, and the planarization layer 210; contact holes exposing the source region 162S and the drain region 162D, respectively, can be formed in the interlayer insulating layer 180 and the planarization layer 210. Then, a conductive layer filling the contact holes can be formed on the planarization layer 210; and the conductive layer can be etched to form the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2.

[0120] Figure 9 This is a schematic cross-sectional view showing a pixel PX according to an embodiment.

[0121] In addition to the pixel PX, it also includes data line 113 and drive voltage line 114, see reference Figure 9 The described pixel PX can be basically compared with the reference. Figure 7 The described pixels PX are the same or similar. Therefore, duplicate descriptions will be omitted.

[0122] Reference Figure 9 In one embodiment, data line 113 and drive voltage line 114 may be arranged between substrate 100 and buffer layer 120. Data line 113, drive voltage line 114, first gate electrode 111, and conductive pattern 112 may be formed on substantially the same layer, may be formed of substantially the same material, and may be spaced apart from each other. Data line 113 and drive voltage line 114 may be spaced apart from first gate electrode 111 and conductive pattern 112.

[0123] Data line 113 can be electrically connected to the first drain electrode D1. For example, the first drain electrode D1 can make electrical contact with data line 113 through contact holes formed in buffer layer 120, insulating layer 150, interlayer insulating layer 180, and planarization layer 210, or through contact holes formed in buffer layer 120, insulating layer 150, interlayer insulating layer 180, and planarization layer 210. Drive voltage line 114 can be electrically connected to the second drain electrode D2. For example, the second drain electrode D2 can make electrical contact with drive voltage line 114 through contact holes formed in buffer layer 120, insulating layer 150, interlayer insulating layer 180, and planarization layer 210, or through contact holes formed in buffer layer 120, insulating layer 150, interlayer insulating layer 180, and planarization layer 210.

[0124] The display device according to the embodiments can be applied to display devices including computers, laptops, mobile phones, smartphones, smart tablets, PMPs, PDAs, MP3 players, etc.

[0125] Although a display device and a method of manufacturing a display device according to embodiments have been described with reference to the accompanying drawings, the embodiments shown are examples and may be modified and altered by those skilled in the art without departing from the spirit of the technology described in the appended claims.

Claims

1. A display device, comprising: A first gate electrode is disposed on a substrate; A buffer layer is disposed on the first gate electrode; A first active pattern is disposed on the buffer layer, overlaps with the first gate electrode, and includes an oxide semiconductor. A source pattern and a drain pattern, wherein the source pattern and the drain pattern are respectively arranged on the ends of the first active pattern; An insulating layer that overlaps with the source pattern and the drain pattern on the buffer layer; An oxygen supply pattern is disposed on the insulating layer, overlaps with the first active pattern, and supplies oxygen to the first active pattern; A second active pattern is disposed on the insulating layer and is completely spaced apart from the oxygen supply pattern in a direction parallel to the main surface of the substrate. The second active pattern includes: Channel area; and A source region and a drain region are respectively arranged at the ends of the channel region; An insulating pattern, the insulating pattern being disposed on the channel region of the second active pattern; and The second gate electrode is disposed on the insulating pattern.

2. The display device according to claim 1, wherein, Each of the oxygen supply pattern and the second active pattern includes an oxide semiconductor.

3. The display device according to claim 2, wherein, The oxygen supply pattern, the second active pattern, and the first active pattern all comprise the same material.

4. The display device according to claim 2, wherein, Each of the oxygen supply pattern and the second active pattern includes a material different from the material of the first active pattern.

5. The display device according to claim 1, further comprising: An interlayer insulating layer, wherein the interlayer insulating layer overlaps with the oxygen supply pattern on the insulating layer and the second gate electrode; A first source electrode and a first drain electrode are disposed on the interlayer insulating layer and electrically connected to the source pattern and the drain pattern, respectively. as well as A second source electrode and a second drain electrode are disposed on the interlayer insulating layer and electrically connected to the source region and the drain region, respectively.

6. The display device according to claim 5, further comprising a planarization layer disposed on the interlayer insulating layer, wherein, The first source electrode includes: A first lower source electrode, the first lower source electrode being disposed on the interlayer insulating layer; and A first upper source electrode is disposed on the planarization layer and electrically connected to the first lower source electrode. The first drain electrode includes: A first lower drain electrode, the first lower drain electrode being disposed on the interlayer insulating layer; and A first upper drain electrode is disposed on the planarization layer and electrically connected to the first lower drain electrode. The second source electrode includes: The second lower source electrode is disposed on the interlayer insulating layer; and The second upper source electrode is disposed on the planarization layer and electrically connected to the second lower source electrode. The second drain electrode includes: The second lower drain electrode is disposed on the interlayer insulating layer; and The second upper drain electrode is disposed on the planarization layer and electrically connected to the second lower drain electrode.

7. The display device according to claim 6, further comprising: A protective layer is disposed between the interlayer insulating layer and the planarization layer and overlaps with the first lower source electrode, the first lower drain electrode, the second lower source electrode, and the second lower drain electrode.

8. The display device according to claim 5, further comprising: A planarization layer, wherein the planarization layer is disposed on the interlayer insulating layer. The first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are arranged on the planarization layer.

9. The display device according to claim 5, further comprising: A conductive pattern is disposed between the substrate and the buffer layer and overlaps with the second active pattern.

10. The display device according to claim 9, wherein, The conductive pattern is electrically connected to the second source electrode or the second gate electrode.

11. The display device according to claim 5, further comprising: A data line is disposed between the substrate and the buffer layer and is electrically connected to the first drain electrode.

12. The display device according to claim 5, further comprising: A driving voltage line is disposed between the substrate and the buffer layer and electrically connected to the second drain electrode.

13. A display device, comprising: A first transistor, disposed on a substrate and having a bottom gate structure, the first transistor including a first active pattern comprising an oxide semiconductor; An oxygen supply pattern is arranged on the first active pattern and supplies oxygen to the first active pattern; as well as A second transistor, disposed on the substrate and having a top-gate structure, includes a second active pattern, wherein... The oxygen supply pattern and the second active pattern are arranged on the same layer.

14. The display device according to claim 13, further comprising: A pixel, the pixel comprising a pixel circuit and a light-emitting element electrically connected to the pixel circuit; as well as A scan driver that supplies scan signals to the pixel circuit.

15. The display device according to claim 14, wherein, The pixel circuit includes the first transistor and the second transistor.

16. The display device according to claim 15, wherein, The second transistor is electrically connected to the light-emitting element.

17. The display device according to claim 14, wherein, The scan driver includes the first transistor and the second transistor.

18. A method of manufacturing a display device, the method comprising: A first gate electrode is formed on the substrate; A buffer layer is formed on the first gate electrode; A first active pattern, which overlaps with the first gate electrode and includes an oxide semiconductor, is formed on the buffer layer; A source pattern and a drain pattern are formed at the ends of the first active pattern, respectively; An insulating layer overlapping the source pattern and the drain pattern is formed on the buffer layer; An oxygen supply pattern overlapping the first active pattern and a second active pattern completely spaced apart from the oxygen supply pattern in a direction parallel to the main surface of the substrate are simultaneously formed on the insulating layer. An insulating pattern is formed on the second active pattern; as well as A second gate electrode is formed on the insulating pattern.

19. The method of claim 18, further comprising: After the oxygen supply pattern is formed and before the insulation pattern is formed, the oxygen supply pattern is heat-treated to supply oxygen from the oxygen supply pattern to the first active pattern.

20. The method according to claim 18, wherein, The first active pattern, the source pattern, and the leak pattern are formed using a halftone mask photolithography process.

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