Adaptive ramp signal generation

Abstract

In some examples, a circuit (600) includes a first charging path including a first capacitor (604) coupled to a first output node (646). A second charging path includes a first switch (614) and a second capacitor (620). A third charging path includes a second switch (636) and a third capacitor (634). A first discharging path includes the second capacitor (620), a third switch (624) coupled between the second charging path and a second output node (656), and a fourth switch (616) coupled between the second charging path and a fourth node (654). A second discharging path includes the third capacitor (634), a fifth switch (630) coupled between the third charging path and the second output node (656), and a sixth switch (638) coupled between the third node and the fourth node (654).

Description

BACKGROUND

[0001] Switched mode power supplies (SMPSs) transfer power from an input power source to a load by switching one or more power transistors coupled through a switching node / terminal to an energy storage element, such as an inductor / transformer and / or a capacitor, which can be coupled to the load. The power transistors can be included in a power converter, which includes or can be coupled to the energy storage element. The SMPS can include an SMPS controller to provide one or more gate control signals to the power transistor(s). The generation of the gate control signals can be controlled at least in part by one or more ramp signals. SUMMARY

[0002] In at least some examples, a circuit includes a first charging path including a first capacitor coupled to a first output node. The circuit also includes a second charging path including a first switch and a second capacitor. The circuit also includes a third charging path including a second switch and a third capacitor. The circuit also includes a first discharging path including the second capacitor, a third switch coupled between the second charging path and the second output node, and a fourth switch coupled between the second charging path and a fourth node. The circuit also includes a second discharging path including the third capacitor, a fifth switch coupled between the third charging path and the second output node, and a sixth switch coupled between the third node and the fourth node.

[0003] In at least some examples, a circuit includes a current signal generation circuit configured to generate a current signal based on an input voltage value, an output voltage value, and an operating frequency. The circuit also includes a ramp signal generation circuit coupled to the current signal generation circuit and configured to generate a first ramp signal by charging a first capacitor based on the current signal, where a voltage of the first capacitor when charged is the first ramp signal. The ramp signal generation circuit is also configured to generate a second ramp signal by charging a second capacitor and a third capacitor based on a scaled version of the current signal. A voltage of the second capacitor when discharged is the second ramp signal during a first time period. A voltage of the third capacitor when discharged is the second ramp signal during a second time period. In this way, the second ramp signal can be referred to as a continuous ramp signal because it transitions from one falling signal (e.g., of the second capacitor) to another falling signal (e.g., of the third capacitor) with substantially no delay (e.g., no delay to recharge the second capacitor or the third capacitor).

[0004] In at least some examples, a system includes a power converter and a controller coupled to the power converter. The controller includes a current signal generation circuit configured to generate a current signal based on an input voltage value of the power converter, an output voltage value of the power converter, and a switching frequency of the power converter. The controller also includes a ramp signal generation circuit configured to generate a first ramp signal by charging a first capacitor based on the current signal, where a voltage of the first capacitor when charged is the first ramp signal. The ramp signal generation circuit is also configured to generate a second ramp signal by charging a second capacitor and a third capacitor based on a scaled version of the current signal. A voltage of the second capacitor when discharged is the second ramp signal during a first time period. A voltage of the third capacitor when discharged is the second ramp signal during a second time period. The controller also includes a comparator configured to compare the first ramp signal or the second ramp signal to an error signal determined at least in part from an output current of the power converter. The comparator is also configured to generate a pulse width modulation signal to specify a duty cycle of the power converter based on the comparison. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 A block diagram of an illustrative power delivery system is shown in accordance with various examples.

[0006] Figure 2 A graph of illustrative power converter signal waveforms is shown in accordance with various examples.

[0007] Figure 3 A graph of illustrative power converter signal waveforms is shown in accordance with various examples.

[0008] Figure 4 A graph of illustrative power converter signal waveforms is shown in accordance with various examples.

[0009] Figure 5 A schematic diagram of an illustrative current signal generation circuit is shown in accordance with various examples.

[0010] Figure 6 A schematic diagram of an illustrative ramp signal generation circuit is shown in accordance with various examples.

[0011] Figure 7 A graph of illustrative ramp and timing signal waveforms is shown in accordance with various examples.

[0012] Figure 8 A flow diagram of an illustrative method of ramp signal generation is shown in accordance with various examples.

[0013] Figure 9 A graph of illustrative operation of a power delivery state machine is shown in accordance with various examples. DETAILED DESCRIPTION

[0014] At least some power converters use a ramp signal when controlling the duty cycle of a switch of the power converter. For example, an error amplifier can output an error signal that is compared to a ramp signal. The error signal can indicate a deviation of an actual output of the power converter from a desired value of the output of the power converter, be proportional to the deviation, or have another relationship. Based on the relationship between the error signal and the ramp signal, the power converter can be controlled to operate in a certain manner. For example, in a buck power converter, the ramp signal can have a positive slope. When the value of the ramp signal reaches the value of the error signal, a high-side transistor that controls the power converter turns on or conducts. When the high-side transistor turns on, the buck power converter is said to be in a buck energize phase. Similarly, in a boost power converter, the ramp signal can have a negative slope. When the value of the ramp signal reaches the value of the error signal, a high-side transistor that controls the power converter turns on. When the high-side transistor turns on, the high-side transistor conducts, and the boost power converter is said to be in a boost de-energize phase. The amount of time or percentage of time that the high-side transistor is on in a given switching cycle of the power converter is the duty cycle of the high-side transistor. Moreover, in at least some examples, the duty cycle of the high-side transistor has a proportional relationship with the output of the power converter. For example, increasing the duty cycle of the high-side transistor increases the output value of the power converter, and decreasing the duty cycle of the high-side transistor decreases the output value of the power converter.

[0015] In some power converters, such as buck-boost power converters, this functionality is combined. For example, both a buck ramp signal and a boost ramp signal are generated and compared to an error signal to determine the duty cycle of a high-side transistor. To provide optimal operation of the power converter, the amplitudes of the buck and boost ramps can be controlled. In at least some examples, optimal operation of the power converter means that the power converter has stable switching behavior and the fastest possible response time to transient signal changes. For example, for a power converter configured to operate for a particular input voltage (VIN), output voltage (VOUT), or switching frequency (SW_FREQ), the buck and boost ramps can have a certain fixed slope value (e.g., a preconfigured value), a certain amplitude, etc. However, the same slope value, amplitude, or other characteristic of the buck and boost ramps can not provide the preferred performance of the power converter for another combination of VIN, VOUT, and SW_FREQ values. Thus, the power converter can have limited efficiency outside of a certain range of VIN, VOUT, and SW_FREQ. For example, the amount of time it takes for the buck or boost ramp to reach the error signal value can be longer than a preferred value, resulting in larger values of voltage overshoot and / or undershoot, and thus larger amplitude ripple. Thus, for some power converters designed to have a wide operating range, buck and boost ramps having a fixed slope or amplitude can not provide the preferred performance across the entire wide operating range. For example, in a power converter suitable for a VIN range of about 2.7 volts (V) to 36V, a VOUT range of about 0.8V to 21.26V, and a SW_FREQ range of about 200 kilohertz to about 2.2 megahertz, buck and boost ramps having a fixed slope or amplitude can not provide the preferred performance across the entire wide operating range.

[0016] In some examples, the ramp signal generation circuit generates a single ramp signal (e.g., a falling ramp signal or a rising ramp signal). In other examples, the ramp signal generation circuit generates multiple ramp signals (e.g., one or more falling ramp signals and one or more rising ramp signals). In at least some examples, the ramp signal is generated dynamically based at least in part on VIN, VOUT, and SW_FREQ. As such, when VIN, VOUT, and / or SW_FREQ vary, the ramp signal can compensate for the variation. For example, a ramp current (IRAMP) is generated based on a minimum of VIN or VOUT and a signal that includes information indicative of SW_FREQ. Subsequently, IRAMP is switched by one or more switches controlled according to multiple clock signals to charge multiple capacitors. The signal present at a node coupled to a top plate of a capacitor by a switch in some examples is the ramp signal. As such, the ramp signal varies with changes in VIN, VOUT, and / or SW_FREQ to provide a ramp slope and / or amplitude that is optimized for a particular combination of VIN, VOUT, and SW_FREQ.

[0017] Figure 1 A block diagram illustrating an illustrative power delivery system 100 is shown. In at least some examples, system 100 represents a consumer electronic device, such as a laptop computer, a tablet device, a smartphone, a wearable device, etc. In other examples, system 100 represents an enterprise electronic device, such as a server, a network appliance, etc. In other examples, system 100 represents an automobile. In general, system 100 represents any system that includes a switch mode power supply that receives VIN and generates VOUT to provide to a load.

[0018] In at least one example, system 100 includes a controller 102, a power converter 104, and a load 106. Power converter 104 is configured to regulate power delivery from a power source 108 that provides VIN as VOUT to load 106. In some examples, power source 108 is a battery, while in other examples, power source 108 is in the form of a main power supply, which itself can be an output of a converter or regulator. Further, in some examples, load 106 is a rechargeable battery, while in other examples, load 106 is one or more components, circuits, subsystems, etc., which can or can not include a rechargeable battery.

[0019] In at least some examples, the controller 102 includes an oscillator 110, a ramp signal generation circuit 112, a comparator 114, an error amplifier 116, an error amplifier 118, and a logic circuit 120. In some examples, the comparator 114 includes an output terminal and three input terminals, such that the comparator 114 compares a signal at the first input terminal to a signal at the third input terminal or compares a signal at the second input terminal to a signal at the third input terminal. In some examples, the comparator 114 includes a multiplexer to select between the first input terminal or the second input terminal for comparison to the third input terminal. In other examples, the comparator 114 represents two separate comparators. In such examples, a first of the comparators receives RAMP BU at a negative or inverting input terminal and CC at a positive or non-inverting input terminal. A second of the comparators receives RAMP BO at a negative or inverting input terminal and CC at a positive or non-inverting input terminal. Each comparator can provide an output signal to the logic circuit 120, or the output signals of the comparators can be processed (e.g., such as via a “logical OR” circuit) before being received by the logic circuit 120. For clarity of illustration, because both RAMP BO and RAMP BU are compared to CC, the comparator 114 is illustrated as receiving both RAMP BO and RAMP BU at the same terminal, but in practice can be modified in accordance with this specification.

[0020] In some examples, the controller 102 also includes a resistor 122, a capacitor 124, a resistor 126, a capacitor 128, and a current sense circuit 130. In at least some examples, the controller 102 also includes a frequency circuit 146. At least one example of the system 100 includes at least some aspects of the controller 102 and the power converter 104 on the same semiconductor die and / or in the same component package, while in other examples the controller 102 and the power converter 104 can be manufactured separately and configured to be coupled together. Further, at least some aspects of the controller 102 can be manufactured separately and coupled together. In some examples, the system 100 also includes a driver 103. In some implementations, the driver 103 can be a component of the controller 102, while in other implementations the controller 102 does not include the driver 103 and is configured to be coupled to the driver 103. In some examples, the power converter 104 includes a transistor 132, a transistor 134, a transistor 136, a transistor 138, and an inductor 140. In at least some examples, the power converter 104 also includes a capacitor 142. In various examples, the logic circuit 120 implements a state machine or other control method or algorithm to control the generation of control signals for controlling the driver 103 for generating gate control signals for controlling the transistors 132, 134, 136, and / or 138. In at least one implementation, the state machine implemented by the logic circuit 120 is substantially similar to the state machine described below with respect to FIG. 2. The logic circuit 120 performs control based at least in part on CLK, the output of the comparator 114, and a control scheme for operating the power converter 104 in a desired mode of operation. The specific architecture of the logic circuit 120 is not limiting herein. Figure 9 The controller 102 also includes a resistor 122, a capacitor 124, a resistor 126, a capacitor 128, and a current sense circuit 130. In at least some examples, the controller 102 also includes a frequency circuit 146. At least one example of the system 100 includes at least some aspects of the controller 102 and the power converter 104 on the same semiconductor die and / or in the same component package, while in other examples the controller 102 and the power converter 104 can be manufactured separately and configured to be coupled together. Further, at least some aspects of the controller 102 can be manufactured separately and coupled together. In some examples, the system 100 also includes a driver 103. In some implementations, the driver 103 can be a component of the controller 102, while in other implementations the controller 102 does not include the driver 103 and is configured to be coupled to the driver 103. In some examples, the power converter 104 includes a transistor 132, a transistor 134, a transistor 136, a transistor 138, and an inductor 140. In at least some examples, the power converter 104 also includes a capacitor 142. In various examples, the logic circuit 120 implements a state machine or other control method or algorithm to control the generation of control signals for controlling the driver 103 for generating gate control signals for controlling the transistors 132, 134, 136, and / or 138. In at least one implementation, the state machine implemented by the logic circuit 120 is substantially similar to the state machine described below with respect to FIG. 2. The logic circuit 120 performs control based at least in part on CLK, the output of the comparator 114, and a control scheme for operating the power converter 104 in a desired mode of operation. The specific architecture of the logic circuit 120 is not limiting herein.

[0021] In at least one example architecture, the frequency circuit 146 has an input terminal configured to be coupled to a ground node 152 through a resistor 150, and an output terminal coupled to a node 156. The oscillator 110 has an input terminal coupled to the node 156 and an output terminal coupled to a node 154. The ramp signal generation circuit 112 has a first input terminal coupled to the node 154, a second input terminal coupled to the power supply 108, and a third input terminal coupled to a node 158. The ramp signal generation circuit also has a first output terminal and a second output terminal, each coupled to a first input terminal (e.g., the negative or inverting input terminal) of the comparator 114. The comparator 114 also has a second input terminal (e.g., the positive or non-inverting input terminal) coupled to a node 160 and an output terminal coupled to an input terminal of the logic circuit 120.

[0022] The error amplifier 116 has a first input terminal (e.g., positive or non-inverting input) coupled to node 162, a second input terminal (e.g., negative or inverting input terminal) coupled to node 164, and an output terminal coupled to node 166. In at least some examples, node 162 is configured to receive a reference voltage (VREF) and node 164 is configured to receive a feedback signal (FB). In some examples, FB is output by a feedback circuit (not shown). In at least one example, the feedback circuit is a voltage divider (not shown) coupled between node 158 and ground node 152 and having an output at node 164. In at least some examples, the top plate of capacitor 124 is coupled to node 166 through resistor 122 and the bottom plate of capacitor 124 is coupled to ground node 152. The error amplifier 118 has a first input terminal (e.g., positive or non-inverting input) coupled to node 166, a second input terminal (e.g., negative or inverting input terminal) coupled to the output terminal of current sense circuit 130, and an output terminal coupled to node 160. In at least some examples, the top plate of capacitor 128 is coupled to node 160 through resistor 126 and the bottom plate of capacitor 128 is coupled to ground node 152. In some examples, logic circuit 120 has another input terminal coupled to node 154 and one or more output terminals. Each output terminal is configured to be coupled to driver 103. In some examples, driver 103 is a single component. In other examples, driver 103 represents multiple drivers, where each driver has an input terminal configured to be coupled to a respective output terminal of logic circuit 120. In at least some examples where driver 103 represents multiple drivers, each of the respective drivers is an inverter (not shown). Driver 103 includes one or more output terminals, each output terminal of driver 103 is configured to be coupled to a gate terminal of a respective one of transistors 132, 134, 136, and 138.

[0023] The transistor 132 has a drain terminal configured to be coupled to the power source 108, a source terminal coupled to the node 168, and a gate terminal coupled to an output terminal of the driver 103. The transistor 134 has a drain terminal coupled to the node 168, a source terminal coupled to the ground node 152, and a gate terminal coupled to another output terminal of the driver 103. The inductor 140 is coupled between the node 168 and the node 170. The transistor 136 has a drain terminal coupled to the node 158, a source terminal coupled to the node 170, and a gate terminal coupled to another output terminal of the driver 103. The transistor 138 has a drain terminal coupled to the node 170, a source terminal coupled to the ground node 152, and a gate terminal coupled to another output terminal of the driver 103. In at least some examples, the capacitor 142 is coupled between the node 158 and the ground node 152. Further, the current sense circuit 130 has an input terminal coupled to the node 158 and the load 106 is configured to be coupled to the power converter 104 at the node 158. The coupling of the current sense circuit 130 is merely an example of an arrangement of the current sense circuit 130. Various other implementations of the system 100 can include the current sense circuit 130 coupled to any other suitable node or component of the power converter 104.

[0024] In at least one example of operation of the system 100, the controller 102 controls the power converter 104 to provide VOUT at the node 158 to the load 106. For example, FB has a value proportional to VOUT and VREF indicates a desired value for FB. The error amplifier 116 outputs an error signal (VC) at the node 166 having a value based on a difference between VREF and VFB and filtered by the resistor 122 and the capacitor 124. The error amplifier 118 then outputs a second error signal (CC) at the node 160 having a value based on a difference between the error signal and a current sense signal (VSENSE) and filtered by the resistor 126 and the capacitor 128. In at least some examples, VSENSE is a voltage signal output by the current sense circuit 130 and having a voltage proportional to an inductor current (IL) of the power converter 104.

[0025] Oscillator 110 receives IOSC at node 156 and generates CLK based on IOSC. In at least some examples, oscillator 110 also generates one or more additional signals based on or derived from CLK. Although shown for simplicity as having only one coupling from oscillator 110 to ramp signal generation circuit 112, in at least some examples, system 100 includes multiple couplings between oscillator 110 and ramp signal generation circuit. The number of couplings may correspond to the number of different clock signals provided by oscillator 110 to ramp signal generation circuit 112. In other examples, ramp signal generation circuit includes a circuit system (not shown) configured to generate one or more additional clock signals derived from, for example, CLK received from oscillator 110. In at least some examples, IOSC is generated by frequency circuit 146 at least in part based on the value of resistor 150. The resistance value of resistor 150 may be referred to herein as RF. For example, IOSC is generated by frequency circuit 146 according to VREF / RF, where VREF has the same value as the value received at node 162, such as... Figure 1 As shown. Although not shown, alternatively, the VREF used to determine IOSC and provide it to the ramp signal generation circuit 112 may not be the same as the value received at node 162, but may be any suitable value other than the VREF value received at node 162. Therefore, in at least some examples, the value of IOSC varies with the resistance of resistor 150. In at least some examples, CLK is generated by charging a capacitor (not shown) using IOSC and comparing the voltage at the top plate of the capacitor with a threshold value via a comparator (not shown). When the voltage at the top plate of the capacitor exceeds the threshold, the comparator outputs CLK with an assert or logic high value. When the voltage at the top plate of the capacitor does not exceed the threshold, the comparator outputs CLK with a de-assert or logic low value. Thus, the frequency of CLK is controlled at least in part by the resistance value of resistor 150.

[0026] Based at least in part on CLK, VIN, and VOUT, ramp signal generation circuit 112 generates a buck ramp signal (RAMP BU) and a boost ramp signal (RAMP BO). In at least some examples, ramp signal generation circuit 112 generates RAMP BU and RAMP BO by selecting the one of VIN or VOUT that has the minimum value and performing one or more multiplication or division operations to generate IRAMP. In at least some examples, the multiplication or division is performed by one or more transistors (not shown) powered by a plurality of current sources (not shown) to generate IRAMP. Subsequently, ramp signal generation circuit controls one or more switches to provide IRAMP or a scaled version of IRAMP to a plurality of capacitors (not shown). This results in RAMP BU existing at the top plate of one of the capacitors and RAMP BO existing at a switch node between the two capacitors. Both RAMP BU and RAMP BO are output by ramp signal generation circuit 112 to comparator 114.

[0027] Comparator 114 compares RAMP BU and RAMP BO to CC. Based on the comparison, comparator 114 outputs a comparison result to logic circuit 120. In at least some examples, the comparison result is a pulse width modulation (PWM) signal, where a duty cycle of the PWM signal at least partially controls operation of power converter 104. Logic circuit 120 receives CLK from node 154 and the PWM signal output by comparator 114. Based on CLK and the PWM signal output by comparator 114, logic circuit 120 generates a plurality of control signals, where each control signal uniquely corresponds to one of transistor 132, transistor 134, transistor 136, or transistor 138. For example, at a rising edge of CLK, in one implementation, logic circuit 120 generates the plurality of control signals to operate power converter 104 in a particular mode of operation and continue to operate in that mode of operation until a minimum on-time has expired, CLK is inactive, and the PWM signal is inactive.

[0028] As described above, based on the control signals received from logic circuit 120, driver 103 generates gate control signals for controlling the power transistors of power converter 104. For example, driver 103 generates gate control signals that alternately and selectively turn on and turn off transistor 132, transistor 134, transistor 136, and / or transistor 138. This on and off sequence causes elements of power converter 104, such as inductor 140 and / or capacitor 142, to be powered on and powered off. The powering on and powering off provides buck, boost, and / or buck-boost functionality of power converter 104. Driver 103 is implemented according to any suitable architecture, the scope of which is not limited herein.

[0029] The power converter 104, when implemented as a buck-boost power converter, can operate in either a buck mode of operation or a boost mode of operation. To control the mode of operation of the power converter 104, the controller 102 provides gate control signals to one or more of the transistor 132, the transistor 134, the transistor 136, and / or the transistor 138. The value of each of these gate control signals determines whether the respective one of the transistor 132, the transistor 134, the transistor 136, and / or the transistor 138 receiving the gate control signal is in a conductive state (e.g., on) or a non-conductive state (e.g., off). To change the mode of operation of the power converter 104, the controller 102 modifies the value of one or more of the gate control signals to turn one or more of the transistor 132, the transistor 134, the transistor 136, and / or the transistor 138 on or off. Further, while remaining in a mode of operation of the power converter 104, the controller 102 can modify the value of one or more of the gate control signals, such as to alternatively turn one or more of the transistor 132, the transistor 134, the transistor 136, and / or the transistor 138 on and off.

[0030] In one example, the transistor 132, the transistor 134, the transistor 136, and / or the transistor 138 are controlled to be on (e.g., to conduct current between their respective drain and source terminals) and / or off (e.g., to stop conducting current between their respective drain and source terminals) based on signals received at their respective gate terminals. For example, one or more of the transistor 132, the transistor 134, the transistor 136, and / or the transistor 138 are controlled to be on or off based on gate control signals received from the controller 102 (e.g., as output by the driver 103 under control of the logic circuit 120). The transistor 132, the transistor 134, the transistor 136, and / or the transistor 138 can be turned on (or off) based on a value present at one or more of their respective gate terminals and / or source terminals or a relationship between values.

[0031] Figure 2 A graph 200 illustrating illustrative power converter signal waveforms is shown. The graph 200 illustrates signal waveforms present in at least some implementations of the system 100 when the power converter 104, also Figure 1 is operating in a buck mode of operation. Thus, reference is made to the Figure 1 system 100 when describing the graph 200. The graph 200 illustrates the voltage at the input terminal 110 (labeled as VIN), the voltage at the output terminal 112 (labeled as VOUT), the voltage at the gate terminal of the transistor 132 (labeled as Vgate132), the voltage at the gate terminal of the transistor 134 (labeled as Vgate134), the voltage at the gate terminal of the transistor 136 (labeled as Vgate136), and the voltage at the gate terminal of the transistor 138 (labeled as Vgate138). The graph 200 also illustrates the current through the transistor 132 (labeled as I132), the current through the transistor 134 (labeled as I134), the current through the transistor 136 (labeled as I136), and the current through the transistor 138 (labeled as I138). Figure 1The graph 200 illustrates signals present in at least some implementations of the system 100 when the power converter 104 is operating in the step-down mode of operation. Thus, reference is made to the components of FIG. 1 in describing the graph 200. Illustrated in the graph 200 are IL and VOUT (e.g., each present at node 158) and VIN (e.g., provided by the power source 108). Further illustrated in the graph 200 are the signals VC, VSENSE, RAMP_BU, RAMP_BU present at node 166, and CC present at node 160. In at least some examples, CC has a value determined from a difference between the illustrated signals VC and VSENSE.

[0032] As illustrated by the graph 200, when the power converter 104 is operating in the step-down mode of operation and the comparator 114 determines that the value of CC is greater than RAMP_BU, the values of IL and VOUT increase. For example, when the value of CC is greater than RAMP_BU, the power converter 104 is controlled to operate in a step-down power-up phase in which the transistors 132 and 136 are controlled to be on and the transistors 134 and 138 are controlled to be off. During the step-down power-up phase, the inductor 140 is charged or powered up. When the power converter 104 is operating in the step-down mode of operation and the comparator 114 determines that the value of CC is not greater than RAMP_BU, the values of IL and VOUT decrease. For example, when the value of CC is not greater than RAMP_BU, the power converter 104 is controlled to operate in a step-down power-down phase in which the transistors 134 and 136 are controlled to be on and the transistors 132 and 138 are controlled to be off. During the step-down power-down phase, the inductor 140 is discharged or powered down.

[0033] Figure 3 A graph 300 illustrating illustrative power converter signal waveforms is shown. The graph 300 illustrates signal waveforms present in at least some implementations of the system 100 when the power converter 104 is operating in the step-up mode of operation. Thus, reference is made to the components of FIG. 1 in describing the graph 300. The signals illustrated in the graph 300 are the same as the signals in the graph 200 and are determined in the same manner. Thus, the description of the signals is not repeated. Figure 1 Figure 1 Figure 1

[0034] ​​​As shown in Figure 300, when the power converter 104 operates in boost mode and the comparator 114 determines that the value of CC is greater than RAMP_BO, the value of IL increases and the value of VOUT decreases. For example, when the value of CC is greater than RAMP_BO, the power converter 104 is controlled to operate in the boost-on phase, in which transistors 132 and 138 are controlled to be turned on, and transistors 134 and 136 are controlled to be turned off. During the boost-on phase, the inductor 140 is charged or energized. When the power converter 104 operates in boost mode and the comparator 114 determines that the value of CC is not greater than RAMP_BO, the value of IL decreases and the value of VOUT increases. For example, when the value of CC is not greater than RAMP_BO, the power converter 104 is controlled to operate in the boost-off phase, in which transistors 132 and 136 are controlled to be turned on, and transistors 134 and 138 are controlled to be turned off. During the boost-off phase, the inductor 140 is discharged or de-energized.

[0035] Figure 4 A graph 400 illustrates the signal waveform of an illustrative power converter. Graph 400 illustrates when the same... Figure 1 When the power converter 104 operates in buck-boost mode, Figure 1 The signal waveforms present in at least some embodiments of system 100. Therefore, reference is made when describing figure 400. Figure 1 The components. The signals illustrated in Figure 400 are the same as those in Figure 200 and are determined in the same way. Therefore, the description of the signals will not be repeated.

[0036] As illustrated in Figure 400, when the power converter 104 operates in buck-boost mode, the controller 102 controls the power converter 104 to operate in alternating buck and boost modes. For example, in the first switching cycle, the controller 102 controls the power converter 104 to operate in buck mode. In the second switching cycle, the controller 102 controls the power converter 104 to operate in boost mode. The operation in buck and boost modes is described above. Figure 2 and Figure 3 The descriptions are essentially the same. For example, control based on a comparison between RAMP_BU and CC occurs when operating in buck mode, and control based on a comparison between RAMP_BO and CC occurs when operating in boost mode. Therefore, regarding Figure 4 No more repeating Figure 2 and Figure 3 The description.

[0037] Figure 5A schematic diagram of an illustrative current signal generation circuit 500 is shown. At least some examples of circuit 500 are suitable for implementation as Figure 1 The components of the ramp signal generation circuit 112. Therefore, when describing circuit 500, reference can be made to... Figure 1 The components or signals. In some examples, circuit 500 is configured to generate IRAMP at least in part based on VIN, VOUT, and / or SW_FREQ. For example, circuit 500 is configured to receive a signal at node 536 that is the product of a constant K multiplied by the minimum value of VIN or VOUT. Circuit 500 multiplies and divides this signal with one or more additional signals (at least including IOSC) to generate IRAMP. In at least some examples, K is a coefficient determined by the implementation of the system implementing circuit 500. The signal received at node 536 can be generated according to one or more suitable techniques, and its scope is not limited herein. In one example, a first voltage divider (not shown) generates K*VIN and a second voltage divider (not shown) generates K*VOUT. Both K*VIN and K*VOUT are fed into a comparator (not shown) as a corresponding input and as a corresponding input to a multiplexer (not shown). The comparator determines which of K*VIN or K*VOUT is less than the other and outputs the result to the multiplexer as a selection signal to select the smallest of K*VIN and K*VOUT for the multiplexer output as the signal received at node 536.

[0038] In at least one example, circuit 500 includes amplifier 502, field-effect transistor (FET) 504, resistor 506, FET 508, FET 510, bipolar junction transistor (BJT) 512, FET 514, current source 516, FET 518, BJT 520, current source 522, current source 524, current source 526, BJT 528, current source 530, FET 532, and BJT 534. In some examples, FET 504 and FET 514 are n-type FETs and FET 508, FET 510, FET 518, and FET 532 are p-type FETs.

[0039] In at least one example architecture of the circuit 500, the amplifier 502 has a first input terminal (e.g., the positive or non-inverting input terminal) configured to be coupled to the node 536 and a second input terminal (e.g., the negative or inverting input terminal) coupled to the node 540. An output terminal of the amplifier 502 is coupled to a gate terminal of the FET 504, which has a drain terminal coupled to the node 538 and a source terminal coupled to the node 540. The resistor 506 is coupled between the node 540 and a ground node 542. The FET 508 has a drain terminal coupled to the node 538, a source terminal coupled to receive a supply voltage (which can be VIN or can be another value of supply voltage) at the node 545, and a gate terminal coupled to the node 538. In at least some examples, the node 545 can be coupled to or be the same node as the node 108 of the system 100. The FET 510 has a drain terminal coupled to the node 546, a source terminal coupled to the node 545, and a gate terminal coupled to the node 538. In at least some examples, the FET 508 and the FET 510 together form a current mirror that mirrors current from the node 538 to the node 546. The BJT 512 has a collector terminal coupled to the node 546, an emitter terminal coupled to the node 542, and a base terminal coupled to the node 550. The FET 514 has a drain terminal coupled to the node 545, a source terminal coupled to the node 548, and a gate terminal coupled to the node 546. The current source 516 is coupled between the node 548 and the ground node 542 and is configured to sink current from the node 548. The FET 518 has a drain terminal coupled to the node 550, a source terminal coupled to the node 545, and a gate terminal coupled to the node 552.

[0040] BJT 520 has a collector terminal coupled to node 552, an emitter terminal coupled to node 550, and a base terminal coupled to node 548. Current source 522 is coupled between node 545 and node 552 and configured to source current to node 552. In at least some examples, the current supplied to node 552 is approximately equal to IOSC (which is proportional to VREF / RF and approximately equal to VREF / RF). Current source 524 is coupled between node 550 and ground node 542 and configured to dissipate current from node 550. Current source 526 is coupled between node 545 and node 556 and configured to supply current to node 556. In at least some examples, the current supplied to node 556 is approximately equal to VREF divided by the resistance value of resistor 506 (e.g., R1). BJT 528 has a collector terminal coupled to node 556, an emitter terminal coupled to node 558, and a base terminal coupled to node 548. A current source 530 is coupled between node 558 and ground node 542 and is configured to dissipate current from node 558. FET 532 has a drain terminal coupled to node 558, a source terminal coupled to node 545, and a gate terminal coupled to node 556. BJT 534 has a collector terminal coupled to node 560, an emitter terminal coupled to ground node 542, and a base terminal coupled to node 558. In at least some examples, node 560 is the output node of circuit 500 with an IRAMP.

[0041] In an example of the operation of circuit 500, amplifier 502 amplifies the difference between the signal received at node 536 and the signal present at node 540. Amplifier 502 outputs this difference as a gate control signal for controlling FET 504. Based on this control, a current approximately equal to K*min(VIN, VOUT) / Rl (described below) is generated. Figure 5 A current (referred to as I1) flows through FET 504 and the corresponding node 538. FET 508 and FET 510 together mirror this current from node 538 to node 546 to inject current into the collector terminal of BJT 512. I0SC is further injected into the collector terminal of BJT 520, and VREF / R1 is injected into the collector terminal of BJT 528 to cause IRAMP to be present at node 560. In at least some examples, VREF / R1 is generated according to any suitable component (not shown) and mirrored to node 556 via a current mirror used as current source 526.

[0042] In some implementations, current source 516 is a constant current bias, current source 524 is a constant current bias dissipating VREF / RF, and current source 530 is a constant current bias dissipating VREF / R1. In some examples, current source 522 is a current source that dissipates VREF / R1 from...Figure 1 the IOSC of the frequency circuit 146 (which is approximately equal to Figure 5 the VREF / RF shown in FIG. 5) mirrors to a branch of a current mirror (not shown) of the node 552. Further, in some examples, the current source 524 is a branch of another current mirror (not shown) that mirrors current to the circuit 500 to sink current from the node 550. In such examples, the node 550 is an input of the branch of the current source to cause the IOSC to be sunk from the node 550 to the ground node 542 by the current source 524.

[0043] When the current II is injected into the collector terminal of the BJT 512, the BJT 512 generates a base-emitter voltage (VBEI) at the node 550 that is approximately equal to VT*ln(Il / IS), where VT is the thermal voltage of the BJTs of the circuit 500 and IS is the saturation current of the BJTs of the circuit 500. When the current VREF / RF (referred to as current I2 hereinafter) is injected into the collector terminal of the BJT 520, the BJT 520 generates a base-emitter voltage (VBE2) that is equal to VT*ln(I2 / IS). Thus, the voltage at the node 548 is approximately equal to VBEI+VBE2, which is approximately equal to VT*[ln(Il*I2) / IS / IS]. When the current VREF / R1 (referred to as current I3 hereinafter) is injected into the collector terminal of the BJT 528, the BJT 528 generates a base-emitter voltage (VBE3) that is equal to VT*ln(I3 / IS). This results in a voltage at the node 558 that is approximately equal to VBEI+VBE2-VBE3, which is approximately equal to VT*ln(I1*I2 / I3 / IS). The base-emitter voltage of the BJT 534 is VBE4, which is equal to the voltage present at the node 558. The collector current of the BJT 534 is determined from VBE4, such that the collector current of the BJT 534 is approximately equal to IS*exp(VBE4 / VT), which is equal to I1*I2 / I3, which is equal to IRAMP, as defined below. In at least some examples, the FET 514, the FET 518, and the FET 532 provide compensation for base current of at least some of the BJT 512, the BJT 520, the BJT 528, and / or the BJT 534. Figure 5 Figure 5 Although a particular architecture is shown and described with respect to the circuit 500 and the generation of IRAMP, other architectures are suitable in various examples. Generally, a circuit that generates IRAMP generates IRAMP according to the following Equation 1.

[0044]

[0045]

[0046] ​​Various circuit implementations (e.g., architectures and / or operations) can be suitable for implementing the above-described equations for IRAMP generation, and the present description is not limited to a single particular implementation. Rather, the present description encompasses implementations that generate a current signal based on information from VIN, VOUT, and SW_FREQ, as described herein, regardless of the particular arrangement of components that generate the current signal.

[0047] As implemented by circuit 500, the IRAMP is generated according to the following Equation 2, where the particular arrangement of components of circuit 500 performs current multiplication and / or division to generate the IRAMP.

[0048]

[0049] Figure 6 A schematic diagram of an illustrative ramp signal generation circuit 600 is shown. At least some examples of circuit 600 are suitable for implementation as components of ramp signal generation circuit 112. Figure 1 For example, at least some implementations of ramp signal generation circuit 112 include circuit 500 and circuit 600. Thus, when circuit 600 is described, reference can be made to components or signals of circuit 500 and / or circuit 600. For example, at least some implementations of circuit 600 receive one or more signals from circuit 500, such that circuit 500 and circuit 600 together perform the functions attributed to ramp signal generation circuit 112. In such examples where circuit 500 and circuit 600 together form ramp signal generation circuit 112, circuit 500 receives both VIN and VOUT. Circuit 600 also receives IOSC and VREF and outputs IRAMP (which is a signal internal to circuit 112 and is not output by ramp signal generation circuit 112). Circuit 600 receives VIN and IRAMP, as well as one or more clock signals (CLK or multiple clock signals derived from CLK), and outputs both RAMP_BU and RAMP_BO. Figure 5 Figure 1 For example, at least some implementations of ramp signal generation circuit 112 include circuit 500 and circuit 600. Thus, when circuit 600 is described, reference can be made to components or signals of circuit 500 and / or circuit 600. For example, at least some implementations of circuit 600 receive one or more signals from circuit 500, such that circuit 500 and circuit 600 together perform the functions attributed to ramp signal generation circuit 112. In such examples where circuit 500 and circuit 600 together form ramp signal generation circuit 112, circuit 500 receives both VIN and VOUT. Circuit 600 also receives IOSC and VREF and outputs IRAMP (which is a signal internal to circuit 112 and is not output by ramp signal generation circuit 112). Circuit 600 receives VIN and IRAMP, as well as one or more clock signals (CLK or multiple clock signals derived from CLK), and outputs both RAMP_BU and RAMP_BO. Figure 5

[0050] ​​In some examples, the circuit 600 is configured to generate RAMP BU and RAMP BO based on the IRAMP and one or more clock signals. For example, the circuit 600 is configured to switch a plurality of switches in accordance with the one or more clock signals to charge one or more capacitors, where a voltage present at a top plate of at least some of the capacitors is RAMP BU or RAMP BO. In at least some examples, the one or more clock signals include CLK and one or more additional clock signals derived from CLK or generated based at least in part on CLK. The generation of the one or more additional clock signals is performed in accordance with any suitable technique(s) and using any suitable components (not shown) such as digital logic gates, latches, delay circuits, etc., the scope of which is not limited herein.

[0051] As illustrated in the present specification, the one or more clock signals other than CLK include CLK1, CLK2, CLKS, CLKR, and CLK2R. In some examples, CLK1 has a frequency approximately one-half that of CLK, such that the width or duty cycle of CLK1 is equal to the period of CLK. CLK2 is an inversion of CLK1. Further, in some examples, CLKR has approximately the same frequency as CLK and a minimum width or duty cycle sufficient to turn on switches 622 and 632 to fully discharge capacitors 620 and 634, respectively. In at least one example, the width is approximately 20 nanoseconds (ns). In other examples, CLKR has another width or duty cycle suitable for the particular implementation of circuit 600 and / or the desired operation of circuit 600. CLK1R has a frequency approximately one-half that of CLKR, and CLK2R has a frequency approximately one-half that of CLKR and a phase shift of approximately 90 degrees. In at least some examples, CLK1R is generated as the output of a “logical AND” operation between CLK1 and CLKR and CLK2R is generated as the output of a “logical AND” operation between CLKS and CLK2R. In some examples, CLKS has approximately the same frequency as CLK and a minimum width or duty cycle sufficient to turn on switches 608 and 626 to fully charge capacitors 610 and 628, respectively. In some examples, the falling edge of CLKS is aligned in time with the rising edge of CLK. Further, in at least one example, the width is approximately 20 ns. In other examples, CLKS has another width or duty cycle suitable for the particular implementation of circuit 600 and / or the desired operation of circuit 600.

[0052] In at least some examples, circuit 600 includes current source 602, capacitor 604, switch 606, switch 608, capacitor 610, current source 612, switch 614, switch 616, current source 618, capacitor 620, switch 622, switch 624, switch 626, capacitor 628, switch 630, switch 632, capacitor 634, switch 636, switch 638, and amplifier 640. In at least some examples, current source 602 is configured to draw current from the IRAMP... Figure 5 A current mirror of node 560 of circuit 500 is mirrored to node 646. Similarly, in at least some examples, current source 612 is another current mirror configured to mirror the IRAMP from node 560 of circuit 500 to node 650 and double the IRAMP. Furthermore, in at least some examples, current source 618 is a current mirror configured to mirror the IRAMP from node 560 of circuit 500, where the source of the current mirror is node 654. Alternatively, current source 618 is a current mirror configured to mirror the IRAMP from an intermediate node, such that the IRAMP is mirrored from node 560 of circuit 500 to that intermediate node, causing current source 618 to dissipate the IRAMP from node 654. Furthermore, in at least some examples, node 642 is a power supply node where a supply voltage (which may be VIN or may be another value of the supply voltage) exists. In at least some examples, node 642 may be coupled to node 108 of system 100 or the same node as node 108 of system 100. Furthermore, each switch in circuit 600 can be implemented according to any suitable technology. For example, the switches can be implemented as mechanical or solid-state devices (e.g., transistors) that can each receive and be controlled by a corresponding clock signal from one or more clock signals. For example, when a clock signal is active, the switch receiving that clock signal can be closed or conduct electricity between the nodes to which the switch is coupled. When a clock signal is inactive, the switch receiving that clock signal can be open or not conduct electricity between the nodes to which the switch is coupled. In at least some other examples, the behavior of the switches can be reversed (e.g., conducting electricity when the clock signal is inactive and not conducting electricity when the clock signal is active).

[0053] In at least one example architecture of circuit 600, current source 602 is coupled between node 642 and node 646 and is configured to (e.g., via current mirroring techniques) supply IRAMP (e.g., a signal approximately equal in size to IRAMP, such as that provided by...) to node 646. Figure 5The capacitor 604 is coupled between the node 646 and the ground node 644. The switch 606 is coupled between the node 646 and the ground node 644. The switch 608 is coupled between the node 646 and the node 648. The capacitor 610 is coupled between the node 648 and the ground node 644. The current source 612 is coupled between the node 642 and the node 650 and is configured to supply 2*IRAMP to the node 650, such as through current mirroring techniques. The switch 614 is coupled between the node 650 and the node 652. The switch 616 is coupled between the node 652 and the node 654. The current source 618 is coupled between the node 654 and the ground node 644 and is configured to dissipate IRAMP from the node 654. The capacitor 620 and the switch 622 are each coupled between the node 652 and the ground node 644. The switch 624 is coupled between the node 652 and the node 656. The switch 626 is coupled between the node 656 and the node 658. The capacitor 628 is coupled between the node 658 and the ground node 644. The switch 630 is coupled between the node 656 and the node 660. The switch 632 and the capacitor 634 are each coupled between the node 660 and the ground node 644. The switch 636 is coupled between the node 660 and the node 650. The switch 638 is coupled between the node 660 and the node 654. The amplifier 640 has a first input terminal (e.g., positive or non-inverting input terminal) coupled to the node 658, a second input terminal (e.g., negative or inverting input terminal) coupled to the node 648, and an output terminal coupled to the node 654.

[0054] Reference is made to both of these concurrently filed patent applications Figure 7 Understanding of the circuit 600 can be enhanced by concurrently referencing Figure 7 A graph 700 illustrating ramp and timing signal waveforms of the circuit 600. For example, the graph 700 illustrates RAMP_BU, RAMP_BO, RAMP_B01 (e.g., the voltage present at the node 660), and RAMP_BO2 (e.g., the voltage present at the node 652). The graph 700 further illustrates CLK, CLK1, received by and controlling the operation of the switches 614, 626, and 630, and CLK2, received by and controlling the operation of the switches 616, 624, and 636. The graph 700 further illustrates CLK1R, received by and controlling the operation of the switch 622, and CLK2R, received by and controlling the operation of the switch 632. The graph 700 further illustrates CLKR, received by and controlling the operation of the switch 606, and CLKS, received by and controlling the operation of the switches 608 and 626.

[0055] In an example of operation of the circuit 600, RAMP_BU is present at node 646. Further, RAMP_BO is present at node 656, which alternates between node 652 and node 660 to cause RAMP_BO to include a falling portion of RAMP_BO1, followed by a falling portion of RAMP_BO2. Based on the IRAMP received at node 646, and when CLKR is inactive, the capacitor 604 charges to generate a voltage at node 646, where the voltage is RAMP_BU. When CLKR is active, and until CLKR is inactive again, the switch 606 closes to discharge the capacitor 604 to the ground node 644. Discharging the capacitor 604 resets the capacitor 604 and generates a new cycle of RAMP_BU.

[0056] When CLK1 is active and CLK2 is inactive, the capacitor 620 charges at a rate determined according to 2*IRAMP and the capacitor 634 discharges to node 656 and node 654 to form a first portion of RAMP_BO. For example, when CLK1 is active, and until CLK1 is inactive again, the switch 614 closes to charge the capacitor 620. Further, when CLK1 is active, and until CLK is inactive again, the switches 630 and 638 close to discharge the capacitor 634 to node 656 and node 654, respectively. In at least some examples, the rate of discharge of the capacitor 634 is determined according to IRAMP as drained by the current source 618. When CLK1 is inactive and CLK2 is active, the capacitor 634 charges at a rate determined according to 2*IRAMP and the capacitor 620 discharges to node 656 and node 654 to form a second portion of RAMP_BO. For example, when CLK2 is active, and until CLK2 is inactive again, the switch 636 closes to charge the capacitor 634. Further, when CLK2 is active, and until CLK2 is inactive again, the switches 624 and 616 close to discharge the capacitor 620 to node 656 and node 654, respectively. In at least some examples, the rate of discharge of the capacitor 620 is determined according to IRAMP as drained by the current source 618. In at least some examples, CLK1R is active just before CLK1 is active to reset the capacitor 620 (e.g., to discharge to ground), and CLK2R is active just before CLK2 is active to reset the capacitor 634. For example, when CLK1R is active, and until CLK1R is inactive again, the switch 622 closes to discharge the capacitor 620 to the ground node 644. Discharging the capacitor 620 resets the capacitor 620 and generates a new generated cycle of RAMP_BO2. Further, when CLK2R is active, and until CLK2R is inactive again, the switch 632 closes to discharge the capacitor 634 to the ground node 644. Discharging the capacitor 634 resets the capacitor 634 and generates a new generated cycle of RAMP_BO1.

[0057] In at least some examples, the peak of RAMP BU and the minimum of RAMP BO are sampled according to CLK S. For example, when CLK S is active, capacitor 610 charges based on RAMP BU and capacitor 628 charges based on RAMP BO. To sample RAMP BU, when CLK S is active, and until CLK S is inactive again, switch 608 is closed to charge capacitor 610 according to RAMP BU. To sample RAMP BO, switch 626 is closed to charge capacitor 628 according to RAMP BO. Amplifier 640 receives the sample of RAMP BO from capacitor 628 and the sample of RAMP BU from capacitor 610 and generates an error current signal (IADJ) based on the difference between the sample of RAMP BO and the sample of RAMP BU. Adding IADJ to node 654 (e.g., supplying to or sinking from node 654) based on the difference between the sample of RAMP BO and the sample of RAMP BU maintains the peak of RAMP BU or the valley of RAMP BO. In at least some examples, this generation of IADJ and providing IADJ to node 654 facilitates smooth transitions between operating modes of power converter 104 (e.g., between a buck operating mode and a boost operating mode). For example, if RAMP BU and RAMP BO have some gap between their respective maximum and minimum values, then when the value of CC is within that gap can affect control of power converter 104. In at least some examples, IADJ mitigates the likelihood of such an effect in control of power converter 104.

[0058] In at least some examples, it can be said that circuit 600 includes a first charging path, a second charging path, a third charging path, a first discharging path, and a second discharging path, each of which is not shown in Figure 6Instead of being shown in the diagram, these components are understood by referring to their respective components. The first charging path includes capacitor 604, which generates RAMP_BU when charged. The second charging path includes switch 614 and capacitor 620. The third charging path includes switch 636 and capacitor 634. The first discharging path includes switch 524, capacitor 620, and switch 616. The second discharging path includes switch 630, capacitor 634, and switch 638. Capacitor 620 is charged via the first charging path based on a signal present at node 650, and capacitor 634 is charged via the second charging path based on a signal present at node 650. Capacitor 620 discharges via the first discharging path based on current dissipated through node 654, generating RAMP_BO2 at node 656 (used as RAMP_BO for one time period). Capacitor 634 discharges via the second discharging path based on current dissipated through node 654, generating RAMP_BO1 at node 656 (used as RAMP_BO for another time period).

[0059] Figure 8 An illustrative flowchart of a method 800 for generating ramp signals is shown. In at least some examples, method 800 consists of, for example... Figure 1 The circuit implementation of the ramp signal generation circuit 112. Therefore, when describing method 800, reference can be made to... Figure 1 The components or signals. In at least one example, method 800 is implemented to generate a ramp signal. The ramp signal can be used to control the power converter, as a compensation signal (e.g., slope compensation), or for any other suitable purpose to which the ramp signal is useful. In at least some examples, the ramp signal has a variable slope that varies with the input variables. For example, instead of generating a ramp signal with the same slope over a wide operating range (such as VIN, VOUT, and / or SW_FREQ range), method 800 generates a ramp signal with a slope that is at least partially determined based on the current or present values ​​of VIN, VOUT, and / or SW_FREQ.

[0060] At operation 802, multiple signals are received. These signals include at least some signals or information about some signals, and the ramp signal will be based on these signals. For example, in at least one embodiment, the minimum value of VIN or VOUT is received multiplied by a constant. Additionally, a current proportional to SW_FREQ is received.

[0061] At operation 804, the received plurality of signals is manipulated to generate an IRAMP. In at least some examples, the plurality of signals is manipulated by a circuit comprising a plurality of transistors and a current source. For example, the plurality of signals can be manipulated by a plurality of transistors coupled in an architecture configured to perform multiplication and / or division operations that accept current signals as input. In other examples, the plurality of signals is manipulated by any suitable component, including a processor or other logic device that implements software to perform at least some of the manipulation. The plurality of signals is manipulated to generate an IRAMP, as defined in Equation 1 above.

[0062] At operation 806, a RAMP BU is generated. In at least some examples, the RAMP BU is generated by charging a capacitor with the IRAMP, where the voltage present at the top plate of the capacitor is the RAMP BU. The top plate of the capacitor can be switched to ground to enable periodic resetting of the capacitor.

[0063] At operation 808, a RAMP BO is generated. In at least some examples, the RAMP BO is generated by charging a plurality of capacitors, where the RAMP BO is alternately formed by the voltage present at the top plate of a capacitor as it discharges. For example, when a first capacitor is charging, a second capacitor is discharging and the voltage present at the top plate of the second capacitor is used as the RAMP BO. Subsequently, when the second capacitor is recharging, the first capacitor is discharging and the voltage present at the top plate of the first capacitor is used as the RAMP BO. In at least some examples, this alternating pattern is implemented by alternately switching the top plates of the first and second capacitors to a common node where the RAMP BO is present. The top plates of the first and second capacitors can each be switched to ground to enable periodic resetting of the first and second capacitors, respectively.

[0064] While the operations of method 800 are described and shown in a particular order, in various examples, method 800 includes additional operations not listed here. In some examples, any one or more of the operations listed here includes one or more sub-operations (e.g., such as intermediate comparisons, logical operations, output selection such as via multiplexers, format conversion, determinations, etc.). In some examples, any one or more of the operations listed here are omitted. In some examples, any one or more of the operations listed here are performed in an order different than presented here (e.g., in reverse order, substantially simultaneously, overlapping, etc.). Each of these alternatives falls within the scope of the present specification.

[0065] Figure 9 An illustrative graph 900 showing the operation of the power delivery state machine is shown. In at least some examples, graph 900 represents the operation of controller 102 in controlling Figure 1 Figure 1 ​at least some of the actions performed by the power converter 104 in the system 100 of FIG. 1. Accordingly, reference can be made to the description of the graph 900 when describing the graph 1000. Figure 1 components or signals of FIG. 1.

[0066] The graph 1000 begins with a state 1002, which in at least some examples is a power-up of the system 100. Upon power-up, the value of VIN is determined relative to the desired value of VOUT. When VIN is less than the desired value of VOUT, the state machine proceeds to a state 1004 in which the power converter 104 is controlled by the controller 102 to operate in a boost mode of operation. When VIN is greater than the desired value of VOUT, the state machine proceeds to a state 1006 in which the power converter 104 is controlled by the controller 102 to operate in a buck mode of operation.

[0067] The state machine remains in the state 1004, controlling the power converter 104 to operate in the boost mode of operation, until the system 100 is powered down or a transition condition is met. For example, if VIN becomes greater than VOUT multiplied by a predefined constant (e.g., such as about 1.3), the state machine transitions from the state 1004 to the state 1006. Further, when the period of the gate control signal of the transistors of the power converter 104 is less than a predefined time for a predefined number of switching cycles, the state machine transitions from the state 1004 to a state 1008. For example, when the period of the gate control signal received by the transistor 138 is less than about 25 nanoseconds (ns) for about 7 switching cycles, the state machine transitions from the state 1004 to the state 1008.

[0068] The state machine remains in the state 1006, controlling the power converter 104 to operate in the buck mode of operation, until the system 100 is powered down or a transition condition is met. For example, if VIN becomes less than VOUT divided by a predefined constant (e.g., such as about 1.3), the state machine transitions from the state 1006 to the state 1004. Further, when the period of the gate control signal of the transistors of the power converter 104 is less than a predefined time for a predefined number of switching cycles, the state machine transitions from the state 1006 to the state 1008. For example, when the period of the gate control signal received by the transistor 134 is less than about 25 ns for about 7 switching cycles, the state machine transitions from the state 1006 to the state 1008.

[0069] The state machine remains in state 908, controlling the power converter 104 to operate in the buck-boost mode of operation, until the system 100 is powered down or a transition condition is met. For example, if the period of the gate control signal of the first transistor of the power converter 104 is greater than the predefined time for a predefined number of switching cycles and the period of the other gate control signal of the second transistor of the power converter 104 is less than the predefined time for a predefined number of switching cycles, the state machine transitions from state 908 to state 904. For example, when the period of the gate control signal received by the transistor 138 is greater than about 300 ns for about 7 switching cycles and the period of the gate control signal received by the transistor 134 is less than about 25 ns for about 7 switching cycles, the state machine transitions from state 908 to state 904. Alternatively, if the VIN becomes less than the VOUT divided by a predefined constant (e.g., such as about 1.3), the state machine transitions from state 908 to state 904.

[0070] Further, when the period of the gate control signal received by the transistor 134 is greater than about 300 ns for about 7 switching cycles and the period of the gate control signal received by the transistor 138 is less than about 25 ns for about 7 switching cycles, the state machine transitions from state 908 to state 906. Alternatively, if the VIN becomes greater than the VOUT multiplied by a predefined constant (e.g., such as about 1.3), the state machine transitions from state 908 to state 906.

[0071] In this specification, the term“coupled” can encompass a connection, communication, or signal path that enables a functional relationship that is consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then in a first example, device A is coupled to device B, or in a second example, device A is coupled to device B through intermediate component C such that device B is controlled by device A via a control signal generated by device A, provided that intermediate component C does not substantially alter the functional relationship between device A and device B. A device that is“configured to” perform a task or function can be configured (e.g., programmed and / or hardwired), at a time of manufacture, by a manufacturer of the device or a user after manufacture, to perform the function and / or can be re-configured or reset by a manufacturer or user after manufacture to perform other tasks or functions. Configuration can be through firmware and / or software programming of the device, through configuration and / or layout of hardware components and interconnections of the device, or combinations thereof. Also, a circuit or device described as including certain components can alternatively be configured to couple to those components to form the described circuitry or device. For example, structures described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) can alternatively include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package) and can be configured to couple to at least some of the passive elements and / or sources to form the described structures, such as by an end user and / or a third party manufacturer, or after manufacture.

[0072] While certain components are described herein as having a particular process technology (e.g., FET, metal oxide semiconductor FET (MOSFET), n-type, p-type, etc.), these components can be exchanged for components of other process technologies (e.g., replace FET and / or MOSFET with BJT, replace n-type with p-type or vice versa, etc.), and reconfiguring the circuit including the replaced components can provide desired functionality at least somewhat similar to the functionality available prior to the component replacement. Unless otherwise noted, components illustrated as resistors generally represent any one or more elements coupled in series and / or in parallel to provide an amount of impedance represented by the illustrated resistor. Also, in this specification, the phrase“ground voltage potential” includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection suited or adapted for use with the teachings of this specification. Unless otherwise indicated, “about,”“approximately,” or“substantially” preceding a value indicates + / - 10% of the stated value.

[0073] Modifications are possible in the described embodiments, and other embodiments are possible. Within the scope of the claims, modifications can be made to the described embodiments, and other embodiments can be made.

Claims

1. A circuit comprising: A first charging path includes a first capacitor coupled to a first output node; The second charging path includes a first switch and a second capacitor; The third charging path includes a second switch and a third capacitor; The first discharge path includes the second capacitor, a third switch coupled between the second charging path and the second output node, and a fourth switch coupled between the second charging path and the fourth node. as well as The second discharge path includes the third capacitor, a fifth switch coupled between the third charging path and the second output node, and a sixth switch coupled between the third node and the fourth node. A buck ramp signal is generated by discharging the second capacitor and the third capacitor, which are charged based on a scaled version of the current signal. The voltage of the second capacitor during discharge is the buck ramp signal during the first time period, and the voltage of the third capacitor during discharge is the buck ramp signal during the second time period.

2. The circuit of claim 1, wherein the first capacitor is coupled between the first output node and the ground node, and the circuit further comprises a seventh switch coupled between the first output node and the ground node.

3. The circuit of claim 1, wherein the first switch is coupled between the first node and the second node, the second capacitor is coupled between the second node and the ground node, and the third switch is coupled between the second node and the second output node.

4. The circuit of claim 3, wherein the second switch is coupled between the first node and the third node, the third capacitor is coupled between the third node and the ground node, and the fourth switch is coupled between the third node and the second output node.

5. The circuit according to claim 3, further comprising: The eighth switch is coupled between the second node and the ground node; as well as The ninth switch is coupled between the third node and the ground node.

6. The circuit according to claim 1, further comprising: The tenth switch is coupled between the second output node and the fifth node; A fourth capacitor is coupled between the fifth node and the ground node; The eleventh switch is coupled between the first output node and the sixth node; A fifth capacitor is coupled between the sixth node and the ground node; as well as An amplifier having a first input terminal coupled to the fifth node, a second input terminal coupled to the sixth node, and an output terminal coupled to the fourth node.

7. The circuit of claim 3, further comprising a first current source, a second current source, and a third current source, wherein the first current source is configured to supply a first current to the first output node to charge the first capacitor via the first charging path, the second current source is configured to supply twice the first current to the first node to charge the second capacitor via the second charging path and the third capacitor via the third charging path, and the third current source is configured to dissipate the first current from the fourth node to facilitate discharging the second capacitor via the first discharge path and the third capacitor via the second discharge path.

8. The circuit of claim 7, wherein the third current source is configured to modify the amount of current dissipated from the fourth node based on the output of an amplifier, the amplifier generating a current signal based on the difference between the current present at the fifth node and the current present at the sixth node.

9. The circuit of claim 7, wherein the first discharge path is configured to discharge the second capacitor to the second output node to generate a first falling edge of the continuous ramp signal, and the second discharge path is configured to discharge the third capacitor to the second output node to generate a second falling edge of the continuous ramp signal.

10. The circuit according to claim 1, further comprising: The first transistor has a collector coupled to a seventh node, an emitter coupled to a ground node, and a base coupled to an eighth node. The second transistor has a collector coupled to the ninth node, an emitter coupled to the tenth node, and a base coupled to the eleventh node. The third transistor has a collector coupled to the twelfth node, an emitter coupled to the thirteenth node, and a base coupled to the eleventh node; as well as The fourth transistor has a collector coupled to the fourteenth node, an emitter coupled to the ground node, and a base coupled to the thirteenth node.

11. The circuit according to claim 10, further comprising: The second amplifier has a first input terminal coupled to the fifteenth node, a second input terminal coupled to the sixteenth node, and an output terminal; The fifth transistor has a drain coupled to the seventeenth node, a source coupled to the sixteenth node, and a gate coupled to the output terminal of the second amplifier; A resistor coupled between the sixteenth node and the ground node; The sixth transistor has a drain coupled to the seventeenth node, a source coupled to the eighteenth node, and a gate coupled to the seventeenth node; as well as The seventh transistor has a drain coupled to the seventh node, a source coupled to the eighteenth node, and a gate coupled to the seventeenth node.

12. The circuit according to claim 11, further comprising: The eighth transistor has a drain coupled to the eighteenth node, a source coupled to the eleventh node, and a gate coupled to the seventh node. A ninth transistor having a drain coupled to the eighth node, a source coupled to the eighteenth node, and a gate coupled to the ninth node; as well as The tenth transistor has a drain coupled to the thirteenth node, a source coupled to the eighteenth node, and a gate coupled to the twelfth node.

13. The circuit of claim 12, further comprising a first current source, a second current source, and a third current source, wherein the first current source is configured to supply the first output node with a current equal to the current flowing through the fourteenth node, the second current source is configured to supply the first node with a current equal to twice the current flowing through the fourteenth node, and the third current source is configured to dissipate from the fourth node a current equal to the current flowing through the fourteenth node.

14. A circuit comprising: A current signal generation circuit is configured to generate a current signal based on an input voltage value, an output voltage value, and an operating frequency. as well as A ramp signal generation circuit, coupled to the current signal generation circuit, is configured to: A boost ramp signal is generated by charging a first capacitor based on the current signal, wherein the voltage of the first capacitor during charging is the boost ramp signal. and A buck ramp signal is generated by discharging a second capacitor and a third capacitor that are charged based on a scaled version of the current signal, wherein the voltage of the second capacitor during discharge is the buck ramp signal during a first time period, and the voltage of the third capacitor during discharge is the buck ramp signal during a second time period.

15. The circuit of claim 14, wherein the ramp signal generation circuit comprises: A first charging path includes a first capacitor coupled to a first output node; The second charging path includes a first switch and a second capacitor; The third charging path includes a second switch and a third capacitor; The first discharge path includes the second capacitor, a third switch coupled between the second charging path and the second output node, and a fourth switch coupled between the second charging path and the fourth node. as well as The second discharge path includes the third capacitor, a fifth switch coupled between the third charging path and the second output node, and a sixth switch coupled between the third node and the fourth node.

16. The circuit of claim 15, wherein the first capacitor is coupled between the first output node and the ground node, and the circuit further comprises a seventh switch coupled between the first output node and the ground node, wherein the first switch is coupled between the first node and the second node, the second capacitor is coupled between the second node and the ground node, the third switch is coupled between the second node and the second output node, the second switch is coupled between the first node and the third node, the third capacitor is coupled between the third node and the ground node, and the fourth switch is coupled between the third node and the second output node.

17. The circuit of claim 16, further comprising: The eighth switch is coupled between the second node and the ground node; The ninth switch is coupled between the third node and the ground node; The tenth switch is coupled between the second output node and the fifth node; A fourth capacitor is coupled between the fifth node and the ground node; The eleventh switch is coupled between the first output node and the sixth node; A fifth capacitor is coupled between the sixth node and the ground node; as well as An amplifier having a first input terminal coupled to the fifth node, a second input terminal coupled to the sixth node, and an output terminal coupled to the fourth node.

18. The circuit of claim 15, wherein the current signal generation circuit comprises: The first transistor has a collector coupled to a seventh node, an emitter coupled to a ground node, and a base coupled to an eighth node. The second transistor has a collector coupled to the ninth node, an emitter coupled to the tenth node, and a base coupled to the eleventh node. The third transistor has a collector coupled to the twelfth node, an emitter coupled to the thirteenth node, and a base coupled to the eleventh node; as well as The fourth transistor has a collector coupled to the fourteenth node, an emitter coupled to the ground node, and a base coupled to the thirteenth node.

19. The circuit of claim 18, wherein the current signal generation circuit further comprises: The second amplifier has a first input terminal coupled to the fifteenth node, a second input terminal coupled to the sixteenth node, and an output terminal; The fifth transistor has a drain coupled to the seventeenth node, a source coupled to the sixteenth node, and a gate coupled to the output terminal of the second amplifier; A resistor coupled between the sixteenth node and the ground node; The sixth transistor has a drain coupled to the seventeenth node, a source coupled to the eighteenth node, and a gate coupled to the seventeenth node; A seventh transistor having a drain coupled to the seventh node, a source coupled to the eighteenth node, and a gate coupled to the seventeenth node; The eighth transistor has a drain coupled to the eighteenth node, a source coupled to the eleventh node, and a gate coupled to the seventh node. The ninth transistor has a drain coupled to the eighth node, a source coupled to the eighteenth node, and a gate coupled to the ninth node. The tenth transistor has a drain coupled to the thirteenth node, a source coupled to the eighteenth node, and a gate coupled to the twelfth node.

20. The circuit of claim 19, wherein the current signal is based on Hereinafter, k is a constant, VIN is the input voltage value, VOUT is the output voltage value, VREF is the reference voltage, RF is the resistor value specifying the operating frequency, and R1 is the resistance value of the resistor.

21. The circuit of claim 18, wherein the fourteenth node is coupled to the ramp signal generation circuit, wherein the ramp signal generation circuit is configured to receive the current signal at the fourteenth node.

22. The circuit of claim 16, wherein the value of the current supplied to the first output node is equal to the value of the current signal, the value of the current supplied to the first node is equal to twice the value of the current signal, and the value of the current dissipated from the fourth node is equal to the value of the current signal.

23. The circuit according to claim 14, wherein the current signal is based on Specifically, k is a constant, VIN is the input voltage value, VOUT is the output voltage value, and RF is the resistance value of the resistor specifying the operating frequency.

24. A system comprising: Power converter; as well as A controller, coupled to the power converter, includes: A current signal generation circuit is configured to generate a current signal based on the input voltage value of the power converter, the output voltage value of the power converter, and the switching frequency of the power converter. The ramp signal generation circuit is configured as follows: A boost ramp signal is generated by charging a first capacitor based on the current signal, wherein the voltage of the first capacitor during charging is the boost ramp signal. and A buck ramp signal is generated by discharging a second capacitor and a third capacitor charged based on a scaled version of the current signal, wherein the voltage of the second capacitor during discharge is the buck ramp signal during a first time period, and the voltage of the third capacitor during discharge is the buck ramp signal during a second time period; and The comparator is configured as follows: The boost ramp signal or the buck ramp signal is compared with an error signal determined at least in part based on the output current of the power converter; and A pulse width modulation signal is generated based on the comparison to specify the duty cycle of the power converter.

25. The system of claim 24, wherein the ramp signal generation circuit comprises: A first charging path includes the first capacitor coupled to a first output node; The second charging path includes a first switch and a second capacitor; The third charging path includes the second switch and the third capacitor; The first discharge path includes the second capacitor, a third switch coupled between the second charging path and the second output node, and a fourth switch coupled between the second charging path and the fourth node. as well as The second discharge path includes the third capacitor, a fifth switch coupled between the third charging path and the second output node, and a sixth switch coupled between the third node and the fourth node.

26. The system of claim 25, wherein the value of the current supplied to the first output node is equal to the value of the current signal, the value of the current supplied to the first node is equal to twice the value of the current signal, and the value of the current dissipated from the fourth node is equal to the value of the current signal.

27. The system of claim 24, wherein the current signal generation circuit includes components configured to... The component that generates the current signal, k is a constant, VIN is the input voltage value of the power converter, VOUT is the output voltage value of the power converter, and RF is the resistance value of the resistor that specifies the switching frequency of the power converter.

28. The system of claim 24, wherein the current signal generation circuit includes a transistor configured to perform current multiplication and current division to generate the current signal based on the input voltage value of the power converter, the output voltage value of the power converter, and a resistor that sets the switching frequency of the power converter.

29. A circuit comprising: The first transistor has a collector coupled to a first node, an emitter coupled to a ground node, and a base coupled to a second node. The second transistor has a collector coupled to the third node, an emitter coupled to the fourth node, and a base coupled to the fifth node; The third transistor has a collector coupled to the sixth node, an emitter coupled to the seventh node, and a base coupled to the fifth node; The fourth transistor has a collector coupled to the eighth node, an emitter coupled to the ground node, and a base coupled to the seventh node; as well as The ramp signal generation circuit, coupled to the eighth node, is configured as follows: A boost ramp signal is generated by charging the first capacitor based on a current signal of equal magnitude to the current dissipated by the fourth transistor, wherein the voltage of the first capacitor during charging is the boost ramp signal. and A buck ramp signal is generated by discharging a second capacitor and a third capacitor that are charged based on a scaled version of the current signal, wherein the voltage of the second capacitor during discharge is the buck ramp signal during a first time period, and the voltage of the third capacitor during discharge is the buck ramp signal during a second time period.

30. The circuit according to claim 29, further comprising: An amplifier having a first input terminal coupled to a ninth node, a second input terminal coupled to a tenth node, and an output terminal; The fifth transistor has a drain coupled to the eleventh node, a source coupled to the tenth node, and a gate coupled to the output terminal of the amplifier. A resistor coupled between the tenth node and the ground node; The sixth transistor has a drain coupled to the eleventh node, a source coupled to the twelfth node, and a gate coupled to the eleventh node. as well as The seventh transistor has a drain coupled to the first node, a source coupled to the twelfth node, and a gate coupled to the eleventh node.

31. The circuit according to claim 30, further comprising: The eighth transistor has a drain coupled to the twelfth node, a source coupled to the fifth node, and a gate coupled to the first node; The ninth transistor has a drain coupled to the second node, a source coupled to the twelfth node, and a gate coupled to the third node; as well as The tenth transistor has a drain coupled to the seventh node, a source coupled to the twelfth node, and a gate coupled to the sixth node.

32. The circuit of claim 31, wherein the fourth transistor is configured to emit an amount equal to [missing information] from the eighth node. The current, k is a constant, VIN is the input voltage at the twelfth node, VOUT is the output voltage of the power converter, VREF is the reference voltage, RF is the resistor value specifying the operating frequency of the power converter, and R1 is the resistance value of the resistor.

33. The circuit of claim 29, wherein the ramp signal generation circuit comprises: A first charging path includes the first capacitor coupled to a first output node, at which the boost ramp signal is present; The second charging path includes a first switch and a second capacitor; The third charging path includes the second switch and the third capacitor; The first discharge path includes the second capacitor, a third switch coupled between the second charging path and the second output node where the buck ramp signal exists, and a fourth switch coupled between the second charging path and the fourth node; as well as The second discharge path includes the third capacitor, a fifth switch coupled between the third charging path and the second output node, and a sixth switch coupled between the third node and the fourth node.

34. A system comprising: Power converter, and A controller having an output coupled to the power converter, and the controller comprising: A ramp signal generation circuit has a first ramp output, a second ramp output, a first input coupled to the input of the power converter, and a second input coupled to the output of the power converter; An error amplifier, the input of which is coupled to the output and reference terminal of the power converter; A comparator, the input of which is coupled to the first ramp output, the second ramp output, and the output of the error amplifier, and the output of which is coupled to the output of the controller.

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