Method of operating an integrated circuit and integrated circuit

Abstract

A method of operating an integrated circuit is provided, including writing data to each memory cell in a first memory cell array, powering off the integrated circuit, powering on the integrated circuit, reading data from each memory cell in the first memory cell array in response to powering on the integrated circuit, and determining whether to allow authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array. An integrated circuit is also provided, including the first memory cell array.

Description

Technical Field

[0001] Embodiments of the present invention relate to methods of operating an integrated circuit and an integrated circuit. Background Art

[0002] The semiconductor integrated circuit (IC) industry has produced a wide variety of digital devices to solve problems in many different fields. Some of these digital devices, such as memory macros, are configured to store data. As ICs become smaller and more complex, the resistance of the wires in these digital devices will also change, affecting the operating voltage of these digital devices and the overall IC performance. Summary of the invention

[0003] According to one aspect of an embodiment of the present invention, a method for operating an integrated circuit is provided, the integrated circuit comprising a first memory cell array, the method comprising: writing data to each memory cell in the first memory cell array; powering off the integrated circuit; powering on the integrated circuit; in response to powering on the integrated circuit, reading data from each memory cell in the first memory cell array; and in response to reading data from each memory cell in the first memory cell array, determining whether authentication operation of the integrated circuit is allowed.

[0004] According to another aspect of an embodiment of the present invention, a method for operating an integrated circuit is provided, the integrated circuit comprising a first memory cell array and a second memory cell array, the method comprising: writing data to each memory cell in the first memory cell array; writing data to each memory cell in the second memory cell array; powering off the integrated circuit; powering on the integrated circuit; in response to powering on the integrated circuit, reading data from each memory cell in the first memory cell array; in response to powering on the integrated circuit, reading data from each memory cell in the second memory cell array; and in response to reading data from each memory cell in at least the first memory cell array or the second memory cell array, determining whether authentication operation of the integrated circuit is allowed.

[0005] According to another aspect of an embodiment of the present invention, an integrated circuit is provided, comprising: a first memory cell array, comprising: a first array of volatile memory cells having a first data retention time; and a controller coupled to the first memory cell array, the controller being configured to: in response to the integrated circuit being successfully logged in, write data to each memory cell in the first memory cell array; in response to the integrated circuit being powered on, read data from each memory cell in the first memory cell array; and in response to reading data from each memory cell in the first memory cell array, determine whether the authentication operation of the integrated circuit is allowed. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a block diagram of an integrated circuit according to some embodiments.

[0008] Figure 2 is a circuit diagram of a memory circuit according to some embodiments.

[0009] Figure 3 is a circuit diagram of a memory cell according to some embodiments.

[0010] Figure 4 is a flow chart of a method of operating an integrated circuit according to some embodiments.

[0011] Figure 5 is a block diagram of an integrated circuit according to some embodiments.

[0012] FIG. 6A to FIG. 6C is a flow chart of a method of operating an integrated circuit according to some embodiments.

[0013] Figure 7 is a circuit diagram of an integrated circuit according to some embodiments.

[0014] Figure 8 is a schematic diagram of a system according to some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] In addition, for ease of description, spacing relation terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, the spacing relation terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spacing relation descriptors used herein should be interpreted accordingly.

[0017] According to some embodiments, a method of operating an integrated circuit includes writing data to each memory cell in a first memory cell array of the integrated circuit, powering off the integrated circuit, powering on the integrated circuit, and reading data from each memory cell in the first memory cell array in response to powering on the integrated circuit.

[0018] In some embodiments, the method further comprises determining whether to allow an authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array. In some embodiments, the authentication operation comprises providing one or more login operations to a user of the integrated circuit.

[0019] In some embodiments, the data retention of the first memory cell array is configured to be used as a log-in timer for the integrated circuit and is usable by the integrated circuit to track the duration since power failure. Thus, the integrated circuit of the present disclosure is configured to provide additional security of the integrated circuit contents compared to other methods.

[0020] Figure 1 is a block diagram of an integrated circuit 100 according to some embodiments. Figure 1 In the exemplary embodiment, integrated circuit 100 is a memory macro.

[0021] Integrated circuit 100 includes a memory cell array 102 and a controller 104. Memory cell array 102 is coupled to controller 104. In some embodiments, memory cell array 102 is coupled to controller 104 via at least bit lines BL ( Figure 2 ), inverted bit line BLB, word line WL or other conductive lines are coupled to controller 104. Controller 104 is configured to control memory cell array 102. In some embodiments, controller 104 is configured to provide one or more security measures (described below) to integrated circuit 100.

[0022] The memory cell array 102 includes a memory cell array having M rows and N columns, where M and N are positive integers (eg, Figure 2 ). In some embodiments, each memory cell in the memory cell array 102 is configured to store 1 bit of data. In some embodiments, each memory cell in the memory cell array 102 is configured to store more than 1 bit of data.

[0023] In some embodiments, the memory cell array 102 is a volatile memory cell array. In some embodiments, the memory cell array 102 includes a volatile memory cell array that is configured to lose stored data therein due to leakage current. In some embodiments, each memory cell in the memory cell array 102 corresponds to a static random access memory (SRAM) cell. In some embodiments, each memory cell in the memory cell array 102 corresponds to a single-port, dual-port, or multi-port memory cell. In some embodiments, each memory cell in the memory cell array 102 corresponds to a dynamic random access memory (DRAM) cell. In some embodiments, each memory cell in the memory cell array 102 corresponds to an embedded dynamic random access memory (eDRAM) cell. Other types of memory cells in the memory cell array 102 are within the intended scope of the present disclosure.

[0024] Other configurations and types of memory cells in the memory cell array 102 are also within the scope of the present disclosure.

[0025] Controller 104 includes X-decoder circuit 106 , Y-decoder circuit 108 , and read circuit 110 .

[0026] The X-decoder circuit 106 is coupled to (not shown) the memory cell array 102 via the word lines WL. The X-decoder circuit 106 is configured to generate word line signals (not shown) on the corresponding word lines WL to the memory cell array 102. In some embodiments, the X-decoder circuit 106 includes a word line driver circuit (not shown) coupled to the word lines WL, and the word line driver circuit (not shown) is configured to generate word line signals sent to the memory cell array 102.

[0027] In some embodiments, a word line driver circuit (not shown) decodes a row address of a memory cell in the memory cell array 102 selected to be accessed in a read operation or a write operation. In some embodiments, the word line driver circuit (not shown) then provides a voltage to a selected word line corresponding to the decoded row address and provides a different voltage to other unselected word lines. In some embodiments, the X-decoder circuit 106 is configured to generate a word line signal in response to a first set of control signals (not shown) received from the controller 104.

[0028] Other configurations of X-decoder circuit 106 are within the scope of the present disclosure.

[0029] Y-decoder circuit 108 is coupled to (not shown) memory cell array 102 via bit line BL and inverted bit line BLB. In some embodiments, the term "inverted" refers to a signal that is logically inverted. In these embodiments, for example, inverted bit line BLB carries a signal that is logically inverted to the signal carried by bit line BL.

[0030] Y-decoder circuit 108 is configured to generate a bit line signal (not shown) on a corresponding bit line BL to memory cell array 102 , and is configured to generate a bit line signal (not shown) on a corresponding barred bit line BLB to memory cell array 102 .

[0031] In some embodiments, the Y-decoder circuit 108 includes a bit line driver circuit (not shown) coupled to the bit line BL, and the bit line driver circuit (not shown) is configured to generate a bit line signal that is sent to the memory cell array 102. In some embodiments, the Y-decoder circuit 108 includes an inverted bit line driver circuit (not shown) coupled to the inverted bit line BLB, and the inverted bit line driver circuit (not shown) is configured to generate an inverted bit line signal that is sent to the memory cell array 102.

[0032] In some embodiments, the bit line driver circuit (not shown) and the inverted bit line driver circuit (not shown) decode the column address of the memory cell in the memory cell array 102 selected to be accessed in the write operation. In some embodiments, the bit line driver circuit (not shown) then provides a voltage to the selected bit line corresponding to the decoded column address, and the inverted bit line driver circuit (not shown) then provides an inverted voltage to the selected bit line corresponding to the decoded column address. In some embodiments, the Y-decoder circuit 108 is configured to generate a bit line signal and an inverted bit line signal in response to a second set of control signals (not shown) received from the controller 104.

[0033] Other configurations of the Y-decoder circuit 108 are within the scope of the present disclosure.

[0034] The read circuit 110 is coupled to the memory cell array 102 (not shown) through the bit line BL and the inverted bit line BLB. The read circuit 110 is configured to read the data stored in the memory cell array 102 during a read operation. In some embodiments, the read circuit 110 includes one or more sense amplifiers (not shown) configured to read the data stored in the memory cell array 102 in response to corresponding sense amplifier enable signals.

[0035] In some embodiments, at least two or more of X-decoder circuit 106, Y-decoder circuit 108, and read circuit 110 are combined into a single peripheral circuit. Other configurations of read circuit 110 are within the scope of the present disclosure.

[0036] In some embodiments, the integrated circuit 100 corresponds to at least a radio frequency identification (RFID) card, a bank card, a payment card, or an identification (ID) card. In some embodiments, the integrated circuit 100 corresponds to an intermittently powered device such as an Internet of Things (IoT) device.

[0037] The controller 104 and the integrated circuit 100 include sensitive data that is protected by one or more security measures. In some embodiments, a method of providing security to the integrated circuit 100 is to prompt the user to enter a password in order to log into the integrated circuit 100. For example, in some embodiments, the integrated circuit 100 is logged in by the user during a login operation. In some embodiments, during the login operation, the controller 104 is configured to provide a login screen to the user, and then the user enters at least a credential or password to log into the integrated circuit 100. In some embodiments, if the credential or password is correct, the user is logged into the integrated circuit 100. In some embodiments, if the credential or password is incorrect, the user is not logged into the integrated circuit 100. As part of the security mechanism, in some embodiments, the user can attempt to log into the integrated circuit 100 for a limited number of attempts or tracking within a time period specified by a login timer. For example, in some embodiments, if the user mistakenly enters an incorrect password more than a limited number of times or attempts within a time period specified by the login timer, the integrated circuit 100 will not provide the user with an opportunity to enter the password again until the login timer expires. However, some users may attempt to gain access to the integrated circuit 100 by powering off or shutting down the integrated circuit 100 while attempting to reset the login timer.

[0038] In some embodiments, the integrated circuit 100 is configured to provide an additional timer that is used as an additional security mechanism, thereby providing additional protection for the contents of the integrated circuit 100 compared to other methods. For example, in some embodiments, the volatility of the data stored in the memory cell array 102 is used as an additional timer. After the memory cell array 102 is removed from the power supply VDD, due to the volatility of the memory cell array 102, over time, the data stored in the memory cell array 102 as a logic 1 will eventually change from a logic 1 to a logic 0 as leakage current in the memory cell array 102 discharges from a higher voltage (e.g., the power supply voltage VDD) to a lower voltage (e.g., the reference voltage VSS). In some embodiments, the integrated circuit 100 is configured to use the amount of time that the logic state of the memory cells in the memory cell array 102 changes as a timer for one or more authentication operations or functions.

[0039] For example, in some embodiments, by the controller 104 writing data to each memory cell in the memory cell array 102 after the integrated circuit 100 successfully logs in, and then reading the data stored in the memory cell array 102 after the integrated circuit 100 is powered off and then subsequently powered on, the memory cell array 102 is configured to function as an additional timer and can be used by the integrated circuit 100 and the controller 104 to track the duration since power off. Thus, the integrated circuit 100 provides an additional timer that functions as an additional security mechanism, thereby providing additional security / protection of the contents of the integrated circuit 100 compared to other methods.

[0040] In some embodiments, a user successfully logs into the integrated circuit 100; thereafter, the controller 104 is configured to write data to each memory cell in the memory cell array 102 in response to the integrated circuit 100 being successfully logged in. In some embodiments, the integrated circuit 100 is powered off or turned off and then subsequently powered on or turned on by one or more users. In some embodiments, the controller 104 is configured to read data from each memory cell in the memory cell array 102 in response to the integrated circuit 100 being powered on. In some embodiments, the controller 104 is configured to determine whether to allow authentication operations of the integrated circuit 100 in response to reading data from each memory cell in the memory cell array 102. In some embodiments, the authentication operation includes providing operations for one or more users who log in to the integrated circuit 100 or 500. Other authentication operations or functions are within the scope of the present disclosure.

[0041] In some embodiments, the controller 104 is configured to determine whether the data read from the memory cell array 102 is equal to the data written to the memory cell array 102. In some embodiments, the memory cell array 102 is configured as a timer and tracks the time since the integrated circuit 100 was powered off by comparing the data read from the memory cell array 102 with the data written to the memory cell array 102.

[0042] In some embodiments, if the data read from the memory cell array 102 is the same as the data written to the memory cell array 102, the leakage current is insufficient to cause the data stored in the memory cell array 102 to change logic states because it is powered off, thus indicating that an insufficient amount of time has passed since the integrated circuit 100 was powered off. In some embodiments, if an insufficient amount of time has passed since the integrated circuit 100 was powered off, the first time T1 since the integrated circuit 100 was powered off is not greater than a login timer (e.g., a minimum time), and the controller 104 does not allow the user to perform an authentication operation (e.g., a password attempt to log into the integrated circuit 100).

[0043] In some embodiments, if the data read from the memory cell array 102 is different from the data written to the memory cell array 102, the leakage current since power off is sufficient to cause the data stored in the memory cell array 102 to change logic states, thus indicating that sufficient time has passed since the integrated circuit 100 was powered off. In some embodiments, if sufficient time has passed since the integrated circuit 100 was powered off, the first time T1 since the integrated circuit 100 was powered off is greater than the login timer (e.g., a minimum time), and the controller 104 allows a user authentication operation (e.g., a password attempt to log into the integrated circuit 100).

[0044] Further details of one or more embodiments of the authentication process are provided in Figure 4 The method 400 is further discussed in detail.

[0045] In some embodiments, by performing a write operation on the memory cell array 102 in response to an initial power-up by the integrated circuit 100, and by performing a read operation on the memory cell array 102 in response to being subsequently powered up, the controller 104 is configured to provide one or more authentication operations to a user of the integrated circuit 100, thereby providing additional security / protection of the data content of the integrated circuit 100 compared to other methods.

[0046] Other configurations of integrated circuit 100 are within the scope of the present disclosure.

[0047] Memory cell array

[0048] Figure 2is a circuit diagram of a memory circuit 200 according to some embodiments.

[0049] The memory circuit 200 is Figure 1 The memory cell array 102 or Figure 5 The present invention is not related to an embodiment of the memory cell array 502 (described below), and thus similar detailed description is omitted.

[0050] With one or more Figures 1 to 8 Components that are the same or similar to those in the drawings are given the same figure marks, and thus their detailed descriptions are omitted.

[0051] exist Figure 2 In some embodiments, the memory circuit 200 is a static random access memory (SRAM) circuit. SRAM is used for illustration, and other types of memory are within the scope of various embodiments. For example, in some embodiments, the memory circuit 200 is a dynamic random access memory (DRAM) circuit. In some embodiments, the memory circuit 200 is an embedded dynamic random access memory (eDRAM) circuit.

[0052] The memory circuit 200 includes a memory cell array 202 having M rows and N columns of memory cells MCB, where N is a positive integer corresponding to the number of columns in the memory cell array 202, and M is a positive integer corresponding to the number of rows in the memory cell array 202. The cell rows in the memory cell array 202 are arranged along a first direction X. The cell columns in the memory cell array 202 are arranged along a second direction Y. The second direction Y is different from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X.

[0053] In some embodiments, each memory cell MCB in the memory cell array 202 is configured to store one bit of data. In some embodiments, the memory circuit 200 is a logic-based memory.

[0054] The number of rows M in the memory cell array 202 is equal to or greater than 1. The number of columns N in the memory cell array 202 is equal to or greater than 1. In some embodiments, the memory cell array 202 includes one or more single-port (SP) SRAM cells. In some embodiments, the memory cell array 202 includes one or more dual-port (DP) SRAM cells. Different types of memory cells MCB in the memory cell array 202 are within the intended scope of the present disclosure.

[0055] The memory circuit 200 further includes N bit lines BL[1], ... BL[N] (collectively referred to as "bit lines BL") and N inverted bit lines BLB[1], ... BLB[N] (collectively referred to as "inverted bit lines BL"). Each column 1, ..., N in the memory cell array 202 overlaps and is coupled to a corresponding bit line BL[1], ..., BL[N] and a corresponding inverted bit line BLB[1], ..., BLB[N]. Each bit line BL or inverted bit line BLB extends in the second direction Y and over a column of cells (e.g., column 1, ..., N).

[0056] In some embodiments, the term "inverted" refers to a signal that is logically inverted. In these embodiments, for example, the inverted bit lines BLB[1], ...BLB[N] carry a signal that is logically inverted from the signal carried by the bit lines BL[1], ...BL[N].

[0057] The memory circuit 200 also includes M word lines WL[1], ..., WL[M] (collectively referred to as "word lines WL"). Each row 1, ..., M in the memory cell array 202 overlaps and is coupled to a corresponding word line WL[1], ..., WL[M]. Each word line WL extends in a first direction X and over a row of cells (e.g., rows 1, ..., M).

[0058] Other configurations of memory circuit 200 are within the scope of the present disclosure. In some embodiments, one or more of the bit line BL, the bar bit line BLB, or the word line WL are not included in memory circuit 200. In some embodiments, one or more of the bit line BL, the bar bit line BLB, or the word line WL are replaced with a corresponding source line SL.

[0059] Memory unit

[0060] According to some embodiments, Figure 3 It is available for Figure 2 Circuit diagram of the memory cell 300 in FIG.

[0061] Memory unit 300 relates to Figure 2 The memory cell 300 is an embodiment of one or more memory cells MCB in the memory cell array 202, and similar detailed description is omitted.

[0062] Memory cell 300 is a six-transistor (6T) single-port (SP) SRAM memory cell for illustration. In some embodiments, memory cell 300 employs a plurality of transistors other than six. Other types of memory are within the scope of various embodiments. For example, in some embodiments, memory cell 300 is a DRAM memory cell or an eDRAM memory cell.

[0063] The memory cell 300 includes two P-type metal oxide semiconductor (PMOS) transistors P1 and P2, and four N-type metal oxide semiconductor (NMOS) transistors N1, N2, N3 and N4. The transistors P1, P2, N1 and N2 form a cross latch or a pair of cross-coupled inverters. For example, the PMOS transistor P1 and the NMOS transistor N1 form a first inverter, and the PMOS transistor P2 and the NMOS transistor N2 form a second inverter.

[0064] A source terminal of each of the PMOS transistors P1 and P2 is configured as a voltage source node NODE_1. Each voltage source node NODE_1 is coupled to a first voltage source VDDI. Each of a drain terminal of the PMOS transistor P1, a drain terminal of the NMOS transistor N1, a gate terminal of the PMOS transistor P2, a gate terminal of the NMOS transistor N2, and a source terminal of the NMOS transistor N3 is coupled together and configured as a storage node ND. Each of a drain terminal of the PMOS transistor P2, a drain terminal of the NMOS transistor N2, a gate terminal of the PMOS transistor P1, a gate terminal of the NMOS transistor N1, and a source terminal of the NMOS transistor N4 is coupled together and configured as a storage node NDB.

[0065] The source terminal of each of the NMOS transistors N1 and N2 is configured as a power supply reference voltage node (not labeled) having a power supply reference voltage VSS. The source terminal of each of the NMOS transistors N1 and N2 is also coupled to provide the reference voltage VSS.

[0066] The word line WL is coupled to the gate terminal of each of the NMOS transistors N3 and N4. The word line WL is also called a write control line because the NMOS transistors N3 and N4 are configured to be controlled by a signal on the word line WL to transfer data between the bit lines BL, BLB and the corresponding nodes ND, NDB.

[0067] The drain terminal of the NMOS transistor N3 is coupled to the bit line BL. The drain terminal of the NMOS transistor N4 is coupled to the bit line BLB. The bit lines BL and BLB are configured as data input and output of the memory cell 300. In some embodiments, in a write operation, applying a logic value to the bit line BL and applying an opposite logic value to the bit line BLB enables the logic value on the bit line to be written to the memory cell 300. Each of the bit lines BL and BLB is referred to as a data line because the data carried on the bit lines BL and BLB are written to and read from the corresponding nodes ND and NDB.

[0068] The word line WL corresponds to Figure 2 One or more word lines WL[1], WL[2], ..., WL[M]. The bit line BL corresponds to Figure 2 One or more bit lines BL[1], BL[2], ..., BL[N] in FIG. Figure 2 One or more inverted bit lines BLB[1], BLB[2], …, BLB[N] in.

[0069] Other configurations of memory cell 300 are within the scope of the present disclosure.

[0070] Figure 4 is a flow chart of a method 400 of operating an integrated circuit according to some embodiments.

[0071] In some embodiments, Figure 4 is to operate the corresponding integrated circuit 100, 700 or Figure 8 800. It should be understood that the Figure 4 Additional operations may be performed before, during, and / or after the method 400 depicted in the embodiment. Some other operations may only be briefly described here. In some embodiments, other operation sequences of the method 400 are within the scope of the present disclosure. In some embodiments, one or more operations of the method 400 are not performed.

[0072] Method 400 includes exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be added, replaced, changed in order, and / or eliminated as appropriate, in accordance with the spirit and scope of the disclosed embodiments. It should be understood that method 400 utilizes features of one or more of integrated circuit 100 or 700, memory circuit 200, memory cell 300, or system 800.

[0073] In operation 402 of method 400, data is written to each memory cell in a first memory cell array. In some embodiments, the first memory cell array of method 400 includes at least memory cell array 102 or 202. In some embodiments, the first memory cell array of method 400 includes memory circuit 200. In some embodiments, the integrated circuit of method 400 includes at least integrated circuit 100 or 700 or system 800.

[0074] In some embodiments, the same data (e.g., a logic "0" or "1") is written to each memory cell in the first memory cell array. In some embodiments, operation 402 includes writing a logic 1 to each memory cell in the first memory cell array. In some embodiments, operation 402 is performed by controller 104. In some embodiments, operation 402 is performed by at least a write driver circuit in X-decoder circuit 106. In some embodiments, each memory cell in the first memory cell array of method 400 includes at least Figure 2 The memory cell MCB or Figure 3Memory cell 300 in.

[0075] In some embodiments, data is written to each memory cell in the first memory cell array in response to powering on or turning on the integrated circuit. In some embodiments, data is written to each memory cell in the first memory cell array in response to a user successfully logging into the integrated circuit. In some embodiments, operation 402 is performed in response to other operations of the integrated circuit.

[0076] In some embodiments, operation 402 includes writing a logic high to memory cell 300. In some embodiments, operation 402 includes turning on NMOS transistors N3 and N4 in response to a word line signal on word line WL, providing a logic high as a voltage on bit line BL or bit line BLB, and then turning off NMOS transistors N3 and N4 in response to the word line signal on word line WL.

[0077] In operation 404 of method 400, the integrated circuit is powered off or shut down. In some embodiments, operation 404 is performed by a user.

[0078] In some embodiments, powering off or shutting down the integrated circuit of method 400 or 600 includes disconnecting the integrated circuit from a power source or supply voltage. In some embodiments, powering off or shutting down the integrated circuit of method 400 or 600 includes removing a battery from the integrated circuit. In some embodiments, powering off or shutting down the integrated circuit of method 400 or 600 includes removing a capacitor from the integrated circuit.

[0079] In operation 406 of method 400, the integrated circuit is powered on or turned on. In some embodiments, operation 406 is performed by a user.

[0080] In some embodiments, powering up or turning on the integrated circuit of method 400 or 600 includes connecting the integrated circuit to a power source or supply voltage. In some embodiments, powering up or turning on the integrated circuit of method 400 or 600 includes connecting a battery to the integrated circuit. In some embodiments, powering up or turning on the integrated circuit of method 400 or 600 includes connecting a capacitor to the integrated circuit.

[0081] In operation 408 of method 400 , in response to the integrated circuit being powered on, data is read from each memory cell in the first memory cell array.

[0082] In some embodiments, operation 408 is performed by controller 104. In some embodiments, operation 408 is performed by at least a sense amplifier circuit in read circuit 110.

[0083] In some embodiments, operation 408 includes precharging the bit line BL and the inverted bit line BLB to a precharge voltage VBL, turning on NMOS transistors N3 and N4 in response to a word line signal on the word line WL, turning on the sense amplifier circuit in response to a sense amplifier enable signal, and latching the data stored in the memory cell 300. In some embodiments, the precharge voltage VBL is equal to the power supply voltage VDD. In some embodiments, the precharge voltage VBL is equal to the power supply reference voltage VSS. In some embodiments, the precharge voltage VBL is between the power supply voltage VDD and the reference voltage VSS.

[0084] In operation 410 of method 400, in response to reading data from each memory cell in the first memory cell array, it is determined whether an authentication operation of the integrated circuit is allowed. In some embodiments, operation 410 is performed by controller 104. In some embodiments, operation 410 is performed by a processor, such as Figure 8 Processor 802.

[0085] In some embodiments, operation 410 includes at least operation 412 , 414 , 416 , 418 , 420 , 422 , or 424 .

[0086] In operation 412 of method 400 , it is determined whether data read from at least one memory cell in the first memory cell array is not equal to data written to at least one memory cell in the first memory cell array.

[0087] In some embodiments, operation 412 is performed by controller 104. In some embodiments, operation 412 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0088] In some embodiments, if the data read from at least one memory cell in the first memory cell array is not equal to the data written to at least one corresponding memory cell in the first memory cell array, the leakage current is sufficient to cause the data stored in the first memory cell array to change logic state after power is removed, indicating that a sufficient amount of time has passed since the integrated circuit 100 was powered off, and the result of operation 412 is "no", and the method 400 proceeds to operation 414.

[0089] In some embodiments, if the data read from at least one memory cell in the first memory cell array is equal to the data written to at least one corresponding memory cell in the first memory cell array, the leakage current is insufficient to cause the data stored in at least one memory cell in the first memory cell array to change logic state since power was turned off, thereby indicating that an insufficient amount of time has passed since the integrated circuit 100 was powered off, and the result of operation 412 is "yes", and the method 400 proceeds to operation 420.

[0090] In operation 414 of method 400, it is determined that the first time T1 since the integrated circuit was powered off is greater than the minimum time of the login timer. In some embodiments, operation 414 indicates that a sufficient amount of time (e.g., the first time T1) has passed since the integrated circuit 100 was powered off, and the amount of time (e.g., the first time T1) is therefore greater than the login timer.

[0091] In some embodiments, operation 414 is performed by controller 104. In some embodiments, operation 414 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0092] In some embodiments, operation 414 includes the controller 104 determining that a sufficient amount of time has elapsed since the integrated circuit 100 was powered off to determine that the first time T1 since the integrated circuit was powered off is substantially greater than the login timer.

[0093] In operation 416 of method 400, in response to determining that the first time T1 since power was turned off for the integrated circuit is greater than the minimum time, the flag is set to a first value. In some embodiments, the flag corresponds to a single data bit. In some embodiments, the flag corresponds to more than one bit of data. In some embodiments, the first value is equal to a logical 1. In some embodiments, the first value is equal to a logical 0.

[0094] In some embodiments, operation 416 is performed by controller 104. In some embodiments, operation 416 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0095] In operation 418 of method 400 , an authentication operation of the integrated circuit is permitted or performed in response to the flag being the first value.

[0096] In some embodiments, operation 418 is performed by controller 104 or system 800. In some embodiments, operation 418 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0097] In some embodiments, operation 418 includes prompting the user with a password authentication or login operation. In some embodiments, operation 418 includes enabling a password authentication or login operation for the user such that the system 800 prompts the user for a password authentication or login operation. In some embodiments, the authentication operation includes providing the user with an attempt to log into the integrated circuit 100 by prompting the user to enter a password.

[0098] In operation 420 of method 400, it is determined that the first time T1 since the integrated circuit was powered off is not greater than the minimum time of the login timer. In some embodiments, operation 420 indicates that an insufficient amount of time (e.g., the first time T1) has passed since the integrated circuit 100 was powered off, and the amount of time (e.g., the first time T1) is therefore not greater than the minimum time login timer.

[0099] In some embodiments, operation 420 is performed by controller 104. In some embodiments, operation 420 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0100] In some embodiments, operation 420 includes the controller 104 determining that an insufficient amount of time has elapsed since the integrated circuit 100 was powered off, thereby determining that the first time T1 since the integrated circuit was powered off is not substantially greater than a minimum time log timer.

[0101] In operation 422 of method 400, in response to determining that the first time T1 since the integrated circuit was powered off is not greater than the minimum time, the flag is set to a second value. In some embodiments, the second value is different from the first value. In some embodiments, the first value is equal to a logical 1 and the second value is a logical 0. In some embodiments, the first value is equal to a logical 0 and the second value is a logical 1.

[0102] In some embodiments, operation 422 is performed by controller 104. In some embodiments, operation 422 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0103] In operation 424 of method 400 , in response to the flag being the second value, an authentication operation of the integrated circuit is not allowed or performed.

[0104] In some embodiments, operation 424 is performed by controller 104 or system 800. In some embodiments, operation 424 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0105] In some embodiments, operation 424 includes not prompting the user for a password authentication or login operation. In some embodiments, operation 424 includes disabling a password authentication or login operation for the user so that the system 800 does not prompt the user for a password authentication or login operation.

[0106] In some embodiments, after operation 424, the method 400 proceeds to operation 408 to perform an additional read operation of the first memory cell array. In some embodiments, the additional read operation is performed in operation 408 to determine whether at least one memory cell in the first memory cell array changes logic state to allow the user to proceed to the authentication operation of operation 418. In other words, after operation 424, the method 400 proceeds to operation 408 to perform additional read operations of the first memory cell array until a sufficient amount of time (e.g., first time T1) has passed since the integrated circuit 100 was powered off to allow the user to proceed to the authentication operation of operation 418. In some embodiments, after operation 424, the method 400 remains in an idle state until the login timer expires.

[0107] By operating the method 400, the integrated circuit operates to achieve the benefits discussed above with respect to the integrated circuit 100. Figure 1 , Figure 2 and Figure 3 Method 400 is described, but it should be understood that method 400 utilizes Figures 7 and 8 In some embodiments, the method 400 is described above with reference to SRAM, but is also applicable to DRAM or eDRAM, and similar detailed description is omitted.

[0108] Figure 5 is a block diagram of an integrated circuit 500 according to some embodiments. In the embodiment of FIG. Figure 5 In FIG. 5 , integrated circuit 500 is a memory macro.

[0109] IC 500 is Figure 1 The integrated circuit 100 is a variant of the integrated circuit 100, and thus similar detailed description is omitted. Figure 1 Compared to the integrated circuit 100, the integrated circuit 500 further includes a memory cell array 502, a power supply 520, and a power supply 522. In some embodiments, the memory cell array 502 has different Figure 1 The size of the memory cell array 102 is as follows.

[0110] By further including memory cell array 502, integrated circuit 500 includes two memory cell arrays (memory cell arrays 102 and 502) that are configured to have different corresponding data retention times, and thus effectively have different corresponding timers, thereby providing further security / protection of the contents of integrated circuit 500 over a range of different temperature regions compared to other approaches.

[0111] The memory cell arrays 102 and 502 are configured to have different corresponding data retention times. The memory cell arrays 102 and 502 have different corresponding data retention times by having different array sizes or being coupled to different corresponding power supplies 520 and 522 with different corresponding capacitances. In some embodiments, by adjusting the size of the memory cell arrays 102 and 502 or adjusting the capacitance of the power supplies 520 and 522 (e.g., Figure 7 The data retention time of the memory cell arrays 102 and 502 is also adjusted so as to adjust the corresponding timer.

[0112] In some embodiments, memory cell arrays 102 and 502 are configured to have different corresponding leakage currents that discharge at different rates, thereby having different corresponding data retention times over a range of different temperature regions.

[0113] In some embodiments, memory cell arrays 102 and 502 are coupled to different corresponding power supplies 520 and 522 that are configured to have different corresponding capacitances, thereby causing corresponding memory cell arrays 102 and 502 to have different corresponding data retention times over a range of different temperature regions.

[0114] Integrated circuit 500 includes memory cell array 102, controller 104, memory cell array 502, power supply 520, and power supply 522. In some embodiments, memory cell array 502 is similar to memory cell array 102, so similar detailed description is omitted. In some embodiments, memory cell array 202 is an embodiment of memory cell array 502, so similar detailed description is omitted.

[0115] and Figure 1 Compared with the memory cell array 102, Figure 5 The memory cell array 102 in the embodiment is coupled to a power supply 520. The power supply 520 is configured to provide a power supply voltage Vddv1 to a node Nde1 of the memory cell array 102. The node Nde1 corresponds to Figure 3 In some embodiments, the power supply voltage Vddv1 is equal to the power supply voltage VDD. In some embodiments, by adjusting the capacitance of the power supply 520 (for example, Figure 7 The capacitor C1 in the memory cell array 102 is used to adjust the data retention time of the memory cell array 102.

[0116] The memory cell array 502 is connected to the controller 104. In some embodiments, the memory cell array 502 is connected to the controller 104 at least through a bit line BL, an inverted bit line BLB, a word line WL, or other conductive lines. The controller 104 is configured to control the memory cell array 502. In some embodiments, the controller 104 is configured to provide one or more safety measures (described below) to the integrated circuit 500. The memory cell array 502 is further coupled to a reference power supply voltage VSS and a power supply 522. The power supply 522 is configured to provide a power supply voltage Vddv2 to the memory cell array 502. In some embodiments, at least the power supply voltage VDD, Vddv1, or Vddv2 is equal to at least another of the power supply voltages VDD, Vddv1, or Vddv2. In some embodiments, at least the power supply voltage VDD, Vddv1, or Vddv2 is different from at least another of the power supply voltages VDD, Vddv1, or Vddv2. In some embodiments, by adjusting the capacitance of the power supply 522 (e.g., Figure 7 The capacitor C1 in the memory cell array 502 is used to adjust the data retention time of the memory cell array 502.

[0117] In some embodiments, the memory cell array 502 is a volatile memory cell array. In some embodiments, the memory cell array 502 includes a volatile memory cell array that is configured to lose stored data therein due to leakage current. In some embodiments, each memory cell in the memory cell array 502 corresponds to an SRAM cell. In some embodiments, each memory cell in the memory cell array 502 corresponds to a DRAM cell. In some embodiments, each memory cell in the memory cell array 102 corresponds to an eDRAM cell. Other types of memory cells in the memory cell array 502 are within the intended scope of the present disclosure.

[0118] In some embodiments, each memory cell in the memory cell array 502 is configured to store 1 bit of data. In some embodiments, each memory cell in the memory cell array 502 is configured to store more than 1 bit of data.

[0119] The memory cell array 502 includes a memory cell array having X rows and Y columns, where X and Y are positive integers (eg, Figure 2 In some embodiments, at least row X or column Y is different from at least corresponding row M or column N.

[0120] The retention time of the memory cell array is inversely proportional to the size of the memory cell array. The size of the memory cell array is directly related to the leakage current speed of the memory cell array, which is inversely proportional to the retention time of the memory cell array. In other words, the speed of the leakage current is based on the size of the memory cell array.

[0121] For example, a larger memory cell array (with more cells) has a larger leakage current and therefore a faster bit flip time than a smaller memory cell array (with fewer cells). Therefore, data stored in a larger memory cell array (with more cells) will discharge faster than a smaller memory cell, and the larger memory cell array will retain the data for a shorter time than data stored in a smaller memory cell.

[0122] Additionally, a smaller memory cell array (with fewer cells) has less leakage current and therefore a slower bit flip time than a larger memory cell array (with more cells). Thus, data stored in a smaller memory cell array (with fewer cells) will discharge more slowly than a larger memory cell, and the smaller memory cell array will retain data longer than data stored in a larger memory cell.

[0123] In some embodiments, memory cell array 502 has a different array size than memory cell array 102. For example, in some embodiments, if memory cell array 102 has N columns or M rows, then memory cell array 502 has at least a different number of columns than N or a different number of rows than M, where M and N are positive integers.

[0124] The memory cell array 102 has a first array size and a first leakage path. The first leakage path has a first leakage current.

[0125] The memory cell array 502 has a second array size and a second leakage path. The second leakage path has a second leakage current. In some embodiments, the first leakage path is smaller than the second leakage path. In some embodiments, the first leakage current is smaller than the second leakage current.

[0126] In some embodiments, the second array size of the memory cell array 502 is larger than the first array size of the memory cell array 102, and thus the second leakage current of the second path of the memory cell array 502 is larger than the first leakage current of the first path of the memory cell array 102. Therefore, in some embodiments, the data stored in the memory cell array 502 will be discharged faster than the data stored in the memory cell array 102. In other words, in some embodiments, the memory cell array 102 will retain the data for a longer duration than the data retained by the memory cell array 502.

[0127] In some embodiments, the second array size of memory cell array 502 is no greater than the first array size of memory cell array 102. In some embodiments, the second array size of memory cell array 502 is equal to the first array size of memory cell array 102.

[0128] The retention time of the memory cell array is directly related to the capacitance of the power supply provided to the memory cell array (eg, power supply 520 or 522). In other words, the retention time of the memory cell array is based on the capacitance of the power supply provided to the memory cell array.

[0129] For example, a memory cell array coupled to a power supply with a larger capacitance (e.g., power supply 520) thus has a larger retention time and a slower bit flip time. Therefore, data stored in a memory cell array coupled to a power supply with a larger capacitance (e.g., power supply 520) will discharge slower and retain data longer than data stored in a memory cell array coupled to a power supply with a lower capacitance (e.g., power supply 522).

[0130] In addition, the memory cell array coupled to the power supply with smaller capacitance (e.g., power supply 522) thus has smaller retention time and faster bit flip time. Therefore, data stored in the memory cell array coupled to the power supply with smaller capacitance (e.g., power supply 522) will discharge faster and retain data for a shorter time than data stored in the memory cell coupled to the power supply with larger capacitance (e.g., power supply 520).

[0131] The memory cell array 102 is coupled to a power supply 520 having a first capacitor. The power supply 520 is coupled to the power supply voltage VDD and is configured to provide a power supply voltage Vddv1 to the node Nde1. The memory cell array 502 is coupled to a power supply 522 having a second capacitor. The power supply 522 is coupled to the power supply voltage VDD and is configured to provide a power supply voltage Vddv2 to the node Nde2.

[0132] In some embodiments, the first capacitance of power source 520 is greater than the second capacitance of power source 522, thereby causing the data stored in memory cell array 102 to discharge more slowly than the data stored in memory cell array 502. In some embodiments, because the data stored in memory cell array 102 discharges more slowly than the data stored in memory cell array 502, the data stored in memory cell array 102 is retained for a longer period of time than the data stored in memory cell array 502. Therefore, in some embodiments, the duration for which memory cell array 102 retains data will be greater than the duration for which memory cell array 502 retains data.

[0133] In some embodiments, the memory cell arrays 102 and 502 have different corresponding data retention times by having different array sizes or being coupled to different corresponding power supplies 520 and 522 with different corresponding capacitances. In some embodiments, the different data retention times of the memory cell arrays 102 and 502 can be used as different corresponding timers (e.g., the first time T1 in the method 600), thereby providing further security / protection of the contents of the integrated circuit 500 over a range of different temperature regions compared to other methods.

[0134] The integrated circuit 500 is configured to operate within different temperature ranges. For example, in some embodiments, as the temperature of the integrated circuit 500 increases, the leakage current or discharge rate of the data stored in the memory cell arrays 102 and 502 also increases, thereby reducing the retention time of the data stored in the memory cell arrays 102 and 502. For example, in some embodiments, as the temperature of the integrated circuit 500 decreases, the leakage current or discharge rate of the data stored in the memory cell arrays 102 and 502 also decreases, thereby increasing the retention time of the data stored in the memory cell arrays 102 and 502.

[0135] The user may attempt to change the temperature of the integrated circuit 500 in order to gain access to the integrated circuit 500, thereby attempting to circumvent the security measures provided by the integrated circuit 100 or 500. For example, the user may heat the integrated circuit 500, thereby increasing the temperature of the integrated circuit 500 to accelerate the leakage current or reduce the retention time of the data stored in the memory cell array 102 or 502. By accelerating the leakage current or reducing the retention time of the data stored in the memory cell array 102 or 502, the user attempts to advance the first time T1 (e.g., method 400 or 600) to be greater than the login timer (e.g., minimum time), thereby attempting to gain unauthorized access to the integrated circuit 100 or 500.

[0136] However, because integrated circuit 500 includes memory cell arrays (eg, memory cell arrays 102 and 502 ) having different data retention times, integrated circuit 500 is able to overcome attempts by users to change the temperature of integrated circuit 500 to gain unauthorized access to integrated circuit 500 .

[0137] For example, in some embodiments, the memory cell array 102 and the memory cell array 502 are configured to lose data retention in two different temperature regions (e.g., a first temperature region T1 and a second temperature region T2), so that temperature acceleration of the leakage current or reduction of the retention time of the data stored in one of the memory cell arrays 102 or 502 by the user 500 cannot successfully accelerate the leakage current in both the memory cell arrays 102 or 502.

[0138] The memory cell array 102 is configured to have memory cells that lose data retention in a first temperature region Templ after a period of time (e.g., a first time T1). In some embodiments, the memory cell array 102 is configured to have a first leakage path (e.g., smaller) with a first leakage current (e.g., smaller) compared to the memory cell array 502, and the memory cells in the memory cell array 102 are configured to lose data retention in a first temperature region Temp1 (e.g., a higher temperature) after a period of time (e.g., a first time T1). In other words, in some embodiments, the memory cell array 102 is configured or designed to discharge at a higher temperature through a low (e.g., slow) leakage path after the duration of the first time T1.

[0139] The memory cell array 502 is configured to have memory cells that lose data retention in a second temperature region Temp2 after a period of time (e.g., a first time T1). In some embodiments, the memory cell array 502 is configured to have a second leakage path (e.g., larger) with a second leakage current (e.g., larger) compared to the memory cell array 102, and the memory cells in the memory cell array 502 are configured to lose data retention in a second temperature region Temp2 (e.g., a lower temperature) after a period of time (e.g., a first time T1). In other words, in some embodiments, the memory cell array 502 is configured or designed to discharge at a lower temperature through a fast (e.g., faster) leakage path after the duration of the first time T1.

[0140] In some embodiments, the first temperature region Templ is greater than the second temperature region Temp2, so the memory cell array 102 is configured to have memory cells that lose data retention at the first temperature region Templ (e.g., a higher temperature) after a duration (e.g., the first time T1), and the memory cell array 502 is configured to have memory cells that lose data retention at the second temperature region Temp2 (e.g., a lower temperature) after a duration (e.g., the first time T1).

[0141] In some embodiments, the user is prevented from heating the integrated circuit 500 to speed up the timer (e.g., first time T1) by having an additional memory cell array (e.g., memory cell array 102) configured to discharge at a higher temperature and at a different rate than the memory cell array 502. For example, in some embodiments, the integrated circuit 500 is designed so that the memory cell array 102 is configured to discharge at a slower rate (e.g., retain data longer) than the memory cell array 502 after a duration T1 has passed at a heated temperature (e.g., first temperature region Temp1). Therefore, if the integrated circuit 500 is heated by the user, the faster-discharging memory cells in the memory cell array 502 will have been discharged, but the slower-discharging memory cells in the memory cell array 102 will not be discharged until the timer expires (e.g., first time T1). Therefore, the user's attempt to heat the integrated circuit 500 to advance the timer is frustrated, and the integrated circuit 500 prevents the user from gaining access.

[0142] In some embodiments, the integrated circuit 500 is prevented from having an excessively long login timer by having an additional memory cell array (e.g., memory cell array 502) configured to discharge at a lower temperature and at a different rate than the memory cell array 102. For example, if the memory cell array 102 with a slower discharge time is used at a temperature lower than the first temperature Temp1 (e.g., the second temperature Temp2), the memory cell array 102 will not discharge until the timer (e.g., the first time T1) is far exceeded, which will cause the login timer to be too long. Therefore, the integrated circuit 500 is prevented from having an excessively long login timer by having the additional memory cell (e.g., memory cell array 502) having a faster discharge time at a temperature lower than the first temperature Temp1 (e.g., the second temperature Temp2).

[0143] In some embodiments, the first temperature region Temp1 is smaller than the second temperature region Temp2.

[0144] In some embodiments, during operation of the integrated circuit 500, a user successfully logs into the integrated circuit 500; thereafter, the controller 104 is configured to write data to each memory cell in the memory cell arrays 102 and 502 in response to the integrated circuit 500 being successfully logged in. In some embodiments, the integrated circuit 500 is powered off or turned off, and then subsequently powered on or turned on by one or more users. In some embodiments, the controller 104 is configured to read data from each memory cell in the memory cell arrays 102 and 502 in response to the integrated circuit 500 being powered on. In some embodiments, the controller 104 is configured to determine whether to allow authentication operations of the integrated circuit 500 in response to reading data from each memory cell in the memory cell arrays 102 and 502. In some embodiments, the authentication operations include providing one or more login operations of the integrated circuit 100 or 500 to the user. Other authentication operations or functions are within the scope of the present disclosure.

[0145] In some embodiments, the controller 104 is configured to determine whether the data read from the memory cell array 102 is equal to the data written to the memory cell array 102, and the controller 104 is configured to determine whether the data read from the memory cell array 502 is equal to the data written to the memory cell array 502. In some embodiments, the memory cell array 102 or 502 is configured as a timer and tracks the time since the integrated circuit 500 was powered off by comparing the data read from the memory cell array 102 with the data written to the memory cell array 102 or by comparing the data read from the memory cell array 502 with the data written to the memory cell array 502.

[0146] For example, in some embodiments, if the temperature of the integrated circuit 500 increases to be equal to or greater than the second temperature region Temp2, the controller 104 will determine that the memory cells in the memory cell array 502 have lost data retention in response to reading the memory cell array 502, and the controller 104 will determine whether the memory cells in the memory cell array 102 have lost data retention in response to reading the memory cell array 102. In these embodiments, if the memory cells in the memory cell array 102 have lost data retention in response to reading the memory cell array 102, the controller 104 determines that a sufficient amount of time has passed since the integrated circuit 500 was powered off, and the first time T1 since the integrated circuit 500 was powered off is greater than the login timer (e.g., a minimum time), and the controller 104 allows the user to perform an authentication operation (e.g., a password attempt to log into the integrated circuit 500). In these embodiments, if the memory cells in the memory cell array 102 have not lost data retention in response to reading the memory cell array 102, the controller 104 waits until the memory cells in the memory cell array 102 have lost data retention in response to performing another read operation of the memory cell array 102. In these embodiments, if a memory cell in the memory cell array 102 loses data retention in response to another read operation of the memory cell array 102, the controller 104 determines that the integrated circuit 500 is powered off and the first time T1 since the integrated circuit 500 was powered off is greater than a login timer (e.g., a minimum time), and the controller 104 allows the user to perform an authentication operation (e.g., a password attempt to log into the integrated circuit 500).

[0147] For example, in some embodiments, if the temperature of the integrated circuit 500 is below the second temperature region Temp2, the controller 104 will determine whether the memory cells in the memory cell array 502 have lost data retention in response to reading the memory cell array 502, and the controller 104 will determine whether the memory cells in the memory cell array 102 have lost data retention in response to reading the memory cell array 102. In these embodiments, if the memory cells in the memory cell array 502 have not lost data retention in response to reading the memory cell array 502, the controller 104 waits until the memory cells in the memory cell array 502 have lost data retention in response to performing another read operation of the memory cell array 502. In these embodiments, if the memory cells in the memory cell array 502 have lost data retention in response to performing another read operation of the memory cell array 502, the controller 104 determines that the integrated circuit 500 has been powered off, and the first time T1 since the integrated circuit 500 was powered off is greater than the login timer (e.g., a minimum time), and the controller 104 allows the user to perform an authentication operation (e.g., a password attempt to log into the integrated circuit 500). In these embodiments, if a memory cell in the memory cell array 502 loses data retention in response to reading the memory cell array 502, the controller 104 will determine whether the memory cells in the memory cell array 102 lose data retention in response to reading the memory cell array 102, similar to the above, and similar descriptions are omitted.

[0148] Other configurations of at least memory cell arrays 102 or 502 are within the scope of the present disclosure. Other numbers of at least memory cell arrays 102 or 502 having different corresponding sizes are within the scope of the present disclosure.

[0149] Other configurations of at least the power circuit 520 or 522 are within the scope of the present disclosure. Other capacitance values ​​of at least the power circuit 520 or 522 are within the scope of the present disclosure.

[0150] Further details of one or more embodiments of the authentication process are provided in Figure 6A-6C The method 600 is further discussed in detail.

[0151] In some embodiments, by having memory cell arrays 102 and 502 with different array sizes or power supply circuits 520 and 522 with different capacitance values, the retention time of data stored in memory cell arrays 102 and 502 is different. In some embodiments, by configuring memory cell arrays 102 and 502 to have different retention times, integrated circuit 500 effectively has two different timers, thereby providing further safety / protection of the contents of integrated circuit 500 over different temperature regions compared to other approaches.

[0152] Other configurations of integrated circuit 500 are within the scope of the present disclosure.

[0153] Figure 6A-6C is a flow chart of a method 600 of operating an integrated circuit according to some embodiments.

[0154] In some embodiments, Figure 6A-6C is a flow chart of a method of operating the integrated circuit 500, 700 or the system 800. It should be understood that the Figure 6A-6C Additional operations may be performed before, during, and / or after the method 600 depicted in the embodiment, and some other operations are only briefly described herein. In some embodiments, other operation sequences of the method 600 are within the scope of the present disclosure. In some embodiments, one or more operations of the method 600 are not performed.

[0155] Method 600 includes exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be added, replaced, changed in order, and / or eliminated as appropriate, in accordance with the spirit and scope of the disclosed embodiments. It should be understood that method 600 utilizes features of one or more of integrated circuit 500 or 700, memory circuit 200, memory cell 300, or system 800.

[0156] In operation 602 of method 600 , data is written to each memory cell in the first memory cell array and the second memory cell array.

[0157] In some embodiments, the first memory cell array of method 600 includes at least memory cell array 202 or 502. In some embodiments, the first memory cell array of method 600 includes memory circuit 200. In some embodiments, integrated circuit method 600 includes at least integrated circuit 500 or 700 or system 800.

[0158] In some embodiments, the second memory cell array of method 600 includes at least memory cell array 102 or 202. In some embodiments, the second memory cell array of method 600 includes memory circuit 200.

[0159] In some embodiments, the same data (e.g., logic "0" or "1") is written to each memory cell in the first memory cell array and the second memory cell array. In some embodiments, operation 602 includes writing a logic 1 to each memory cell in the first memory cell array and the second memory cell array. In some embodiments, operation 602 is performed by controller 104. In some embodiments, operation 602 is performed by at least a write driver circuit in X decoder circuit 106. In some embodiments, each memory cell in the first memory cell array and the second memory cell array of method 600 includes at least Figure 2 The memory cell MCB or Figure 3 Memory cell 300 in.

[0160] In some embodiments, data is written to each memory cell in the first memory cell array and the second memory cell array in response to powering on or turning on the integrated circuit 500. In some embodiments, data is written to each memory cell in the first memory cell array and the second memory cell array. In response to a user successfully logging into the integrated circuit, the first memory cell array and the second memory cell array. In some embodiments, operation 602 is performed in response to other operations of the integrated circuit.

[0161] In some embodiments, operation 602 includes writing a logic high to memory cell 300. In some embodiments, operation 602 includes turning on NMOS transistors N3 and N4 in response to a word line signal on word line WL, providing a logic high as a voltage on bit line BL or bit line BLB, and then turning off NMOS transistors N3 and N4 in response to a word line signal on word line WL.

[0162] In operation 604 of method 600, the integrated circuit is powered off or shut down. In some embodiments, operation 604 is performed by a user.

[0163] In some embodiments, powering off or shutting down the integrated circuit of method 600 includes disconnecting the integrated circuit from a power source or supply voltage. In some embodiments, powering off or shutting down the integrated circuit of method 600 includes removing a battery from the integrated circuit. In some embodiments, powering off or shutting down the integrated circuit of method 600 includes removing a capacitor from the integrated circuit.

[0164] In operation 606 of method 600, the integrated circuit is powered on or turned on. In some embodiments, operation 606 is performed by a user.

[0165] In some embodiments, powering up or turning on the integrated circuit of method 600 includes connecting the integrated circuit to a power source or supply voltage. In some embodiments, powering up or turning on the integrated circuit of method 600 includes connecting a battery to the integrated circuit. In some embodiments, powering up or turning on the integrated circuit of method 600 includes connecting a capacitor to the integrated circuit.

[0166] In operation 608 of method 600 , in response to the integrated circuit being powered on, data is read from at least each memory cell in the first memory cell array or the second memory cell array.

[0167] In some embodiments, operation 608 is performed by controller 104. In some embodiments, operation 608 is performed by at least a sense amplifier circuit in read circuit 110.

[0168] In some embodiments, operation 608 includes precharging the bit line BL and the inverted bit line BLB to a precharge voltage VBL, turning on the NMOS transistors N3 and N4 in response to a word line signal on the word line WL, turning on the sense amplifier circuit in response to a sense amplifier enable signal, and latching the data stored in the memory cell 300. In some embodiments, the precharge voltage VBL is equal to the power supply voltage VDD. In some embodiments, the precharge voltage VBL is equal to the power supply reference voltage VSS. In some embodiments, the precharge voltage VBL is between the power supply voltage VDD and the reference voltage VSS.

[0169] In operation 610 of method 600, in response to reading data from at least each memory cell in the first memory cell array or the second memory cell array, it is determined whether to allow an authentication operation of the integrated circuit. In some embodiments, operation 610 is performed by the controller 104. In some embodiments, operation 610 is performed by a processor, such as Figure 8 Processor 802.

[0170] In some embodiments, operation 610 includes at least operation 612 , 614 , 616 , 618 , 620 , 622 , 624 , 626 , 628 , 630 , 632 , 634 , 636 , 638 , 640 , or 642 .

[0171] In operation 612 of method 600, it is determined whether the data read from the first memory cell array is equal to the data written to the first memory cell array. In some embodiments, operation 612 also includes determining whether the data read from at least one memory cell in the first memory cell array is equal to the data written to at least one memory cell in the first memory cell array.

[0172] In some embodiments, operation 612 is performed by controller 104. In some embodiments, operation 612 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0173] In some embodiments, if the data read from at least one memory cell in the first memory cell array is equal to the data written to at least one corresponding memory cell in the first memory cell array, the first leakage current is insufficient to cause the data stored in the first memory cell array to change logic state after power is removed, thereby indicating that an insufficient amount of time has passed since the integrated circuit 500 was powered off, and the result of operation 612 is "yes", and the method 600 proceeds to operation 614.

[0174] In some embodiments, the first memory cell array of method 600 includes memory cell array 502. In some embodiments, the first leakage current of method 600 includes the second leakage current of memory cell array 502. In some embodiments, the first leakage current of method 600 is determined by at least a size of the first memory cell array or a capacitance of a first power supply to which the first memory cell array is coupled. In some embodiments, the first power supply of method 600 is power supply 522.

[0175] In some embodiments, the memory cell array 502 is configured to have memory cells that lose data retention in a second temperature region Temp2 after a period of time (e.g., a first time T1). In some embodiments, the memory cell array 502 is configured to have a second leakage path (e.g., larger) with a second leakage current (e.g., larger) compared to the memory cell array 102, and the memory cells in the memory cell array 502 are configured to lose data retention in a second temperature region Temp2 (e.g., a lower temperature) after a period of time (e.g., a first time T1). In other words, in some embodiments, the memory cell array 502 is configured or designed to discharge at a lower temperature through a fast (e.g., faster) leakage path after the duration of the first time T1.

[0176] In some embodiments, if the data read from at least one memory cell in the first memory cell array is not equal to the data written to at least one corresponding memory cell in the first memory cell array, the first leakage current is sufficient to cause the data stored in at least one memory cell in the first memory cell array to change logic state after power is removed, thereby indicating that a sufficient amount of time has passed since the integrated circuit 500 was powered off, and the result of operation 612 is "no", and the method 600 proceeds to operation 620.

[0177] In operation 614 of method 600, it is determined that the first time T1 since the integrated circuit was powered off is not greater than the minimum time of the login timer. In some embodiments, operation 614 indicates that an insufficient amount of time (e.g., the first time T1) has passed since the integrated circuit 500 was powered off, and the amount of time (e.g., the first time T1) is therefore not greater than the minimum time login timer.

[0178] In some embodiments, operation 614 is performed by controller 104. In some embodiments, operation 614 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0179] In some embodiments, operation 614 includes the controller 104 determining that an insufficient amount of time has elapsed since the integrated circuit 500 was powered off, thereby determining that the first time T1 since the integrated circuit was powered off is not substantially greater than a minimum time log timer.

[0180] In operation 616 of method 600 , in response to determining that the first time T1 since the integrated circuit was turned off is not greater than a minimum time, a first flag is set to a first value.

[0181] In some embodiments, the first flag of method 600 corresponds to a single bit of data. In some embodiments, the first flag method 600 corresponds to more than one bit of data. In some embodiments, the first value of the first flag is equal to a logical 1. In some embodiments, the first value of the first flag is equal to a logical 0.

[0182] In some embodiments, operation 616 is performed by controller 104. In some embodiments, operation 616 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0183] In operation 618 of method 600 , in response to the first flag being the first value, an authentication operation of the integrated circuit is not allowed or performed.

[0184] In some embodiments, operation 618 is performed by controller 104 or system 800. In some embodiments, operation 618 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0185] In some embodiments, operation 618 includes not prompting the user for a password authentication or login operation. In some embodiments, operation 618 includes disabling a password authentication or login operation for the user so that the system 800 does not prompt the user for a password authentication or login operation.

[0186] In operation 620 of method 600, an additional read operation of the first memory cell array is performed. In some embodiments, the additional read operation of operation 620 is performed until the data read from the first memory cell is not equal to the data written to the first memory cell. In some embodiments, the additional read operation of operation 620 is performed until the data read from at least one memory cell in the first memory cell array changes a logic state. In some embodiments, the additional read operation is performed in operation 620 to determine whether at least one memory cell in the first memory cell array changes a logic state.

[0187] In some embodiments, operation 620 is performed by controller 104 or system 800. In some embodiments, operation 620 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0188] In some embodiments, after operation 618, the method 600 proceeds to operation 620 to perform additional read operations of the first memory cell array until a sufficient amount of time (e.g., first time T1) has passed since the integrated circuit 500 was powered off, thereby allowing the user to perform an authentication operation of operation 626. In some embodiments, in operation 620, the method 600 remains in an idle state until the login timer expires.

[0189] In operation 622 of method 600, it is determined that the first time T1 since the integrated circuit was turned off is greater than the minimum time of the login timer. In some embodiments, operation 622 indicates that a sufficient amount of time (e.g., the first time T1) has passed since the integrated circuit 500 was powered off, and the amount of time (e.g., the first time T1) is therefore greater than the login timer.

[0190] In some embodiments, operation 622 is performed by controller 104. In some embodiments, operation 622 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0191] In some embodiments, operation 622 includes the controller 104 determining that a sufficient amount of time has elapsed since the integrated circuit 500 was powered off to determine that the first time T1 since the integrated circuit was powered off is substantially greater than the login timer.

[0192] In operation 624 of method 600 , in response to determining that the first time T1 since the integrated circuit was powered off is greater than the minimum time, the first flag is set to a second value.

[0193] In some embodiments, the second value of the first flag is different from the first value of the first flag. In some embodiments, the first value of the first flag is equal to a logical 1, and the second value of the first flag is a logical 0. In some embodiments, the first value of the first flag is equal to a logical 0, and the second value of the first flag is a logical 1.

[0194] In some embodiments, operation 624 is performed by controller 104. In some embodiments, operation 624 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0195] In operation 626 of method 600 , in response to the first flag being the second value, an authentication operation of the integrated circuit is permitted or performed.

[0196] In some embodiments, operation 626 is performed by controller 104 or system 800. In some embodiments, operation 626 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0197] In some embodiments, operation 626 includes prompting the user with a password authentication or login operation. In some embodiments, operation 626 includes enabling a password authentication or login operation for the user so that the system 800 prompts the user for a password authentication or login operation. In some embodiments, the authentication operation includes providing the user with an attempt to log into the integrated circuit 500 by prompting the user to enter a password.

[0198] In operation 628 of method 600 , it is determined whether the data read from the second memory cell array is equal to the data written to the second memory cell array.

[0199] In some embodiments, operation 628 further includes determining whether data read from at least one memory cell in the second memory cell array is equal to data written to at least one memory cell in the second memory cell array.

[0200] In some embodiments, operation 628 is performed by controller 104. In some embodiments, operation 628 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0201] In some embodiments, if the data read from at least one memory cell in the second memory cell array is not equal to the data written to at least one corresponding memory cell in the second memory cell array, the second leakage current is sufficient to cause the data stored in at least one memory cell in the second memory cell array to change logic state after power is removed, thereby indicating that a sufficient amount of time has passed since the integrated circuit 500 was powered off, and the result of operation 628 is "no", and the method 600 proceeds to operation 630.

[0202] In some embodiments, the second memory cell array of method 600 includes memory cell array 102. In some embodiments, the second leakage current of method 600 includes Figure 5 In some embodiments, the second leakage current of method 600 is determined by at least the size of the second memory cell array or the capacitance of a second power supply to which the second memory cell array is coupled. In some embodiments, the second power supply of method 600 is power supply 520.

[0203] In some embodiments, the memory cell array 102 is configured to have memory cells that lose data retention in a first temperature region Templ after a period of time (e.g., a first time T1). In some embodiments, the memory cell array 102 is configured to have a first leakage path (e.g., smaller) with a first leakage current (e.g., smaller) compared to the memory cell array 502, and the memory cells in the memory cell array 102 are configured to lose data retention in a first temperature region Temp1 (e.g., a higher temperature) after a period of time (e.g., a first time T1). In other words, in some embodiments, the memory cell array 102 is configured or designed to discharge at a higher temperature through a low (e.g., slow) leakage path after the duration of the first time T1.

[0204] In some embodiments, if the data read from at least one memory cell in the second memory cell array is equal to the data written to at least one corresponding memory cell in the second memory cell array, the second leakage current is insufficient to cause the data stored in the second memory cell array to change logic state after power is removed, thereby indicating that the amount of time that has passed since the integrated circuit 500 was powered off is insufficient, and the result of operation 628 is "yes", and the method 600 proceeds to operation 636.

[0205] In operation 630 of method 600, it is determined that the first time T1 since the integrated circuit was turned off is greater than the minimum time of the login timer. In some embodiments, operation 630 indicates that a sufficient amount of time (e.g., the first time T1) has passed since the integrated circuit 500 was powered off, and the amount of time (e.g., the first time T1) is therefore greater than the login timer.

[0206] In some embodiments, operation 630 is performed by controller 104. In some embodiments, operation 630 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0207] In some embodiments, operation 630 includes the controller 104 determining that a sufficient amount of time has elapsed since the integrated circuit 500 was powered off to determine that the first time T1 since the integrated circuit was powered off is substantially greater than the login timer.

[0208] In operation 632 of method 600 , in response to determining that the first time T1 since the integrated circuit was turned off is greater than the minimum time, the second flag is set to a first value.

[0209] In some embodiments, the second flag of method 600 corresponds to a single data bit. In some embodiments, the second flag method 600 corresponds to more than one bit of data. In some embodiments, the first value of the second flag is equal to a logical 1. In some embodiments, the first value of the second flag is equal to a logical 0.

[0210] In some embodiments, operation 632 is performed by controller 104. In some embodiments, operation 632 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0211] In operation 634 of method 600 , in response to the second flag being the first value, an authentication operation of the integrated circuit is permitted or performed.

[0212] In some embodiments, operation 634 is performed by controller 104 or system 800. In some embodiments, operation 634 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0213] In some embodiments, operation 634 includes prompting the user with a password authentication or login operation. In some embodiments, operation 634 includes enabling a password authentication or login operation for the user so that the system 800 prompts the user for a password authentication or login operation. In some embodiments, the authentication operation includes providing the user with an attempt to log into the integrated circuit 500 by prompting the user to enter a password.

[0214] In operation 636 of method 600, it is determined that the first time T1 since the integrated circuit was powered off is not greater than the minimum time of the login timer. In some embodiments, operation 636 indicates that an insufficient amount of time (e.g., the first time T1) has passed since the integrated circuit 500 was powered off, and the amount of time (e.g., the first time T1) is therefore not greater than the minimum time login timer.

[0215] In some embodiments, operation 636 is performed by controller 104. In some embodiments, operation 636 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0216] In some embodiments, operation 636 includes the controller 104 determining that an insufficient amount of time has elapsed since the integrated circuit 500 was powered off, thereby determining that the first time T1 since the integrated circuit was powered off is not substantially greater than a minimum time log timer.

[0217] In operation 638 of method 600 , in response to determining that the first time T1 since the integrated circuit was turned off is not greater than the minimum time, the second flag is set to a second value.

[0218] In some embodiments, the second value of the second flag is different from the first value of the second flag. In some embodiments, the second value of the second flag is equal to a logical 1 and the first value of the second flag is a logical 0. In some embodiments, the second value of the second flag is equal to a logical 0 and the first value of the second flag is a logical 1.

[0219] In some embodiments, operation 638 is performed by controller 104. In some embodiments, operation 638 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0220] In operation 640 of method 600 , in response to the second flag being the second value, an authentication operation of the integrated circuit is not allowed or performed.

[0221] In some embodiments, operation 640 is performed by controller 104 or system 800. In some embodiments, operation 640 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0222] In some embodiments, operation 640 includes not prompting the user for a password authentication or login operation. In some embodiments, operation 640 includes disabling a password authentication or login operation for the user so that the system 800 does not prompt the user for a password authentication or login operation.

[0223] In operation 642 of method 600, an additional read operation of the second memory cell array is performed. In some embodiments, the additional read operation of operation 642 is performed until the data read from the second memory cell is not equal to the data written to the second memory cell. In some embodiments, the additional read operation of operation 642 is performed until the data read from at least one memory cell in the second memory cell array changes a logic state. In some embodiments, the additional read operation is performed in operation 642 to determine whether at least one memory cell in the second memory cell array changes a logic state. In some embodiments, in operation 642, method 600 remains in an idle state until a login timer expires.

[0224] In some embodiments, operation 642 is performed by controller 104 or system 800. In some embodiments, operation 642 is performed by a processor, such as Figure 8 The processor 802 in the system 800.

[0225] In some embodiments, after operation 642 , method 600 proceeds to operation 630 .

[0226] By operating method 600, the integrated circuit operates to achieve the benefits discussed above with respect to integrated circuit 500. Figure 1 , Figure 2and Figure 3 Method 600 is described, but it should be understood that method 600 utilizes Figure 7-Figure 8 In some embodiments, the method 600 is described above with reference to SRAM, but is also applicable to DRAM or eDRAM, and similar detailed description is omitted.

[0227] Figure 7 is a circuit diagram of an integrated circuit 700 according to some embodiments.

[0228] Integrated circuit 700 involves Figure 5 The integrated circuit 700 is an embodiment of a portion of the integrated circuit 500, and similar detailed description is omitted.

[0229] Integrated circuit 700 includes controller 104 , memory cell array 702 , and power supply circuit 710 .

[0230] The memory cell array 702 is Figure 5 In an embodiment of a portion of the memory cell array 102 or 502, the power supply circuit 710 is Figure 5 For example, in some embodiments, the memory cell array 702 is Figure 1 In the embodiment of two memory cells in the memory cell array 102, the power supply circuit 710 is Figure 5 For example, in some embodiments, the memory cell array 702 is Figure 5 In the embodiment of two memory cells in the memory cell array 502, the power supply circuit 710 is Figure 5 The embodiment of the power supply circuit 522 in FIG. 5 is omitted for similar detailed description.

[0231] The memory cell array 702 is Figure 2 In the embodiment of the two memory cells MCB of the memory cell array 202, similar detailed description is omitted.

[0232] The memory cell array 702 includes a memory cell 704 and a memory cell 706. In some embodiments, the memory cell 704 is an embodiment of the memory cell MCB in the 1st column and the 1st row of the memory cell array 202, and the memory cell 706 is an embodiment of the memory cell MCB in the 1st column and the 2nd row of the memory cell array 202, and similar detailed descriptions are omitted. In some embodiments, each of the memory cells 704 and the memory cells 706 corresponds to Figure 3 Similar detailed descriptions are omitted for the memory cell 300 in the memory cell array 202. Other memory cells in the memory cell array 202 are within the scope of the present disclosure.

[0233] Memory cell 704 is coupled to word line WL[1], bit line BL[1], inverted bit line BLB[1], controller 102, and power supply circuitry via node Nde3. Memory cell 706 is coupled to word line WL[2], bit line BL[2], inverted bit line BLB[2], controller 102, and power supply circuitry via node Nde3.

[0234] In some embodiments, the node Nde3 is an embodiment of the node Nde1 of the power circuit 520 or the node Nde2 of the power circuit 520 , and similar detailed description is omitted.

[0235] In some embodiments, the node Nde3 is configured to receive the power supply voltage Vddv from the power supply circuit 710. In some embodiments, the power supply voltage Vddv corresponds to the power supply voltage Vddv1 of the power supply circuit 520 or the power supply voltage Vddv2 of the power supply circuit 520, and similar detailed description is omitted.

[0236] The power supply circuit 710 is configured to provide a power supply Vddv that adjusts the discharge time of the memory cell 704 or 706. The power supply circuit 710 is coupled to the memory cells 704 and 706 through the node Nde3. The power supply circuit 710 is configured to provide the power supply voltage Vddv at the node Nde3 for the memory cells 704 and 706. In some embodiments, the power supply circuit 710 is coupled to the memory cell 704, and the memory cell 706 is directly coupled to the power supply voltage VDD.

[0237] The power supply circuit 710 includes a driver circuit I1, a PMOS transistor P3, a resistor R1, and a capacitor C1. In some embodiments, the driver circuit I1 is an inverter.

[0238] The driver circuit I1 is coupled to the gate of the PMOS transistor P3. The input terminal of the driver circuit I1 is used to receive the power control signal Pwr_Up. The output terminal of the driver circuit I1 is used to generate the output power control signal Pwr_UpB. In some embodiments, in response to the driver circuit I1 being an inverter, the output power control signal Pwr_UpB is inverted from the power control signal Pwr_Up.

[0239] The output terminal of the driving circuit I1 is coupled to the gate of the PMOS transistor P3. The driving circuit I1 is configured to turn on / off the PMOS transistor P3 based on the output power control signal Pwr_UpB.

[0240] The source of the PMOS transistor P3 is coupled to the power supply voltage VDD. The drain of the PMOS transistor P3 is coupled to the first end of the resistor R1. The second end of the resistor R1 is coupled to at least the node Nde3 and the first end of the capacitor C1. The second end of the capacitor C1 is coupled to the reference power supply voltage VSS.

[0241] In response to being turned on, the PMOS transistor P3 is configured to provide the power supply voltage VDD to the first end of the resistor R1. In response to being turned off, the PMOS transistor P3 is configured not to provide the power supply voltage VDD to the first end of the resistor R1. In some embodiments, the power supply voltage VDD is equal to the power supply voltage Vddv. In some embodiments, the power supply voltage VDD is different from the power supply voltage Vddv.

[0242] In some embodiments, resistor R1 corresponds to the internal resistance of power supply circuit 710. In some embodiments, resistor R1 corresponds to an additional resistor added to power supply circuit 710. In some embodiments, resistor R1 is a thin film resistor or a well resistor. In some embodiments, resistor R1 is a polysilicon resistor.

[0243] In some embodiments, capacitor C1 corresponds to an internal capacitance of power circuit 710. In some embodiments, capacitor C1 corresponds to an additional capacitor added to power circuit 710 to adjust the capacitance of the power circuit. Figure 5 The data retention time of the memory cell array 102 or 502 is adjusted as discussed in the above, thereby adjusting the data retention time of the memory cell array 102 or 502. In some embodiments, the capacitor C1 is implemented by a metal insulator metal (MIM) capacitor or a metal oxide metal (MOM) capacitor. In some embodiments, the capacitance per unit area of ​​the capacitor C1 ranges from about 2 fF / μm 2 To about 5fF / μm 2 In some embodiments, the power per unit area of ​​resistor R1 ranges from about 5KW / μm 2 To about 10KW / μm 2 .

[0244] Other configurations or numbers of elements of the power circuit 710 are within the scope of the present disclosure.

[0245] Other configurations or numbers of elements for integrated circuit 700 are within the scope of the present disclosure.

[0246] Figure 8 is a schematic diagram of a system 800 according to some embodiments. In some embodiments, the system 800 is at least Figure 1 , Figure 5 or Figure 7 The embodiments of the controller 104 are described below, and thus similar detailed description is omitted.

[0247] In some embodiments, system 800 is at least Figure 1 , Figure 4 or Figure 7 The present invention is not related to the embodiments of the integrated circuit 100, 400 or 700, and thus similar detailed description is omitted.

[0248] In some embodiments, portions of system 800 are at least Figure 2 The memory circuit 200 or Figure 3 The present invention is an embodiment of the memory cell 300, and thus similar detailed description is omitted.

[0249] In some embodiments, system 800 is configured to control one or more of memory cell array 102 or 202, memory cell 300, X-decoder circuit 106, Y-decoder circuit 108, read circuit 110, or memory circuit 200 or 702. In some embodiments, system 800 is configured to perform one or more operations of method 400 or method 600.

[0250] The system 800 includes a hardware processor 802 and a non-transitory computer-readable storage medium 804 (e.g., memory 804) that encodes (i.e., stores) computer program code 806 (i.e., a set of executable instructions 806). The computer-readable storage medium 804 is configured to communicate with at least the memory cell array 102 or 202, the memory cell 300, the X-decoder circuit 106, the Y-decoder circuit 108, the read circuit 110, or the memory circuit 200 or 702, or at least Figure 1 , Figure 5 or Figure 7 The controller 104 at least Figure 1 , Figure 4 or Figure 7 Integrated circuit 100, 400 or 700 interface.

[0251] The processor 802 is electrically coupled to the computer readable storage medium 804 via a bus 808. The processor 802 is also electrically coupled to an I / O interface 810 via the bus 808. A network interface 812 is also electrically coupled to the processor 802 via the bus 808. The network interface 812 is connected to a network 814, enabling the processor 802 and the computer readable storage medium 804 to be connected to external elements via the network 814. The processor 802 is configured to execute computer program code 806 encoded in the computer readable storage medium 804 so that the system 800 can be used to perform at least some or all of the operations described in the method 400 or 600. In some embodiments, the network 814 is not part of the system 800.

[0252] In some embodiments, processor 802 is a central processing unit (CPU), a multi-processor, a distributed processing read circuit, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0253] In some embodiments, the computer-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared and / or semiconductor reading circuit (or device or device). For example, the computer-readable storage medium 804 includes a semiconductor or solid-state memory, a magnetic tape, a removable computer floppy disk, a random access memory (RAM), a read-only memory (ROM), a hard disk and / or an optical disk. In some embodiments using optical disks, the computer-readable storage medium 804 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W) and / or a digital video disk (DVD).

[0254] In some embodiments, storage medium 804 stores computer program code 806 configured to cause system 800 to perform at least one or more operations of method 400 or 600. In some embodiments, storage medium 804 also stores information generated during the execution of at least method 400 or 600, such as first time 816, minimum time 818, data 820, flag 822, and user interface 824, and / or a set of executable instructions to perform at least one or more operations of method 400 or 600.

[0255] In some embodiments, the storage medium 804 stores instructions for interfacing with at least the memory cell array 102 or 202, the memory cell 300, the X-decoder circuit 106, the Y-decoder circuit 108, the read circuit 110, or the memory circuit 200 or 702, the controller 104, the integrated circuit 100, 400, or 700. The instructions (e.g., computer program code 806) enable the processor 802 to generate instructions that are readable by at least the memory cell array 102 or 202, the memory cell 300, the X-decoder circuit 106, the Y-decoder circuit 108, the read circuit 110, or the memory circuit 200 or 702, the controller 104, the integrated circuit 100, 400, or 700 to effectively implement one or more operations of at least the method 400 or 600 during operation of the integrated circuit 100, 500, or 700.

[0256] System 800 includes an I / O interface 810. I / O interface 810 is coupled to external circuitry. In some embodiments, I / O interface 810 includes a keyboard, keypad, mouse, trackball, trackpad, and / or cursor direction keys for transmitting information and commands to processor 802.

[0257] The system 800 also includes a network interface 812 coupled to the processor 802. The network interface 812 allows the system 800 to communicate with a network 814, to which one or more other computer reading circuits are connected. The network interface 812 includes a wireless network interface such as Bluetooth, WIFI, WIMAX, GPRS, WCDMA, etc.; or a wired network interface such as ETHERNET, USB, or IEEE-884. In some embodiments, at least the method 400 or 600 is implemented in two or more reading circuits 800, and information such as the first time, the minimum time, data, flags, and user interfaces are exchanged between different reading circuits 800 via the network 814.

[0258] The system 800 is configured to receive information related to the first time value through the I / O interface 810 or the network interface 812. The information is transmitted to the processor 802 through the bus 808 to determine, measure or compare the first time value since the integrated circuit 100, 500 or 700 is powered off. The first time value is then stored in the computer-readable medium 804 as a first time 816. In some embodiments, the first time 816 includes one or more of the first times from the method 400 or 600. The system 800 is configured to receive information related to the shortest time through the I / O interface 810 or the network interface 812. The information is stored in the computer-readable medium 804 as the shortest time 818. In some embodiments, the shortest time includes the shortest time of the method 400 or 600. The system 800 is configured to receive information related to data through the I / O interface 810 or the network interface 812. The information is stored in the computer-readable medium 804 as data 820. In some embodiments, the data includes at least the write data or read data of the method 400 or 600. The system 800 is configured to receive information related to the flag through the I / O interface 810 or the network interface 812. The information is stored in the computer-readable medium 804 as the flag 822. In some embodiments, the flag includes at least the flag of the method 400, the first flag of the method 600, or the second flag of the method 600. The system 800 is configured to receive information related to the user interface through the I / O interface 810 or the network interface 812. The information is stored in the computer-readable medium 804 as the user interface 824.

[0259] In some embodiments, at least method 400 or 600 is implemented as a standalone software application executed by a processor. In some embodiments, at least method 400 or 600 is implemented as a software application that is part of an additional software application. In some embodiments, at least method 400 or 600 is implemented as a plug-in for a software application. In some embodiments, at least method 400 or 600 is implemented as a software application that is part of an authentication tool. In some embodiments, at least method 400 or 600 is implemented as a software application used by an authentication tool. In some embodiments, the authentication tool is used to authenticate the credentials of a user of at least memory circuit 100, 400, or 500.

[0260] In some embodiments, at least method 400 or 600 is implemented by an integrated circuit such as integrated circuit 100 , 500 or 700 to operate at least memory circuit 200 or memory cell array 102 or 202 based on one or more instructions by system 800 .

[0261] In some embodiments, one or more operations of method 400 or 600 are not performed. Figure 3 The various N-type or P-type transistors shown in FIG. are of a specific dopant type (eg, N-type or P-type). The embodiments of the present disclosure are not limited to a specific transistor type, and Figure 3 One or more of the N-type transistors or P-type transistors shown in the figure may be replaced with corresponding transistors of different transistor / dopant types. Similarly, the low or high logic values ​​of various signals used in the above description are also for illustration. The embodiments of the present disclosure are not limited to specific logic values ​​when signals are activated and / or deactivated. It is within the scope of various embodiments to select different logic values. Figure 3 Different numbers of transistors in are within the scope of various embodiments.

[0262] Those skilled in the art will readily appreciate that one or more of the disclosed embodiments achieve one or more of the above advantages. After reading the foregoing description, those skilled in the art will be able to effect various changes, substitutions of equivalents, and various other embodiments as broadly disclosed herein. Therefore, the protection granted herein is intended to be limited only by the definitions contained in this disclosure.

[0263] One aspect of the present specification relates to a method of operating an integrated circuit including a first memory cell array. In some embodiments, the method includes writing data to each memory cell in the first memory cell array, powering off the integrated circuit, powering on the integrated circuit, reading data from each memory cell in the first memory cell array in response to powering on the integrated circuit, and determining whether to allow authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array.

[0264] In the above method, writing data to each memory cell in the first memory cell array includes: writing logic 1 to each memory cell in the first memory cell array.

[0265] In the above method, determining whether to allow the authentication operation of the integrated circuit includes: determining that data read from at least one memory cell in the first memory cell array is not equal to data written to at least one memory cell in the first memory cell array.

[0266] In the above method, determining whether to allow the authentication operation of the integrated circuit also includes: in response to determining that the data read from at least one memory cell in the first memory cell array is not equal to the data written to at least one memory cell in the first memory cell array, determining that the first time since the self-powered integrated circuit was powered off is greater than the minimum time; in response to determining that the first time since the self-powered integrated circuit was powered off is greater than the minimum time, setting a flag to a first value; and in response to the flag being the first value, allowing the authentication operation of the integrated circuit.

[0267] In the above method, determining whether to allow the authentication operation of the integrated circuit includes: determining that data read from at least one memory cell in the first memory cell array is equal to data written to at least one memory cell in the first memory cell array.

[0268] In the above method, determining whether to allow the authentication operation of the integrated circuit also includes: in response to determining that data read from at least one memory cell in the first memory cell array is equal to data written to at least one memory cell in the first memory cell array, determining that a first time since the integrated circuit was powered off is not greater than a minimum time; in response to determining that the first time since the integrated circuit was powered off is not greater than the minimum time, setting a flag to a second value, the second value being different from the first value; and in response to the flag being the second value, not allowing the authentication operation of the integrated circuit.

[0269] Another aspect of the present specification relates to a method of operating an integrated circuit, the integrated circuit including a first memory cell array and a second memory cell array. In some embodiments, the method includes writing data to each memory cell in the first memory cell array, writing data to each memory cell in the second memory cell array, powering off the integrated circuit, powering on the integrated circuit, reading data from each memory cell in the first memory cell array in response to powering on the integrated circuit, reading data from each memory cell in the second memory cell array in response to powering on the integrated circuit, and determining whether to allow authentication operation of the integrated circuit in response to reading data from each memory cell in at least the first memory cell array or the second memory cell array.

[0270] In the above method, in response to reading data from each memory cell in the first memory cell array, determining whether to allow the authentication operation of the integrated circuit includes: determining whether the data read from at least one memory cell in the first memory cell array is equal to the data written to at least one memory cell in the first memory cell array.

[0271] In the above method, determining whether data read from at least one memory cell in the first memory cell array is equal to data written to at least one memory cell in the first memory cell array includes: determining that the data read from at least one memory cell in the first memory cell array is equal to the data written to at least one memory cell in the first memory cell array.

[0272] In the above method, in response to reading data from each memory cell in the first memory cell array, determining whether to allow the authentication operation of the integrated circuit also includes: in response to determining that the data read from at least one memory cell in the first memory cell array is equal to the data written to at least one memory cell in the first memory cell array, determining that the first time since the self-powered integrated circuit was powered off is not greater than the minimum time; in response to determining that the first time since the self-powered integrated circuit was powered off is not greater than the minimum time, setting the first flag to a first value; and in response to the first flag being the first value, not allowing the authentication operation of the integrated circuit.

[0273] In the above method, in response to reading data from each memory cell in the first memory cell array, determining whether to allow the authentication operation of the integrated circuit also includes: waiting until the data read from at least one memory cell in the first memory cell array is not equal to the data written to at least one memory cell in the first memory cell array; in response to determining that the data read from at least one memory cell in the first memory cell array is not equal to the data written to at least one memory cell in the first memory cell array, determining that the first time since the integrated circuit was powered off is greater than the minimum time; in response to determining that the first time since the integrated circuit was powered off is greater than the minimum time, setting the first flag to a second value, the second value being different from the first value; and in response to the first flag being the second value, allowing the authentication operation of the integrated circuit.

[0274] In the above method, determining whether data read from at least one memory cell in the first memory cell array is equal to data written to at least one memory cell in the first memory cell array includes: determining that the data read from at least one memory cell in the first memory cell array is not equal to the data written to at least one memory cell in the first memory cell array.

[0275] In the above method, determining whether to allow the authentication operation of the integrated circuit in response to reading data from the second memory cell array includes: in response to determining that the data read from at least one memory cell in the first memory cell array is not equal to the data written to at least one memory cell in the first memory cell array, determining whether the data read from at least one memory cell in the second memory cell array is equal to the data written to at least one memory cell in the second memory cell array.

[0276] In the above method, determining whether data read from at least one memory cell in the second memory cell array is equal to data written to at least one memory cell in the second memory cell array includes: determining that the data read from at least one memory cell in the second memory cell array is not equal to the data written to at least one memory cell in the second memory cell array.

[0277] In the above method, determining whether to allow the authentication operation of the integrated circuit in response to reading data from the second memory cell array also includes: in response to determining that the data read from at least one memory cell in the second memory cell array is not equal to the data written to at least one memory cell in the second memory cell array, determining that the first time since the self-powered integrated circuit was powered off is greater than the minimum time; in response to determining that the first time since the self-powered integrated circuit was powered off is greater than the minimum time, setting the first flag to a first value; and in response to the first flag being the first value, allowing the authentication operation of the integrated circuit.

[0278] In the above method, determining whether data read from at least one memory cell in the second memory cell array is equal to data written to at least one memory cell in the second memory cell array includes: determining that the data read from at least one memory cell in the second memory cell array is equal to the data written to at least one memory cell in the second memory cell array.

[0279] In the above method, determining whether to allow the authentication operation of the integrated circuit in response to reading data from the second memory cell array also includes: in response to determining that the data read from at least one memory cell in the second memory cell array is equal to the data written to at least one memory cell in the second memory cell array, determining that the first time since the self-powered integrated circuit was powered off is not greater than the minimum time; in response to determining that the first time since the self-powered integrated circuit was powered off is not greater than the minimum time, setting the first flag to a second value, the second value being different from the first value; and in response to the first flag being the second value, not allowing the authentication operation of the integrated circuit.

[0280] In the above method, writing data to each memory cell in the first memory cell array includes: writing logic 1 to each memory cell in the first memory cell array; and writing data to each memory cell in the second memory cell array includes: writing logic 1 to each memory cell in the second memory cell array.

[0281] Another aspect of the specification relates to an integrated circuit. The integrated circuit includes a first memory cell array and a controller coupled to the first memory cell array. In some embodiments, the first memory cell array includes a first array of volatile memory cells having a first retention data time. In some embodiments, the controller is configured to: write data to each memory cell in the first memory cell array in response to the integrated circuit being successfully logged in, read data from each memory cell in the first memory cell array in response to the integrated circuit being powered on, and determine whether to allow authentication operations of the integrated circuit in response to reading data from each memory cell in the first memory cell array.

[0282] In the above-mentioned integrated circuit, it also includes: a second memory cell array, coupled to the controller, the second memory cell array includes: a second array of volatile memory cells, having a second data retention time different from the first data retention time; wherein the first size of the first memory cell array is different from the second size of the second memory cell array; and wherein the controller is also configured to: write data to each memory cell in the second memory cell array in response to the integrated circuit being successfully logged in; read data from each memory cell in the second memory cell array in response to the integrated circuit being powered on; and determine whether to allow the authentication operation of the integrated circuit in response to reading data from each memory cell in the second memory cell array.

[0283] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A method of operating an integrated circuit, the integrated circuit comprising a first memory cell array, the method comprising: In response to the integrated circuit being successfully logged in, writing data to each memory cell in the first memory cell array; De-energizing the integrated circuit; Powering on the integrated circuit; in response to powering on the integrated circuit, reading data from each memory cell in the first memory cell array; as well as In response to reading data from each memory cell in the first memory cell array, determining whether to allow an authentication operation of the integrated circuit includes providing one or more login operations to a user of the integrated circuit.

2. The method according to claim 1, wherein: Writing data to each memory cell in the first memory cell array comprises: A logic "1" is written to each memory cell in the first memory cell array.

3. The method of claim 1 , determining whether to allow the authentication operation of the integrated circuit comprises: It is determined that data read from at least one memory cell in the first memory cell array is not equal to data written to at least one memory cell in the first memory cell array.

4. The method according to claim 3, wherein: Determining whether to allow the authentication operation of the integrated circuit further includes: in response to determining that the data read from the at least one memory cell in the first memory cell array is not equal to the data written to the at least one memory cell in the first memory cell array, determining that a first time since power was removed from the integrated circuit is greater than a minimum time; In response to determining that the first time since power was removed from the integrated circuit is greater than the minimum time, setting a flag to a first value; and In response to the flag being the first value, the authentication operation of the integrated circuit is permitted.

5. The method according to claim 4, wherein: Determining whether to allow the authentication operation of the integrated circuit includes: It is determined that data read from at least one memory cell in the first memory cell array is equal to data written to the at least one memory cell in the first memory cell array.

6. The method according to claim 5, wherein: Determining whether to allow the authentication operation of the integrated circuit further includes: in response to determining that the data read from the at least one memory cell in the first memory cell array is equal to the data written to the at least one memory cell in the first memory cell array, determining that the first time since the integrated circuit was powered off is not greater than the minimum time; In response to determining that the first time since the integrated circuit was powered off is not greater than the minimum time, setting the flag to a second value, the second value being different from the first value; and In response to the flag being the second value, the authentication operation of the integrated circuit is not permitted.

7. A method of operating an integrated circuit, the integrated circuit comprising a first memory cell array and a second memory cell array, the method comprising: Writing data to each memory cell in the first memory cell array; Writing data to each memory cell in the second memory cell array; De-energizing the integrated circuit; Powering on the integrated circuit; in response to powering on the integrated circuit, reading data from each memory cell in the first memory cell array; in response to powering on the integrated circuit, reading data from each memory cell in the second memory cell array; as well as In response to reading data from each memory cell in at least the first memory cell array or the second memory cell array, it is determined whether an authentication operation of the integrated circuit is permitted.

8. The method according to claim 7, wherein: In response to reading data from each memory cell in the first memory cell array, determining whether to allow the authentication operation of the integrated circuit includes: It is determined whether data read from at least one memory cell in the first memory cell array is equal to data written to the at least one memory cell in the first memory cell array.

9. The method according to claim 8, wherein: Determining whether the data read from the at least one memory cell in the first memory cell array is equal to the data written to the at least one memory cell in the first memory cell array comprises: It is determined that the data read from the at least one memory cell in the first memory cell array is equal to the data written to the at least one memory cell in the first memory cell array.

10. The method according to claim 9, wherein: In response to reading data from each memory cell in the first memory cell array, determining whether to allow the authentication operation of the integrated circuit further comprises: in response to determining that the data read from the at least one memory cell in the first memory cell array is equal to the data written to the at least one memory cell in the first memory cell array, determining that a first time since power was removed from the integrated circuit is not greater than a minimum time; In response to determining that the first time since the integrated circuit was powered off is not greater than the minimum time, setting a first flag to a first value; and In response to the first flag being the first value, the authentication operation of the integrated circuit is not permitted.

11. The method according to claim 10, wherein: In response to reading data from each memory cell in the first memory cell array, determining whether to allow the authentication operation of the integrated circuit further comprises: waiting until the data read from the at least one memory cell in the first memory cell array is not equal to the data written to the at least one memory cell in the first memory cell array; in response to determining that the data read from the at least one memory cell in the first memory cell array is not equal to the data written to the at least one memory cell in the first memory cell array, determining that the first time since power was removed from the integrated circuit is greater than the minimum time; setting the first flag to a second value different from the first value in response to determining that the first time since the integrated circuit was powered off is greater than the minimum time; and In response to the first flag being the second value, allowing the authentication operation of the integrated circuit.

12. The method according to claim 8, wherein: Determining whether the data read from the at least one memory cell in the first memory cell array is equal to the data written to the at least one memory cell in the first memory cell array comprises: It is determined that the data read from the at least one memory cell in the first memory cell array is not equal to the data written to the at least one memory cell in the first memory cell array.

13. The method according to claim 12, wherein: Determining whether to allow the authentication operation of the integrated circuit in response to reading data from the second memory cell array includes: In response to determining that the data read from the at least one memory cell in the first memory cell array is not equal to the data written to the at least one memory cell in the first memory cell array, it is determined whether the data read from the at least one memory cell in the second memory cell array is equal to the data written to the at least one memory cell in the second memory cell array.

14. The method according to claim 13, wherein: Determining whether the data read from the at least one memory cell in the second memory cell array is equal to the data written to the at least one memory cell in the second memory cell array comprises: It is determined that the data read from the at least one memory cell in the second memory cell array is not equal to the data written to the at least one memory cell in the second memory cell array.

15. The method according to claim 14, wherein: Determining whether to allow the authentication operation of the integrated circuit in response to reading data from the second memory cell array further comprises: in response to determining that the data read from the at least one memory cell in the second memory cell array is not equal to the data written to the at least one memory cell in the second memory cell array, determining that a first time since power was removed from the integrated circuit is greater than a minimum time; In response to determining that the first time since the integrated circuit was powered off is greater than the minimum time, setting a first flag to a first value; and In response to the first flag being the first value, allowing the authentication operation of the integrated circuit.

16. The method according to claim 15, wherein: Determining whether the data read from the at least one memory cell in the second memory cell array is equal to the data written to the at least one memory cell in the second memory cell array comprises: It is determined that the data read from the at least one memory cell in the second memory cell array is equal to the data written to the at least one memory cell in the second memory cell array.

17. The method according to claim 16, wherein: Determining whether to allow the authentication operation of the integrated circuit in response to reading data from the second memory cell array further comprises: in response to determining that the data read from the at least one memory cell in the second memory cell array is equal to the data written to the at least one memory cell in the second memory cell array, determining that the first time since power was removed from the integrated circuit is not greater than the minimum time; In response to determining that the first time since the integrated circuit was powered off is not greater than the minimum time, setting the first flag to a second value, the second value being different from the first value; and In response to the first flag being the second value, the authentication operation of the integrated circuit is not permitted.

18. The method according to claim 7, wherein Writing data to each memory cell in the first memory cell array comprises: Writing a logic "1" into each memory cell in the first memory cell array; as well as Writing data to each memory cell in the second memory cell array comprises: A logic "1" is written to each memory cell in the second memory cell array.

19. An integrated circuit comprising: A first memory cell array comprises: a first array of volatile memory cells having a first retention data time; and a controller coupled to the first array of memory cells, the controller being configured to: In response to the integrated circuit being successfully logged in, writing data to each memory cell in the first memory cell array; In response to the integrated circuit being powered on, reading data from each memory cell in the first memory cell array; and In response to reading data from each memory cell in the first memory cell array, it is determined whether an authentication operation of the integrated circuit is permitted.

20. The integrated circuit of claim 19, further comprising: A second memory cell array, coupled to the controller, the second memory cell array comprising: a second array of volatile memory cells having a second data retention time different from the first data retention time; wherein a first size of the first memory cell array is different from a second size of the second memory cell array; and Wherein, the controller is further configured as: In response to the integrated circuit being successfully logged in, writing data to each memory cell in the second memory cell array; in response to the integrated circuit being powered on, reading data from each memory cell in the second memory cell array; and In response to reading data from each memory cell in the second memory cell array, it is determined whether the authentication operation of the integrated circuit is permitted.

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