Subdivision method using recursive subdivision of triangles

Abstract

The present disclosure relates to a subdivision method using recursive subdivision of triangles. A subdivision method using a subdivision factor defined for each vertex of a patch which may be a quadrilateral, a triangle, or a contour line is described. The method is implemented in a computer graphics system and involves comparing the vertex subdivision factor to a threshold value. If the vertex subdivision factor of either the left vertex or the right vertex of an edge defining an initial patch exceeds the threshold value, the edge is subdivided by the addition of a new vertex that divides the edge into two parts and two new patches are formed. A new vertex subdivision factor is calculated for each vertex in each newly formed patch, both patches including the newly added vertex. The method is then repeated for each newly formed patch until no vertex subdivision factor exceeds the threshold value.

Description

[0001] This application is a divisional application of an application with application date of June 6, 2016, application number 201610392316.9, and invention name “Subdivision method using recursive subdivision of triangles”.

[0002] background

[0003] Subdivision is a technique used in computer graphics to split a set of surfaces representing objects in a scene into multiple smaller and simpler pieces, typically triangles, called primitives, which are easier to render. The resulting subdivided surface is typically an approximation of the original surface, but the accuracy of this approximation can be improved by increasing the number of primitives generated, which in turn typically results in smaller primitives. The amount of subdivision / subdivision is typically determined by the level of detail (LOD). An increased number of primitives is therefore typically used where a higher level of detail is desired, for example because the object is closer to the viewer and / or the object has a more complex shape. However, the use of a greater number of triangles increases the processing power required to render the scene.

[0004] Typically subdivision is performed on patches into triangular primitives, which are either square or triangular in shape (i.e., quadrilaterals or triangles) and may be curved to conform to the surface of the object they represent (and may therefore be referred to as "surface patches") and / or to enable displacement mapping to be applied. However, subdivision is not performed on curved patches but instead is performed in the domain of the patch (e.g., as if the patch were planar, rather than defined by, e.g., polynomial equations), which may be defined in terms of (u,v) parameters and referred to as "parametric space". This means that the subdivision process is independent of any curvature present in the final surface.

[0005] The tessellation may be performed in advance (e.g., to compute multiple different views of a scene at different levels of detail and / or from different viewpoints) or may be performed on the fly (e.g., to provide a continuous or view-dependent level of detail). Using some existing tessellation methods, users may experience undesirable visual artifacts where, although the requested level of detail changes smoothly, the resulting tessellation changes in a discontinuous manner.

[0006] The embodiments described below are provided as examples only and are not limitations of implementations that address any or all disadvantages of known methods and apparatus for performing segmentation.

[0007] Overview

[0008] This Summary is provided to introduce selected concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0009] A tessellation method is described which uses a tessellation factor defined for each vertex of a patch, which may be a quadrilateral, a triangle, or a contour. The method is implemented in a computer graphics system and involves comparing the vertex tessellation factor to a threshold value. If the vertex tessellation factor of either the left or right vertex of an edge defining an initial patch exceeds the threshold value, the edge is subdivided by the addition of a new vertex that divides the edge into two parts and two new patches are formed. A new vertex tessellation factor is calculated for each vertex in each of the newly formed patches, both of which include the newly added vertex. The method is then repeated for each of the newly formed patches until no vertex tessellation factor exceeds the threshold value.

[0010] A first aspect provides a method for performing subdivision in a computer graphics system, the method comprising: for an initial patch including a left vertex and a right vertex connected by an edge and defined in a domain space: comparing a vertex subdivision factor of the left vertex and a vertex subdivision factor of the right vertex with a threshold; in response to determining that none of the vertex subdivision factors of the left vertex and the right vertex exceeds the threshold, outputting data describing the initial patch; and in response to determining that any one of the vertex subdivision factors of the left vertex and the right vertex exceeds the threshold, forming a new vertex that divides the edge into two parts, calculating the vertex subdivision factor of the new vertex, splitting the initial patch to form a first new patch including the left vertex and the new vertex and a second new patch including the right vertex and the new vertex, and reducing the vertex subdivision factor of each vertex in each newly formed patch.

[0011] The new vertex bisects the edge.

[0012] The method may also include repeating the method using each newly formed patch as an initial patch. Repeating the method for each newly formed patch as an initial patch may include repeating the method for each newly formed patch as an initial patch until the vertex subdivision factor of the left and right vertices in each patch does not exceed a threshold value.

[0013] Calculating the vertex subdivision factor of the new vertex may include: calculating an average of the vertex subdivision factors of the left vertex and the right vertex; and setting the vertex subdivision factor of the new vertex equal to the calculated average. The average of the vertex subdivision factors of the left vertex and the right vertex may be given by the following formula:

[0014] MEAN(LEFT.TF,RIGHT.TF)=MIN(AVG(LEFT.TF,RIGHT.TF),MIN(LEFT.TF,RIGHT.TF)+INTERVAL)

[0015] Where LEFT.TF is the vertex subdivision factor for the left vertex, RIGHT.TF is the vertex subdivision factor for the right vertex, AVG() is the arithmetic mean of the values ​​in parentheses, MIN() is the minimum value in the list of values ​​in parentheses, and INTERVAL is a predefined parameter.

[0016] Reducing the vertex subdivision factor of each vertex in each newly formed patch may include reducing each vertex subdivision factor by a predefined parameter INTERVAL. The parameter INTERVAL may be 0.5.

[0017] The threshold value may be equal to zero.

[0018] The initial patch may be a contour patch defined by two vertices, the two vertices comprising a left vertex and a right vertex.

[0019] The initial patch may be a triangular patch, and wherein the triangular patch is an ordered set of three vertices: an upper vertex, a right vertex, and a left vertex. The split patch may be a parent patch of two newly formed patches, and wherein the first new patch is an ordered set of three vertices: an upper vertex that is the new vertex added to the parent patch; a right vertex that is the left vertex of the parent patch; and a left vertex that is the upper vertex of the parent patch; and wherein the second new patch is an ordered set of three vertices: an upper vertex that is the new vertex added to the parent patch; a right vertex that is the upper vertex of the parent patch; and a left vertex that is the right vertex of the parent patch.

[0020] The method, wherein the initial patch is a triangular patch, may also include: receiving an input patch; and generating one or more initial patches from the input patch; and repeating the method for each of the plurality of initial patches. The input patch may be a triangular patch having three vertices, and wherein generating the one or more initial patches may include: comparing a vertex subdivision factor of each of the three vertices to a threshold; in response to determining that none of the vertex subdivision factors exceeds the threshold, outputting data describing the input patch; and in response to determining that at least one vertex subdivision factor exceeds the threshold, forming a new vertex at the center of the triangle, calculating a vertex subdivision factor for the new vertex, splitting the input patch to form three initial patches, each of which is a triangular patch with the new vertex as an upper vertex, and reducing the vertex subdivision factor of each vertex in each newly formed initial patch. The new vertex may be formed at the mass center of the triangle. The three vertices of the input patch may be an upper vertex, a left vertex, and a right vertex, and the vertex subdivision factor of the new vertex at the center of the triangle may be calculated using the following formula:

[0021] MID.TF=MEAN(TOP.TF,LEFT.TF,RIGHT.TF)

[0022] Where MID.TF is the vertex subdivision factor of the new vertex, TOP.TF is the vertex subdivision factor of the top vertex, LEFT.TF is the vertex subdivision factor of the left vertex, and RIGHT.TF is the vertex subdivision factor of the right vertex, and MEAN() is the average of the values ​​in parentheses.

[0023] MEAN(TOP.TF,LEFT.TF,RIGHT.TF) can be calculated using the following formula:

[0024] MEAN(TOP.TF,LEFT.TF,RIGHT.TF)=MIN(AVG(TOP.TF,LEFT.TF,RIGHT.TF),MIN(TOP.TF,LEFT.TF,RIGHT.TF)+INTERVAL)

[0025] where AVG() is the arithmetic mean of the values ​​in parentheses, MIN() is the minimum value in a list of values ​​in parentheses, and INTERVAL is a predefined parameter.

[0026] The input patch may be a quadrilateral patch having four vertices, and wherein generating one or more initial patches may include: forming a new vertex at the center of the quadrilateral patch; calculating a vertex subdivision factor of the new vertex; splitting the input patch to form four initial patches, each initial patch being a triangular patch with the new vertex as an upper vertex; and reducing the vertex subdivision factor of each vertex in each newly formed initial patch.

[0027] The input patch may be a quadrilateral patch having four vertices and a center subdivision factor, and wherein generating one or more initial patches may include: adding five new vertices to subdivide the input patch into four sub-input quadrilateral patches; calculating the vertex subdivision factor for each of the five most recently added vertices; reducing the vertex subdivision factor for each vertex in the four most recently formed sub-input patches; and for each sub-input patch: forming a new vertex at the center of the quadrilateral patch; calculating the vertex subdivision factor for the new vertex; splitting the input patch to form four initial patches, each initial patch being a triangular patch with the new vertex as an upper vertex; and reducing the vertex subdivision factor for each vertex in each of the most recently formed initial patches.

[0028] The input patch may be a triangular patch having three vertices and a center subdivision factor, and wherein generating one or more initial patches may include: adding four new vertices to subdivide the input patch into three sub-input quadrilateral patches; calculating the vertex subdivision factor for each of the four most recently added vertices; reducing the vertex subdivision factor for each vertex in the three most recently formed sub-input patches; and for each sub-input patch: forming a new vertex at the center of the quadrilateral patch; calculating the vertex subdivision factor for the new vertex; splitting the input patch to form four initial patches, each initial patch being a triangular patch with the new vertex as an upper vertex; and reducing the vertex subdivision factor for each vertex in each most recently formed initial patch.

[0029] The four vertices of the input patch can be the upper left vertex, the upper right vertex, the lower left vertex, and the lower right vertex, and the vertex subdivision factor of the new vertex at the center of the quadrilateral can be calculated using the following formula:

[0030] MID.TF=MEAN(TLEFT.TF,TRIGHT.TF,BLEFT.TF,BRIGHT.TF)

[0031] where MID.TF is the vertex subdivision factor of the new vertex, TLEFT.TF is the vertex subdivision factor of the upper left vertex, TRIGHT.TF is the vertex subdivision factor of the upper right vertex, BLEFT.TF is the vertex subdivision factor of the lower left vertex, BRIGHT.TF is the vertex subdivision factor of the lower right vertex, and MEAN() is the average of the values ​​in parentheses.

[0032] MEAN(TLEFT.TF,TRIGHT.TF,BLEFT.TF,BRIGHT.TF) can be calculated using the following formula:

[0033] MEAN(TLEFT.TF,TRIGHT.TF,BLEFT.TF,BRIGHT.TF)=MIN(AVG(TLEFT.TF,TRIGHT.TF,BLEFT.TF,BRIGHT.TF),MIN(TLEFT.TF,TRIGHT.TF,BLEFT.TF,BRIGHT.TF)+INTERVAL)

[0034] where AVG() is the arithmetic mean of the values ​​in parentheses, MIN() is the minimum value in a list of values ​​in parentheses, and INTERVAL is a predefined parameter.

[0035] Reducing the vertex tessellation factor of each vertex in each newly formed initial patch may include reducing each vertex tessellation factor by a predefined parameter INTERVAL.

[0036] A second aspect provides a hardware subdivision unit including hardware logic, the hardware logic being configured to: for an initial patch including a left vertex and a right vertex connected by an edge and defined in a domain space: compare the vertex subdivision factor of the left vertex and the vertex subdivision factor of the right vertex with a threshold; in response to determining that none of the vertex subdivision factors of the left vertex and the right vertex exceeds the threshold, output data describing the initial patch; and in response to determining that either of the vertex subdivision factors of the left vertex and the right vertex exceeds the threshold, form a new vertex that divides the edge into two parts, calculate the vertex subdivision factor of the new vertex, split the initial patch to form a first new patch including the left vertex and the new vertex and a second new patch including the right vertex and the new vertex, and reduce the vertex subdivision factor of each vertex in each newly formed patch.

[0037] The new vertex bisects the edge.

[0038] The hardware logic may also be configured to repeat the operation of the hardware logic using the most recently formed patch as the initial patch.

[0039] The hardware logic is configured to repeat the operation of the hardware logic for each newly formed patch as the initial patch until the vertex subdivision factor of the left vertex and the right vertex in each patch does not exceed the threshold.

[0040] The hardware logic configured to calculate the vertex tessellation factor for the new vertex may include hardware logic configured to: calculate an average of the vertex tessellation factors of the left vertex and the right vertex; and set the vertex tessellation factor for the new vertex equal to the calculated average.

[0041] The average value of the vertex subdivision factors of the left vertex and the right vertex is given by the following formula:

[0042] MEAN(LEFT.TF,RIGHT.TF)=MIN(AVG(LEFT.TF,RIGHT.TF),MIN(LEFT.TF,RIGHT.TF)+INTERVAL)

[0043] Where LEFT.TF is the vertex subdivision factor of the left vertex, RIGHT.TF is the vertex subdivision factor of the right vertex, AVG() is the arithmetic mean of the values ​​in parentheses, MIN() is the minimum value in the list of values ​​in parentheses, and INTERVAL is a predefined parameter.

[0044] Wherein the hardware logic configured to reduce the vertex tessellation factor of each vertex in each newly formed patch includes reducing each vertex tessellation factor by a predefined parameter INTERVAL.

[0045] The initial patch may be a contour patch defined by two vertices (a left vertex and a right vertex).

[0046] The initial patch may be a triangular patch, and wherein the triangular patch is an ordered set of three vertices: an upper vertex, a right vertex, and a left vertex. The split patch may be a parent patch of two newly formed patches, and wherein the first new patch is an ordered set of three vertices: an upper vertex that is the new vertex added to the parent patch; a right vertex that is the left vertex of the parent patch; and a left vertex that is the upper vertex of the parent patch; and wherein the second new patch is an ordered set of three vertices: an upper vertex that is the new vertex added to the parent patch; a right vertex that is the upper vertex of the parent patch; and a left vertex that is the right vertex of the parent patch.

[0047] The hardware tessellation unit may also include hardware logic configured to: receive an input patch; generate one or more initial patches from the input patch; and repeat the operations of the hardware logic for each of the plurality of initial patches.

[0048] The input patch may be a triangular patch having three vertices, and wherein the hardware logic configured to generate one or more initial patches may include hardware logic configured to perform the following operations: comparing a vertex subdivision factor of each of the three vertices to a threshold; in response to determining that none of the vertex subdivision factors exceeds the threshold, outputting data describing the input patch; and in response to determining that at least one vertex subdivision factor exceeds the threshold, forming a new vertex at the center of the triangular patch, calculating a vertex subdivision factor for the new vertex, splitting the input patch to form three initial patches, each initial patch being a triangular patch with the new vertex as an upper vertex, and reducing the vertex subdivision factor of each vertex in each newly formed initial patch.

[0049] The input patch may be a quadrilateral patch having four vertices, and the hardware logic configured to generate one or more initial patches may include hardware logic that performs the following operations: forming a new vertex at the center of the quadrilateral patch; calculating a vertex subdivision factor for the new vertex; splitting the input patch to form four initial patches, each initial patch being a triangular patch with the new vertex as an upper vertex; and reducing the vertex subdivision factor for each vertex in each newly formed initial patch.

[0050] The input patch may be a quadrilateral patch having four vertices and a center subdivision factor, and wherein the hardware logic configured to generate one or more initial patches may include hardware logic configured to perform the following operations: adding five new vertices to subdivide the input patch into four sub-input quadrilateral patches; calculating the vertex subdivision factor for each of the five most recently added vertices; reducing the vertex subdivision factor for each vertex in the four most recently formed sub-input quadrilateral patches; and for each sub-input quadrilateral patch: forming a new vertex at the center of each sub-input quadrilateral patch; calculating the vertex subdivision factor for the new vertex; splitting each sub-input quadrilateral patch to form four initial patches, each initial patch being a triangular patch with the new vertex as an upper vertex; and reducing the vertex subdivision factor for each vertex in each most recently formed initial patch.

[0051] The input patch may be a triangular patch having three vertices and a center subdivision factor, and the hardware logic configured to generate one or more initial patches may include hardware logic configured to perform the following operations: adding four new vertices to subdivide the input patch into three sub-input quadrilateral patches; calculating the vertex subdivision factor for each of the four most recently added vertices; reducing the vertex subdivision factor for each vertex in the three most recently formed sub-input quadrilateral patches; and for each sub-input quadrilateral patch: forming a new vertex at the center of each sub-input quadrilateral patch; calculating the vertex subdivision factor for the new vertex; splitting each sub-input quadrilateral patch to form four initial patches, each initial patch being a triangular patch with the new vertex as an upper vertex; and reducing the vertex subdivision factor for each vertex in each most recently formed initial patch.

[0052] A third aspect provides a graphics processing unit comprising a hardware tessellation unit as set out above.

[0053] Additional aspects provide a non-transitory computer-readable storage medium having stored thereon computer-executable program code that, when executed, causes at least one processor to perform a method as set forth above, a graphics processing unit including a hardware subdivision unit as set forth above, a computer-readable storage medium having computer-readable program code encoded thereon defining a hardware subdivision unit as set forth above, and a computer-readable storage medium having computer-readable program code encoded thereon defining a hardware subdivision unit configured to perform a method as set forth above.

[0054] As will be apparent to the skilled person, the preferred features may be combined as appropriate and with any aspect of the invention.

[0055] BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:

[0057] Figure 1 shows the results of using various known segmentation methods;

[0058] Figure 2 is a schematic diagram showing an example of different results obtained using a prior art method with an edge subdivision factor and the method described herein using a vertex subdivision factor;

[0059] Figure 3 Various examples showing example results obtained using the improved segmentation method described herein;

[0060] Figure 4 shows additional example results obtained using the improved segmentation method described herein;

[0061] Figure 5 is a flow chart of the improved segmentation method;

[0062] Figure 6 is to show various input patches and to show Figure 5 Schematic diagram of the preprocessing stage of the method;

[0063] Figure 7 is for the triangle input patch Figure 5 Flow chart of the preprocessing stage of the method;

[0064] Figure 8 is for quadrilateral input patches Figure 5 Flow chart of the preprocessing stage of the method;

[0065] Fig. 9 is a flow chart for recursively applying the algorithm to each of the three or four triangle patches output by the preprocessing stage or to the input contour patch;

[0066] Fig.10 It shows the description Fig. 9 Schematic diagram of the triangle of the method;

[0067] Fig.11 is a schematic diagram showing a triangle illustrating the improved subdivision method described herein;

[0068] Fig.12 is an illustrated example of the improved segmentation method described herein;

[0069] Fig.13 is a schematic diagram illustrating the categories of triangles that may be generated using the improved subdivision method described herein;

[0070] Fig.14 shows a comparison between the results obtained using the improved segmentation method described herein and a known segmentation method;

[0071] Fig.15 is another example flow chart of the improved segmentation method and is Figure 5 Variations of the method shown;

[0072] Fig.16 It is shown Fig.15 A schematic diagram of the method;

[0073] Fig.17 yes Fig.15 A flowchart of an additional preprocessing stage of the method;

[0074] Fig.18 Show use Fig.15 Example results obtained by the method:

[0075] Fig.19 is a schematic diagram of an exemplary GPU pipeline; and

[0076] Fig. 20 Various components of an exemplary computing-based device are shown that may be implemented as any form of computing and / or electronic device and that may be configured to implement the improved segmentation methods described herein.

[0077] Common reference numbers are used throughout the drawings to indicate similar features.

[0078] Detailed Description

[0079] The following is a description of embodiments of the present invention as examples only. These examples represent the best mode currently known to the applicant for implementing the present invention, although they are not the only way in which the present invention can be implemented. This description sets forth the functions of the examples and the order of steps for constructing and operating the examples. However, the same or equivalent functions and sequences can be implemented by different examples.

[0080] There are several known tessellation methods that use an edge tessellation factor (TF) which defines for each edge of a (eg quadrilateral or triangle) patch and determines how many times the edge (and thus the patch) should be subdivided. Figure 1 Shows how the resulting triangles are different when using different edge subdivision factors, but the same subdivision factor for each edge.

[0081] exist Figure 1 The first four examples (a)-(d) in show:

[0082] (a) Integer partitioning, for all four edges, edge TF = 3

[0083] (b) Integer partitioning, for all four edges, edge TF = 4

[0084] (c) Second-power integer partitioning, for all four edges, edge TF = 3

[0085] (d) Second power integer partitioning, for all four edges, edge TF = 4

[0086] With integer and power-of-two integer subdivision, vertices along each edge are always evenly spaced; however, unwanted visual artifacts (such as explained below) are very likely to appear where the subdivision level changes and the triangles are not very small, but making polygons so small is undesirable as small polygons incur additional rendering overhead. This effect is particularly dynamic with power-of-two integer subdivision, because the step size can be much larger.

[0087] exist Figure 1 The last four examples (e)-(h) in show (unlike examples (a)-(d)) a fractional segmentation method that produces vertices at varying offsets:

[0088] e) Odd fractional split, for all four edges, edge TF = 3.0

[0089] f) Odd fractional split, for all four edges, edge TF = 4.0

[0090] g) Even fractional split, edge TF = 3.0 for all four edges

[0091] h) Even fractional split, for all four edges, edge TF = 4.0

[0092] When choosing a tessellation method, other considerations include not only the number of triangles produced for a given combination of edge tessellation settings (since the rendering cost of a tessellated model depends in part on the number of triangles), but also the aspect ratio of those triangles. In general, a graphics system (software or hardware) will render "equilateral" triangles for a given screen area (i.e., screen pixels) that imply a minimum perimeter-to-area ratio faster than it will render (skinny) triangles that have the same area but a higher perimeter-to-area ratio. Furthermore, triangles with a more equilateral shape should result in fewer artifacts when values ​​(e.g., the results of shading) are calculated at the vertices and then interpolated across triangles.

[0093] Another consideration is the complexity of the algorithm used to generate the pattern of triangles. If the algorithm can be kept simple and / or regular (e.g., without many "special cases" that need to be handled differently), this can reduce hardware or software implementation costs.

[0094] A final desirable consideration is rotational / reflection symmetry in the tessellation pattern. For example, it would be preferable for a quadrilateral patch defined using vertices given in, say, clockwise order ABCD and using an appropriate tessellation factor to produce the same final triangle mesh as an "equivalent" quadrilateral with vertices listed as BCDA. Some existing tessellation schemes do not guarantee this property (see, for example, Figure 1Examples of the middle square in (e) and (f) for the “odd” subdivision method).

[0095] In this description, a surface patch refers to a generally finite N-dimensional surface (or, in the case of contours, an N-dimensional curve segment) which is the result of applying a parametric mapping function to a bounded 2D domain, which is a quadrilateral or triangle (or, in the case of contours, a 1D line segment). The resulting surface or contour may be considered N-dimensional, as it may include not only 3 (or 4) dimensions for Cartesian (or homogeneous) spatial positioning, but also other parameters such as texture coordinates. As described above, surface patches may be curved to conform to the surface of the object they represent and / or to have displacement mapping applied. However, tessellation (i.e., subdivision of the patch) is not performed in "world space" (i.e., it is not performed on curved surface patches) but instead in domain space (which may also be referred to as parametric space or parameter space), where any position in the domain may be described by two coordinates (u, v) referred to as domain space coordinates, which means that the tessellation process is independent of any curvature present in the final surface.

[0096] An improved subdivision method is described herein, and when describing this subdivision method, the term "patch" is used to refer to an ordered set of two, three or four vertices (for contours, triangles or quadrilaterals, respectively) that form the boundaries of a domain. The term "domain" therefore refers to a two-dimensional space bounded by the vertices of the patch. The term "vertex" is generally used to describe a position plus other attributes, where these attributes differ depending on the context. For example, the input control points and output vertices from a domain shader include a 3D position plus other parameters, such as normals, tangents, textures, etc., while the vertices in the subdivision device (i.e., the vertices used in the subdivision method) include domain space coordinates and vertex subdivision factors. These vertices in the subdivision device are therefore different from the input control points or the resulting N-dimensional vertices that form the final triangle.

[0097] An improved subdivision method is described herein that does not use edge subdivision factors but instead uses subdivision factors defined for each corner vertex of a quadrilateral or triangle or each end vertex of a contour line. These subdivision factors are referred to as "vertex subdivision factors" to distinguish them from the edge subdivision factors used in the known methods described above. As described in detail below, subdivision (i.e., subdivision of the patch) occurs when any vertex subdivision factor of the patch exceeds a specified threshold. When new vertices are added, these subdivide the edge into two parts (wherein in various examples, these two parts may be equal, so that the edge is bisected), and the method acts recursively on the triangle patch.

[0098] The improved segmentation method described herein addresses one or more (and in various examples, all) of the following problems that arise in known segmentation methods:

[0099] Snapping - the effect of a large number of subdivisions occurring at once. This can cause not only temporary visual artifacts in the animation, but also discontinuous rendering times. This is especially true for "power of two" methods (e.g. Figure 1 The problem with examples (c) and (d) in .

[0100] • Breaks - The redistribution of edges on a boundary needs to be consistent to avoid T-junctions. After applying the displacement mapping, any T-junctions will almost certainly result in the appearance of cracks where the viewer can see through the object.

[0101] Float - Shifting the position of vertices in domain space according to their tessellation factor results in geometry that appears to shimmer or "float" as the amount of displacement changes.

[0102] No over / under subdivision - For example, a subdivision factor of 32 requires the edges to be subdivided into 32 segments. Any less than this may result in a mesh that is not refined enough to model the scene. Any more than this may result in a mesh that is too refined and uses too much computation.

[0103] Thin triangles - Rendering thin triangles can result in more aliasing artifacts and is computationally expensive, since the rendering cost of a triangle depends not only on its screen pixel area but also to some extent on the length of its perimeter in screen pixels. It is therefore often more efficient to render a patch represented by N "nearly equilateral" triangles than the same patch represented by N "long and thin" triangles, especially when thin triangles disappear as the LOD changes and are essentially redundant. Therefore, the method described below aims to maximize the minimum square root of the area to perimeter ratio (RootArea toPerimeter Ratio).

[0104] Space / Time Complexity - Any tessellation method should ideally be simple and highly parallelizable and minimize time and space complexity (i.e., the time it takes to perform the rendering and the amount of memory required to implement the algorithm). It must also not add too many bits to the size of the vertices, as this increases the memory requirements. Space and time complexity also affect the physical area of ​​the hardware required to perform the tessellation.

[0105] Specifying TFs at the corners of a patch results in less abrupt changes in the size and shape of the resulting triangles within the tessellated patch, because the division of the edge is not fixed (i.e. to the value specified by the edge TF), but is instead determined by the vertex TFs at each end of the edge, and changes smoothly not only along the original edge (in the 1D direction in parameter space) to produce a gradual transition between subdivision levels, but also in conjunction with other TFs to allow it to change smoothly across the patch in the 2D direction. This is in Figure 2 As shown in the figure, Figure 2 204) and the difference between a tessellation factor defined at an edge (illustrated 202) and a tessellation factor defined at a corner (or vertex, illustrated 204) in domain space using known methods. The first graph 202 is the result of using a tessellation factor defined by a defined power of two across the edges for two quadrilaterals with edge tessellation factors of 2 and 4. The second graph 204 uses the method described below and vertex tessellation factors of 2 (for vertices 206, 208) and 4 (for vertices 210-216).

[0106] exist Figure 3 and Figure 4 Additional examples with various integer and fractional subdivision factors for quadrilateral and triangular patches are shown in . Note that, for comparison purposes only, in the examples, a given numerical vertex subdivision factor takes the base-2 logarithm of the factor in a known edge-based subdivision scheme approximately equivalently. The text below each example shows the vertex subdivision factors in the following order: for a quadrilateral patch (upper left, upper right, lower left, lower right) and for a triangular patch (upper, lower left, lower right). From these examples, it can be seen that there is a gradual transition between subdivision levels within the patch, no long thin triangles are created, and that vertices are placed at their final positions in domain space and do not move when the LOD is increased (they only appear or disappear at fixed positions in domain space).

[0107] As described below, together with the vertex-based tessellation factor, this improved tessellation method minimizes (or eliminates) undesirable visual artifacts because each vertex (e.g., each new vertex added as part of a subdivision into a triangle) is always added at its final position in domain space. As a result, when the level of detail (and thus TF) changes, the vertices do not "slide" across the surface as in some prior art techniques, which can cause floating / wobbling artifacts.

[0108] Figure 5 606. The method begins when a patch (referred to as an input patch) is fed into a tessellation device. The tessellation device (which may be a hardware tessellation device) receives the input patch (block 502), where the input patch may be a triangle patch 602, a quadrilateral patch 604, or a contour patch 606, such as Figure 6 As shown. Although the quadrilateral patch 606 is a square in domain space (with vertices (0,0), (1,0), (0,1), and (1,1)), the shape it represents in world space (i.e., within a 3D or 2D environment) may be a different shape. As described above, subdivision is performed in domain space rather than world space.

[0109] If the input patch is a triangular patch or a quadrilateral patch, the patch undergoes a "pre-processing" stage (block 504) before the subdivision algorithm is recursively applied to the triangular patches within the input patch (block 506). The pre-processing stage is used to ensure that the subdivision is independent of orientation, and is therefore not required for contour patches 606 (because the algorithm works symmetrically and there is no orientation dependency of any resulting subdivision).

[0110] If the input patch is a triangle patch 602, the pre-processing stage (block 504) outputs one triangle patch 602 (which is identical to the input triangle patch and no subdivision is required therein) or three triangle patches 608-610. If the input patch is a quadrilateral patch 604, the pre-processing stage (block 504) outputs four triangle patches 612-615. If the input patch is a contour patch, no pre-processing is required (for the reasons set forth above) and the subdivision algorithm is recursively applied to the input contour patch (block 508).

[0111] Figure 7-10 The stages of the improved segmentation method are shown in more detail. The method as described uses the following notation:

[0112] THRES - threshold for subdivision, which may be set, for example, to 0.0 or 0.5, where the vertex TF is the value of the amount of subdivision to base 2 logarithm.

[0113] VERTEX.TF - the tessellation factor of the vertex, which can be any real number (although in various examples, any negative values ​​can be coerced to zero so that the tessellation factor is a non-negative real number). In various examples, the vertex TF is at least 0.0 (no tessellation) and at most 6.0 (maximum tessellation), where the value is the base-2 logarithm of the amount of tessellation, e.g., a tessellation factor of 5.0 corresponds to 32 subdivisions. In other examples, however, the maximum vertex TF can exceed 6.0 (or 64, where the base-2 logarithm is not used).

[0114] INTERVAL - the non-zero amount by which VERTEX.TF is decreased after each iteration, which may be set, for example, to 0.5, where Vertex TF is the value of the amount of subdivisions in base-2 logarithm.

[0115] MEAN() - a symmetric function that gives the "average" of two, three, or four vertex subdivision factors. This can be an arithmetic mean or an optional function, and one such optional function is described in more detail below.

[0116] For purposes of the following description, the vertex TF is the base-2 logarithm of the amount of tessellation; however, it will be appreciated that it may alternatively be written as its actual full value, and in this case the calculation of the vertex TF set forth below, as well as the values ​​of the parameters THRES and INTERVAL, will be modified accordingly. However, because hardware implementations are much faster where base-2 logarithms are used, in instances where the input to the tessellation device includes the actual vertex TF (rather than using base-2 logarithms), the input vertex TF may be converted to base-2 logarithms prior to implementing the improved tessellation method described herein.

[0117] Figure 7 is a flow chart of the pre-processing stage 504 of the triangle input patch 602, and as Figure 6 As shown, the vertices of the triangle patch may be labeled "TOP", "RIGHT", and "LEFT". Which vertex is "top" is chosen arbitrarily, and this pre-processing stage ensures that the algorithm is rotationally and reflectionally symmetric (i.e., so that the same subdivision results are achieved regardless of the order in which the vertices are considered in this pre-processing stage).

[0118] like Figure 7 As described, when a triangle patch (TOP, RIGHT, LEFT) 602 is fed into the tessellation device and any vertex tessellation factor is greater than a threshold, THRES ("YES" in block 702) tessellation occurs. A new vertex 616 denoted "MID" is formed at the center of the triangle (e.g., at the center of mass) (block 704), and the vertex TF of the new MID vertex is calculated (in block 706) as:

[0119] MID.TF=MEAN(TOP.TF,LEFT.TF,RIGHT.TF) (1)

[0120] Where MID.TF is the vertex TF of the MID vertex, TOP.TF is the vertex TF of the TOP vertex, LEFT.TF is the vertex TF of the LEFT vertex, and RIGHT.TF is the vertex TF of the RIGHT vertex. All four subdivision factors (i.e., TOP.TF, LEFT.TF, RIGHT.TF, and MID.TF) are then reduced by the parameter INTERVAL (i.e., by subtracting INTERVAL, where logarithmic notation with base 2 is used) as some subdivision occurs (block 708).

[0121] Three triangle patches (MID, RIGHT, LEFT) 610, (MID, LEFT, TOP) 609, and (MID, TOP, RIGHT) 608 are then formed (block 710), and it is these triangle patches that are tessellated (in block 506) using a tessellation algorithm as described below.

[0122] If no vertex tessellation factor is greater than the threshold value THRES ("No" in block 702), no tessellation occurs. In this case, the patch is simply passed through the tessellation device as a primitive (block 712) so that the method does not over-tessellate.

[0123] Figure 8 is a flow chart of the preprocessing stage 504 of the quadrilateral input patch 604, and as Figure 6 As shown, the vertices of the quadrilateral patch may be labeled "TLEFT (or top left)", "TRIGHT (or top right)", "BRIGHT (or bottom right)", and "BLEFT (or bottom left)". Which vertices are "top" and which are "bottom" is chosen arbitrarily, and this pre-processing stage ensures that the algorithm is rotationally and reflectionally symmetric (i.e., so that the same subdivision results are achieved regardless of the order in which the vertices are considered in this pre-processing stage).

[0124] like Figure 8 As described above, when the quadrilateral patch (TLEFT, TRIGHT, BLEFT, BRIGHT) 604 is fed into the tessellator, a new vertex 618 denoted "MID" is formed at the center of the quadrilateral, i.e., at domain space coordinates (0.5, 0.5) (block 804), and the vertex TF of the new MID vertex is calculated (in block 806) as:

[0125] MID.TF=MEAN(TLEFT.TF,TRIGHT.TF,BLEFT.TF,BRIGHT.TF) (2)

[0126] Where MID.TF is the vertex TF of the MID vertex, TLEFT.TF is the vertex TF of the TLEFT vertex, etc. All five subdivision factors (i.e., TLEFT.TF, TRIGHT.TF, BRIGHT.TF, BLEFT.TF, and MID.TF) are then reduced by the parameter INTERVAL (i.e., by subtracting INTERVAL, where logarithmic notation with base 2 is used) as some subdivision occurs (block 808).

[0127] Four triangular patches (MID, TLEFT, TRIGHT) 612, (MID, TRIGHT, BRIGHT) 613, (MID, BRIGHT, BLEFT) 614, and (MID, BLEFT, TLEFT) 615 are then formed (block 810), and it is these triangular patches that are tessellated (in block 506) using the tessellation method described below.

[0128] Fig. 9is a flowchart that recursively applies the algorithm to each of the three or four triangle patches output by the preprocessing stage, and this can be referred to Fig.10 The triangle shown is described. Fig.10 As shown, a triangle patch is an ordered set of three vertices (TOP, RIGHT, LEFT) in a clockwise direction. Note that the first vertex is always the "TOP" vertex, and for the initial triangle patch (as output by the pre-processing stage), this "TOP" vertex corresponds to the "MID" vertex 608, 618 added during pre-processing (blocks 704, 804).

[0129] like Fig. 9 As shown, given a triangle patch 1000 (which is the initial patch 900 in the first iteration), subdivision occurs if and only if the following holds:

[0130] LEFT.TF>THRES or RIGHT.TF>THRES (3)

[0131] Where LEFT.TF is the vertex TF of the LEFT vertex, and RIGHT.TF is the vertex TF of the RIGHT vertex ("YES" in block 902).

[0132] If LEFT.TF>THRES or RIGHT.TF>THRES ("yes" in block 902), a new vertex MID 1002 is formed (in block 904) which divides the edge LEFT->RIGHT into two parts in the domain space (indicated by arrow 1004). The vertex subdivision factor of the new MID vertex is then calculated (in block 906) as:

[0133] MID.TF=MEAN(LEFT.TF,RIGHT.TF) (4)

[0134] where MID.TF is vertex TF of the MID vertex, LEFT.TF is vertex TF of the LEFT vertex, and RIGHT.TF is vertex TF of the RIGHT vertex. For the sake of convention, the vertices LEFT and RIGHT that define the edges that subdivide MID are denoted as "fathers" of MID.

[0135] In many examples, the new vertex MID is added as a bisector of the edge LEFT->RIGHT in the domain space. However, in other examples, the new vertex MID may be added at a position that is on the edge LEFT->RIGHT in the domain space but does not absolutely bisect it. In various examples, the position of the MID along the edge may be weighted, for example, using the vertex TF of the parent vertex.

[0136] Two child triangle patches (MID, LEFT, TOP) 1006 and (MID, TOP, RIGHT) 1008 are formed (blocks 908 and 910), and all tessellation factors in each triangle patch 1006, 1008 are reduced by the parameter INTERVAL (block 912, i.e., by subtracting INTERVAL, where logarithmic notation with base 2 is used). The method is then recursively performed on each of these patches. When the method is performed on a triangle patch created in block 908 or block 910, the "TOP" vertex corresponds to the "MID" vertex 1002 that was added (in block 904) to create the patch, and the "TOP" vertex of the pair of parent patches will be different (e.g., patch 1000 can be considered the parent of patches 1006 and 1008, and the "TOP" vertex 1010 of 1000 is different from the "TOP" vertex 1002 of each of patches 1006 and 1008).

[0137] If no tessellation occurs at any stage ("NO" in block 902), the primitive (which is a patch) is added to a buffer (block 914), such as an index buffer.

[0138] As mentioned above, Fig. 9 The method is applied to each of the three or four triangle patches produced by the pre-processing stage (block 504) and recursively to any patches created by subdivision of those initial patches.

[0139] Because the vertex tessellation factors are finite and INTERVAL is constant and non-zero, eventually all vertex tessellation factors (in all triangle patches) will be at most THRES and the process will terminate.

[0140] If available Fig.10 As can be seen in FIG. 9 , the most recently added MID vertex is a vertex in both patches being formed (in blocks 908 and 910), and in both patches this vertex is considered the "TOP" vertex. When recursing into the two sub-patches, the current value of the vertex subdivision factor of the most recently added MID vertex must be used. In an example implementation that can be ensured by duplicating the vertex TF for each sub-patch or having a last step of the algorithm, where for any patch and after recursing on its two sub-patches, each vertex TF is increased by the parameter INTERVAL.

[0141] exist Fig. 9 The same algorithm used in can also be applied to contour patches (in block 508), although as mentioned above, no pre-processing is required and in the case of contour patches, the algorithm is applied to lines (i.e., contours and sub-contours) rather than to the contours as may be referenced. Figure 6 The triangle.

[0142] If the contour patch (LEFT, RIGHT) 606 is fed to the tessellation device (as the initial patch 900), then if LEFT.TF or RIGHT.TF is above THRES ("yes" in block 902), the line is subdivided. If LEFT.TF or RIGHT.TF is above THRES ("yes" in block 902), then a new MID vertex 620 is added that subdivides (e.g., bisects) the LEFT->RIGHT contour 606 in domain space (block 904). The vertex TF of the newly added MID vertex is calculated (in block 906) as:

[0143] MID.TF=MEAN(LEFT.TF,RIGHT.TF) (5)

[0144] Where MID.TF is the vertex TF of the MID vertex, LEFT.TF is the vertex TF of the LEFT vertex, and RIGHT.TF is the vertex TF of the RIGHT vertex.

[0145] The addition of the MID vertex 620 divides the original contour 606 into two sub-contours 622, 624 (formed in blocks 908 and 910), and each vertex TF is reduced by 2*INTERVAL (in block 912, i.e., by subtracting 2*INTERVAL, where base-2 logarithmic notation is used) - note that this reduces the vertex TF faster than the triangle patch produces the correct amount of subdivision. The method then recurses on each of these sub-contours and terminates when all vertex subdivision factors are at most THRES.

[0146] The improved subdivision method described above uses the MEAN() function. While this could in some examples be the arithmetic mean of the vertex subdivision factors, which would result in a smooth introduction of geometry when moving from one vertex to another, such a function would often result in T-junctions appearing and thus breaking for certain values ​​of vertex TF (e.g. the differences in vertex TF across the patch are quite extreme). Therefore, in many examples, an alternative function is used for MEAN() as follows:

[0147] MEAN(TF1,TF2,…)=MIN(AVG(TF1,TF2,…),MIN(TF1,TF2,…)+INTERVAL) (6)

[0148] Where AVG() is the arithmetic mean of the list of values ​​in the brackets (e.g. vertex TF1, vertex TF2, ... in the above example), and MIN() is the minimum value in the list of values ​​in the brackets (e.g. vertex TF1, vertex TF2, ... in the above example).

[0149] The MEAN() function given above is the function that is closest to the arithmetic mean ensuring that there are no breaks, and this can be demonstrated as explained below.

[0150] As mentioned above, T-junctions within a subdivision can lead to ruptures, and therefore it may be desirable to ensure that no T-junctions can be created in the interior of a domain or along an edge shared by two domains. The improved subdivision method described herein ensures this by ensuring that the subdivision of any edge is uniquely defined by the subdivision factor of the end vertices of the edge (and not by others). Thus, if an edge is shared by two domains (i.e., two adjacent domains), the domains share its two end vertices (and their vertex subdivision factors), and identical subdivisions will result.

[0151] As mentioned above, subdivision occurs only when the end vertex subdivision factor exceeds the threshold, so no additional subdivisions can occur. The only possible problem is if subdivision does not occur when it should because the previous level of subdivision did not occur earlier, and so to avoid this problem, the following condition must be met (which refers to having Fig.10 A triangle patch with the vertices marked as shown in 1000):

[0152] The subdivision required on the TOP->LEFT edge implies that the subdivision occurs on the LEFT->RIGHT edge

[0153] That is (TOP.TF>THRES or LEFT.TF>THRES)

[0154] =>(LEFT.TF+INTERVAL>THRES or RIGHT.TF+INTERVAL>THRES)

[0155] This condition is considered without loss of generality by considering only the left-hand side due to symmetry.

[0156] We can then prove that the MEAN() function specified above satisfies this condition:

[0157] Case 1: If LEFT.TF>THRES then LEFT>TF+INTERVAL>THRES

[0158] Case 2: TOP.TF>THRES has the following two sub-cases:

[0159] Case 2.1 (TOP is as in Fig.10 The middle vertex of the patch shown in patch 1000 in FIG. 10 and this corresponds to the middle vertex of the patch shown in FIG. Figure 6 616 or 618), that is, TOP.TF = MEAN(LEFT.TF, RIGHT.TF, ...), so

[0160] THRES <TOP.TF

[0161] =MIN(AVG(LEFT.TF,RIGHT.TF,…),MIN(LEFT.TF,RIGHT.TF,…)+INTERVAL)

[0162] <=MIN(LEFT.TF,RIGHT.TF,…)+INTERVAL

[0163] <=LEFT.TF+INTERVAL

[0164] So LEFT.TF+INTERVAL>THRES.

[0165] Case 2.2 (TOP is generated by subdivision with LEFT as the terminal vertex, as in Fig.11 As shown in the patch 1100 in FIG. 1 , TOP 1102 is generated by the subdivision of the edge LEFT->OTHER, that is, TOP.TF = MEAN(LEFT.TF, ...)), so

[0166] THRES <TOP.TF

[0167] =MIN(AVG(LEFT.TF,…),MIN(LEFT.TF,…)+INTERVAL)

[0168] <=MIN(LEFT.TF,…)+INTERVAL

[0169] <=LEFT.TF+INTERVAL

[0170] So LEFT.TF+INTERVAL>THRES.

[0171] In case 2.2, the same logic can be applied to TOP.TF = MEAN(RIGHT.TF, ...) (which corresponds to Fig.11 ) to get RIGHT.TF+INTERVAL>THRES as desired. Note also that the choice of function is optimal, since any function beyond the minimum plus INTERVAL will not always satisfy these inequalities. Therefore, the MEAN() function cannot be any function that is closer to the arithmetic mean.

[0172] By using base 2 logarithmic notation and Fig.12 The example of subdividing quadrilateral 1202 with THRES=0.0 and INTERVAL=0.5 with subdivision factor (2,1,1,1) is shown to further illustrate the improved subdivision method. Figure 8), the middle vertex 1204 with the tessellation factor 1.25 (the arithmetic mean calculated in block 806) is added (in block 804). Four triangle patches are formed (in block 810), with the middle vertex as the upper vertex of each patch, and each TF is reduced by 0.5 (in block 808, which can be performed before or after block 810), as shown in Fig.12 As shown in the second example 1206.

[0173] In each triangle patch (block 506 and Fig. 9 ), each lower edge is subdivided (in block 902, because 0.5 is above the threshold THRES=0.0), and four new vertices (with new vertex TF) and eight new patches are formed (in blocks 904-910), as in Fig.12 All subdivision factors are then reduced by 0.5 - as in the third example 1208 of Fig.12 The value of INTERVAL (in block 912) shown in the fourth example 1210.

[0174] In the next recursion on each of the eight triangle patches, the new vertices are added, the vertex TFs of those new vertices are calculated, and the vertex TFs are formed as in Fig.12 The 16 new patches shown in the fifth example 1212 in FIG. 1 are subdivided (in block 902, because 0.25 is above THRES) below each of the eight patches. All subdivision factors are then reduced by 0.5 again (in block 912), and in another recursion, the last two subdivisions are performed (as in Fig.12 ), where only the top left vertex subdivision factor (0.5) is above the threshold. After this step, all vertex subdivision factors are at most 0 (and Fig.12 As shown, vertex TF may be negative) and the process terminates.

[0175] Because the improved subdivision method described above processes each patch independently, it can be implemented with a high degree of parallelism. As with any subdivision method, vertices that are shared along domain boundaries can be cached so that they are not duplicated. Because the method is recursive, the amount of chip (e.g., silicon) space and memory required is minimal. Example requirements are outlined below:

[0176]

[0177]

[0178] The additional vertex member required by the proposed method is a fixed-point subdivision factor for each input vertex. M is the current size of the output vertex buffer, and α() is some function of M, depending on how the buffer is constructed. α() is generally a number between log(M) and M.

[0179] As described above, the minimum number of loops to render is achieved when rendering equilateral triangles or those triangles with a high square root of the area-to-perimeter ratio. Similarly, the worst performance occurs when the square root of the area-to-perimeter ratio vanishes, e.g., deteriorating the triangles. For a given triangle patch with edge lengths a, b, and c, the proposed method generates at most four different classes of triangles (up to similarity) A (having edges in the ratio a:b:c), B (having edges in the ratio a:d:c / 2), C (having edges in the ratio d:b:c / 2), and D (having edges in the ratio a / 2:b / 2:d), as Fig.13 As shown. In the case where the patches are contours (i.e. a=b), then B is similar to C, and therefore there are only three classes. If the patches are all contours and are at right angles at the upper vertices, then there is complete similarity (i.e. there is only a single class of triangles). In all cases, the number of triangle classes is finite; therefore the minimum square root of the area to perimeter ratio is bounded and cannot vanish unless the patch itself deteriorates. In contrast, many known subdivision methods have no lower bound on the square root of the area to perimeter ratio, and in practice vanishing triangles occur in large numbers.

[0180] Fig.14 It is shown that the improved subdivision method described in this article and the known subdivision method - odd fraction segmentation (as shown in the above reference Figure 1 Eight separate comparisons 1401-1408 are shown, and for each comparison, the results obtained using the improved segmentation method are shown on the left, while the results obtained using the odd fraction segmentation are shown on the right.

[0181] As shown in the first comparison 1401, the improved subdivision method starts with two more primitives than the odd fraction segmentation to ensure that the subdivision is independent of orientation. As described above, these four triangle primitives are generated in the preprocessing stage (block 504). The subdivision (in block 506) using the algorithm in the improved subdivision method begins by dividing the two patches into similar triangles, as shown in the second comparison 1402. In contrast, in the odd fraction segmentation (shown on the right), the subdivision starts by adding 12 new thin triangles and then adding many more triangles, all of which are almost redundant (because they are so thin that almost the entire domain consists of only two primitives, as clearly visible in the second comparison 1402, which means that these thin triangles do not add any detail to most of the domain after the shift), as shown in comparison 1403.

[0182] As shown in subsequent comparisons 1403-1408, the improved subdivision method continues to add similar triangles of half area to approximate the increase in the subdivision factor. The odd fraction segmentation continues to add too many initially redundant thin triangles to achieve the same effect. The improved subdivision method introduces vertices that do not move in domain space. On the contrary, in odd fraction segmentation, vertices start on top of old vertices and grow outward into the appropriate position, and therefore, the geometry looks undulating. The improved subdivision method stabilizes in a cross pattern as shown in the last comparison 1408, while the odd fraction segmentation continues to add entire rows and columns of vertices at each odd LOD / TF, which in turn moves all vertices in domain space.

[0183] It may sometimes be desirable to allow the user to specify a center TF for a patch that is different in LOD from the vertex TFs of the corners of the center of the patch, especially in animations. This can be used, for example, to better approximate a height map associated with a texture over a quad or triangle patch, if the map has a very fast jump in the middle, such as in the case of an animal's spur. Fig.15 The addition of another optional pre-processing stage (block 1502) is shown. Figure 5 A variation of the method (described above), this preprocessing stage implements the use of the center TF of a quadrilateral or triangular patch. Fig.15 As shown, this additional pre-processing stage (in block 1502) is implemented before the pre-processing stage (in block 504) described above, and segments the input patch (which can be a quadrilateral or a triangle). Unlike the original pre-processing stage (block 504), the additional pre-processing stage (block 1502) can also be applied to contour lines; however, it is less useful in this context. In the case of contour lines, the contour line is subdivided and the most recently added middle vertex is assigned a center TF. The subdivision then continues on the two sub-contour lines (e.g., LEFT-MID and MID-RIGHT) as described above.

[0184] For reference Fig.16 and 17 An additional pre-processing stage (block 1502) is described. Fig.16 A schematic diagram showing the application of the stage to a quadrilateral input patch 1602 or a triangular input patch 1604, and Fig.17 A flowchart showing an additional pre-processing stage.With center tessellation factor enabled, the user has to provide the tessellator with a per-patch center TF as well as a vertex TF for each corner vertex (three for triangular patches and four for quad patches).

[0185] like Fig.16As shown, an additional pre-processing stage divides the quadrilateral input patch 1602 into four quadrilateral patches 1606-1609 and divides the triangular input patch 1604 into three quadrilateral patches 1610-1612. To achieve this, pre-processing the quadrilateral input patch 1602 requires adding five new vertices (block 1702): a center vertex 1614 with a center TF (shared by all four subdomains 1606-1609), a middle top vertex 1616, a middle right vertex 1618, a middle bottom vertex 1620, and a middle left vertex 1622. The tessellation factor for each of the newly added vertices is calculated (in block 1706) by taking the MEAN() of their neighboring corner TFs. In various examples, the MEAN() function given by equation (6) may be used because it results in a more consistent tessellation pattern; however, in other examples, an arithmetic mean may be used.

[0186] Preprocessing the triangle input patch 1604 requires adding four new vertices (block 1704): a center vertex 1624 with a center TF (common to all three subdomains), a center right vertex 1626, a center bottom vertex 1628, and a center left vertex 1630. Each of the newly added vertices is given its tessellation factor (as calculated in block 1706) by taking the MEAN() of its neighboring corner TFs. As described above, in various examples, the MEAN() function given by equation (6) may be used because it results in a more consistent tessellation pattern; however, in other examples, an arithmetic mean may be used.

[0187] The final stage of the additional pre-processing stage (block 1708) reduces each subdivision factor, and in various examples, each TF is reduced by 2*INTERVAL. This reduction of the TF (before input to the original pre-processing stage of block 504) ensures that the correct number of subdivisions are made on each boundary edge of the patch and indicates that subdivision has occurred.

[0188] After the original input patch is subdivided into three or four quadrilateral patches, in the additional pre-processing stage (block 1502), these three or four quadrilateral patches (with their vertex TFs as calculated in block 1708) are input to the original pre-processing stage (block 504) as if they were the original input patches, and the method continues as described above. Fig.18 Shows that you can use Fig.15 Various example segmentations obtained by the method.

[0189] Due to the additional preprocessing stages (blocks 1502 and Fig.17) subdivides each domain edge at least once, even with a TF of 0.0, any single connected net should be fully subdivided with or without a central TF to ensure that no breaks occur (i.e., all patches in a single connected net should use the same method, i.e., they should all use Figure 5 method or Fig.15 method, and did not use Figure 5 Some input patches and usage of the method Fig.15 other input patches of the method).

[0190] The improved segmentation method described herein addresses one or more of the above-described problems that arise in known segmentation methods. In various examples, the improved segmentation method can address many or all of the problems detailed above, as follows:

[0191] No sudden moves - Using an improved subdivision method, geometry is increased in small increments to produce smooth transitions as the subdivision factor is increased. This helps with render time predictability.

[0192] No breakage - As demonstrated above, the improved subdivision method does not produce T-junctions within domains or along the boundaries of domains.

[0193] No Floating - When the tessellation factor increases, each vertex introduced by the tessellator maintains its domain space position and therefore there are no "floating" artifacts.

[0194] No over / under subdivision - integer vertex subdivision factor t at each end of the edge corresponds to 2 t Furthermore, the average vertex subdivision factor of t on a quadrilateral corresponds approximately to 2 2t vertices and up to twice as many primitives (which is the minimum). Similarly, a triangle patch corresponds to vertices and twice as many primitives.

[0195] No thin triangles - As mentioned above, the improved subdivision method produces only four (or fewer) categories of triangles per patch, and this limits the minimum value of the square root of the area to perimeter ratio per patch.

[0196] Space / time complexity — the algorithm is recursive (e.g. Fig. 9 ), and each sub-domain / patch can be processed independently, supporting considerable parallelism. The input vertices require additional fixed-point values ​​for the vertex subdivision factor.

[0197] Furthermore, the improved segmentation method described herein has the following additional characteristics in various examples:

[0198] • Orientation independence - by dividing the patch into fans of triangular patches, with the middle vertex as the vertex of each (in the pre-processing stage, block 504), no choice is made about the orientation of the triangles, so the same subdivision will always result.

[0199] N-gons - The improved subdivision method can be easily adapted to support any polygonal patch with N sides by dividing the patch into fans of triangles (in a variant of the preprocessing stage 504). In each case, for an average subdivision factor t, the method will produce approximately vertices and twice as many primitives.

[0200] Although the above examples (such as in Figure 5 ) shows that the improved subdivision method is implemented for triangular, quadrilateral and contour patches, it will be appreciated that the method can be implemented for only a subset of those patches (e.g. only quadrilateral patches, only triangular patches, or only quadrilateral and triangular patches).

[0201] Although Figure 5 5. The improved segmentation method is shown including a pre-processing stage (block 504) and a recursive application of a segmentation algorithm (in blocks 506 and 508), it will be appreciated that Fig. 9 The method shown may optionally be implemented independently without the preprocessing stage (block 504 and as Figure 7 and Figure 8 ), or alternatively, the preprocessing stage (block 504) may be used in conjunction with Figure 7 and Figure 8 Similarly, when using a center subdivision factor (such as Fig.15 ), the method may be implemented without the preprocessing stage (block 504 and as shown in Figure 7 and Figure 8 ), or alternatively, the preprocessing stage (block 504) may be used in conjunction with Figure 7 and Figure 8 The different ways of implementation are shown in .

[0202] In another variation of the improved subdivision method described above, the vertex subdivision factors may be represented differently, i.e., by transforming them by one or more scaling, translation or other transformations. Generating updated vertex subdivision factors (e.g., in blocks 708, 808, and 912) is therefore different from subtracting INTERVAL, e.g., vertex TF may be represented by raising two to their power and by dividing by the square root of 2. More generally, for any F(x) - a reversible function on real numbers, the subdivision factor TF' may be given by TF' = F(TF). Instead of subtracting INTERVAL, the following function may be used to update vertex TF (as calculated in blocks 708, 808, and 912):

[0203] TF’ := F(F -1 (TF’)-INTERVAL)

[0204] In this example, the test condition (instead of the condition given by Equation (3) above) would be TF’ > F(THRES) or TF’ < F(THRES), where the choice of inequality depends on whether F is order-preserving or order-reversing. By conjugating by F(), there is no semantic difference in the method.

[0205] In the example, if TF’ = F(TF) = 2 TF (i.e., no longer works in base-2 logarithm), the function used to update vertex TF (e.g., in blocks 708, 808, and 912) would be:

[0206]

[0207] The test condition would then be TF’ > 2 0 = 1, since 2 TF is order-preserving.

[0208] Although specific examples of the values of THRES and INTERVAL were provided in the above description, in other examples, different values of one or both of these parameters may be used.

[0209] In the above example, two possible functions MEAN() were described: the arithmetic mean and the MEAN() function given by Equation (6) above. In other example implementations of the improved subdivision method described herein, another function may optionally be used as the MEAN() function which may be symmetric or asymmetric (although this would result in a loss of azimuth independence).

[0210] Although the above example used single values for each of THRES and INTERVAL and a single MEAN() function (e.g., the arithmetic mean and the MEAN() function given by Equation (6)), other examples may use multiple values of THRES and / or MEAN and / or multiple MEAN() functions.

[0211] In the improved subdivision method described above, if LEFT.TF or RIGHT.TF exceeds THRES, a new vertex is added (and in cases where “or” is used, e.g., in Equation (3), in its standard meaning, a new vertex is added if one or both of LEFT.TF and RIGHT.TF exceed the threshold). In a variation of the above example, the subdivision may be performed only when both LEFT.TF and RIGHT.TF exceed THRES.

[0212] Although in the improved subdivision method described above, new vertices are added if LEFT.TF or RIGHT.TF exceeds THRES (as in equation (3)), it will be appreciated that in variations of the method described, new vertices may be added if LEFT.TF or RIGHT.TF exceeds or equals THRES.

[0213] In the above description, the subdivision is described as being applied recursively (e.g., in blocks 506 and 508). However, in other examples, the method may not be applied recursively, for example, it may be applied iteratively (performing a single level of subdivision on all current patches before performing the next level of subdivision on all generated patches). In another example, another non-recursive method may be implemented, such as testing whether each vertex on the 65 by 65 grid should be included and then determining which primitives any included vertex is part of based on the position of the vertex.

[0214] In the examples described above, the improved segmentation method is described as being performed in the domain space. In another variation of the method, the segmentation may optionally be applied outside the domain space.

[0215] The vertex TFs input to the improved tessellation method may be generated by a separate application (e.g., based on the distance of the viewer from each vertex, e.g., the vertex TF of a vertex may be proportional to the inverse of the distance of the vertex from the eye). In various examples, an API may be provided that converts edge TFs to vertex TFs before inputting them into the methods described herein (e.g., by averaging all edge TFs of edges that meet at a vertex).

[0216] The improved tessellation method described herein may be used to perform tessellation on the fly (eg, as the viewpoint changes in a 3D scene), or alternatively, the method may be used offline to precompute triangles for multiple different viewpoints.

[0217] The improved segmentation method described herein can be implemented in hardware. In various examples, the Fig.19 The method is implemented in a hardware subdivision unit within a graphics processing unit (GPU) as shown. Fig.19 Schematic diagram of an example GPU pipeline 1900 that may be implemented in hardware within a GPU is shown. Fig.19 As shown, pipeline 1900 includes a vertex shader 1902, which is responsible for performing each vertex calculation, including calculating all of the vertex subdivision factors (e.g., based on the position of the vertex from the camera). Before calculating the vertex TF, the vertex shader transforms the vertex into world space and may apply one or more other linear transformations. Vertex shader 1902 is unaware of the mesh topology and only knows the current vertex fed to it.

[0218] Between the vertex shader 1902 and the hardware tessellation unit (or tessellation unit) 1904 (or between the vertex shader and Fig.19 1904, where pipeline 1900 includes one or more optional hull shaders between vertex shader 1902 and tessellator 1904, a patch (i.e., an ordered set of vertices) is constructed using the topology (where this can be a pre-built selection stored in a tessellator selected by the user prior to the outgoing call). This patch information is passed to the hull shader (where provided). However, tessellator 1904 only uses the vertex TF, and the rest of the patch information is passed on to domain shader 1906.

[0219] The hardware tessellation unit (or tessellation device) 1904 includes a processor that uses the received vertex TF to implement the improved tessellation method described above (e.g., as in Figure 5 , 7 -9, 15 and 17). Unlike the vertex shader, the hardware tessellation unit (and any optional hull shader) operates per patch rather than per vertex. In order to simplify the hardware required to implement the equations for calculating the new vertex TF (e.g., in blocks 706, 806, 906 and 1706), the calculations may be performed in log2 (as in the examples described above) and so may be implemented as additions and subtractions (or alternatively multiplications and divisions would be used). As described above, the hardware tessellation unit 1904 may be configured to perform aspects of the method described above in parallel (e.g., the recursions in blocks 506 and 608 on different patches, for example, as Fig. 9 The hardware tessellation unit 1904 outputs the domain space coordinates of each new vertex and passes it to the domain shader 1906 (e.g., by storing the details of each patch in a buffer, as in Fig. 9 ).

[0220] The domain shader 1906 acts as the second vertex shader for the vertices produced by the tessellation 1904 and is executed once per vertex (which is produced by the tessellation). The domain shader is provided with a domain space position (u,v) and given all patch information and outputs a full vertex structure. The domain shader uses the patch control points and domain space coordinates to construct a new vertex and apply any displacement mapping (e.g. by sampling some bumps or height map encoded in a texture).

[0221] After the domain shader 1906 is run on each generated vertex for each patch, the vertex is passed to the rasterizer (not in Fig.19 In tandem, primitives (in the form of index buffers) are passed from the tessellator to the rasterizer.

[0222] Fig.19The GPU pipeline 1900 is shown only as an example, and the improved tessellation method using vertex TF described herein can be used in any GPU architecture. It will also be appreciated that the hardware tessellation unit 1904 can be used in the GPU pipeline, in addition to or in place of the vertex shader 1902, the optional shell shader and the domain shader 1906, the GPU also includes other shaders.

[0223] The improved subdivision method described above may optionally be implemented in software (or a combination of software and hardware). Fig. 20 Various components of an exemplary computing-based device 2000 are shown that may be implemented as any form of computing and / or electronic device and that may be configured to implement the segmentation method described above.

[0224] The computing-based device 2000 includes one or more processors 2002, which may be microprocessors, controllers, or any other suitable type of processor for processing computer executable instructions to control the operation of the device so as to perform the improved segmentation method described above. In some examples, such as where a system-on-chip architecture is used, the processor 2002 may include one or more fixed function blocks (also referred to as accelerators) that implement a portion of the improved segmentation method in hardware (rather than software or firmware). Platform software including an operating system 2004 or any other suitable platform software may be provided at the computing-based device to enable application software 2006 to execute on the device, and the application software may include a segmentation module 2008. This segmentation module 2008 may, for example, include a pre-processing module (which implements Figure 5 or Fig.15 Block 504), optionally an additional pre-processing module (which implements Fig.15 1502) and a recursive subdivision module (which implements Figure 5 or Fig.15 Blocks 506 and / or 508).

[0225] Computer executable instructions can be provided using any computer-readable medium accessed by computing-based device 2000. Computer-readable media may include, for example, computer storage media, such as memory 2010 and communication media. Computer storage media (i.e., non-temporary machine-readable media), such as memory 2010, include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EPROM, EEPROM, flash memory or other storage technology, CD-ROM, digital versatile disc (DVD) or other optical storage, cassettes, magnetic tapes, disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information accessed by a computing device. On the contrary, communication media may embody computer-readable instructions, data structures, program modules or other data in modulated data signals, such as carrier waves or other transmission mechanisms. As defined herein, computer storage media do not include communication media. Although computer storage media (i.e., non-transitory machine-readable media, such as memory 2010) are shown within computing-based device 2000, it should be understood that the memory may be distributed or located remotely and accessed via a network or other communication link (e.g., using communication interface 2012).

[0226] The computing-based device 2000 may also include an input / output controller arranged to display information to a display device that may be separate from or integrated into an integral part of the computing-based device 2000. The display information may provide a graphical user interface. The input / output controller may also be arranged to receive and process input from one or more devices, such as a user input device (e.g., a mouse or keyboard). In an embodiment, the display device may also serve as a user input device if it is a touch-sensitive display device. The input / output controller may also output data to a device other than the display device, such as a locally connected printing device.

[0227] The terms "processor" and "computer" are used herein to refer to any device or part thereof having processing capabilities so that it can execute instructions. The term "processor" may include, for example, a central processing unit (CPU), a graphics processing unit (GPU or VPU), a physical processing unit (PPU), a radio processing unit (RPU), a digital signal processor (DSP), a general-purpose processor (such as a general-purpose GPU), a microprocessor, any processing unit designed to accelerate tasks outside the CPU, etc. Those skilled in the art will recognize that such processing capabilities are incorporated into many different devices, and therefore the term "computer" includes set-top boxes, media players, digital radios, PCs, servers, mobile phones, personal digital assistants, and many other devices.

[0228] Those skilled in the art will recognize that storage devices for storing program instructions can be distributed in the network. For example, a remote computer can store examples of processes described as software. A local or terminal computer can access the remote computer and download a portion or all of the software to run the program. Alternatively, the local computer can download fragments of the software as needed or execute some software instructions at the local terminal and some instructions at the remote computer (or computer network). Those skilled in the art will also recognize that all or part of the software instructions can be implemented by a dedicated circuit (e.g., DSP, programmable logic array, etc.) by utilizing conventional techniques known to those skilled in the art.

[0229] The methods described herein may be performed by a computer configured with software in a machine-readable form stored on a tangible storage medium, for example in the form of a computer program including computer-readable program code for configuring a computer to perform the components of the method or in the form of a computer program including computer program code modules suitable for performing all the steps of any method described herein when the program is run on a computer, and wherein the computer program may be embodied on a computer-readable storage medium. Examples of tangible (or non-transitory) storage media include disks, thumb drives, memory cards, etc., and do not include propagating signals. The software may be suitable for execution on a parallel processor or a serial processor, so that the method steps may be executed in any suitable order or simultaneously.

[0230] The hardware components described herein may be produced by a non-transitory computer-readable storage medium having a computer-readable program code encoded thereon.

[0231] It is intended to also include software that "describes" or defines the configuration of the hardware that implements the modules, functions, components or logic described above, such as HDL (hardware description language) software, such as used for designing integrated circuits or for configuring programmable chips to achieve the desired functions. That is, a computer-readable storage medium may be provided, which has a computer-readable program code stored thereon for generating a processing unit configured to perform any method described herein or for generating a processing unit including any device described herein. That is, a computer system may be configured to generate a representation of a digital circuit from the definition of circuit elements and data for defining the rules for combining those circuit elements, wherein a non-transitory computer-readable storage medium may have processor-executable instructions stored thereon, which when executed at such a computer system causes the computer system to generate a processing unit as described herein. For example, a non-transitory computer-readable storage medium may have computer-readable instructions stored thereon, which when executed at a computer system for generating a representation of an integrated circuit causes the computer system to generate a representation of a processor of a receiver as described in the examples herein or to generate a representation of a processor configured to perform the methods as described in the examples herein. The representation of a processor may be the processor itself or a representation (e.g., a mask) of a processor that can be used to generate a processor.

[0232] The memory storing the machine executable data used in implementing the disclosed aspects may be a non-transitory medium. The non-transitory medium may be volatile or non-volatile. Examples of volatile non-transitory media include semiconductor-based memories such as SRAM or DRAM. Examples of technologies that can be used to implement non-volatile memory include optical and magnetic memory technologies, flash memory, phase change memory, and persistent RAM.

[0233] A specific reference to "logic" refers to a structure that performs one or more functions. Examples of logic include circuits that are arranged to perform those functions. For example, such circuits may include transistors and / or other hardware elements available during the manufacturing process. As an example, such transistors and / or other elements may be used to form circuits or structures that implement and / or contain memories such as registers, flip-flops or latches, logic operators such as Boolean operations, mathematical operators such as adders, multipliers or shifters, and interconnections. Such elements may be provided as custom circuits or standard cell libraries, macros, or at other abstract levels. Such elements may be interconnected in a specific arrangement. Logic may include fixed-function circuits, and the circuits may be programmed to perform one or more functions; such programming may be provided from firmware or software updates or control mechanisms. Logic that is identified as performing a function may also include logic that implements constituent functions or subprocesses. In an example, hardware logic has circuits that implement fixed-function operations or multiple operations, state machines, or processes.

[0234] As will be apparent to the skilled artisan, any range or device value given herein may be expanded or altered without losing the effect sought.

[0235] It will be understood that the benefits and advantages described above may relate to one embodiment or may relate to several embodiments. The embodiments are not limited to those that solve any or all of the stated problems or those that have any or all of the stated benefits and advantages.

[0236] Any reference to "an" item refers to one or more of those items. The term "comprising" is used herein to mean including the identified method blocks or elements, but such blocks or elements do not comprise an exclusive list, and an apparatus may include additional blocks or elements, and a method may include additional operations or elements. Furthermore, blocks, elements, and operations are not themselves implicitly closed.

[0237] The steps of the method described herein can be performed in any appropriate order or simultaneously on appropriate occasions. The arrows between the boxes in the accompanying drawings illustrate an example order of method steps, but are not intended to exclude the execution of other orders or parallel multiple steps. In addition, a separate block can be deleted from any method without departing from the spirit and scope of the subject matter described herein. The aspects of any example described above can be combined with any aspect of the other examples described to form other examples without losing the effect sought. In the case where the elements of the accompanying drawings are shown as being connected by arrows, it is to be understood that these arrows illustrate only an example flow of the communication (including data and control messages) between the elements. The flow between the elements can be in either direction or in both directions.

[0238] It is to be understood that the above description of the preferred embodiment is given only as an example, and various modifications may be made by those skilled in the art. Although various embodiments have been described above with a certain degree of detail or with reference to one or more individual embodiments, those skilled in the art may make many changes to the disclosed embodiments without departing from the spirit or scope of the invention.

Claims

1. A hardware subdivision unit, the hardware subdivision unit comprising hardware logic, the hardware logic configured to: for an initial patch including a left vertex and a right vertex connected by an edge and defined in a domain space: comparing the vertex subdivision factor of the left vertex and the vertex subdivision factor of the right vertex with a threshold; and In response to determining that either the vertex subdivision factor of the left vertex or the right vertex exceeds or equals the threshold, forming a new vertex that subdivides the edge into two parts, calculating the vertex subdivision factor of the new vertex, splitting the initial patch to form a first new patch including the left vertex and the new vertex and a second new patch including the right vertex and the new vertex, and reducing the vertex subdivision factor of each vertex in each newly formed patch.

2. The hardware tessellation unit of claim 1, wherein the new vertex bisects the edge.

3. The hardware tessellation unit of claim 1, wherein the hardware logic is further configured to repeat operations of the hardware logic using each newly formed patch as the initial patch.

4. The hardware tessellation unit of claim 3 , wherein the hardware logic is configured to repeat the operation of the hardware logic for each newly formed patch as the initial patch until the vertex tessellation factors of the left and right vertices in each patch do not exceed the threshold.

5. The hardware tessellation unit of claim 1 , wherein the hardware logic configured to calculate the vertex tessellation factor for the new vertex comprises hardware logic configured to: Calculating an average value of vertex subdivision factors of the left vertex and the right vertex; and The vertex subdivision factor of the new vertex is set equal to the calculated average value.

6. The hardware tessellation unit according to claim 5, wherein the average of the vertex tessellation factors of the left vertex and the right vertex is given by: MEAN(LEFT.TF,RIGHT.TF)=MIN(AVG(LEFT.TF,RIGHT.TF),MIN(LEFT.TF,RIGHT.TF)+INTERVAL) Where LEFT.TF is the vertex subdivision factor of the left vertex, RIGHT.TF is the vertex subdivision factor of the right vertex, AVG() is the arithmetic mean of the values ​​in parentheses, MIN() is the minimum value in the list of values ​​in parentheses, and INTERVAL is a predefined parameter.

7. The hardware tessellation unit of claim 1, wherein the hardware logic configured to reduce the vertex tessellation factor of each vertex in each newly formed patch comprises reducing each vertex tessellation factor by a predefined parameter INTERVAL.

8. The hardware tessellation unit of claim 1, wherein the initial patch is a contour patch defined by two vertices, the left vertex and the right vertex.

9. The hardware tessellation unit of claim 1, wherein the initial patch is a triangle patch, and wherein the triangle patch is an ordered set of three vertices: an upper vertex, the right vertex, and the left vertex.

10. The hardware tessellation unit of claim 9, wherein the patch being split is a parent patch of two newly formed patches, and wherein the first new patch is an ordered set of three vertices: an upper vertex that is a new vertex added to the parent patch, a right vertex that is a left vertex of the parent patch, and a left vertex that is an upper vertex of the parent patch; and wherein the second new patch is an ordered set of three vertices: an upper vertex that is a new vertex added to the parent patch, a right vertex that is a upper vertex of the parent patch, and a left vertex that is a right vertex of the parent patch.

11. The hardware subdivision unit of claim 9, further comprising hardware logic configured to perform the following operations: Receive input patch; generating one or more initial patches from the input patches; and The operation of the hardware logic is repeated for each of a plurality of initial patches.

12. The hardware tessellation unit of claim 11, wherein the input patch is a triangular patch having three vertices, and wherein the hardware logic configured to generate one or more initial patches comprises hardware logic configured to: comparing a vertex subdivision factor of each of the three vertices to a threshold value; In response to determining that none of the vertex tessellation factors exceeds the threshold, outputting data describing the input patch; and In response to determining that at least one of the vertex subdivision factors exceeds the threshold, a new vertex is formed at the center of the triangular patch, a vertex subdivision factor of the new vertex is calculated, the input patch is split to form three initial patches, each initial patch is a triangular patch with the new vertex as an upper vertex, and the vertex subdivision factor of each vertex in each newly formed initial patch is reduced.

13. The hardware tessellation unit of claim 11 , wherein the input patch is a quadrilateral patch having four vertices, and wherein the hardware logic configured to generate one or more initial patches comprises hardware logic that: forming a new vertex at the center of the quadrilateral patch; Calculating a vertex subdivision factor for the new vertex; Splitting the input patch to form four initial patches, each initial patch being a triangular patch with the new vertex as an upper vertex; and Reduce the vertex subdivision factor for each vertex in each newly formed initial patch.

14. The hardware tessellation unit of claim 11, wherein the input patch is a quadrilateral patch having four vertices and a center tessellation factor, and wherein the hardware logic configured to generate one or more initial patches comprises hardware logic configured to: Adding five new vertices to subdivide the input patch into four sub-input quadrilateral patches; Calculate the vertex subdivision factor for each of the five most recently added vertices; reducing the vertex subdivision factor of each vertex in the newly formed four sub-input quadrilateral patches; as well as For each sub-input quadrilateral patch: forming a new vertex at the center of each of said sub-input quadrilateral patches; Calculating a vertex subdivision factor for the new vertex; splitting each of the sub-input quadrilateral patches to form four initial patches, each initial patch being a triangular patch with the new vertex as an upper vertex; and Reduce the vertex subdivision factor for each vertex in each newly formed initial patch.

15. The hardware tessellation unit of claim 11, wherein the input patch is a triangle patch having three vertices and a center tessellation factor, and wherein the hardware logic configured to generate one or more initial patches comprises hardware logic configured to: Adding four new vertices to subdivide the input patch into three sub-input quadrilateral patches; Calculate the vertex subdivision factor for each of the four most recently added vertices; Decrease the vertex subdivision factor of each vertex in the three newly formed sub-input quadrilateral patches; as well as For each sub-input quadrilateral patch: forming a new vertex at the center of each of said sub-input quadrilateral patches; Calculating a vertex subdivision factor for the new vertex; splitting each of the sub-input quadrilateral patches to form four initial patches, each initial patch being a triangular patch with the new vertex as an upper vertex; and Reduce the vertex subdivision factor for each vertex in each newly formed initial patch.

16. A graphics processing unit, comprising the hardware subdivision unit according to any one of claims 1-15.

17. A method of performing subdivision in a computer graphics system, the method comprising: For an initial patch consisting of a left vertex and a right vertex connected by an edge and defined in the domain space ： Comparing the vertex subdivision factor of the left vertex and the vertex subdivision factor of the right vertex with a threshold; as well as In response to determining that either the vertex subdivision factor of the left vertex or the right vertex exceeds or equals the threshold, forming a new vertex that subdivides the edge into two parts, calculating the vertex subdivision factor of the new vertex, splitting the initial patch to form a first new patch including the left vertex and the new vertex and a second new patch including the right vertex and the new vertex, and reducing the vertex subdivision factor of each vertex in each newly formed patch.

Images