Organic Light-Emitting Diode Display Device and Pixel Thereof

Abstract

The present invention discloses an organic light emitting diode (OLED) display device and a pixel thereof. The OLED display device includes: a first transistor including a gate coupled to a first node, a second transistor including a gate receiving a first scan signal, a third transistor including a gate receiving a first scan signal, a fourth transistor including a gate receiving a second scan signal, a fifth transistor including a gate receiving a second scan signal, a sixth transistor including a gate receiving a third scan signal, a seventh transistor including a gate receiving an emission signal, a first capacitor including a first electrode coupled to a line of a first power supply voltage and a second electrode coupled to a second node, a second capacitor including a first electrode coupled to the second node and a second electrode coupled to the first node, and an OLED including an anode and a cathode coupled to a line of a second power supply voltage.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2020 - 0055731, filed on May 11, 2020, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] Example embodiments of the present disclosure relate to a display device, and more particularly, to a pixel of an organic light - emitting diode (OLED) display device and an OLED display device. Background art

[0004] In recent years, due to the high demand in the information technology (IT) industry, the demand for organic light - emitting diode (OLED) display devices has increased rapidly. However, there are still many problems associated with OLED display devices. One of these problems is that OLED display devices may consume most of the power of the device. Therefore, it may be desirable to reduce power consumption in OLED display devices adopted in portable devices such as smart phones, tablet computers, etc. In recent years, in order to reduce the power consumption of OLED display devices, a low - frequency driving technique has been developed to drive or refresh a display panel at a frequency lower than the normal driving frequency by analyzing image data. For example, when performing low - frequency driving, the OLED display device may not drive the display panel for at least one frame, or may not supply a data voltage to the display panel so that the display panel displays an image based on the stored data voltage, thereby reducing power consumption.

[0005] However, when the display panel displays an image based on the stored data voltage, the stored data voltage may be distorted due to the leakage current of transistors included in the pixels of the display panel. Therefore, when the driving frequency of the display panel changes, the brightness of the display panel may change, and the image quality of the OLED display device may be degraded. Therefore, there is a need for a novel OLED display device that maintains a constant brightness so that the image quality does not degrade when the driving frequency of the display panel changes. Summary of the invention

[0006] Some example embodiments provide a pixel of an organic light - emitting diode (OLED) display device that can have substantially constant brightness even when the driving frequency changes.

[0007] Some example embodiments provide an OLED display device that can have substantially constant brightness even when the driving frequency changes.

[0008] According to an exemplary embodiment, a pixel of an OLED display device is provided. The pixel includes: a first transistor including a gate coupled to a first node, a first terminal coupled to a line of a first power voltage, and a second terminal; a second transistor including a gate receiving a first scan signal, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to the first node; a third transistor including a gate receiving the first scan signal, a first terminal coupled to the line of the initialization voltage, and a second terminal coupled to an anode of an organic light-emitting diode; a fourth transistor including a gate receiving a second scan signal, a first terminal coupled to a line of a reference voltage, and a second terminal coupled to a second node; a fifth transistor including a gate receiving the second scan signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the first node; a sixth transistor including a gate receiving a third scan signal, a first terminal coupled to a data line, and a second terminal coupled to the second node; a seventh transistor including a gate receiving an emission signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the organic light-emitting diode; a first capacitor including a first electrode coupled to the line of the first power voltage and a second electrode coupled to the second node; a second capacitor including a first electrode coupled to the second node and a second electrode coupled to the first node; and an organic light-emitting diode including an anode and a cathode coupled to a line of a second power voltage.

[0009] In the exemplary embodiment, the first transistor and the seventh transistor may be PMOS transistors, and the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor may be NMOS transistors.

[0010] In the exemplary embodiment, a frame period of the pixel may include: a gate and anode initialization period in which a gate of the first transistor and an anode of the organic light-emitting diode are initialized; a threshold voltage compensation period in which a threshold voltage of the first transistor is compensated; a data writing period in which a data voltage of the data line is applied to the second node; and an emission period in which the organic light-emitting diode emits light.

[0011] In the exemplary embodiment, during the gate and anode initialization period, the emission signal may have a cut-off level, the first scan signal may have a conductive level, the second scan signal and the third scan signal may respectively have cut-off levels, the second transistor and the third transistor may be turned on, the second transistor may apply the initialization voltage to the first node, and the third transistor may apply the initialization voltage to the anode of the organic light-emitting diode.

[0012] In an exemplary embodiment, during a threshold voltage compensation period, the emission signal may have a cut-off level, the second scan signal may have a conduction level, the first scan signal and the third scan signal may have cut-off levels respectively, the fourth transistor and the fifth transistor may be turned on, the fourth transistor may apply a reference voltage to the second node, the fifth transistor may diode-connect the first transistor, and a voltage obtained by subtracting the threshold voltage from the first power supply voltage may be applied to the first node through the diode-connected first transistor.

[0013] In an exemplary embodiment, during a data writing period, the emission signal may have a cut-off level, the third scan signal may have a conduction level, the first scan signal and the second scan signal may have cut-off levels respectively, the sixth transistor may be turned on, and the sixth transistor may apply a data voltage to the second node.

[0014] In an exemplary embodiment, during an emission period, the emission signal may have a conduction level, the first scan signal, the second scan signal and the third scan signal may have cut-off levels respectively, the seventh transistor may be turned on, the first transistor may generate a driving current based on the voltage of the first node, and the seventh transistor may supply the driving current to the organic light emitting diode.

[0015] In an exemplary embodiment, the time length of the threshold voltage compensation period may be longer than the time length of the data writing period.

[0016] In an exemplary embodiment, the gate and anode initialization period, the threshold voltage compensation period, and the data writing period may have equal time lengths.

[0017] In an exemplary embodiment, the pixel may further include an eighth transistor, the eighth transistor including a gate receiving a fourth scan signal, a first terminal receiving the emission signal, and a second terminal coupled to the second terminal of the first transistor.

[0018] In an exemplary embodiment, the first transistor may be a PMOS transistor, and the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor may be NMOS transistors.

[0019] In an exemplary embodiment, a frame period of the pixel may include: a gate and anode initialization period during which the gate of the first transistor and the anode of the organic light emitting diode are initialized; a drain initialization period during which the second terminal of the first transistor is initialized; a threshold voltage compensation period during which the threshold voltage of the first transistor is compensated; a data writing period during which a data voltage of a data line is applied to the second node; and an emission period during which the organic light emitting diode emits light.

[0020] In an exemplary embodiment, during a drain initialization period, a transmission signal may have a cut-off level, a fourth scan signal may have a conductive level, a first scan signal, a second scan signal, and a third scan signal may respectively have a cut-off level, an eighth transistor may be turned on, and the eighth transistor may apply the transmission signal having the cut-off level to a second terminal of the first transistor.

[0021] In an exemplary embodiment, the drain initialization period may be located between a gate and anode initialization period and a threshold voltage compensation period, and may not overlap with the gate and anode initialization period and the threshold voltage compensation period.

[0022] In an exemplary embodiment, the drain initialization period may be located between a gate and anode initialization period and a threshold voltage compensation period, and may partially overlap with the gate and anode initialization period and the threshold voltage compensation period.

[0023] In an exemplary embodiment, during a period in which the drain initialization period and the threshold voltage compensation period overlap with each other, the transmission signal may have a cut-off level, the second scan signal and the fourth scan signal may respectively have a conductive level, the first scan signal and the third scan signal may respectively have a cut-off level, a fifth transistor and an eighth transistor may be turned on, and the transmission signal having the cut-off level may be applied to a first node through the eighth transistor and the fifth transistor.

[0024] According to an exemplary embodiment, a pixel of an OLED display device is provided. The pixel includes: a first transistor including a gate coupled to a first node, a first terminal coupled to a line of a first power voltage, and a second terminal; a second transistor including a gate receiving a first scan signal, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to the first node; a third transistor including a gate receiving a fourth scan signal, a first terminal coupled to a line of the initialization voltage, and a second terminal coupled to an anode of an organic light-emitting diode; a fourth transistor including a gate receiving a second scan signal, a first terminal coupled to a line of a reference voltage, and a second terminal coupled to a second node; a fifth transistor including a gate receiving the second scan signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the first node; a sixth transistor including a gate receiving a third scan signal, a first terminal coupled to a data line, and a second terminal coupled to the second node; a seventh transistor including a gate receiving an emission signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the organic light-emitting diode; a first capacitor including a first electrode coupled to the line of the first power voltage and a second electrode coupled to the second node; a second capacitor including a first electrode coupled to the second node and a second electrode coupled to the first node; and an organic light-emitting diode including an anode and a cathode coupled to a line of a second power voltage.

[0025] In the exemplary embodiment, the first transistor, the third transistor, and the seventh transistor may be PMOS transistors, and the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor may be NMOS transistors.

[0026] In the exemplary embodiment, the fourth scan signal may be an inverted version of the first scan signal.

[0027] According to an exemplary embodiment, an OLED display device is provided, including: a display panel including a plurality of pixels; a data driver configured to provide data voltages to the plurality of pixels; a scan driver configured to provide a first scan signal, a second scan signal, and a third scan signal to the plurality of pixels; an emission driver configured to provide an emission signal to the plurality of pixels; and a controller configured to control the data driver, the scan driver, and the emission driver. Each of the plurality of pixels includes: a first transistor including a gate coupled to a first node, a first terminal coupled to a line of a first power voltage, and a second terminal; a second transistor including a gate receiving the first scan signal, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to the first node; a third transistor including a gate receiving the first scan signal, a first terminal coupled to a line of the initialization voltage, and a second terminal coupled to an anode of an organic light-emitting diode; a fourth transistor including a gate receiving the second scan signal, a first terminal coupled to a line of a reference voltage, and a second terminal coupled to a second node; a fifth transistor including a gate receiving the second scan signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the first node; a sixth transistor including a gate receiving the third scan signal, a first terminal coupled to a data line, and a second terminal coupled to the second node; a seventh transistor including a gate receiving the emission signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the organic light-emitting diode; a first capacitor including a first electrode coupled to a line of the first power voltage and a second electrode coupled to the second node; a second capacitor including a first electrode coupled to the second node and a second electrode coupled to the first node; and an organic light-emitting diode including an anode and a cathode coupled to a line of a second power voltage.

[0028] As described above, in the pixel of the OLED display device and the OLED display device, the pixel may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, a second capacitor, and an organic light-emitting diode, and a part of the first to seventh transistors may be implemented using NMOS transistors. Therefore, even if the driving frequency of the display panel including the pixels changes, the pixels can emit light with substantially constant brightness at the same gray level. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Exemplary non-limiting example embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings.

[0030] Figure 1 is a circuit diagram showing a pixel of an organic light-emitting diode (OLED) display device according to an exemplary embodiment.

[0031] Figure 2It is a timing diagram of an example for describing the operation of a pixel according to an exemplary embodiment.

[0032] Figure 3 It is a circuit diagram of an example for describing the operation of a pixel during a gate and anode initialization period.

[0033] Figure 4 It is a circuit diagram of an example for describing the operation of a pixel during a threshold voltage compensation period.

[0034] Figure 5 It is a circuit diagram of an example for describing the operation of a pixel during a data writing period.

[0035] Figure 6 It is a circuit diagram of an example for describing the operation of a pixel during an emission period.

[0036] Figure 7 It is a timing diagram of another example for describing the operation of a pixel according to an exemplary embodiment.

[0037] Figure 8 It is a timing diagram of yet another example for describing the operation of a pixel according to an exemplary embodiment.

[0038] Figure 9 It is a circuit diagram showing a pixel of an OLED display device according to an exemplary embodiment.

[0039] Figure 10 It is a timing diagram of an example for describing the operation of a pixel according to an exemplary embodiment.

[0040] Figure 11 It is a circuit diagram showing a pixel of an OLED display device according to an exemplary embodiment.

[0041] Figure 12 It is a timing diagram of an example for describing the operation of a pixel according to an exemplary embodiment.

[0042] Figure 13 It is a circuit diagram of an example for describing the operation of a pixel during a drain initialization period.

[0043] Figure 14 It is a timing diagram of another example for describing the operation of a pixel according to an exemplary embodiment.

[0044] Figure 15 It is a circuit diagram of an example for describing the operation of a pixel during a period in which a drain initialization period and a threshold voltage compensation period overlap each other.

[0045] Figure 16 It is a block diagram showing an OLED display device according to an exemplary embodiment.

[0046] Figure 17It is a timing diagram showing examples of an emission signal, a first scan signal, a second scan signal, and a third scan signal in an OLED display device according to an exemplary embodiment.

[0047] Figure 18 It is a timing diagram for describing an example of the operation of an OLED display device according to an exemplary embodiment.

[0048] Figure 19 It is an electronic device including an OLED display device according to an exemplary embodiment. Detailed Description

[0049] Hereinafter, embodiments of the present disclosure will be explained in detail with reference to the accompanying drawings.

[0050] Figure 1 It is a circuit diagram showing a pixel of an organic light emitting diode (OLED) display device according to an exemplary embodiment.

[0051] Referring to Figure 1 , a pixel 100 of an OLED display device according to an exemplary embodiment may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C1, a second capacitor C2, and an organic light emitting diode EL.

[0052] The first transistor T1 may generate a driving current based on the voltage of the first node N1 or the voltage of the second electrode of the first capacitor C1. For example, the first transistor T1 may be a driving transistor for generating a driving current. In some exemplary embodiments, the first transistor T1 may include a gate coupled to the first node N1, a first terminal coupled to a line of a first power supply voltage VDD (e.g., a high power supply voltage), and a second terminal.

[0053] The second transistor T2 may apply an initialization voltage VINIT to the first node N1 in response to the first scan signal SCAN1. In some exemplary embodiments, the second transistor T2 may include a gate receiving the first scan signal SCAN1, a first terminal coupled to a line of the initialization voltage VINIT, and a second terminal coupled to the first node N1.

[0054] The third transistor T3 may apply an initialization voltage VINIT to the anode of the organic light emitting diode EL in response to the first scan signal SCAN1. In some exemplary embodiments, the third transistor T3 may include a gate receiving the first scan signal SCAN1, a first terminal coupled to a line of the initialization voltage VINIT, and a second terminal coupled to the anode of the organic light emitting diode EL.

[0055] The fourth transistor T4 can apply a reference voltage VREF to the second node N2 in response to the second scan signal SCAN2. In some example embodiments, the fourth transistor T4 can include a gate that receives the second scan signal SCAN2, a first terminal coupled to a line of the reference voltage VREF, and a second terminal coupled to the second node N2.

[0056] The fifth transistor T5 can diode-connect the first transistor T1 in response to the second scan signal SCAN2. In some example embodiments, the fifth transistor T5 can include a gate that receives the second scan signal SCAN2, a first terminal coupled to the second terminal of the first transistor T1, and a second terminal coupled to the first node N1.

[0057] The sixth transistor T6 can transfer the data voltage of the data line DL to the second node N2 in response to the third scan signal SCAN3. In some example embodiments, the sixth transistor T6 can include a gate that receives the third scan signal SCAN3, a first terminal coupled to the data line DL, and a second terminal coupled to the second node N2. Further, in some example embodiments, the sixth transistor T6 can have a double-gate structure including an upper gate and a lower gate. The sixth transistor T6 having the double-gate structure can transfer the data voltage quickly and efficiently.

[0058] The seventh transistor T7 can supply the drive current generated by the first transistor T1 to the organic light-emitting diode EL in response to the emission signal EM. In some example embodiments, the seventh transistor T7 can include a gate that receives the emission signal EM, a first terminal coupled to the second terminal of the first transistor T1, and a second terminal coupled to the anode of the organic light-emitting diode EL.

[0059] The first capacitor C1 can be coupled between the line of the first power supply voltage VDD and the second node N2. In some example embodiments, the first capacitor C1 can include a first electrode coupled to the line of the first power supply voltage VDD and a second electrode coupled to the second node N2.

[0060] The second capacitor C2 can be coupled between the second node N2 and the first node N1. In some example embodiments, the second capacitor C2 can include a first electrode coupled to the second node N2 and a second electrode coupled to the first node N1. Further, in some example embodiments, the second capacitor C2 can have a high capacitance and thus can stably store the data voltage. For example, the capacitance of the second capacitor C2 can be higher than the capacitance of the first capacitor C1, but the capacitances of the first capacitor C1 and the second capacitor C2 are not limited thereto.

[0061] When the seventh transistor T7 is turned on, the organic light-emitting diode EL can emit light based on the driving current generated by the first transistor T1. In some exemplary embodiments, the organic light-emitting diode EL may include an anode coupled to the second terminal of the seventh transistor T7 and a cathode coupled to a line of the second power supply voltage VSS (e.g., a low power supply voltage).

[0062] The OLED display device supporting the low-frequency driving technology can analyze the input image data and can change the driving frequency of the display panel according to the image corresponding to the input image data. For example, the OLED display device can drive the display panel at a normal driving frequency (e.g., about 240 Hz, about 120 Hz, etc.) or at the input frame frequency of the input image data when the input image data represents a moving image, and can drive the display panel at a low frequency lower than the normal driving frequency or the input frame frequency when the input image data represents a still image. Therefore, when displaying a still image, the power consumption of the OLED display device can be reduced. However, when the driving frequency of the display panel changes, even if the input image data represents the same gray level, as the time length of each frame period increases, the brightness of the pixels of the display panel may decrease due to the leakage current of the transistors T1, T2, T3, T4, T5, T6, and T7 of the pixels or the leakage current of the transistors T2, T4, T5, and T6 whose terminals (e.g., source and / or drain) are directly coupled to the first capacitor C1 and the second capacitor C2 (especially at high gray levels).

[0063] However, in the pixel 100 of the OLED display device according to the exemplary embodiment, as Figure 1 shown, the first transistor T1 and the seventh transistor T7 can be implemented using PMOS transistors, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be implemented using NMOS transistors having relatively small leakage current. In this case, since the transistors T2, T4, T5, and T6 whose terminals (e.g., source and / or drain) are directly coupled to the first capacitor C1 and the second capacitor C2 are implemented using NMOS transistors, the leakage current of the transistors T2, T4, T5, and T6 from the first capacitor C1 and the second capacitor C2 can be reduced. Therefore, even if the driving frequency of the display panel changes, the pixel 100 of the display panel can display an image with a substantially constant brightness at the same gray level. Therefore, the pixel 100 according to the exemplary embodiment can display an image with a substantially constant brightness in a wide driving frequency range (e.g., from about 10 Hz to about 240 Hz).

[0064] Figure 2 is a timing diagram for describing an example of the operation of the pixel according to the exemplary embodiment, Figure 3A circuit diagram for an example describing the operation of a pixel during a gate and anode initialization period. Figure 4 A circuit diagram for an example describing the operation of a pixel during a threshold voltage compensation period. Figure 5 A circuit diagram for an example describing the operation of a pixel during a data writing period, and Figure 6 A circuit diagram for an example describing the operation of a pixel during an emission period.

[0065] Referring to Figure 1 and Figure 2 , the frame period FP of pixel 100 may include a gate and anode initialization period GAIP, a threshold voltage compensation period CMPP, a data writing period DWP, and an emission period EMP. In some example embodiments, as Figure 1 and Figure 2 shown, the emission signal EM may be an active-low signal having a low level as the conduction level ON and a high level as the cut-off level OFF, and the first to third scan signals SCAN1, SCAN2, and SCAN3 may be active-high signals having a high level as the conduction level ON and a low level as the cut-off level OFF. For example, the high levels of signals EM, SCAN1, SCAN2, and SCAN3 may be, but are not limited to, approximately 8V, and the low levels of signals EM, SCAN1, SCAN2, and SCAN3 may be, but are not limited to, approximately -6V.

[0066] During the gate and anode initialization period GAIP, the gate of the first transistor T1 and the anode of the organic light-emitting diode EL may be initialized. During the gate and anode initialization period GAIP, the emission signal EM may have the cut-off level OFF, the first scan signal SCAN1 may have the conduction level ON, and the second scan signal SCAN2 and the third scan signal SCAN3 may have the cut-off level OFF. In some example embodiments, the emission signal EM may be changed to the cut-off level OFF, and then the first scan signal SCAN1 may be changed to the conduction level ON. In other example embodiments, the emission signal EM and the first scan signal SCAN1 may be changed to the cut-off level OFF and the conduction level ON, respectively, substantially simultaneously. Further, in some example embodiments, the gate and anode initialization period GAIP may have a time length corresponding to, but not limited to, three horizontal times (or 3H time). Further, in some example embodiments, one horizontal time (or 1H time) of the OLED display device may be determined according to the maximum driving frequency of the display panel (e.g., approximately 240 Hz). Here, one horizontal time may indicate the time allocated to process one row of pixels within the frame period.

[0067] During the gate and anode initialization period GAIP, as Figure 3As shown, the seventh transistor T7 can be turned off in response to the emission signal EM having a cut-off level OFF, and the second transistor T2 and the third transistor T3 can be turned on in response to the first scan signal SCAN1 having a conduction level ON. Accordingly, the second transistor T2 can apply the initialization voltage VINIT to the first node N1 or the gate of the first transistor T1, and thus the gate of the first transistor T1 can be initialized. Further, the third transistor T3 can apply the initialization voltage VINIT to the anode of the organic light-emitting diode EL, and thus the anode of the organic light-emitting diode EL can be initialized. For example, the initialization voltage VINIT can be, but is not limited to, about -1V.

[0068] During the threshold voltage compensation period CMPP, the threshold voltage of the first transistor T1 (e.g., the driving transistor) can be compensated. During the threshold voltage compensation period CMPP, the emission signal EM can have a cut-off level OFF, the second scan signal SCAN2 can have a conduction level ON, and the first scan signal SCAN1 and the third scan signal SCAN3 can have a cut-off level OFF. In some example embodiments, the first scan signal SCAN1 can be changed to the cut-off level OFF, and then the second scan signal SCAN2 can be changed to the conduction level ON. In other example embodiments, the first scan signal SCAN1 and the second scan signal SCAN2 can be changed to the cut-off level OFF and the conduction level ON, respectively, substantially simultaneously. Further, in some example embodiments, the threshold voltage compensation period CMPP can have a time length corresponding to, but not limited to, three horizontal times (or 3H time). In some example embodiments, as Figure 2 shown, the threshold voltage compensation period CMPP and the data write period DWP can be separated from each other, and the time length of the threshold voltage compensation period CMPP (e.g., 3H time) can be longer than the time length of the data write period DWP (e.g., 1H time). In this case, since the threshold voltage compensation period CMPP has a time length longer than the time length of the data write period DWP, the threshold voltage of the first transistor T1 (e.g., the driving transistor) can be sufficiently compensated.

[0069] During the threshold voltage compensation period CMPP, as Figure 4As shown, the fourth transistor T4 and the fifth transistor T5 can be turned on in response to the second scan signal SCAN2 having an on level ON. Accordingly, the fourth transistor T4 can apply the reference voltage VREF to the second node N2 or the first electrode of the second capacitor C2. For example, the reference voltage VREF can be, but is not limited to, about 2V. Further, the fifth transistor T5 can diode-connect the first transistor T1. Accordingly, the voltage VDD-VTH obtained by subtracting the threshold voltage VTH from the first power supply voltage VDD can be applied to the first node N1 or the second electrode of the second capacitor C2 through the diode-connected first transistor T1. For example, the first power supply voltage VDD can be, but is not limited to, about 8V, and the second power supply voltage VSS can be, but is not limited to, about -5V.

[0070] During the data write period DWP, the data voltage of the data line DL can be applied to the second node N2 or the first electrode of the second capacitor C2. During the data write period DWP, the emission signal EM can have an off level OFF, the third scan signal SCAN3 can have an on level ON, and the first scan signal SCAN1 and the second scan signal SCAN2 can have an off level OFF. In some example embodiments, the second scan signal SCAN2 can be changed to the off level OFF, and then the third scan signal SCAN3 can be changed to the on level ON. In other example embodiments, the second scan signal SCAN2 and the third scan signal SCAN3 can be changed to the off level OFF and the on level ON, respectively, substantially simultaneously. Further, in some example embodiments, the data write period DWP can have a time length corresponding to, but not limited to, one horizontal time (or 1H time).

[0071] During the data write period DWP, as Figure 5As shown, the sixth transistor T6 can be turned on in response to a third scan signal SCAN3 having an on level ON. Accordingly, the sixth transistor T6 can apply a data voltage VDAT to the second node N2 or the first electrode of the second capacitor C2. Accordingly, the voltage of the first electrode of the second capacitor C2 can be changed from a reference voltage VREF by a difference VDAT-VREF between the data voltage VDAT and the reference voltage VREF to be changed to the data voltage VDAT. If the voltage of the first electrode of the second capacitor C2 is changed by the difference VDAT-VREF between the data voltage VDAT and the reference voltage VREF, the voltage of the second electrode of the second capacitor C2 in a floating state can also be changed by the difference VDAT-VREF between the data voltage VDAT and the reference voltage VREF. Accordingly, in a data write period DWP, the voltage of the second electrode of the second capacitor C2 or the voltage of the first node N1 can become a voltage VDD-VTH+VDAT-VREF, where the difference VDAT-VREF between the data voltage VDAT and the reference voltage VREF is added to a voltage VDD-VTH obtained by subtracting a threshold voltage VTH from a first power supply voltage VDD.

[0072] In an emission period EMP, the organic light emitting diode EL can emit light. In the emission period EMP, an emission signal EM can have an on level ON, and a first scan signal SCAN1, a second scan signal SCAN2, and a third scan signal SCAN3 can have an off level OFF. In some exemplary embodiments, the third scan signal SCAN3 can be changed to the off level OFF, and then the emission signal EM can be changed to the on level ON. In other exemplary embodiments, the third scan signal SCAN3 and the emission signal EM can be changed to the off level OFF and the on level ON, respectively, substantially simultaneously.

[0073] In the emission period EMP, as Figure 6 shown, the seventh transistor T7 can be turned on in response to the emission signal EM having the on level ON. Accordingly, the first transistor T1 can generate a drive current IDR based on the voltage VDD-VTH+VDAT-VREF of the first node N1 or the voltage VDD-VTH+VDAT-VREF of the second electrode of the second capacitor C2, the seventh transistor T7 can supply the drive current IDR to the organic light emitting diode EL, and the organic light emitting diode EL can emit light based on the drive current IDR. The drive current IDR generated by the first transistor T1 can be according to an equation “β / 2*(VSG-VTH) 2”to determine. Here, β can be the transistor gain determined by the mobility, capacitance, and width and length of the channel of the first transistor T1, VSG can be the source-gate voltage of the first transistor T1, and VTH can be the threshold voltage of the first transistor T1. Further, since the source voltage of the first transistor T1 is the first power supply voltage VDD, and the gate voltage of the first transistor T1 is the voltage of the first node N1, VDD - VTH + VDAT - VREF, so "VSG - VTH" can be "VDD - VDD + VTH - VDAT + VREF - VTH = VREF - VDAT". Therefore, the drive current IDR can be determined based on the reference voltage VREF and the data voltage VDAT, regardless of the threshold voltage VTH of the first transistor T1.

[0074] Figure 7 is a timing diagram for describing another example of the operation of a pixel according to an exemplary embodiment.

[0075] Referring to Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 and Figure 7 , the frame period FP of the pixel 100 can include a gate and anode initialization period GAIP, a threshold voltage compensation period CMPP, a data write period DWP, and an emission period EMP. Except that the time length of the data write period DWP increases from one horizontal time (1H time) to three horizontal times (3H time), Figure 7 the frame period FP shown in Figure 2 can be substantially the same as the frame period FP shown in

[0076] In some exemplary embodiments, as shown in Figure 7 , the gate and anode initialization period GAIP, the threshold voltage compensation period CMPP, and the data write period DWP can have the same time length, for example, three horizontal times (3H time). Figure 7An example of the emission signal EM of the pixel 100 in the Nth row and the first to third scan signals SCAN1, SCAN2, and SCAN3 is shown, where N is an integer greater than 2. The first data voltage may be written to the pixel 100 in the (N - 2)th row during the first 1H time of the data write period DWP, the second data voltage may be written to the pixel 100 in the (N - 1)th row during the second 1H time of the data write period DWP, and the third data voltage may be written to the pixel 100 in the Nth row during the third 1H time of the data write period DWP. In this case, since the first data voltage and the second data voltage for the pixels 100 in the (N - 2)th row and the (N - 1)th row are provided before the third data voltage is written to the pixel 100 in the Nth row, a precharge operation may be performed on the pixel 100 in the Nth row.

[0077] Figure 8 is a timing diagram for describing another example of the operation of a pixel according to an exemplary embodiment.

[0078] Referring to Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 and Figure 8 , the frame period FP of the pixel 100 may include a gate and anode initialization period GAIP, a threshold voltage compensation period CMPP, a data write period DWP, and an emission period EMP. Except that the time length of the gate and anode initialization period GAIP is reduced and the time length of the threshold voltage compensation period CMPP is increased, Figure 8 the frame period FP shown in Figure 2 may be substantially the same as the frame period FP shown in

[0079] In some exemplary embodiments, compared with the frame period FP shown in Figure 2 , the gate and anode initialization period GAIP shown in Figure 8 may be reduced from three horizontal times (3H time) to two horizontal times (2H time), and the threshold voltage compensation period CMPP may be increased from three horizontal times (3H time) to four horizontal times (4H time). In this case, while maintaining the time length of the emission period EMP, the time length of the threshold voltage compensation period CMPP may be increased, and thus the threshold voltage of the first transistor T1 (e.g., a driving transistor) may be compensated more fully.

[0080] Figure 9 is a circuit diagram showing a pixel of an OLED display device according to an exemplary embodiment, and Figure 10It is a timing diagram of an example for describing the operation of a pixel according to an example embodiment.

[0081] Referring to Figure 9 and Figure 10 , the pixel 200 of the OLED display device according to the example embodiment may include a first transistor T1, a second transistor T2, a third transistor T3', a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C1, a second capacitor C2, and an organic light-emitting diode EL. Except that the third transistor T3' is implemented using a PMOS transistor and the third transistor T3' may receive a fourth scan signal SCAN1B instead of the first scan signal SCAN1, Figure 9 the pixel 200 may have substantially the same configuration as the pixel 100 of Figure 1 . Further, except that the pixel 200 further receives the fourth scan signal SCAN1B, Figure 10 the signals EM, SCAN1, SCAN1B, SCAN2, and SCAN3 provided to the pixel 200 as shown in Figure 2 may be substantially the same as the signals EM, SCAN1, SCAN2, and SCAN3 provided to the pixel 100 as shown in Figure 2 . That is, during the gate and anode initialization period GAIP, the fourth scan signal SCAN1B has a conductive level ON, and during the periods CMPP, DWP, and EMP, the fourth scan signal SCAN1B has a cut-off level OFF.

[0082] The third transistor T3' may apply an initialization voltage VINIT to the anode of the organic light-emitting diode EL in response to the fourth scan signal SCAN1B. In some example embodiments, the third transistor T3' may include a gate that receives the fourth scan signal SCAN1B, a first terminal coupled to the line of the initialization voltage VINIT, and a second terminal coupled to the anode of the organic light-emitting diode EL. Further, in some example embodiments, as shown in Figure 9 and Figure 10 , the third transistor T3' may be a PMOS transistor, and the fourth scan signal SCAN1B may be an inverted version of the first scan signal SCAN1. Therefore, the third transistor T3' may be turned on while the second transistor T2 is turned on.

[0083] As shown in Figure 9As shown, the first transistor T1, the third transistor T3', and the seventh transistor T7 may be implemented using PMOS transistors, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be implemented using NMOS transistors having a relatively small leakage current. In this case, since the transistors T2, T4, T5, and T6 whose terminals (e.g., source and / or drain) are directly coupled to the first capacitor C1 and the second capacitor C2 are implemented using NMOS transistors, the leakage current of the transistors T2, T4, T5, and T6 from the first capacitor C1 and the second capacitor C2 can be reduced. Accordingly, even if the driving frequency of the display panel changes, the pixel 200 of the display panel can display an image at a substantially constant luminance at the same gray level. Accordingly, the pixel 200 according to the exemplary embodiment can display an image at a substantially constant luminance in a wide driving frequency range (e.g., from about 10 Hz to about 240 Hz).

[0084] Figure 11 is a circuit diagram showing a pixel of an OLED display device according to an exemplary embodiment, Figure 12 is a timing diagram for describing an example of an operation of a pixel according to an exemplary embodiment, and Figure 13 is a circuit diagram for describing an example of an operation of a pixel during a drain initialization period.

[0085] Referring to Figure 11 and Figure 12 , a pixel 300 of an OLED display device according to an exemplary embodiment may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7', an eighth transistor T8, a first capacitor C1, a second capacitor C2, and an organic light emitting diode EL. Except that the seventh transistor T7' is implemented using an NMOS transistor and the pixel 300 further includes an eighth transistor T8, Figure 11 the pixel 300 of Figure 1 may have substantially the same configuration as the pixel 100 of Figure 12 . Further, except that the pixel 300 further receives a fourth scan signal SCAN4, Figure 2 the signals EM, SCAN1, SCAN2, SCAN3, and SCAN4 provided to the pixel 300 as shown in Figure 12 may be substantially the same as the signals EM, SCAN1, SCAN2, and SCAN3 provided to the pixel 100 as shown in Figure 12 . Further, except that Figure 2 the frame period FP of

[0086] The seventh transistor T7' can supply the driving current generated by the first transistor T1 to the organic light-emitting diode EL in response to the emission signal EM. In some example embodiments, the seventh transistor T7' can be an NMOS transistor, and the emission signal EM can be an active-high signal having a high level as the conduction level ON and a low level as the cutoff level OFF. For example, the high level or conduction level ON of the emission signal EM can be, but is not limited to, about 8V, and the low level or cutoff level OFF of the emission signal EM can be, but is not limited to, about -6V.

[0087] The eighth transistor T8 can apply the emission signal EM having a cutoff level OFF (e.g., a low level) to the second terminal or drain of the first transistor T1 in response to the fourth scan signal SCAN4. In some example embodiments, the eighth transistor T8 can include a gate receiving the fourth scan signal SCAN4, a first terminal receiving the emission signal EM, and a second terminal coupled to the second terminal of the first transistor T1. Further, in some example embodiments, the eighth transistor T8 can have, but is not limited to, a double-gate structure including an upper gate and a lower gate.

[0088] As Figure 11 shown, the first transistor T1 can be implemented using a PMOS transistor, and the second to eighth transistors T2, T3, T4, T5, T6, T7', and T8 can be implemented using NMOS transistors having relatively small leakage currents. In this case, since the transistors T2, T3, T4, T5, T6, T7', and T8 whose terminals (e.g., source and / or drain) are directly or indirectly coupled to the first capacitor C1 and the second capacitor C2 are implemented using NMOS transistors, the leakage currents of the transistors T2, T3, T4, T5, T6, T7', and T8 from the first capacitor C1 and the second capacitor C2 can be reduced. Thus, even when the driving frequency of the display panel changes, the pixel 300 of the display panel can display an image at a substantially constant brightness at the same gray level. Therefore, the pixel 300 according to the example embodiments can display an image at a substantially constant brightness in a wide driving frequency range (e.g., from about 10Hz to about 240Hz).

[0089] Further, as Figure 12 shown, the frame period FP of the pixel 300 can include a gate and anode initialization period GAIP, a drain initialization period DIP, a threshold voltage compensation period CMPP, a data write period DWP, and an emission period EMP. In some example embodiments, the drain initialization period DIP may not overlap with the threshold voltage compensation period CMPP. For example, as Figure 12As shown, the drain initialization period DIP can be located between the gate and anode initialization period GAIP and the threshold voltage compensation period CMPP, and may not overlap with the gate and anode initialization period GAIP and the threshold voltage compensation period CMPP.

[0090] During the drain initialization period DIP, the second terminal or drain of the first transistor T1 can be initialized. During the drain initialization period DIP, the emission signal EM can have a cut-off level OFF, the fourth scan signal SCAN4 can have a conduction level ON, and the first scan signal SCAN1, the second scan signal SCAN2, and the third scan signal SCAN3 can have a cut-off level OFF. In some exemplary embodiments, the first scan signal SCAN1 can be changed to the cut-off level OFF, and then the fourth scan signal SCAN4 can be changed to the conduction level ON. In other exemplary embodiments, the first scan signal SCAN1 and the fourth scan signal SCAN4 can be changed to the cut-off level OFF and the conduction level ON respectively substantially simultaneously. Further, in some exemplary embodiments, the drain initialization period DIP can have a time length corresponding to but not limited to two horizontal times (or 2H time).

[0091] During the drain initialization period DIP, as Figure 13 shown, the eighth transistor T8 can be turned on in response to the fourth scan signal SCAN4 having a conduction level ON (e.g., high level). Thus, the eighth transistor T8 can apply the emission signal EM having a cut-off level OFF (e.g., low level) to the second terminal or drain of the first transistor T1, and thus can initialize the drain of the first transistor T1. For example, the emission signal EM having a cut-off level OFF can be but not limited to about -6V.

[0092] Figure 14 is a timing diagram for describing another example of the operation of a pixel according to an exemplary embodiment, and Figure 15 is a circuit diagram for describing an example of the operation of a pixel during a period in which the drain initialization period and the threshold voltage compensation period overlap each other.

[0093] Referring to Figure 11 , Figure 12 , Figure 13 and Figure 14 , the frame period FP of the pixel 300 can include a gate and anode initialization period GAIP, a drain initialization period DIP, a threshold voltage compensation period CMPP, a data write period DWP, and an emission period EMP. In some exemplary embodiments, the drain initialization period DIP can partially overlap with the threshold voltage compensation period CMPP. For example, as Figure 14As shown, the drain initialization period DIP may have a time length corresponding to two horizontal times (or 2H time). The first 1H time of the drain initialization period DIP may overlap with the gate and anode initialization period GAIP, and the second 1H time of the drain initialization period DIP may overlap with the threshold voltage compensation period CMPP.

[0094] During the gate and anode initialization period GAIP, the gate of the first transistor T1 and the anode of the organic light emitting diode EL may be initialized. During the drain initialization period DIP, the second terminal or drain of the first transistor T1 may be initialized by the emission signal EM having a cut-off level OFF (e.g., a low level). Further, during the period OP in which the drain initialization period DIP and the threshold voltage compensation period CMPP overlap each other, the emission signal may have a cut-off level OFF, the second scan signal SCAN2 and the fourth scan signal SCAN4 may have a conductive level ON, and the first scan signal SCAN1 and the third scan signal SCAN3 may have a cut-off level OFF. In this case, as Figure 15 shown, the fourth transistor T4 and the fifth transistor T5 may be turned on in response to the second scan signal SCAN2 having a conductive level ON, and the eighth transistor T8 may be turned on in response to the fourth scan signal SCAN4 having a conductive level ON. The eighth transistor T8 may apply the emission signal EM having a cut-off level OFF (e.g., a low level) to the second terminal or drain of the first transistor T1, and thus the drain of the first transistor T1 may be initialized. Further, the emission signal EM having a cut-off level OFF may be applied to the first node N1 or the gate of the first transistor T1 through the eighth transistor T8 and the fifth transistor T5, and thus, the gate of the first transistor T1 may be initialized by the emission signal EM having a cut-off level OFF. Therefore, the gate of the first transistor T1 may be initialized by the initialization voltage VINIT during the gate and anode initialization period GAIP, and then may be further initialized by the emission signal EM having a cut-off level OFF during the period OP in which the drain initialization period DIP and the threshold voltage compensation period CMPP overlap each other. Further, since the anode of the organic light emitting diode EL is initialized by the initialization voltage VINIT, and the gate of the first transistor T1 is initialized not only by the initialization voltage VINIT but also by the emission signal EM having a cut-off level OFF, the voltages for initializing the anode of the organic light emitting diode EL and the gate of the first transistor T1 may be separated from each other.

[0095] Figure 16 is a block diagram showing an OLED display device according to an exemplary embodiment, Figure 17is a timing diagram showing examples of an emission signal, a first scan signal, a second scan signal, and a third scan signal in an OLED display device according to an exemplary embodiment, and Figure 18 is a timing diagram for describing an example of an operation of an OLED display device according to an exemplary embodiment.

[0096] Referring to Figure 16 , an OLED display device 400 according to an exemplary embodiment may include a display panel 410, a data driver 420, a scan driver 430, an emission driver 440, and a controller 450.

[0097] The display panel 410 may include a plurality of pixels PX. According to an exemplary embodiment, each pixel PX may be a pixel 100 having a seven-transistor and two-capacitor (7T-2C) structure shown in Figure 1 , a pixel 200 having a seven-transistor and two-capacitor (7T-2C) structure shown in Figure 9 , or a pixel 300 having an eight-transistor and two-capacitor (8T-2C) structure shown in Figure 11 , etc. As shown in Figure 1 , Figure 9 , or Figure 11 , the first transistor of the pixel PX may be implemented using a PMOS transistor, and one or more other transistors may be implemented using NMOS transistors. Thus, even if the driving frequency DF of the display panel 410 changes, the pixel PX may emit light at a substantially constant luminance at the same gray level.

[0098] The data driver 420 may provide a data voltage VDAT to the plurality of pixels PX based on a data control signal DCTRL and output image data ODAT received from the controller 450. In some exemplary embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a horizontal start signal, and a load signal. The data driver 420 may receive frame data as the output image data ODAT at the driving frequency DF of the display panel 410. In some exemplary embodiments, the data driver 420 and the controller 450 may be implemented using a signal integrated circuit, and the signal integrated circuit may be referred to as a timing controller embedded data driver (TED). In other exemplary embodiments, the data driver 420 and the controller 450 may be implemented using separate integrated circuits.

[0099] The scan driver 430 may provide the first scan signal SCAN1, the second scan signal SCAN2, and the third scan signal SCAN3 to the plurality of pixels PX based on a scan control signal SCTRL received from the controller 450. In some example embodiments, the scan control signal SCTRL may include, but is not limited to, a scan start signal and a scan clock signal. In some example embodiments, the first scan signal SCAN1, the second scan signal SCAN2, and the third scan signal SCAN3 may be provided to the plurality of pixels PX in a row-by-row sequential order. For example, the display panel 410 may include N rows of pixels PX, and as Figure 17 shown, the scan driver 430 may output the first scan signal SCAN1_1, the second scan signal SCAN2_1, and the third scan signal SCAN3_1 for the first row of pixels PX, and may output the first scan signal SCAN1_2, the second scan signal SCAN2_2, and the third scan signal SCAN3_2 for the second row of pixels PX that are shifted by one horizontal time (1H time) compared to the first scan signal SCAN1_1, the second scan signal SCAN2_1, and the third scan signal SCAN3_1 for the first row of pixels PX. In this way, the scan driver 430 may shift the first scan signal SCAN1, the second scan signal SCAN2, and the third scan signal SCAN3 by one horizontal time (1H time) to output the shifted first scan signal SCAN1, the second scan signal SCAN2, and the third scan signal SCAN3 in a row-by-row sequential order until the first scan signal SCAN1_N, the second scan signal SCAN2_N, and the third scan signal SCAN3_N for the last row of pixels PX are output. Although Figure 17 illustrates an example corresponding to the signals EM, SCAN1, SCAN2, and SCAN3 shown in Figure 2 , the operation of the scan driver 430 is not limited to the Figure 17 example. For example, the scan driver 430 may operate according to the Figure 7 , Figure 8 , Figure 10 , Figure 12 or Figure 14 shown in. In some example embodiments, in the case where each pixel PX is the Figure 11 pixel 300, the scan driver 430 may further provide a fourth scan signal SCAN4 to the plurality of pixels PX. In some example embodiments, the scan driver 430 may be integrated or formed in the peripheral portion of the display panel 410. In other example embodiments, the scan driver 430 may be implemented using one or more integrated circuits.

[0100] The emission driver 440 may supply an emission signal EM to a plurality of pixels PX based on an emission control signal EMCTRL received from the controller 450. In some example embodiments, the emission control signal EMCTRL may include, but is not limited to, an emission start signal and an emission clock signal. In some example embodiments, the emission driver 440 may supply the emission signal EM to the plurality of pixels PX in a row-by-row sequential manner. For example, the display panel 410 may include N rows of pixels PX, and as Figure 17 shown, the emission driver 440 may output an emission signal EM_1 for the first row of pixels PX, and may output an emission signal EM_2 for the second row of pixels PX that is shifted by one horizontal time (1H time) compared to the emission signal EM_1 for the first row of pixels PX. In this way, the emission driver 440 may shift the emission signal EM by one horizontal time (1H time) to output the shifted emission signal EM in a row-by-row sequential manner until the emission signal EM_N for the last row of pixels PX is output. Although Figure 17 illustrates an example corresponding to the signals EM, SCAN1, SCAN2, and SCAN3 shown in Figure 2 , the operation of the emission driver 440 is not limited to the Figure 17 example. For example, the emission driver 440 may operate according to the Figure 7 , Figure 8 , Figure 10 , Figure 12 or Figure 14 example shown. In some example embodiments, the emission driver 440 may be integrated or formed in the peripheral portion of the display panel 410. In other example embodiments, the emission driver 440 may be implemented using one or more integrated circuits.

[0101] The controller 450 (e.g., a timing controller (TCON)) can receive input image data IDAT and a control signal CTRL from an external host processor (e.g., an application processor (AP), a graphics processing unit (GPU), or a graphics card). In some example embodiments, the control signal CTRL can include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a main clock signal, etc. The controller 450 can generate output image data ODAT, a data control signal DCTRL, a scan control signal SCTRL, and a transmit control signal EMCTRL based on the input image data IDAT and the control signal CTRL. The controller 450 can control the operation of the data driver 420 by providing the output image data ODAT and the data control signal DCTRL to the data driver 420, can control the operation of the scan driver 430 by providing the scan control signal SCTRL to the scan driver 430, and can control the operation of the transmit driver 440 by providing the transmit control signal EMCTRL to the transmit driver 440.

[0102] In some example embodiments, the controller 450 of the OLED display device 400 can change the driving frequency DF of the display panel 410 by analyzing the input image data IDAT. For example, the OLED display device 400 can drive the display panel 410 at a normal driving frequency (e.g., about 240 Hz) or the input frame frequency IFF of the input image data IDAT when the input image data IDAT represents a moving image, and can drive the display panel 410 at a low frequency lower than the normal driving frequency or the input frame frequency IFF when the input image data IDAT represents a still image. Thus, even if the controller 450 receives the input image data IDAT at a fixed input frame frequency IFF (e.g., about 240 Hz), the controller 450 can provide the output image data ODAT to the data driver 420 at a driving frequency DF within a wide driving frequency range (e.g., from about 10 Hz to about 240 Hz). For example, as Figure 18As shown, during the first frame period FP1 and the second frame period FP2 of the moving image represented by the input image data IDAT, the controller 450 can receive the frame data FDAT at an input frame frequency IFF of approximately 240 Hz, and can provide the frame data FDAT as the output image data ODAT to the data driver 420 at a driving frequency DF of approximately 240 Hz that is substantially the same as the input frame frequency IFF. Accordingly, the display panel 410 can be driven at a driving frequency DF of approximately 240 Hz. If a still image is detected, the controller 450 can determine the driving frequency DF of the display panel 410 to be a low frequency, such as approximately 80 Hz that is lower than the input frame frequency IFF of approximately 240 Hz. In the case where the input image data IDAT represents a still image, the controller 450 can provide the frame data FDAT to the data driver 420 during the third frame period FP3 and the sixth frame period FP6, and can refrain from providing the frame data FDAT to the data driver 420 during the fourth frame period FP4, the fifth frame period FP5, the seventh frame period FP7, and the eighth frame period FP8. Accordingly, during the third frame period FP3 to the eighth frame period FP8, the controller 450 can provide the frame data FDAT to the data driver 420 at a driving frequency DF of approximately 80 Hz that is one third of the input frame frequency IFF of approximately 240 Hz, and the data driver 420 can drive the display panel 410 at a driving frequency DF of approximately 80 Hz. Although Figure 18 an example of driving the display panel 410 at a driving frequency DF of approximately 240 Hz or a driving frequency DF of approximately 80 Hz is shown, in some example embodiments, the display panel 410 can be driven at a driving frequency DF within a wide driving frequency range (e.g., from approximately 10 Hz to approximately 240 Hz).

[0103] Further, although Figure 18 an example of the controller 450 receiving the input image data IDAT at a fixed input frame frequency IFF of approximately 240 Hz is shown, in other example embodiments, the controller 450 can receive the input image data IDAT at a variable input frame frequency IFF (e.g., from approximately 10 Hz to approximately 240 Hz). In this case, the controller 450 can drive the display panel 410 at a variable driving frequency DF corresponding to the variable input frame frequency IFF.

[0104] As described above, the driving frequency DF of the display panel 410 can be changed. However, in the OLED display device 400 according to the example embodiments, one or more transistors of each pixel PX of the display panel 410 can be implemented using NMOS transistors. Accordingly, even if the driving frequency DF of the display panel 410 is changed, each pixel PX can emit light at a substantially constant luminance at the same gray level.

[0105] Figure 19 is an electronic device including an OLED display device according to an exemplary embodiment.

[0106] Referring Figure 19 , the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and an OLED display device 1160. Although not shown in Figure 19 , the electronic device 1100 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0107] The processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor (AP), a microprocessor, a central processing unit (CPU), or the like. The processor 1110 may be coupled to other components via an address bus, a control bus, a data bus, and the like. Further, in some exemplary embodiments, the processor 1110 may be further coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0108] The memory device 1120 may store data for the operation of the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile dynamic random access memory (mobile DRAM) device, etc.).

[0109] The storage device 1130 may be a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1140 may be an input device such as a keyboard, a keypad, a mouse, and a touch screen, and an output device such as a printer and a speaker. The power supply 1150 may supply power for the operation of the electronic device 1100. The OLED display device 1160 may be coupled to other components via a bus or other communication link.

[0110] In the OLED display device 1160, each pixel may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, a second capacitor, and an organic light-emitting diode, and a part of the first to seventh transistors may be implemented using NMOS transistors. Therefore, even if the driving frequency of the display panel including the pixels changes, the pixels can emit light with a substantially constant brightness at the same gray level.

[0111] The present disclosure may be applied to any OLED display device 1160 and any electronic device 1100 including the OLED display device 1160. For example, the present disclosure may be applied to mobile phones, smart phones, wearable electronic devices, tablet computers, televisions (TVs), digital TVs, 3D TVs, personal computers (PCs), household appliances, notebook computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, and navigation devices, etc.

[0112] The foregoing is an illustration of example embodiments and should not be construed as a limitation thereof. Although some example embodiments have been described, those skilled in the art will readily understand that many modifications to the example embodiments are possible without substantially departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. Accordingly, it should be understood that the foregoing is an illustration of various example embodiments and should not be construed as limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A pixel of an organic light emitting diode display device, the pixel comprising: A first transistor, including a gate coupled to a first node, a first terminal coupled to a line of a first power supply voltage, and a second terminal; A second transistor, including a gate receiving a first scan signal, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to the first node; A third transistor, including a gate receiving the first scan signal, a first terminal coupled to the line of the initialization voltage, and a second terminal coupled to an anode of an organic light emitting diode; A fourth transistor, including a gate receiving a second scan signal, a first terminal coupled to a line of a reference voltage, and a second terminal coupled to a second node; A fifth transistor, including a gate receiving the second scan signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the first node; A sixth transistor, including a gate receiving a third scan signal, a first terminal coupled to a data line, and a second terminal coupled to the second node; A seventh transistor, including a gate receiving an emission signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the organic light emitting diode; A first capacitor, including a first electrode coupled to the line of the first power supply voltage and a second electrode coupled to the second node; A second capacitor, including a first electrode coupled to the second node and a second electrode coupled to the first node; And The organic light emitting diode, including the anode and a cathode coupled to a line of a second power supply voltage, Wherein, the first transistor and the seventh transistor are PMOS transistors, and Wherein, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are NMOS transistors.

2. The pixel according to claim 1, wherein The frame period of the pixel includes: A gate and anode initialization period, in which the gate of the first transistor and the anode of the organic light emitting diode are initialized; A threshold voltage compensation period, in which the threshold voltage of the first transistor is compensated; A data writing period, in which a data voltage of the data line is applied to the second node; and An emission period, in which the organic light emitting diode emits light.

3. The pixel according to claim 2, wherein, In the gate and anode initialization period, The emission signal has a cut-off level, the first scan signal has a conducting level, and the second scan signal and the third scan signal respectively have cut-off levels, The second transistor and the third transistor are turned on, The second transistor applies the initialization voltage to the first node, and The third transistor applies the initialization voltage to the anode of the organic light emitting diode.

4. The pixel according to claim 2, wherein, In the threshold voltage compensation period, The emission signal has a cut-off level, the second scan signal has a conducting level, and the first scan signal and the third scan signal respectively have cut-off levels, The fourth transistor and the fifth transistor are turned on, the fourth transistor applies the reference voltage to the second node, the fifth transistor diode - connects the first transistor, and a voltage obtained by subtracting the threshold voltage from the first power supply voltage is applied to the first node through the diode - connected first transistor.

5. The pixel according to claim 2, wherein During the data writing period, the emission signal has a cut - off level, the third scan signal has a conduction level, and the first scan signal and the second scan signal respectively have cut - off levels, the sixth transistor is turned on, and the sixth transistor applies the data voltage to the second node.

6. The pixel according to claim 2, wherein, During the emission period, the emission signal has a conduction level, and the first scan signal, the second scan signal, and the third scan signal respectively have cut - off levels, the seventh transistor is turned on, the first transistor generates a driving current based on the voltage of the first node, and the seventh transistor supplies the driving current to the organic light - emitting diode.

7. A pixel of an organic light - emitting diode display device, the pixel comprising: A first transistor, including a gate coupled to a first node, a first terminal coupled to a line of a first power supply voltage, and a second terminal; A second transistor, including a gate receiving a first scan signal, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to the first node; A third transistor, including a gate receiving the first scan signal, a first terminal coupled to the line of the initialization voltage, and a second terminal coupled to an anode of an organic light - emitting diode; A fourth transistor, including a gate receiving a second scan signal, a first terminal coupled to a line of a reference voltage, and a second terminal coupled to a second node; A fifth transistor, including a gate receiving the second scan signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the first node; A sixth transistor, including a gate receiving a third scan signal, a first terminal coupled to a data line, and a second terminal coupled to the second node; A seventh transistor, including a gate receiving an emission signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the organic light - emitting diode; An eighth transistor, including a gate receiving a fourth scan signal, a first terminal receiving the emission signal, and a second terminal coupled to the second terminal of the first transistor; A first capacitor, including a first electrode coupled to the line of the first power supply voltage and a second electrode coupled to the second node; A second capacitor, including a first electrode coupled to the second node and a second electrode coupled to the first node; and the organic light - emitting diode, including the anode and a cathode coupled to a line of a second power supply voltage, wherein the first transistor is a PMOS transistor, and wherein the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are NMOS transistors.

8. A pixel of an organic light emitting diode display device, the pixel comprising: A first transistor, comprising a gate coupled to a first node, a first terminal coupled to a line of a first power supply voltage, and a second terminal; A second transistor, comprising a gate receiving a first scan signal, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to the first node; A third transistor, comprising a gate receiving a fourth scan signal, a first terminal coupled to the line of the initialization voltage, and a second terminal coupled to an anode of an organic light emitting diode; A fourth transistor, comprising a gate receiving a second scan signal, a first terminal coupled to a line of a reference voltage, and a second terminal coupled to a second node; A fifth transistor, comprising a gate receiving the second scan signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the first node; A sixth transistor, comprising a gate receiving a third scan signal, a first terminal coupled to a data line, and a second terminal coupled to the second node; A seventh transistor, comprising a gate receiving an emission signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the organic light emitting diode; A first capacitor, comprising a first electrode coupled to the line of the first power supply voltage and a second electrode coupled to the second node; A second capacitor, comprising a first electrode coupled to the second node and a second electrode coupled to the first node; And The organic light emitting diode, comprising the anode and a cathode coupled to a line of a second power supply voltage, Wherein, the first transistor, the third transistor, and the seventh transistor are PMOS transistors, and Wherein, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are NMOS transistors.

9. An organic light emitting diode display device, comprising: A display panel, comprising a plurality of pixels; A data driver, configured to provide data voltages to the plurality of pixels; A scan driver, configured to provide a first scan signal, a second scan signal, and a third scan signal to the plurality of pixels; An emission driver, configured to provide an emission signal to the plurality of pixels; And A controller, configured to control the data driver, the scan driver, and the emission driver, Wherein, each of the plurality of pixels comprises: A first transistor, comprising a gate coupled to a first node, a first terminal coupled to a line of a first power supply voltage, and a second terminal; A second transistor, comprising a gate receiving the first scan signal, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to the first node; A third transistor, comprising a gate receiving the first scan signal, a first terminal coupled to the line of the initialization voltage, and a second terminal coupled to an anode of an organic light emitting diode; A fourth transistor, comprising a gate receiving the second scan signal, a first terminal coupled to a line of a reference voltage, and a second terminal coupled to a second node; A fifth transistor, including a gate receiving the second scan signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the first node; A sixth transistor, including a gate receiving the third scan signal, a first terminal coupled to the data line, and a second terminal coupled to the second node; A seventh transistor, including a gate receiving the emission signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the organic light emitting diode; A first capacitor, including a first electrode coupled to the line of the first power supply voltage and a second electrode coupled to the second node; A second capacitor, including a first electrode coupled to the second node and a second electrode coupled to the first node; and The organic light emitting diode, including the anode and a cathode coupled to the line of the second power supply voltage wherein the first transistor and the seventh transistor are PMOS transistors, and wherein the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are NMOS transistors.

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