Display device

Abstract

The present invention relates to a display device. The display device includes: a pixel connected to a first scan line, a second scan line, and a third scan line, a data line, and an emission line, the pixel including: an LED; a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between the data line and the first node and including a gate electrode connected to the first scan line; a third transistor connected between the second node and the third node and including a gate electrode connected to the second scan line; a fourth transistor connected between the second node and a power supply and including a gate electrode connected to the third scan line; and a fifth transistor connected between the second node and an anode of the LED and including a gate electrode connected to the second scan line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0052784 filed on April 29, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a display device, and more particularly, to a pixel capable of displaying an image with desired brightness and an organic light emitting display device having the pixel. Background Art

[0004] With the development of information technology, display devices, which serve as a connection medium between users and information, play an important role. Accordingly, the use of high-quality display devices such as liquid crystal display devices and organic light emitting display devices has increased.

[0005] Among display devices, organic light-emitting display devices use organic light-emitting diodes (OLEDs) that generate light through the recombination of electrons and holes to display images. For example, an OLED includes an emissive electroluminescent layer of an organic compound that emits light in response to an electric current. Organic light-emitting display devices have a fast response speed and can be driven with low power.

[0006] An organic light-emitting display device includes pixels connected to data lines and scan lines, also known as gate lines. Each pixel may include a single organic light-emitting diode (OLED) and a drive transistor for controlling the amount of current flowing through the OLED. When current is supplied from the drive transistor to the OLED in response to a data signal, the pixel generates light with a predetermined brightness.

[0007] The pixel may further include multiple transistors and multiple capacitors to compensate for variations in the threshold voltage of the driving transistor. However, as more transistors are included in a single pixel, the application of the pixel to high-resolution panels is limited. Summary of the Invention

[0008] According to an exemplary embodiment of the present invention, a display device is provided, comprising: pixels connected to a first scan line, a second scan line, a third scan line, a data line, and an emission control line, wherein the pixels include: a light-emitting diode; a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node, wherein the first node is electrically connected to a first power source; a second transistor connected between the data line and the first node and including a gate electrode connected to the first scan line; a third transistor connected between the second node and the third node and including a gate electrode connected to the second scan line; a fourth transistor connected between the second node and the third power source and including a gate electrode connected to the third scan line; and a fifth transistor connected between the second node and an anode of the light-emitting diode and including a gate electrode connected to the second scan line, wherein a conduction period of the third transistor does not overlap with a conduction period of the fifth transistor.

[0009] The pixel may further include a sixth transistor connected between the first node and the first power source and including a gate electrode connected to the emission control line.

[0010] When the fourth transistor is turned on, the third transistor may be turned on, and when the third transistor is turned off, the fifth transistor may be turned on.

[0011] The first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor may be P-type low temperature polysilicon (LTPS) thin film transistors, and the third transistor may be an N-type oxide semiconductor thin film transistor.

[0012] The pixel may further include a storage capacitor connected between the first power source and the third node.

[0013] The cathode of the light emitting diode may be electrically connected to a second power source.

[0014] The voltage of the first power supply may be higher than the voltage of the second power supply.

[0015] The display device may further include a data driver for supplying a data signal corresponding to a grayscale of an image to the data line.

[0016] The voltage of the third power source may be lower than the voltage of the data signal.

[0017] The display device may further include a scan driver for supplying first, second, and third scan signals to the first, second, and third scan lines, respectively, during a frame period including the non-emission period and the emission period.

[0018] The non-emission period may include a first period in which the anode of the light emitting diode is initialized, a second period in which the gate electrode of the first transistor is initialized, and a third period in which a data signal supplied from the data line to the gate electrode of the first transistor is stored, and the emission period may include a fourth period in which the light emitting diode emits light.

[0019] The display device may further include an emission driver for supplying an emission control signal to the emission control line, wherein the emission control signal of a logic high level is supplied during a non-emission period and the emission control signal of a logic low level is supplied during an emission period.

[0020] During the first period, the second scan signal may have a logic low level, and the third scan signal may have a logic low level.

[0021] During the second period, the second scan signal may have a logic high level, and the third scan signal may have a logic low level.

[0022] During the third period, the first scan signal may have a logic low level, and the second scan signal may have a logic high level.

[0023] During the non-emission period, the first scan signal and the third scan signal may be alternately supplied, and the second scan signal and the third scan signal may be supplied to overlap in some periods.

[0024] The display device may further include a scan driver for supplying two or more first scan pulses, one second scan pulse, and two or more third scan pulses to the first scan line, the second scan line, and the third scan line, respectively, during a frame period including a non-emission period and an emission period.

[0025] The display device may further include an emission driver for supplying an emission control pulse having a turn-off level to the emission control line during the non-emission period.

[0026] During the non-emission period, the first scan pulse and the third scan pulse may be alternately supplied, and a first scan pulse of the two or more third scan pulses may partially overlap with the second scan pulse.

[0027] In the emission period, when a last scan pulse of two or more first scan pulses is supplied, the light emitting diode may emit light at a gray level corresponding to the voltage of the third node.

[0028] According to an exemplary embodiment of the present invention, a display device is provided, comprising: a pixel, wherein the pixel includes: a light emitting diode; a third transistor connected between a second node and a third node; a fourth transistor connected between the second node and a third power supply; and a fifth transistor connected between the second node and an anode of the light emitting diode.

[0029] The type of the third transistor may be different from the type of the fifth transistor.

[0030] A turn-on period of the third transistor may not overlap with a turn-on period of the fifth transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other features of the present invention will become more apparent by describing in detail exemplary embodiments of the present invention with reference to the attached drawings.

[0032] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

[0033] Figure 2 is a diagram showing an exemplary embodiment according to the present invention, Figure 1 Circuit diagram of a pixel included in the display device shown in .

[0034] Figure 3 According to an exemplary embodiment of the present invention, a driver Figure 1 The timing diagram of the display device shown in .

[0035] Figure 4 、 Figure 5 、 Figure 6 and Figure 7 The present invention is an exemplary embodiment of the present invention. Figure 2 The pixels shown in Figure 3 The diagram shows the operation process of the timing diagram of the display device.

[0036] Figure 8 According to an exemplary embodiment of the present invention, a driver Figure 1 The timing diagram of the display device shown in . DETAILED DESCRIPTION

[0037] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Throughout the specification, the same reference numerals may be used to refer to the same components, and thus, repeated description of the same components may be omitted.

[0038] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

[0039] refer to Figure 1, the display device 1000 may include a pixel unit 100 , a scan driver 200 , an emission driver 300 , a data driver 400 , and a timing controller 500 .

[0040] In an exemplary embodiment of the present invention, the display device 1000 may further include a power supply unit that supplies voltages of a first power source ELVDD, a second power source ELVSS, and a third power source VINT to the pixel unit 100. However, this is an example, and at least one of the voltages of the first power source ELVDD, the second power source ELVSS, and the third power source VINT may be provided from the timing controller 500 or the data driver 400. For example, the voltage of the first power source ELVDD may be supplied from the timing controller 500, and the voltage of the second power source ELVSS may be supplied from the data driver 400.

[0041] The pixel unit 100 may include a plurality of first scan lines SL11 to SL1n, a plurality of second scan lines SL21 to SL2n, a plurality of third scan lines SL31 to SL3n, a plurality of emission control lines EL1 to ELn, and a plurality of data lines DL1 to DLm. Furthermore, the pixel unit 100 may include a plurality of pixels PX connected to the first scan lines SL11 to SL1n, the second scan lines SL21 to SL2n, the third scan lines SL31 to SL3n, the emission control lines EL1 to ELn, and the data lines DL1 to DLm, respectively, where n and m are integers greater than 1. For example, a first pixel among the pixels PX may be connected to the first scan line SL11, the second scan line SL21, the third scan line SL31, the data line DL1, and the emission control line EL1. Each of the pixels PX may include a driving transistor and a plurality of switching transistors.

[0042] The scan driver 200 may sequentially supply scan signals to the pixels PX through the first, second, and third scan lines SL11 to SL1n, SL21 to SL2n, and SL31 to SL3n based on the first control signal SCS. The scan driver 200 may receive the first control signal SCS and at least one clock signal from the timing controller 500.

[0043] In an exemplary embodiment of the present invention, a scan signal supplied to one scan line during one frame period may include at least one scan pulse. For example, the scan signal may include a first scan signal sequentially supplied to the first scan lines SL11 to SL1n, a second scan signal sequentially supplied to the second scan lines SL21 to SL2n, and a third scan signal sequentially supplied to the third scan lines SL31 to SL3n.

[0044] The first scan signal may include at least one first scan pulse, the second scan signal may include at least one second scan pulse, and the third scan signal may include at least one third scan pulse.

[0045] Here, the first scan pulse, the second scan pulse, and the third scan pulse may be gate-on voltages for turning on the transistor included in the pixel PX. For example, when the transistor included in the pixel PX is a P-channel metal oxide semiconductor (PMOS) transistor, the gate-on voltage may be set to a logic low level, while the gate-off voltage may be set to a logic high level. When the transistor included in the pixel PX is an N-channel metal oxide semiconductor (NMOS) transistor, the gate-on voltage may be set to a logic high level, while the gate-off voltage may be set to a logic low level.

[0046] In an exemplary embodiment of the present invention, the scan driver 200 may include a first stage connected to each other to sequentially output a first scan signal (e.g., a first scan pulse) to the first scan lines SL11 to SL1n, a second stage connected to each other to sequentially output a second scan signal (e.g., a second scan pulse) to the second scan lines SL21 to SL2n, and a third stage connected to each other to sequentially output a third scan signal (e.g., a third scan pulse) to the third scan lines SL31 to SL3n.

[0047] The emission driver 300 may sequentially supply emission control signals to the pixels PX via the emission control lines EL1 to ELn based on the second control signal ECS. The emission driver 300 may receive the second control signal ECS and a clock signal, etc., from the timing controller 500. The emission control signal may divide a frame period into an emission period and a non-emission period for pixels PX located on the same horizontal line (e.g., the same row). For example, in response to the emission control signal, a frame period may begin as a non-emission frame period and then switch to an emission frame period.

[0048] The data driver 400 may receive a third control signal DCS and an image data signal RGB from the timing controller 500. The data driver 400 may supply data signals (or data voltages) to the pixels PX via the data lines DL1 to DLm based on the third control signal DCS and the image data signal RGB. In an exemplary embodiment of the present invention, the data driver 400 may supply data signals corresponding to the grayscale of the image to the data lines DL1 to DLm. For example, the data signal of the corresponding pixel PX may be supplied to the corresponding pixel PX in synchronization with each of the first scan signals (e.g., the first scan pulses).

[0049] The timing controller 500 can control the driving of the scan driver 200, the emission driver 300, and the data driver 400 based on a timing signal supplied from the outside. The timing controller 500 can supply a control signal including a first control signal SCS and a scan clock signal to the scan driver 200, and can supply a control signal including a second control signal ECS and an emission control clock signal to the emission driver 300. The third control signal DCS for controlling the data driver 400 can include a source start signal, a source output enable signal, a source sampling clock, and the like.

[0050] Figure 2 is a diagram showing an exemplary embodiment according to the present invention, Figure 1 Circuit diagram of a pixel included in the display device shown in .

[0051] refer to Figure 1 and Figure 2 , the pixel PX may include a light emitting diode LD and a pixel circuit PC connected to the light emitting diode LD.

[0052] Figure 2 The pixel PX shown in may be a pixel arranged in the k-th row and the p-th column of the pixel unit 100 , where k and p are natural numbers.

[0053] The anode of the light emitting diode LD may be connected to the pixel circuit PC, and the cathode of the light emitting diode LD may be connected to the second power supply ELVSS. In other words, the first electrode of the light emitting diode LD may be connected to the pixel circuit PC, and the second electrode of the light emitting diode LD may be connected to the second power supply ELVSS. The light emitting diode LD may generate light having a predetermined brightness corresponding to the amount of current supplied from the pixel circuit PC.

[0054] The pixel circuit PC can control the amount of current flowing from the first power source ELVDD to the second power source ELVSS via the light emitting diode LD in response to the data signal Vdata. To this end, the first power source ELVDD can be set to a voltage higher than the second power source ELVSS.

[0055] The pixel circuit PC may include a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , and a sixth transistor T6 , and a storage capacitor Cst.

[0056] The first transistor T1 may be coupled between a first node N1 electrically connected to a first power source ELVDD via a sixth transistor T6 and a second node N2 electrically connected to an anode of a light emitting diode LD via a fifth transistor T5. For example, a first electrode of the first transistor T1 may be connected to the first node N1, and a second electrode of the first transistor T1 may be connected to the second node N2. A gate electrode of the first transistor T1 may be coupled to a third node N3. The first transistor T1 may supply a driving current corresponding to a voltage at the third node N3 to the light emitting diode LD. The first transistor T1 may function as a driving transistor for the pixel PX.

[0057] The second transistor T2 may be coupled between the p-th data line DLp and the first node N1. For example, a first electrode of the second transistor T2 may be connected to the p-th data line DLp, and a second electrode of the second transistor T2 may be connected to the first node N1. The second transistor T2 may include a gate electrode for receiving a first scan signal GWP[k]. The first scan signal GWP[k] may be provided from the k-th first scan line SL1k to the gate electrode of the second transistor T2. When the second transistor T2 is turned on, the data signal Vdata may be transmitted to the first node N1.

[0058] The third transistor T3 may be coupled between the second node N2 and the third node N3. For example, a first electrode of the third transistor T3 may be connected to the second node N2, and a second electrode of the third transistor T3 may be connected to the third node N3. The third transistor T3 may include a gate electrode for receiving a second scan signal GWN[k]. The second scan signal GWN[k] may be provided from the k-th second scan line SL2k to the gate electrode of the third transistor T3. The third transistor T3 may be turned on by the second scan signal GWN[k] to electrically connect the electrode of the first transistor T1 (e.g., the second node N2) and the third node N3. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be connected in a diode form.

[0059] The storage capacitor Cst may be connected between the first power source ELVDD and the third node N3. The storage capacitor Cst may store a voltage corresponding to a difference between the data signal Vdata and the threshold voltage of the first transistor T1.

[0060] The fourth transistor T4 may be coupled between the second node N2 and the third power supply VINT. For example, a first electrode of the fourth transistor T4 may be connected to the second node N2, and a second electrode of the fourth transistor T4 may be connected to the third power supply VINT. The fourth transistor T4 may include a gate electrode for receiving a third scan signal GI[k]. The third scan signal GI[k] may be provided via the k-th third scan line SL3k. Figure 3, the third scan signal GI[k] may correspond to the first scan signal of the previous pixel row. When the third scan signal GI[k] is supplied to supply the voltage of the third power supply VINT to the second node N2, the fourth transistor T4 may be turned on.

[0061] The second scan signal GWN[k] may be set to a logic low level during a portion of the time when the third scan signal GI[k] is supplied, and may be set to a logic high level during the remaining time when the third scan signal GI[k] is supplied.

[0062] During a period when the second scan signal GWN[k] is set to a logic low level, the fifth transistor T5 may be turned on to initialize the anode of the light emitting diode LD. During a period when the second scan signal GWN[k] is set to a logic high level, the third transistor T3 may be turned on to initialize the third node N3. Thus, the voltages of the anode of the light emitting diode LD and the third node N3 (in other words, the gate voltage of the first transistor T1) may be initialized to the voltage of the third power supply VINT. In an exemplary embodiment of the present invention, the third power supply VINT may be set to a voltage lower than the lowest voltage of the data signal Vdata.

[0063] The fifth transistor T5 may be coupled between the second node N2 and the anode of the light-emitting diode LD. For example, a first electrode of the fifth transistor T5 may be connected to the second node N2, and a second electrode of the fifth transistor T5 may be connected to the anode of the light-emitting diode LD. The fifth transistor T5 may include a gate electrode for receiving a second scan signal GWN[k]. When the second scan signal GWN[k] is set to a logic low level to electrically connect the second node N2 and the anode of the light-emitting diode LD, the fifth transistor T5 may be turned on.

[0064] The sixth transistor T6 may be coupled between the first power supply ELVDD and the first node N1. For example, a first electrode of the sixth transistor T6 may be connected to the first power supply ELVDD, and a second electrode of the sixth transistor T6 may be connected to the first node N1. The sixth transistor T6 may include a gate electrode for receiving an emission control signal EM[k]. The emission control signal EM[k] may be provided via the kth emission control line ELk. When the emission control signal EM[k] is at a logic low level, the sixth transistor T6 may be turned on, and when the emission control signal EM[k] is at a logic high level, the sixth transistor T6 may be turned off.

[0065] The light-emitting diode LD may be coupled between the fifth transistor T5 and the second power supply ELVSS. The cathode of the light-emitting diode LD may be supplied with the second power supply ELVSS. The first power supply ELVDD and the second power supply ELVSS may have different potentials. For example, the first power supply ELVDD may be a high potential power supply, and the second power supply ELVSS may be a low potential power supply. In this case, during the emission period of the pixel PX, the potential difference between the first power supply ELVDD and the second power supply ELVSS may be equal to or higher than the threshold voltage of the light-emitting diode LD. In an exemplary embodiment of the present invention, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be P-type low-temperature polysilicon (LTPS) thin-film transistors, and the third transistor T3 may be an N-type oxide semiconductor thin-film transistor. N-type oxide semiconductor thin-film transistors may have better current leakage characteristics than P-type LTPS thin-film transistors. Therefore, when the third transistor T3 connected to the third node N3 is formed of an N-type oxide semiconductor thin-film transistor, the leakage current flowing from the third node N3 to the second node N2 may be significantly reduced, thereby reducing power consumption.

[0066] Typically, in order to initialize the gate electrode (or third node N3) of the first transistor T1 to the third power supply VINT, an initialization transistor directly connected to the third node N3 may be further provided. However, when the initialization transistor is additionally provided, leakage current may be additionally generated by the current path from the third node N3 to the third power supply VINT.

[0067] In addition, the initialization transistor may be formed of an N-type oxide semiconductor thin film transistor to minimize leakage current. However, in this case, since an additional transistor is employed, the area of ​​the pixel increases.

[0068] In contrast, according to an exemplary embodiment of the present invention, the third node N3 and the anode of the light emitting diode LD can be initialized using the fourth transistor T4 connected to the second node N2. Figure 2 According to the embodiment of the present invention shown in FIG, the initialization transistor connected to the third node N3 can be removed, and thus, the area of ​​the pixel PX is reduced, and the pixel PX can be applied to a high-resolution panel.

[0069] In addition, the fourth transistor T4 may be indirectly connected to the gate electrode (or third node N3) of the first transistor T1 via the third transistor T3. Therefore, the fourth transistor T4 may not need to be formed of an N-type oxide semiconductor thin film transistor to prevent leakage current.

[0070] Typically, N-type oxide semiconductor thin film transistors occupy more space in a pixel circuit than P-type LTPS thin film transistors. Thus, when the number of oxide semiconductor thin film transistors formed in a unit pixel circuit is reduced, the size of the unit pixel circuit can be reduced. Consequently, a high-resolution (or more highly integrated pixel circuit) display device 1000 can be realized.

[0071] According to an exemplary embodiment of the present invention, a display device 1000 may include a pixel PX connected to a first scan line, a second scan line, a third scan line, a data line, and an emission control line. The pixel PX may include: a light emitting diode LD; a first transistor T1 including a first electrode connected to a first node N1, a second electrode connected to a second node N2, and a gate electrode connected to a third node N3, wherein the first node N1 is electrically connected to a first power source ELVDD; a second transistor T2 connected between the data line and the first node N1 and including a gate electrode connected to the first scan line; a third transistor T3 connected between the second node N2 and the third node N3 and including a gate electrode connected to the second scan line; a fourth transistor T4 connected between the second node N2 and the third power source VINT and including a gate electrode connected to the third scan line; and a fifth transistor T5 connected between the second node N2 and the anode of the light emitting diode LD and including a gate electrode connected to the second scan line.

[0072] In the following, the following will be described in detail including Figure 2 1 and 2. A driving method of the pixel PX of the display device 1000 shown in FIG.

[0073] Figure 3 According to an exemplary embodiment of the present invention, a driver Figure 1 The timing diagram of the display device shown in .

[0074] refer to Figures 1 to 3 , one frame period of the display device 1000 may include an emission period EP and a non-emission period NEP.

[0075] The non-emission period NEP may be divided into a first period P1, a second period P2, and a third period P3 for driving, and the emission period EP may include a fourth period P4.

[0076] Figure 3 An example of signals supplied to the pixels PX included in the k-th row of the pixel unit 100 is shown.

[0077] exist Figure 3 , the lengths of the emission period EP and the non-emission period NEP included in one frame period are shown similarly to each other. However, it should be understood that the length of the emission period EP is substantially longer than that of the non-emission period NEP.

[0078] In the first period P1, the anode of the light emitting diode LD may be initialized to the third power supply VINT. In the second period P2, the gate electrode (or third node N3) of the first transistor T1 may be initialized to the third power supply VINT. In the third period P3, a voltage corresponding to the difference between the data signal Vdata and the threshold voltage of the first transistor T1 may be stored in the storage capacitor Cst. In the fourth period P4, a predetermined current may be supplied from the first transistor T1 to the light emitting diode LD in response to the voltage of the third node N3. In this case, the light emitting diode LD may generate light having a predetermined brightness corresponding to the amount of current supplied from the first transistor T1.

[0079] Figures 4 to 7 According to an exemplary embodiment of the present invention, Figure 2 The pixels shown in Figure 3 The diagram shows the operation process of the timing diagram of the display device.

[0080] refer to Figures 1 to 7 Since the first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 are P-type LTPS transistors, the gate-on voltages of the first scan signal GWP[k] and the third scan signal GI[k] may be at a logic low level. Similarly, the gate-on voltage of the emission control signal EM[k] may be at a logic low level.

[0081] Since the third transistor T3 is an N-type oxide semiconductor thin film transistor, the gate-on voltage of the second scan signal GWN[k] may be a logic high level. However, since the fifth transistor T5 is a P-type LTPS transistor, in this case, the gate-on voltage of the second scan signal GWN[k] may be a logic low level.

[0082] refer to Figure 4 During the non-emission period NEP, a logic high-level emission control signal EM[k] may be supplied to the k-th emission control line ELk. When the logic high-level emission control signal EM[k] is supplied to the k-th emission control line ELk, the sixth transistor T6 may be turned off. When the sixth transistor T6 is turned off, current does not flow from the first power supply ELVDD to the first transistor T1. Thus, the light emitting diode LD may maintain a non-light emitting state.

[0083] In the first period P1, the third scan signal GI[k] of a logic low level may be supplied to the kth third scan line SL3k. Also, in the first period P1, the first scan signal GWP[k] of a logic high level may be supplied to the kth first scan line SL1k, and the second scan signal GWN[k] of a logic low level may be supplied to the kth second scan line SL2k.

[0084] When the third scan signal GI[k] of a logic low level is supplied to the kth third scan line SL3k, the fourth transistor T4 may be turned on. When the fourth transistor T4 is turned on, the third power source VINT may be supplied to the second node N2. The application of the third power source VINT is performed by Figure 4 Indicated by the arrows in .

[0085] For example, since the fifth transistor T5 is set to a turned-on state by the second scan signal GWN[k] of a logic low level, the third power VINT supplied to the second node N2 may be supplied to the anode of the light emitting diode LD via the fifth transistor T5 .

[0086] When the second scan signal GWN[k] of a logic low level is supplied to the kth second scan line SL2k, the third transistor T3 is turned off, thereby disconnecting the third power source VINT supplied to the second node N2 from the third node N3.

[0087] refer to Figure 5 , in the second period P2, the third scan signal GI[k] supplied to the k-th third scan line SL3k may be maintained. In other words, the third scan signal GI[k] may be maintained at a low level. In addition, in the second period P2, the second scan signal GWN[k] of a logic high level may be supplied to the k-th second scan line SL2k. In other words, in the second period P2, the second scan signal GWN[k] may transition from a low level to a high level.

[0088] When the third scan signal GI[k] supplied to the k-th third scan line SL3k is maintained at a low level, the fourth transistor T4 can remain in the on state. When the fourth transistor T4 remains in the on state, the third power source VINT can still be supplied to the second node N2. Figure 5 Indicated by the arrows in .

[0089] When the second scan signal GWN[k] of a logic high level is supplied to the k-th second scan line SL2k, the third transistor T3 may be turned on and the fifth transistor T5 may be turned off. When the fifth transistor T5 is turned off, the electrical connection between the third power supply VINT supplied to the second node N2 and the anode of the light emitting diode LD may be cut off. However, since the third transistor T3 is turned on, the third power supply VINT supplied to the second node N2 and the gate electrode of the first transistor T1 may be electrically connected. Thus, in the second period P2, the gate electrode of the first transistor T1 (or the third node N3) may be initialized to the third power supply VINT.

[0090] After the second period P2 , the third scan signal GI[k] may change to a logic high level, and thus, the fourth transistor T4 may be turned off.

[0091] In an exemplary embodiment of the present invention, the period during which the fourth transistor T4 is turned on can be divided into a first period P1 and a second period P2, and the anode of the light emitting diode LD can be initialized during the first period P1 and the third node N3 can be initialized during the second period P2. In other words, in the first period P1, the anode of the light emitting diode LD is provided with a voltage of the third power supply VINT through the fourth transistor T4 and the fifth transistor T5, and in the second period P2, the third node N3 is provided with a voltage of the third power supply VINT through the third transistor T3 and the fourth transistor T4. In this case, the anode of the light emitting diode LD and the third node N3 can be initialized by one fourth transistor T4. Therefore, the number of transistors included in the unit pixel circuit can be reduced. When the number of transistors formed in the unit pixel circuit is reduced, the size of the unit pixel circuit can be reduced. Therefore, a high-resolution (or highly integrated pixel circuit) display device 1000 can be implemented.

[0092] refer to Figure 6 In the third period P3, the first scan signal GWP[k] may be supplied to the kth first scan line SL1k. For example, the low-level first scan signal GWP[k] is supplied to the kth first scan line SL1k. At this time, the second scan signal GWN[k] may maintain a logic high level.

[0093] In this case, when the first scan signal GWP[k] of a logic low level is supplied to the kth first scan line SL1k, the second transistor T2 may be turned on. When the second scan signal GWN[k] supplied to the kth second scan line SL2k maintains a logic high level, the third transistor T3 may remain in a turned-on state and the fifth transistor T5 may remain in a turned-off state. When the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode. Thus, in the third period P3, a voltage corresponding to the difference between the data signal Vdata and the threshold voltage of the first transistor T1 may be stored in the storage capacitor Cst. This is caused by Figure 6 Indicated by the arrows in .

[0094] After the third period P3, the first scan signal GWP[k] may be changed to a logic high level, and thus the second transistor T2 may be turned off. In addition, the second scan signal GWN[k] may be changed to a logic low level, and thus the third transistor T3 may be turned off and the fifth transistor T5 may be turned on.

[0095] refer to Figure 7In the fourth period P4, the emission control signal EM[k] of a logic low level may be supplied to the kth emission control line ELk. When the emission control signal EM[k] of a logic low level is supplied to the kth emission control line ELk, the sixth transistor T6 may be turned on. When the sixth transistor T6 is turned on, the first power source ELVDD and the first electrode of the first transistor T1 may be electrically connected.

[0096] In this case, when the second scan signal GWN[k] of the logic low level supplied to the k-th second scan line SL2k is maintained, the third transistor T3 may be maintained in the off state and the fifth transistor T5 may be maintained in the on state. Thus, in the fourth period P4, in response to the voltage of the third node N3, a predetermined current may be supplied from the first transistor T1 to the light emitting diode LD. This is caused by Figure 7 In this case, the light emitting diode LD may generate light having a predetermined brightness corresponding to the amount of current supplied from the first transistor T1.

[0097] Hereinafter, other exemplary embodiments of the present invention will be described. The following embodiments will be mainly described with respect to differences from the above-described embodiments.

[0098] Figure 8 According to an exemplary embodiment of the present invention, a driver Figure 1 The timing diagram of the display device shown in .

[0099] refer to Figure 1 、 Figure 2 and Figure 8 , one frame period of the display device 1000 may include an emission period EP' and a non-emission period NEP'.

[0100] The non-emission period NEP' may be divided into a first period P1, a second period P2, a 2-1st period P2', a 2-2nd period P2", a third period P3, a 3-1st period P3', and a 3-2nd period P3" for driving, and the emission period EP' may include a fourth period P4.

[0101] During the non-emission period NEP', a logic high-level emission control signal EM[k] may be supplied to the k-th emission control line ELk. When the logic high-level emission control signal EM[k] is supplied to the k-th emission control line ELk, the sixth transistor T6 may be turned off. When the sixth transistor T6 is turned off, current does not flow from the first power supply ELVDD to the first transistor T1. Thus, the light emitting diode LD may maintain a non-light emitting state.

[0102] During the non-emission period NEP', two or more scan pulses of the first scan signal GWP[k] (hereinafter, first scan pulses) may be supplied to the kth first scan line SL1k, and two or more scan pulses of the third scan signal GI[k] (hereinafter, third scan pulses) may be supplied to the kth third scan line SL3k.

[0103] exist Figure 8 , the lengths of the emission period EP' and the non-emission period NEP' included in one frame period are shown similarly to each other. However, it should be understood that the length of the emission period EP' is substantially longer than that of the non-emission period NEP'.

[0104] in addition, Figure 8 The length of the non-transmission period NEP' shown in Figure 3 The length of the non-emission period NEP shown in is the same as that in Figure 8 The length of the non-emission period NEP′ shown in FIG. 8 is not limited thereto and may be greater than Figure 3 The length of the non-emission period NEP shown in is long. Figure 8 The length of the transmission period EP' shown in Figure 3 The length of the emission period EP shown in is short.

[0105] According to an exemplary embodiment of the present invention, during the non-emission period NEP', three scan pulses of each of the first scan signal GWP[k] and the third scan signal GI[k] (in other words, three first scan pulses and three third scan pulses) may be supplied to the pixel PX. For example, the three first scan pulses and the three third scan pulses may be supplied alternately.

[0106] In addition, during the non-emission period NEP', one scan pulse of the second scan signal GWN[k] (hereinafter, one second scan pulse) may be supplied to the pixel PX. In this case, while the one second scan pulse is maintained, three first scan pulses may be supplied, and all third scan pulses except a portion of the first pulse among the three third scan pulses may be supplied.

[0107] In the first period P1, the first pulse of the three third scan pulses may be supplied at a logic low level to turn on the fourth transistor T4, and the second scan signal GWN[k] of a logic low level may be supplied to turn on the fifth transistor T5. Therefore, the anode of the light emitting diode LD may be initialized to the third power supply VINT.

[0108] In the second period P2, the second scan pulse may be supplied at a logic high level. Thereafter, the second scan pulse may be maintained during the non-emission period NEP'. When the second scan pulse of the logic high level is supplied, the third transistor T3 may be turned on to initialize the third node N3. Thereafter, during the 2-1 period P2' and the 2-2 period P2", the second pulse and the third pulse of the three third scan pulses may be supplied to turn on the fourth transistor T4. Thus, the third node N3 may be initialized multiple times. In other words, each time the third scan pulse is supplied to turn on the fourth transistor T4, the third node N3 is initialized.

[0109] During the third period P3 and the 3-1 period P3', the first pulse and the second pulse of the three first scan pulses may be supplied to turn on the second transistor T2. Then, the data signal Vdata corresponding to the previous horizontal line (previous row) may be supplied to the first node N1. In this case, the first transistor T1 may be initialized to the voltage of the first node N1 (in other words, the first transistor T1 is provided with a bias voltage).

[0110] During the 3-2 period P3″, the third pulse of the three first scan pulses may be supplied to turn on the second transistor T2. In this case, the data signal Vdata corresponding to the current pixel PX may be supplied to the first node N1. Then, a voltage of the data signal Vdata corresponding to the current pixel PX, which is lowered by the threshold voltage of the first transistor T1, may be stored in the storage capacitor Cst.

[0111] Typically, the driving transistor (or first transistor T1) included in the pixel PX may have a hysteresis characteristic in which the threshold voltage is shifted and the current is changed according to the change in the gate voltage of the driving transistor. Due to the hysteresis characteristic of the driving transistor (or first transistor T1), a current different from the current set in the pixel PX may flow according to the previous data signal Vdata of the corresponding pixel PX. As a result, the pixel PX does not generate light with the desired brightness in the current frame.

[0112] However, according to an exemplary embodiment of the present invention, when the first scan pulse and the third scan pulse are supplied multiple times, the gate voltage (and gate-source voltage) of the first transistor T1 can be repeatedly changed. Therefore, the change in the hysteresis of the first transistor T1 caused by the difference between the voltage of the data signal Vdata of the previous frame and the voltage of the data signal Vdata of the current frame can be reduced. Thus, the instantaneous afterimage that may occur when the brightness changes greatly can be eliminated or reduced.

[0113] In the fourth period P4, a control pulse of the emission control signal EM[k] of a logic low level (hereinafter, an emission control pulse) may be supplied to the kth emission control line ELk. When the emission control pulse of a logic low level is supplied to the kth emission control line ELk, the sixth transistor T6 may be turned on. When the sixth transistor T6 is turned on, the first power source ELVDD and the first electrode of the first transistor T1 may be electrically connected. Thus, the light emitting diode LD may generate light having a predetermined brightness corresponding to the amount of current supplied from the first transistor T1.

[0114] In a display device according to an exemplary embodiment of the present invention, a transistor located in a leakage path of current in a unit pixel circuit can be formed of an oxide semiconductor transistor. Therefore, leakage current can be minimized and an image with desired brightness can be displayed.

[0115] Furthermore, in the display device according to the exemplary embodiment of the present invention, the number of oxide semiconductor transistors used in a unit pixel circuit can be reduced, thereby realizing a high-resolution (or highly integrated pixel circuit) display device.

[0116] Although the present invention has been described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as set forth in the following claims.

Claims

1. A display device, comprising: pixels connected to the first scan line, the second scan line, the third scan line, the data line and the emission control line, The pixels include: light-emitting diodes; a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node, wherein the first node is electrically connected to a first power source; a second transistor connected between the data line and the first node and including a gate electrode connected to the first scan line; a third transistor connected between the second node and the third node and including a gate electrode connected to the second scan line; and a fourth transistor connected between the second node and a third power source and including a gate electrode connected to the third scan line, In which, in a frame period including a non-emission period and an emission period, the non-emission period includes a first period in which the anode of the light-emitting diode is initialized, a second period in which the gate electrode of the first transistor is initialized, and a third period in which the data signal supplied from the data line to the gate electrode of the first transistor is stored, and the emission period includes a fourth period in which the light-emitting diode emits light.

2. The display device according to claim 1, wherein The pixel further comprises: a fifth transistor connected between the second node and the anode of the light emitting diode; and A sixth transistor is connected between the first node and the first power source and includes a gate electrode connected to the emission control line.

3. The display device according to claim 2, wherein: During the second period, the third transistor is turned on and the fourth transistor is turned on, and during the fourth period, the fifth transistor is turned on and the third transistor is turned off.

4. The display device according to claim 2, wherein The first transistor, the second transistor, the fourth transistor, the fifth transistor and the sixth transistor are P-type low temperature polysilicon thin film transistors, and Wherein, the third transistor is an N-type oxide semiconductor thin film transistor.

5. The display device according to claim 1, wherein The pixel further comprises: A storage capacitor is connected between the first power source and the third node. The display device according to claim 1 , wherein: The cathode of the light emitting diode is electrically connected to a second power source.

7. The display device according to claim 6, wherein: The voltage of the first power supply is higher than the voltage of the second power supply.

8. The display device according to claim 1, further comprising: The data driver is configured to supply a data signal corresponding to a grayscale of an image to the data line.

9. The display device according to claim 8, wherein A voltage of the third power source is lower than a voltage of the data signal.

10. The display device according to claim 1, further comprising: A scan driver is configured to supply a first scan signal, a second scan signal, and a third scan signal to the first scan line, the second scan line, and the third scan line, respectively, during the frame period.

11. The display device according to claim 10, further comprising: an emission driver for supplying an emission control signal to the emission control line, The emission control signal of a logic high level is supplied during the non-emission period, and the emission control signal of a logic low level is supplied during the emission period.

12. The display device according to claim 10, wherein: During the first period, the second scan signal has a logic low level, and the third scan signal has the logic low level.

13. The display device according to claim 10, wherein: During the second period, the second scan signal has a logic high level, and the third scan signal has a logic low level.

14. The display device according to claim 10, wherein: During the third period, the first scan signal has a logic low level, and the second scan signal has a logic high level.

15. The display device according to claim 10, wherein During the non-emission period, the first scan signal and the third scan signal are alternately supplied, and the second scan signal and the third scan signal are supplied to overlap in some periods.

16. The display device according to claim 1, further comprising: A scan driver is configured to supply two or more first scan pulses, one second scan pulse, and two or more third scan pulses to the first scan line, the second scan line, and the third scan line, respectively, during the frame period.

17. The display device according to claim 16, further comprising: An emission driver is configured to supply an emission control pulse having an off level to the emission control line during the non-emission period.

18. The display device according to claim 16, wherein: During the non-emission period, the first scan pulse and the third scan pulse are alternately supplied, and a first scan pulse of the two or more third scan pulses partially overlaps with the second scan pulse.

19. The display device according to claim 16, wherein: In the emission period, when a last scan pulse of the two or more first scan pulses is supplied, the light emitting diode emits light at a grayscale corresponding to a voltage of the third node.

20. A display device comprising: Pixels, The pixels include: light-emitting diodes; a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node, wherein the first node is electrically connected to a first power source; a third transistor connected between the second node and a third node; a fourth transistor connected between the second node and a third power supply; and a fifth transistor connected between the second node and the anode of the light emitting diode, wherein the type of the third transistor is different from the type of the fifth transistor, and In which, in a frame period including a non-emission period and an emission period, the non-emission period includes a first period in which the anode of the light-emitting diode is initialized, a second period in which the gate electrode of the first transistor is initialized, and a third period in which a data signal supplied from the data line to the gate electrode of the first transistor is stored, and the emission period includes a fourth period in which the light-emitting diode emits light.

Images