Source Driver

Abstract

The present disclosure discloses a source driver capable of accurately sensing the characteristics of a display panel by minimizing the influence of a floating channel. The source driver may include: a normal channel connected to a pixel of the display panel; a floating channel in an unloaded state; and a sampling circuit configured to sample signals of the normal channel and the floating channel. The source driver may provide a first reference voltage to the floating channel in a first cycle of sensing the characteristics of a pixel.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, to a source driver capable of accurately sensing characteristics of a display panel by minimizing the influence of a floating channel. Background Art

[0002] Typically, a display device may include a display panel, a source driver, a timing controller, and the like.

[0003] The source driver converts the image data provided by the timing controller into a data voltage and provides the data voltage to the display panel. The source driver can be integrated into a chip. The number of source drivers configured in the display panel can be determined by considering the size and resolution of the display panel.

[0004] The horizontal resolution of the display panel may be defined as the product of the number of sub-pixels, the number of channels of the source driver, and the number of source drivers.

[0005] However, if the horizontal resolution of the display panel and the number of channels of the source driver are not a positive multiple, some of the plurality of source drivers may include floating channels in an idle state.

[0006] A source driver according to the conventional art is configured by setting the state of a floating channel to a disabled state to prevent an abnormal output in an idle state.

[0007] A sensing circuit for compensating pixel deviation is embedded in a source driver for an OLED panel. The sensing circuit is arranged in an array with respect to the channels of the source driver and is configured to receive a sensing signal through each channel. In this case, the sensing circuit can sense an unknown input through a floating channel of the source driver.

[0008] If the sensing circuit senses an unknown input, the following problems may occur.

[0009] Since the sensing of the floating channel operates through the unknown input of the floating channel, the sensing circuit may affect the data of the adjacent normal channel. In this case, there is a problem of mismatch between channels.

[0010] In addition, the source driver outputs an output code corresponding to the unknown input through the floating channel to the timing controller. Therefore, the timing controller has a problem in that it requires a separate calculation process for distinguishing output codes of a normal channel and a floating channel at the time of data processing. Summary of the invention

[0011] Various embodiments are directed to providing a source driver capable of accurately sensing characteristics of a display panel by minimizing the influence of a floating channel.

[0012] In an embodiment, the source driver may include: a normal channel connected to a pixel of the display panel; a floating channel in an unloaded state; and a sampling circuit configured to sample signals of the normal channel and the floating channel. The source driver may provide a first reference voltage to the floating channel in a first cycle of sensing a characteristic of the pixel.

[0013] In an embodiment, the source driver may include: a sampling circuit configured to sample signals of multiple channels including a normal channel and a floating channel and provide a sampling signal; a multiplexer configured to output the sampling signal to an analog-to-digital converter in a preset sequence; and an analog-to-digital converter configured to convert the sampling signal into digital data. The source driver may provide a first reference voltage to the floating channel through the normal channel in a first period of sensing the characteristics of a pixel of the display panel.

[0014] According to an embodiment, a problem in which an operation of a floating channel for sensing an unknown input affects data of an adjacent normal channel may be prevented by providing a first reference voltage to the floating channel when sensing characteristics of a pixel.

[0015] Furthermore, the embodiment can simplify the process of calculating the characteristics of the source driver and the characteristics of the pixel because the timing controller can distinguish between digital data of the normal channel and the floating channel at the time of data processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a diagram for describing a floating channel of a source driver according to an embodiment.

[0017] Figure 2 is a block diagram of a display device including a source driver according to an embodiment.

[0018] Figure 3 is a block diagram of a control signal generator of a source driver according to an embodiment.

[0019] Figure 4 is a timing diagram for describing an operation of sampling characteristics of a source driver according to an embodiment.

[0020] Figure 5 is a timing diagram for describing an operation of a source driver sampling characteristics of a pixel according to an embodiment. DETAILED DESCRIPTION

[0021] Embodiments provide a source driver capable of accurately sensing characteristics of a display panel by minimizing the influence of a floating channel.

[0022] If the horizontal resolution of the display panel and the number of channels of the source driver are not positive multiples, the source driver may include a floating channel.

[0023] In an embodiment, a normal channel may be defined as a channel connected to a pixel of a display panel. A floating channel may be defined as a channel not connected to a pixel, that is, the floating channel is in an idle state.

[0024] In an embodiment, a display period may be defined as a period in which a source signal corresponding to image data is provided to a display panel. A sensing period may be defined as a first period including sensing pixel characteristics of a display panel and a second period sensing characteristics of a source driver.

[0025] In an embodiment, the operation of the first cycle of sensing pixel characteristics can be divided into an initialization mode, a programming mode, and a sampling mode. In this case, the initialization mode can be defined as a mode in which an operation of initializing all pixels is performed using an initialization voltage. The programming mode can be defined as a mode in which an operation of programming pixels based on reference data is performed after the initialization mode. The sampling mode can be defined as a mode in which an operation of sampling signals of all pixels is performed after the programming mode.

[0026] In an embodiment, the first reference voltage may be defined as a voltage provided to the floating channel in a first cycle of sensing pixel characteristics. The second reference voltage may be defined as a voltage provided to the normal channel and the floating channel in a second cycle of sensing characteristics of the source driver. The third reference voltage may be defined as a voltage used to initialize all pixels in an initialization mode.

[0027] In the embodiment, terms such as “first” and “second” may be used to distinguish various elements. These elements are not limited by the terms such as “first” and “second”.

[0028] Figure 1 is a diagram for describing a floating channel CH_F of a source driver SDIC according to an embodiment.

[0029] refer to Figure 1 , the display device 100 may include a display panel 110 and a plurality of source drivers SDIC1 to SDIC5. For example, the display panel 110 may be composed of an OLED panel.

[0030] If the number of channels of the plurality of source drivers SDIC1 to SDIC5 and the horizontal resolution of the display panel 110 are not positive multiples, some of the channels of some source drivers SDIC1 and SDIC5 may be floated. In this specification, an idle channel of the source drivers SDIC1 and SDIC5 that is not connected to a pixel of the display panel 110 is referred to as a floating channel CH_F.

[0031] If the horizontal resolution of the display panel 100 and the number of channels of the plurality of source drivers SDIC1 to SDIC5 are not positive multiples, at least one floating channel CH_F may exist in each of the source drivers SDIC1 and SDIC5. In this specification, for convenience of description, one floating channel is shown.

[0032] Figure 2 is a block diagram of a display device 100 illustrating connection between a source driver SDIC and a display panel 110 according to an embodiment. Figure 2 The source driver SDIC in the Figure 1 Corresponding to one of the source drivers SDIC1 and SDIC5.

[0033] refer to Figure 2 The source driver SDIC may include a sampling circuit 10 , a multiplexer MUX, an analog-to-digital converter ADC and a data processing unit 20 .

[0034] The sampling circuit 10 may sample signals of multiple channels of the source driver SDIC and may provide the sampling signals to the multiplexer MUX.

[0035] The multi-channel means a channel of the source driver SDIC and may include normal channels CH1 and CH2 and a floating channel CH_F. The normal channels CH1 and CH2 may be defined as channels connected to pixels of the display panel 110. The floating channel CH_F may be defined as an idle channel not connected to pixels of the display panel 110.

[0036] The sampling circuit 10 may sample signals of normal channels CH1 and CH2 and a floating channel CH_F. For example, the sampling circuit 10 may sample signals of normal channels CH1 and CH2 and a floating channel CH_F in a first cycle of sensing characteristics of a pixel and a second cycle of sensing characteristics of a source driver SDIC in response to a first sampling signal SAM and a second sampling signal SVR. For example, the sampling circuit 10 may include a sampling capacitor for each multi-channel. When the sampling circuit 10 samples signals of a multi-channel, one end of the sampling capacitor may be connected to the multi-channel in response to the first sampling signal SAM, and the other end of the sampling capacitor may be connected to a terminal T1 for a first reference voltage VREF in response to a second sampling signal SVR.

[0037] The source driver SDIC may provide a first reference voltage VREF to the floating channel CH_F in a first period of sensing characteristics of the pixel, and may provide a second reference voltage VSEN to the normal channels CH1 and CH2 and the floating channel CH_F in a second period of sensing characteristics of the source driver SDIC.

[0038] The first reference voltage VREF and the second reference voltage VSEN may be set to have different levels.

[0039] For example, the first reference voltage VREF may be set to have a level corresponding to a bottom voltage for sensing of the sampling circuit 10. The level corresponding to the bottom voltage may vary according to a desired voltage range for sampling in the sampling circuit 10. Therefore, the level of the first reference voltage VREF may also vary according to the bottom voltage.

[0040] In addition, the second reference voltage VSEN can be set to have a level corresponding to 1 / 2 of the highest level of the driving voltage. The driving voltage can be understood as a voltage for driving analog components of the source driver SDIC. The first reference voltage VREF can be understood as corresponding to an intermediate voltage within the full range in which the driving voltage swings.

[0041] The source driver SDIC may include a first switch SW1 for providing a first reference voltage VREF to the floating channel CH_F in a first period.

[0042] The first switch SW1 may connect the terminal T1 for the first reference voltage VREF and the floating channel CH_F in the first period. In this case, the first switch SW1 may be turned on in the first period, and may be turned off in the second period.

[0043] The source driver SDIC may include a control signal generator 30 (refer to Figure 3 ). The control signal generator 30 may generate a second control signal SREF1 in response to the first control signal SEN and the floating channel selection signal CH_SEL.

[0044] In this case, the first control signal SEN may be enabled in the second cycle.The floating channel selection signal CH_SEL may be enabled with respect to the floating channel CH_F of the multi-channel in the first cycle.

[0045] In addition, the source driver SDIC may provide the second reference voltage VSEN to the floating channel CH_F and the normal channels CH1 and CH2 in the second period.

[0046] The source driver SDIC may include a second switch SW2 for providing the second reference voltage VSEN to the floating channel CH_F and the normal channels CH1 and CH2 in the second period.

[0047] The second switch SW2 may connect the terminal T2 for the second reference voltage VSEN with the floating channel CH_F, and may connect the terminal T2 for the second reference voltage VSEN with each of the normal channels CH1 and CH2 .

[0048] In the second period, the source driver SDIC may turn on the second switch SW2 and may prevent the first reference voltage VREF from being provided to the floating channel CH_F by turning off the first switch SW1 .

[0049] In addition, the source driver SDIC may include a third switch SW3 for providing the first reference voltage VREF to each of the normal channels CH1 and CH2. If the multi-channel includes the normal channels CH1 and CH2 connected to the pixel, the third switch SW3 may be turned off in the first period and the second period.

[0050] In addition, the source driver SDIC may initialize the pixels of the display panel 110 based on the third reference voltage VPRE in response to the initialization signal SPRE in the initialization mode of the first period.

[0051] The source driver SDIC may include a fourth switch SW4 for providing a third reference voltage VPRE to the floating channel CH_F and the normal channels CH1 and CH2 in the initialization mode.

[0052] The fourth switch SW4 may connect the terminal T3 for the third reference voltage VPRE with the floating channel CH_F, and may connect the terminal T3 for the third reference voltage VPRE with each of the normal channels CH1 and CH2.

[0053] The source driver SDIC may turn on the fourth switch SW4 in the initialization mode and may prevent the first reference voltage VREF from being supplied to the floating channel CH_F by turning off the first switch SW1 and may prevent the second reference voltage VSEN from being supplied to the floating channel CH_F and the normal channels CH1 and CH2 by turning off the second switch SW2 .

[0054] At this time, the sensing switch SSW connected to the pixel of the display panel 110 may be turned on, and the sampling circuit 10 may be turned off.

[0055] The multiplexer MUX may receive the sampling signals from the sampling circuit 10 and may provide the sampling signals to the analog-to-digital converter ADC in a preset sequence.

[0056] The analog-to-digital converter ADC may convert the sampling signals sequentially provided by the multiplexer MUX into digital data and may provide the digital data to the data processing unit 20 .

[0057] The data processing unit 20 may provide digital data D1 and D2 corresponding to normal channels CH1 and CH2 to a timing controller (not shown). In addition, the data processing unit 20 may process digital data D0 corresponding to a floating channel CH_F into a fixed digital code and may provide the fixed digital code to the timing controller.

[0058] The data processing unit 20 may include a floating data processing circuit 22. The floating data processing circuit 22 may process the digital data D0 of the floating channel CH_F into a fixed digital code in response to a floating channel selection signal CH_SEL. For example, the floating channel selection signal CH_SEL may be recovered from a packet form of input data provided by a timing controller, or may be generated internally.

[0059] Figure 3 is a block diagram of a control signal generator 30 of a source driver SDIC according to an embodiment.

[0060] refer to Figure 3 , the control signal generator 30 may generate a second control signal SREF1 for controlling the first switch SW1 in response to the first control signal SEN and the floating channel selection signal CH_SEL.

[0061] The control signal generator 30 may enable the second control signal SREF1 in the first cycle in response to the first control signal SEN and the floating channel selection signal CH_SEL, and may disable the second control signal SREF1 in the second cycle. In this case, the first control signal SEN may be enabled in the second cycle, and the floating channel selection signal CH_SEL may be enabled with respect to the floating channel CH_F of the multi-channel in the first cycle.

[0062] Figure 4 : is a timing diagram for describing an operation of sampling characteristics of the source driver SDIC according to an embodiment.

[0063] refer to Figure 2 and Figure 4 , first, the source driver SDIC may provide the second reference voltage VSEN to the normal channels CH1 and CH2 and the floating channel CH_F in the second period in response to the first control signal SEN.

[0064] At this time, the source driver SDIC can turn off the first switch SW1 and turn on the second switch SW2 in the second period. As described above, in the second period, the source driver SDIC can prevent the first reference voltage VREF from being provided to the floating channel CH_F and provide the second reference voltage VSEN to the normal channels CH1 and CH2 and the floating channel CH_F.

[0065] In this case, a given margin time may be set between the off time of the first switch SW1 and the on time of the second switch SW2 and between the off time of the second switch SW2 and the on time of the first switch SW1 .

[0066] Thereafter, the source driver SDIC may sample signals of the normal channels CH1 and CH2 and the floating channel CH_F in response to the first sampling signal SAM and the second sampling signal SVR, and may sequentially convert the sampled signals into digital data.

[0067] At this time, the source driver SDIC may process digital data corresponding to the signal of the floating channel CH_F into a fixed digital code.

[0068] Thereafter, the source driver SDIC may provide the timing controller with digital data corresponding to the normal channels CH1 and CH2 and a fixed digital code corresponding to the floating channel CH_F.

[0069] The timing controller may calculate the characteristics of the source driver by using digital data provided by the source driver SDIC. In this case, the timing controller may distinguish digital data corresponding to the normal channels CH1 and CH2 from data corresponding to the floating channel CH_F by using a fixed digital code.

[0070] Figure 5 is a timing diagram for describing an operation of a source driver sampling characteristics of a pixel according to an embodiment.

[0071] refer to Figure 2 and Figure 5 , the source driver SDIC may respond to the initialization signal SPRE, in the initialization mode of the first cycle, to initialize the pixels of the display panel 110 based on the third reference voltage VPR. At this time, the sensing switch SSW connected to the pixel of the display panel 110 may be turned on. The second switch SW2, the first switch SW1, and the sampling circuit 10 may be turned off.

[0072] In addition, for example, the source driver SDIC may initialize the pixels of the display panel 110 based on the second reference voltage VSEN in the initialization mode of the first period in response to the first control signal SEN. At this time, the sensing switch SSW and the second switch SW2 connected to the pixels of the display panel 110 may be turned on, and the first switch SW1 and the sampling circuit 10 may be turned off.

[0073] Thereafter, the source driver SDIC may program the pixels of the display panel 100 in the programming mode of the first cycle based on the reference data. At this time, the second switch SW2 and the sampling circuit 10 may be turned off, and the first switch SW1 may be turned on.

[0074] Thereafter, the source driver SDIC may sample the signals of the pixels of the display panel 100 in the sampling mode of the first period. At this time, the second switch SW2 may be turned off, and the sampling circuit 10 and the first switch SW1 may be turned on.

[0075] In this case, a given margin time may be set between the enable time of the second control signal SREF1 and the enable time of the initialization signal SPRE.

[0076] Thereafter, the source driver SDIC may sample signals of the normal channels CH1 and CH2 and the floating channel CH_F in response to the first sampling signal SAM and the second sampling signal SVR, and may sequentially convert the sampled signals into digital data.

[0077] At this time, the source driver SDIC may process digital data corresponding to the signal of the floating channel CH_F into a fixed digital code.

[0078] Thereafter, the source driver SDIC may provide the timing controller with digital data corresponding to the normal channels CH1 and CH2 and a fixed digital code corresponding to the floating channel CH_F.

[0079] The timing controller may calculate characteristics of pixels of the display panel 110 by using digital data provided by the source driver SDIC. In this case, the timing controller may distinguish digital data corresponding to normal channels CH1 and CH2 from data corresponding to the floating channel CH_F by using a fixed digital code.

[0080] As described above, according to an embodiment, the problem that the operation of the floating channel CH_F for sensing an unknown input affects data of normal channels CH1 and CH2 adjacent to the floating channel CH_F can be prevented by providing the first reference voltage VREF to the floating channel CH_F when sensing characteristics of a pixel.

[0081] Furthermore, the embodiment may simplify the process of calculating the characteristics of the source driver and the characteristics of the pixel because the timing controller may distinguish between digital data of the normal channels CH1 and CH2 and the floating channel CH_F at the time of data processing.

Claims

1. Source driver, including: Normal channel, connected to the pixels of the display panel; Floating channel, in no-load state; A sampling circuit configured to sample signals of the normal channel and the floating channel; as well as a first switch configured to provide a first reference voltage to the floating channel in a first cycle, wherein the source driver provides the first reference voltage to the floating channel in the first period of sensing the characteristics of the pixel, The first switch is turned on in the first period, and is turned off in the second period for sensing the characteristics of the source driver.

2. The source driver according to claim 1, further comprising: A control signal generator is configured to generate a second control signal that is enabled in the first cycle and disabled in the second cycle, and is configured to provide the second control signal to the first switch.

3. The source driver according to claim 1, wherein: The first reference voltage is set to have a level corresponding to a bottom voltage for sensing of the sampling circuit.

4. The source driver according to claim 1, wherein: In the second period of sensing the characteristics of the source driver, a second reference voltage is provided to the normal channel and the floating channel.

5. The source driver according to claim 4, further comprising: a second switch configured to provide the second reference voltage to the normal channel and the floating channel in the second period, The second switch is turned on in the second period, and is turned off in the first period.

6. The source driver according to claim 4, wherein: The second reference voltage is set to have a level corresponding to 1 / 2 of the highest level of the driving voltage.

7. The source driver according to claim 1, further comprising: The data processing unit is configured to process the digital data of the floating channel into a fixed digital code.

8. Source driver, including: A sampling circuit configured to sample signals of multiple channels including a normal channel and a floating channel and provide a sampling signal; a multiplexer configured to output the sampled signals to an analog-to-digital converter in a preset sequence; The analog-to-digital converter is configured to convert the sampled signal into digital data; as well as a first switch configured to provide a first reference voltage to the floating channel in a first cycle, wherein the source driver provides the first reference voltage to the floating channel through the normal channel in the first period of sensing the characteristics of the pixels of the display panel, The first switch is turned on in the first period, and is turned off in the second period for sensing the characteristics of the source driver.

9. The source driver according to claim 8, wherein: In the second period of sensing the characteristics of the source driver, a second reference voltage is provided to the normal channel and the floating channel.

10. The source driver according to claim 8, wherein: The first reference voltage is set to have a level corresponding to a bottom voltage for sensing of the sampling circuit.

11. The source driver according to claim 8, further comprising: a second switch configured to provide a second reference voltage to the normal channel and the floating channel in the second period of sensing the characteristic of the source driver, The second switch is turned on in the second period, and is turned off in the first period.

12. The source driver according to claim 11, wherein: The second reference voltage is set to have a level corresponding to 1 / 2 of the highest level of the driving voltage.

13. The source driver according to claim 8, further comprising: The data processing unit is configured to process the digital data of the floating channel into a fixed digital code.

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