Memory device, storage device, and operating method of storage device

Abstract

Disclosed are a memory device, a storage device, and an operating method of a storage device. The operating method of the storage device includes detecting whether a recycling event has occurred in a source memory area including a plurality of memory areas, setting a recycling priority value to each of the plurality of memory areas, and performing a recycling operation on the source memory area according to the recycling priority value of each of the plurality of memory areas. The recycling operation moves data stored in the source memory area to a destination memory area.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2020-0057190, filed on May 13, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0002] The inventive concept relates to a memory device, and more specifically, to a memory device, a storage device including the memory device, and a method of operating the storage device. Background Technology

[0003] Flash memory, as a non-volatile storage medium, retains stored data even when power is off. Recently, storage devices, including flash memory (such as embedded multimedia cards (eMMC), universal flash memory (UFS), solid-state drives (SSDs), and memory cards), have been widely used for storing or moving large amounts of data. There has been a continuous need for methods and devices to improve the reliability of storage devices. Summary of the Invention

[0004] The inventive concept provides a memory device that can improve the reliability of a storage device, a storage device including the memory device, and a method of operating the storage device.

[0005] According to an exemplary embodiment of the present invention, a method of operating a storage device includes: detecting whether a reclamation event has occurred in a source memory region comprising a plurality of memory regions; setting a reclamation priority value to each of the plurality of memory regions; and performing a reclamation operation on the source memory region according to the reclamation priority value of each of the plurality of memory regions. The reclamation operation moves data stored in the source memory region to a destination memory region.

[0006] According to an exemplary embodiment of the present invention, a storage device includes: a non-volatile memory device; and a controller operatively coupled to the non-volatile memory device and configured to: detect whether a reclamation event has occurred in a source memory region of the non-volatile memory device, wherein the source memory region includes a plurality of memory regions; set a reclamation priority value to each of the plurality of memory regions; and perform a reclamation operation on the source memory region based on the reclamation priority value of each of the plurality of memory regions.

[0007] According to an exemplary embodiment of the present invention, a memory device includes: a memory cell array including: a plurality of memory blocks, each of the plurality of memory blocks including a plurality of pages; and control logic circuitry configured to: generate control signals for performing a reclamation operation on a unit basis of memory blocks. The control logic circuitry is configured to: perform a reclamation operation by moving data of each page of a source block among the plurality of memory blocks to a destination block among the plurality of memory blocks, based on a reclamation priority value for each page. Attached Figure Description

[0008] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 This is a block diagram illustrating a storage system according to an embodiment;

[0010] Figure 2 It is shown that it includes Figure 1 A block diagram of the controller in the storage device;

[0011] Figure 3 This is a flowchart illustrating an operation method of a storage device according to an embodiment;

[0012] Figure 4 It is shown that it includes Figure 1 A block diagram of a memory device in a non-volatile memory;

[0013] Figure 5 This is an equivalent circuit diagram of a memory block included in a memory cell array of a memory device according to an embodiment;

[0014] Figure 6A and Figure 6B This is a diagram illustrating the reclaim operation of a storage device according to an embodiment;

[0015] Figure 7 This is a diagram illustrating the recycling operation of a storage device according to an embodiment;

[0016] Figure 8 This is a flowchart illustrating an operation method of a storage device according to an embodiment;

[0017] Figure 9A and Figure 9B It is shown Figure 8 A diagram illustrating operation S23;

[0018] Figure 10A and Figure 10B It is shown Figure 8 A diagram illustrating operation S23;

[0019] Figure 11This is a flowchart illustrating an operation method of a storage device according to an embodiment;

[0020] Figure 12 This is a flowchart illustrating an operation method of a storage device according to an embodiment;

[0021] Figures 13 to 16 This is a flowchart illustrating an operation method of a storage device according to an embodiment; and

[0022] Figure 17 This is a block diagram illustrating the grouping of superblocks in a non-volatile memory according to an embodiment. Detailed Implementation

[0023] Figure 1 This is a block diagram illustrating a storage system 10 according to an embodiment.

[0024] Storage system 10 can be implemented as, for example, a personal computer (PC), a data server, network attached storage (NAS), an Internet of Things (IoT) device, or a portable electronic device. Portable electronic devices may include laptops, mobile phones, smartphones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital cameras, digital camcorders, audio devices, portable multimedia players (PMPs), personal navigation devices (PNDs), MP3 players, handheld game consoles, e-readers, wearable devices, etc.

[0025] Storage system 10 may include storage device 100 and host 200. Host 200 may control the operation of storage device 100. In one embodiment, storage device 100 may include one or more solid-state drives (SSDs). When storage device 100 includes SSDs, storage device 100 may include multiple flash memory devices (e.g., NAND memory devices) for storing data.

[0026] Storage device 100 may include one or more flash memory devices. In one embodiment, storage device 100 may be an embedded memory embedded in storage system 10. For example, storage device 100 may be an embedded multimedia card (eMMC) or an embedded universal flash memory (UFS) device. In one embodiment, storage device 100 may be an external memory removable from storage system 10. For example, storage device 100 may be a UFS memory card, a compact flash (CF) card, a secure digital card (SD) card, a micro-secure digital card (Micro-SD) card, a mini-secure digital card (Mini-SD) card, an extreme digital card (xD), or a memory stick.

[0027] Reference Figure 1The storage system 10 may include a storage device 100 and a host 200, and the storage device 100 may include a controller 110 and non-volatile memory 120. The host 200 may communicate with the storage device 100 through various interfaces and may transmit request REQs (such as read requests and programming requests) to the storage device 100. In one embodiment, the host 200 may be implemented as an application processor (AP) or a system-on-a-chip (SoC).

[0028] The controller 110 can control the operation of the non-volatile memory 120 via channels CH1 to CHi. The controller 110 can control the non-volatile memory 120 to read data DATA stored in the non-volatile memory 120 in response to a read request from the host 200, or to program data DATA into the non-volatile memory 120 in response to a write request from the host 200.

[0029] When a reclaim event has occurred, controller 110 can perform a reclamation operation by controlling non-volatile memory 120. In this case, a "reclaim operation" refers to the operation of moving data from the source memory region to the destination memory region and reusing the source memory region by erasing the data in the source memory region. Specifically, in a reclamation operation, controller 110 can read valid data stored in the source memory region and program the read valid data into the destination memory region. Therefore, the address corresponding to the valid data in the mapping table can be changed from the source memory region to the destination memory region. In one example embodiment, the source memory region may correspond to a memory block having at least one page where a reclamation event has occurred, and the destination memory region may correspond to a free block used to store the valid data moved from the source memory. The invention is not limited thereto. In one example embodiment, the source memory region may correspond to a portion of a memory block, and the destination memory region may correspond to a portion of a free block. The memory block may be a unit of the erase operation (i.e., the erase operation is performed on a memory block basis).

[0030] In one embodiment, controller 110 may include a recycling scheduler 114. The recycling scheduler 114 may set recycling priority values ​​for memory regions targeted by recycling operations, and may set the order in which recycling operations are performed on memory regions based on the set priority values. Figure 2 The priority value of the memory region in the RQ (Reclaimed Memory Queues) increases, and the reclamation operation to be performed is scheduled according to the priority. In one embodiment, the reclamation scheduler 114 may be configured to include the source memory block (e.g., the target of the reclamation operation) as the target of the reclamation operation. Figure 4 Multiple pages in one of BLK1 to BLKn (e.g., Figure 4The recycling priority values ​​for recycling operations (PG1 to PGm).

[0031] In one embodiment, the reclamation scheduler 114 may set a priority of a first value (i.e., a first reclamation priority value) for memory regions where reclamation events have already occurred, a priority of a second value (i.e., a second reclamation priority value) for memory regions where reclamation events are expected to occur, and a priority of a third value (i.e., a third reclamation priority value) for other memory regions. The memory regions where reclamation events are expected to occur may be previously designated memory regions that have low data reliability due to their physical structure. (Refer to...) Figure 9B and Figure 10A The previously specified memory regions are described. In a reclamation operation, a first value may take precedence over a second value, and a second value may take precedence over a third value; however, the inventive concept is not limited thereto, and the second value may take precedence over the first value, and the first value may take precedence over the third value. As the priority value increases, the reclamation operation can be performed earlier on memory regions with higher values. In one example embodiment, in a reclamation operation, a memory region with a first value may take precedence over memory regions with second and third values. In a reclamation operation, data in memory regions with first values ​​may be moved to the destination region first, and data in memory regions with second and third values ​​may be moved to the destination region later. Of the memory regions with second and third values, data in the memory region with the second value is moved to the destination region, and then data in the memory region with the third value is moved to the destination region.

[0032] In one embodiment, the non-volatile memory 120 may include a plurality of memory devices NVM1 to NVMi for storing data. Each of the plurality of memory devices NVM1 to NVMi may be a semiconductor chip or a semiconductor die. Each of the plurality of memory devices NVM1 to NVMi may be connected to a corresponding channel. For example, the non-volatile memory 120 may include a memory device NVM1 connected to the controller 110 via a first channel CH1, a memory device NVM2 connected to the controller 110 via a second channel CH2, and a memory device NVMi connected to the controller 110 via an i-th channel CHi. Here, i may be an integer of 3 or greater. Among the plurality of memory devices NVM1 to NVMi, a group of memory devices connected to the same channel may perform programming, reading, and erasing operations in an interleaved manner.

[0033] Each of the plurality of memory devices NVM1 to NVMi may include an array of memory cells (e.g., Figure 4(122). In one embodiment, the memory cell array 122 may include flash memory cells. For example, the flash memory cells may be NAND flash memory cells. However, the inventive concept is not limited thereto, and the memory cells may be resistive memory cells (such as resistive RAM (ReRAM) cells, phase change RAM (PRAM) cells, or magnetic RAM (MRAM) cells).

[0034] The storage device 100 according to the inventive concept can pre-set the recycling priority of memory regions as targets of recycling operations, and perform recycling operations according to the recycling priority. The storage device 100 can prioritize performing recycling operations on source memory regions where recycling events have already occurred, thereby preventing excessive delays in recycling operations on source memory regions even when a REQ request is received from the host 200.

[0035] Figure 2 It is shown in detail that includes Figure 1 A block diagram of the controller 110 in the storage device 100.

[0036] Reference Figure 1 and Figure 2 The controller 110 may include a processor 111, a host interface 112, a memory 113, a garbage collection scheduler 114, and a non-volatile memory interface 115, which can communicate with each other via a bus 116. The processor 111 may include a central processing unit or a microprocessor and controls all operations of the controller 110. The processor 111 may include one or more processor cores capable of executing an instruction set of program code configured to perform specific operations. For example, the processor 111 may execute command code of firmware stored in the memory 113.

[0037] The reclamation scheduler 114 can set the priority of reclamation operations for memory regions that are the targets of reclamation operations, and schedule the reclamation operations to be executed according to the reclamation priorities. The reclamation scheduler 114 can be implemented in hardware, software, or firmware. When the reclamation scheduler 114 is implemented in software or firmware, the reclamation scheduler 114 can be loaded into memory 113 and operate under the control of processor 111. Memory 113 can be used as operational memory, buffer memory, cache memory, etc., and is implemented, for example, as dynamic random access memory (DRAM), static random access memory (SRAM), phase-change memory (PRAM), or flash memory.

[0038] The command queue CQ can be implemented as a portion of memory 113. Commands based on requests REQ received from host 200 can be queued into the command queue CQ. For example, when a write request is received, the write command corresponding to the write request can be queued into the command queue CQ, and when a read request is received, the read command corresponding to the read request can be queued into the command queue CQ.

[0039] The reclamation queue RQ can be implemented as a portion of memory 113. In the reclamation queue RQ, information about memory regions where reclamation events have occurred can be stored, and information about the reclamation priority of the memory regions targeted by reclamation operations can be stored. That is, in the reclamation queue RQ, the addresses of source memory regions can be registered, and their corresponding reclamation priority values ​​can be stored. For example, the reclamation queue RQ can store priority values ​​indicating the reclamation priority of each page in a memory block. Alternatively, for example, the reclamation queue RQ can store priority values ​​indicating the reclamation priority of each memory block.

[0040] The metadata buffer MB can be implemented as part of or a separate DRAM chip of memory 113. The metadata stored in the metadata buffer MB can be stored in the metadata region of non-volatile memory 120, and can be loaded into the metadata buffer MB in non-volatile memory 120 when power is applied to storage device 100.

[0041] Degradation information about memory regions of non-volatile memory 120 can be stored as metadata in a metadata buffer (MB). In one embodiment, degradation information can be stored per memory block or per page. For example, degradation information indicating memory regions where a reclamation event is expected can be stored in the metadata buffer (MB). For example, degradation information such as indicating memory regions with low data reliability due to the physical structure of the memory region, or indicating memory regions with erase counts greater than a reference value, can be stored in the metadata buffer (MB). The erase count represents the number of times an erase operation has been performed on the memory region. For example, degradation information may include the row address of a memory region with low data reliability or the row address of a memory array with an erase count greater than a reference value. The reclamation scheduler 114 can set the reclamation priority of memory regions targeted for reclamation operations based on the degradation information stored in the metadata buffer (MB).

[0042] Host interface 112 provides an interface between host 200 and controller 110. For example, host interface 112 may provide an interface based on Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect Fast (PCI-E), Advanced Technology Accessories (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Enhanced Small Device Interface (ESDI), and Intelligent Drive Electronic Devices (IDE). Non-volatile memory interface 115 provides an interface between controller 110 and non-volatile memory 120. For example, degradation information, mapping tables, write data, and read data can be sent and received between controller 110 and non-volatile memory 120 via non-volatile memory interface 115.

[0043] Figure 3 This is a flowchart illustrating an operation method of the storage device 100 according to an embodiment. Figure 3 The operation methods shown in S10 to S30 can be continuously performed in time by... Figure 1 The storage device 100 executes.

[0044] Reference Figure 1 and Figure 3 In operation S10, the storage device 100 can detect the occurrence of a reclamation event. In one embodiment, the storage device 100 can read data in a specific memory region and determine that a reclamation event has occurred when the error bit rate (EBR) of the data is greater than or equal to a reference value. Optionally, in one embodiment, when a read operation on a specific memory region fails, the storage device 100 can execute recovery code via firmware and, in response to specific defense code implemented in the recovery code in the firmware, determine that a reclamation event has occurred in the specific memory region. An algorithm called the "defense code" can be implemented... Figure 1 The controller 110 is implemented to correct or recover from read errors. Defensive code, acting as recovery code for handling read errors that have already occurred, can be implemented in the firmware. In one example embodiment, the recovery code may allow repeated read operations (i.e., read retry operations) using a varying read reference voltage until error correction is complete.

[0045] For example, when a read request is received from host 200, storage device 100 can read data DATA from a specific memory region of non-volatile memory 120 via a host read operation, and determine whether to perform a recycling operation based on the read data DATA. This will be discussed later. Figure 12 Operation S10 describes a detailed example of how to determine whether to perform a recycling operation by reading operations from the host.

[0046] Alternatively, for example, storage device 100 may read data from a specific memory region of non-volatile memory 120 via a background read operation, and determine whether to perform a recycling operation based on the read data. A "background read operation" refers to an operation in which the controller 110 issues a read command itself to read data from non-volatile memory 120 without receiving a read request from the host 200. This will be discussed later. Figures 13 to 16 The operations S10a to S10d describe detailed examples of methods for determining whether to perform a recycling operation by reading operations from the background.

[0047] In operation S20, the storage device 100 can set the recycling priority of the recycling operation target. For example, in operation S10, the recycling priority value can be set to the memory region where a recycling event has occurred, so that the recycling operation can be executed first, and the recycling priority value of the subsequent order can be set to the memory region where no recycling event has occurred but which is the target of the recycling operation.

[0048] In operation S30, the storage device 100 may perform a recycling operation according to a set recycling priority. For example, in operation S10, the storage device 100 may first perform a recycling operation on the memory region where a recycling event has occurred, and then perform a recycling operation on the memory region that has not experienced a recycling event but is the target of the recycling operation.

[0049] The storage device 100 according to the inventive concept can pre-set priority values ​​for reclamation operations on memory regions and perform reclamation operations according to the set priority values. Therefore, even when a REQ request is received from the host 200, the storage device 100 can prevent excessive delays in reclamation operations on memory regions where reclamation events have already occurred. The data reliability of the non-volatile memory 120 and the storage device 100 can be improved.

[0050] Figure 4 It is shown that it includes Figure 1 Block diagram of memory device 120A in non-volatile memory 120.

[0051] Reference Figure 1 and Figure 4 The memory device 120A may include a memory cell array 122, an address decoder 123, a control logic block 124, a page buffer 125, input / output circuitry 126, and a voltage generator 127. Although not shown, the memory device 120A may also include an input / output interface.

[0052] The memory cell array 122 can be connected to the word line WL, the serial select line SSL, the ground select line GSL, and the bit line BL. The memory cell array 122 can be connected to the address decoder 123 via the word line WL, the serial select line SSL, and the ground select line GSL, and can also be connected to the page buffer 125 via the bit line BL. The memory cell array 122 can include multiple memory blocks BLK1 to BLKn.

[0053] Each of the memory blocks BLK1 to BLKn may include multiple memory cells and multiple select transistors. Memory cells may be connected to word lines WL, and select transistors may be connected to serial select line SSL or ground select line GSL. The memory cells of each of the memory blocks BLK1 to BLKn may include single-level cells (SLC) storing 1 bit of data or multi-level cells (MLC) storing 2 bits or more of data.

[0054] Each of the plurality of memory blocks BLK1 to BLKn may include a plurality of pages PG1 to PGm. Each page PG1 to PGm may correspond to a programming unit or a reading unit of data in a memory block. In one embodiment, the memory cells included in each of pages PG1 to PGm may be connected to the same word line.

[0055] Address decoder 123 can select one of a plurality of memory blocks BLK1 to BLKn of memory cell array 122, can select one of the word lines WL of the selected memory block, and can select one of a plurality of string selection lines SSL.

[0056] Control logic block 124 (or control logic circuit) can output various control signals for performing programming, reading, and erasing operations on memory cell array 122 based on command CMD, address ADDR, and control signal CTRL. Control logic block 124 can provide row address X-ADDR to address decoder 123, column address Y-ADDR to page buffer 125, and voltage control signal CTRL_Vol to voltage generator 127.

[0057] Control logic block 124 can perform erase operations on a per-block basis, from BLK1 to BLKn. Control logic block 124 can also perform read or program operations on a per-page basis, from PG1 to PGm.

[0058] In one embodiment, control logic block 124 may perform a reclamation operation on a per-unit basis among a plurality of memory blocks BLK1 to BLKn. For example, control logic block 124 may perform a reclamation operation by reading data per page included in a second memory block BLK2 (which is the source memory block among the plurality of memory blocks BLK1 to BLKn where a reclamation event has already occurred), programming the data per page to the destination memory block among the plurality of memory blocks BLK1 to BLKn, and erasing the second memory block BLK2.

[0059] In one embodiment, when performing a reclamation operation on the second memory block BLK2, the control logic block 124 may prioritize performing reclamation operations on the second page PG2, the fourth page PG4, and the (m-1)th page PGm-1, which have already undergone reclamation events. Therefore, the control logic block 124 may not perform reclamation operations on the second memory block BLK2 in the order of row addresses X-ADDR. For example, when performing a reclamation operation on the second memory block BLK2, the control logic block 124 may prioritize performing reclamation operations on the second page PG2, the fourth page PG4, and the (m-1)th page PGm-1, and then perform reclamation operations on the remaining pages in either a top-down order from the first page PG1 to the mth page PGm of the second memory block BLK2, or a bottom-up order from the mth page PGm to the first page PG1.

[0060] Page buffer 125 can operate as a write driver or a sense amplifier depending on the operating mode. During a read operation, page buffer 125 can sense the bit line BL of the selected memory cell under the control of control logic block 124. The sensed data can be stored in a latch provided internally by page buffer 125. Page buffer 125 can dump the data stored in the latch to input / output circuit 126 under the control of control logic block 124.

[0061] The input / output circuit 126 can temporarily store commands CMD, address ADDR, control signals CTRL, and data DATA provided from the external memory device 120A via input / output lines I / O. The input / output circuit 126 can also temporarily store read data from the memory device 120A and output the read data to the external device via input / output lines I / O at specified times.

[0062] Voltage generator 127 can generate various types of voltages for performing programming, reading, and erasing operations on memory cell array 122 based on the voltage control signal CTRL_Vol. Specifically, for example, voltage generator 127 can generate word line voltage VWL, programming voltage, reading voltage, pass voltage, erase verification voltage, or programming verification voltage. Furthermore, voltage generator 127 can generate serial select line voltage and ground select line voltage based on the voltage control signal CTRL_Vol. Additionally, voltage generator 127 can generate the erase voltage to be supplied to memory cell array 122.

[0063] Figure 5 This is an equivalent circuit diagram of a memory block BLK included in a memory cell array 121 of a memory device 120A according to an embodiment. Figure 5 The equivalent circuit diagram of a NAND flash memory device with a vertical channel structure formed on a substrate is shown in the figure.

[0064] Reference Figure 5 The memory block BLK included in the memory cell array 121 may include multiple memory cell strings MS. The memory block BLK may include multiple bit lines BL (e.g., BL1 to BLk), multiple word lines WL (e.g., WL1 to WLm), multiple string select lines SSL (e.g., SSL1 to SSLk), at least one ground select line GSL, and a common source line CSL. The multiple memory cell strings MS may be formed between the multiple bit lines BL1 to BLk and the common source line CSL.

[0065] Each of the multiple memory cell strings MS may include a string select transistor SST, a ground select transistor GST, and multiple memory cells MC1 to MCm. The drain region of the string select transistor SST may be connected to the bit line BL, and the source region of the ground select transistor GST may be connected to a common source line CSL. The common source line CSL may be a region where the source regions of multiple ground select transistors GST are connected together.

[0066] To independently control multiple memory cell strings (MS), a string select transistor (SST) in each of the multiple memory cell strings (MS) can be connected to a different string select line (SSL). For example, the string select transistor (SST) can be connected to a string select line (e.g., one of SSL1, SSL2, and SSL3).

[0067] The ground select transistor GST can be connected to the ground select line GSL. In one embodiment, different ground select transistors GST included in multiple memory cell strings MS of memory block BLK can be connected to the same ground select line GSL, but are not limited thereto, and can be connected to different ground select lines GSL.

[0068] Multiple memory cells MC1 to MCm constituting the memory cell string MS in the memory block BLK may have a structure in which they are connected in series in the Z-axis direction perpendicular to the main surface of the substrate. In the memory block BLK, multiple word lines WL may extend in the X-axis direction, and multiple bit lines BL may extend in the Y-axis direction.

[0069] Memory cells MC1 to MCm of the memory cell string MS can be connected to multiple word lines WL respectively. Each of the multiple memory cells MC1 to MCm can store one bit of data or two or more bits of data. In one embodiment, some memory cells of the multiple memory cells MC1 to MCm can be single-layer cells, while other memory cells of the multiple memory cells MC1 to MCm can be multi-layer cells. For example, the first memory cell MC1 of the multiple memory cells MC1 to MCm formed in the lowest layer (i.e., located closest to the substrate) and connected to the first word line WL1 can be a single-layer cell. Furthermore, for example, the m-th memory cell MCm of the multiple memory cells MC1 to MCm formed in the highest layer and connected to the m-th word line WLm can be a single-layer cell. The memory cells in the multiple memory cells MC1 to MCm formed in the highest and lowest layers (e.g., the first memory cell MC1 and the m-th memory cell MCm) can be formed as single-layer cells, thus improving data reliability.

[0070] In a series of memory cells MS, programming and reading operations can be performed on a page-by-page basis. A page can be a row of memory cells connected to a word line. In one example embodiment, each of the multiple memory cells MC1 to MCm can be selected on a page-by-page basis by a corresponding word line WL.

[0071] Figure 6A and Figure 6B This is a diagram illustrating the recycling operation of the storage device 100 according to an embodiment.

[0072] Reference Figure 2 and Figure 6A ,according to Figure 3The second memory block BLK2, whose reclamation event has occurred in operation S10, can be registered as a source block in the reclamation queue RQ. Information about the second memory block BLK2 can be stored in the reclamation queue RQ. In one embodiment, for each physical address (PA) of the plurality of pages PG1 to PGm included in the second memory block BLK2, a reclamation priority value can be stored in the reclamation queue RQ. For example, in the reclamation queue RQ, the reclamation priority of the first value PV1 corresponding to the fourth page PG4 can be set, the reclamation priority of the second value PV2 corresponding to the (m-1)th page PGm-1 can be set, and the reclamation priority of the third value PV3 corresponding to the other pages can be set.

[0073] In one embodiment, page 4 (PG4) can be a target memory region where a reclamation event has already occurred. In another embodiment, page (PGm-1) can be a memory region where a reclamation event is expected to occur.

[0074] The controller 110 can determine the order of reclamation operations for multiple pages PG1 to PGm included in the second memory block BLK2 based on reclamation priority values ​​stored in the reclamation queue RQ. For example, the first value PV1 may be larger than the second value PV2, and the second value PV2 may be larger than the third value PV3. The controller 110 can prioritize performing reclamation operations on memory regions with relatively large reclamation priority values. Figure 6A In this example, three different recycling priority values, PV1, PV2, and PV3, are described for ease of description, and the recycling priority values ​​can be set differently.

[0075] Controller 110 can read data from the fourth page PG4 of the second memory block BLK2 connected to the fourth word line WL4, and then move the read data to the first page PG1 of the destination block DB. Subsequently, controller 110 can read data from the (m-1)th page PGm-1 of the second memory block BLK2 connected to the (m-1)th word line WLm-1, and then move the read data to the second page PG2 of the destination block DB. The destination block DB can be one of the free blocks excluding the second memory block BLK2 from a plurality of memory blocks BLK1 to BLKn.

[0076] The controller 110 can perform recycling operations on pages with the same recycling priority value in row address order. For example, the recycling operation can be performed sequentially in the order of the first page PG1 of the second memory block BLK2 connected to the first word line WL1, the second page PG2 of the second memory block BLK2 connected to the second word line WL2, the third page PG3 of the second memory block BLK2 connected to the third word line WL3, and the m-th page PGm of the second memory block BLK2 connected to the m-th word line WLm, and data can be sequentially programmed into pages PG3 to PGm of the destination block DB. However, the storage device 100 according to the inventive concept is not limited to programming data in the destination block DB in bottom-up row address order. The storage device 100 can program data in the destination block DB in top-down row address order.

[0077] Reference Figure 2 and Figure 6B The controller 110 can move data programmed in a multi-level cell to a single-level cell, store 2 or more bits of data of a second memory block BLK2 as a source block in the multi-level cell, and store 1 bit of data of a destination block DB in the single-level cell.

[0078] For example, the fourth page PG4 and the (m-1)th page PGm-1 of the second memory block BLK2 may include multi-level cells storing 2 bits of data, while the first page PG1 and the second page PG2 of the destination block DB may include single-level cells storing 1 bit of data, and the third page PG3 of the destination block DB may include multi-level cells storing 2 bits of data. The controller 110 may read the fourth page PG4 of the second memory block BLK2 connected to the fourth word line WL4, and then move the data to the first page PG1 and the second page PG2 of the destination block DB. Subsequently, the controller 110 may read the (m-1)th page PGm-1 of the second memory block BLK2 connected to the (m-1)th word line WLm-1, and then move the data to the third page PG3 of the destination block DB. The above description may also apply when data moves from a three-level cell storing 3 bits of data to a single-level cell, or when data moves from a three-level cell to a multi-level cell storing 2 bits of data. Conversely, the above description may also apply when data moves from a single-level cell to a multi-level cell storing 2 or more bits of data.

[0079] Figure 7 This is a diagram illustrating the recycling operation of the storage device 100 according to an embodiment.

[0080] Reference Figure 1 and Figure 7 ,according to Figure 3In operation S10, the first memory block BLK1, the third memory block BLK3, and the nth memory block that have already undergone reclamation events can be registered as the first to third source blocks in the reclamation queue RQ, respectively. The physical address of the source block and the reclamation priority value corresponding to the physical address can be stored in the reclamation queue RQ. For example, in the reclamation queue RQ, the reclamation priority value of the first value PV1 corresponding to the first memory block BLK1 can be set, the reclamation priority value of the second value PV2 corresponding to the nth memory block BLKn can be set, and the reclamation priority value of the third value PV3 corresponding to the third memory block BLK3 can be set.

[0081] The controller 110 can determine the priority of reclamation operations among memory blocks registered in the reclamation queue RQ based on reclamation priority values ​​stored in the reclamation queue RQ. For example, a first value PV1 may be larger than a second value PV2, and a second value PV2 may be larger than a third value PV3. The controller 110 may prioritize performing reclamation operations on memory regions with relatively large reclamation priority values.

[0082] Controller 110 can read data from a first memory block BLK1, which serves as a first source block, move the data to a first destination block DB1, and then erase the first memory block BLK1. Next, controller 110 can read data from an nth memory block BLKn, which serves as a second source block, move the data to a second destination block DB2, and then erase the nth memory block BLKn. Then, controller 110 can read data from a third memory block BLK3, which serves as a third source block, move the data to a third destination block DB3, and then erase the third memory block BLK3. The first destination blocks DB1 to the third destination blocks DB3 can be included in a free block excluding the first memory block BLK1, the third memory block BLK3, and the nth memory block BLKn among the plurality of memory blocks BLK1 to BLKn.

[0083] When controller 110 performs a reclamation operation on each of the first memory block BLK1, the third memory block BLK3, and the nth memory block BLKn, refer to Figure 6A and Figure 6BThe provided description can be applied to the order of reclamation operations among multiple pages PG1 to PGm included in each of the first memory block BLK1, the third memory block BLK3, and the nth memory block BLKn. That is, among the multiple pages PG1 to PGm included in each of the first memory block BLK1, the third memory block BLK3, and the nth memory block BLKn, reclamation operations can be preferentially performed on pages that have already undergone reclamation events. Optionally, reclamation operations on multiple pages PG1 to PGm included in each of the first memory block BLK1, the third memory block BLK3, and the nth memory block BLKn can be performed in either bottom-up row address order or top-down row address order.

[0084] Figure 8 This is a flowchart illustrating an operation method of the storage device 100 according to an embodiment, and is... Figure 3 An example of operation S20. Operation S20 may include operations S21 through S25.

[0085] Reference Figure 1 and Figure 8 In operation S21, the storage device 100 may set a first value for a first memory region where a recycling event has occurred among the recycling operation targets. In one embodiment, the storage device 100 may determine that a recycling event has occurred in the first memory region when the error bit rate of data read from the first memory region is equal to or greater than a reference value, or when specific predetermined defense code is executed (to eliminate data errors) for retrying reads from the first memory region.

[0086] In operation S23, storage device 100 may set a second recycling priority value for a second memory region where a recycling event is expected to occur within the recycling operation target. For example, even if storage device 100 has not determined whether a recycling event has occurred, storage device 100 may set a second recycling priority value when a recycling event is highly likely to occur. In one embodiment, the second memory region where a recycling event is expected to occur may be a previously designated memory region or a memory region with low data reliability due to its physical structure. See below. Figure 9A , Figure 9B , Figure 10A and Figure 10B A description of the memory region where a reclamation event is expected to occur.

[0087] In operation S25, the storage device 100 may set a third value of recycling priority for a third memory region other than the target of the recycling operation (i.e., a third memory region where no recycling event has occurred and no recycling event is expected).

[0088] After performing operation S20, the storage device 100 may perform a reclamation operation on the first memory region, then on the second memory region, and finally on the third memory region having a third value. According to the inventive concept, the storage device 100 can first perform reclamation operations on memory regions where reclamation events have already occurred, and then perform reclamation operations on memory regions where reclamation events are expected to occur, thereby preventing data degradation.

[0089] Figure 9A and Figure 9B It is shown Figure 8 The diagram illustrates operation S23. Figure 9A and Figure 9B This is a diagram illustrating a method for identifying memory regions within multiple pages of a memory block where a reclamation event is expected to occur.

[0090] Reference Figure 9A It can be assumed that a read command (READ CMD) is issued for the second page PG2 of memory block BLK2. In this case, the READ CMD command may be issued due to a host read operation, or it may be issued due to a background read operation.

[0091] A read voltage can be applied to the second word line WL2 connected to the second page PG2 to read the second page PG2. Therefore, stress can be applied to each of the first word lines WL1 and the third word line WL3, which are adjacent to the second word line WL2, and the data programmed into the first page PG1 and the third page PG3, respectively connected to the first word line WL1 and the third word line WL3, may be corrupted. In other words, read disturbance can occur in the first page PG1 and the third page PG3.

[0092] Therefore, the first page PG1 and the third page PG3, connected to the word line adjacent to the second word line WL2 where the read operation is performed, can be stored in the metadata buffer (e.g., Figure 2 Degradation information in the memory region (MB) is managed separately as a memory region where a reclamation event is expected. Figure 9A In this description, only the first page PG1 and the third page PG3, which are directly adjacent to the first word line WL1 and the third word line WL3, respectively, are described; however, the inventive concept is not limited thereto. The fourth page PG4, which is connected to the fourth word line WL4, can also be identified as the memory region where a recycling event is expected to occur.

[0093] Reference Figure 5 and Figure 9BWhen the memory device is implemented as a NAND flash memory device having a vertical structure, the first word lines WL1 to the m-th word lines WLm can be formed to be stacked sequentially relative to the substrate in the Z-axis direction. The first pages PG1 to the m-th page PGm, which are respectively connected to the first word lines WL1 to the m-th word lines WLm, can also be formed to be stacked sequentially relative to the substrate.

[0094] The memory block BLK2 may include a bottom layer region BLA near the substrate, an intermediate layer region MLA disposed above the bottom layer region BLA, and a top layer region TLA disposed above the intermediate layer region MLA (i.e., the top layer region TLA furthest from the substrate). For example, the bottom layer region BLA may include the first page PG1 and the second page PG2, the top layer region TLA may include the (m-1)th page PGm-1 and the mth page PGm, and the intermediate layer region MLA may include the remaining pages.

[0095] Compared to the intermediate layer region MLA, pages included in the bottom layer region BLA (e.g., page PG1 and page PG2) can structurally have relatively low data reliability. Furthermore, compared to the intermediate layer region MLA, pages included in the top layer region TLA (e.g., page m-1 PGm-1 and page m PGm) can structurally have relatively low data reliability. Therefore, by storing data in a metadata buffer (e.g., ... Figure 2 The degradation information in the memory region (MB) includes pages in the lower-level region (BLA) that can be managed as memory regions where reclamation events are expected to occur, and pages in the top-level region (TLA) that can be managed as memory regions where reclamation events are expected to occur. In one example embodiment, the degradation information may include the page address of a page located in the lower-level region (BLA) or the page address of a page located in the top-level region (TLA). In one example embodiment, Figure 1 The controller 110 can treat the page address stored as degradation information as an expected reclamation event and check whether a reclamation event has already occurred on the page corresponding to the page address stored as degradation information.

[0096] Figure 10A and Figure 10B It is shown Figure 8 The diagram illustrates operation S23. Figure 10A and Figure 10B This is a diagram illustrating a method for identifying memory blocks among multiple memory blocks from which a reclamation event is expected to occur.

[0097] Reference Figure 5 and Figure 10A The memory cell array region (MCA) and the address decoder region (RDA) can be arranged side by side in the X-axis direction. The memory cell array 122 can be located in the memory cell array region (MCA), and the address decoder 123 can be located in the address decoder region (RDA).

[0098] The memory cell array region (MCA) may include a central region (CA) located at the center, and first edge regions (EA1) and second edge regions (EA2) located above and below the central region (CA). Compared to memory blocks arranged in the central region (CA), memory blocks arranged in the first edge regions (EA1) and second edge regions (EA2) may have relatively lower data reliability in structure. Therefore, memory blocks arranged in the first edge regions (EA1) and second edge regions (EA2) can be stored in a metadata buffer (e.g., Figure 2 The degradation information in the MB is managed as a memory region where a reclamation event is expected to occur. In one example embodiment, the degradation information may include the row address of a page located in a first edge region EA1 and a second edge region EA2. In one example embodiment, Figure 1 The controller 110 can treat the page address stored as degradation information as an expected reclamation event and check whether a reclamation event has already occurred on the page corresponding to the page address stored as degradation information.

[0099] Reference Figure 10B The degradation information MBLK1 to MBLKn of multiple memory blocks BLK1 to BLKn can be stored in the metadata buffer MB. For example, the erase counts EC1 to ECn of multiple memory blocks BLK1 to BLKn can be stored in the metadata buffer MB as degradation information MBLK1 to MBLKn respectively.

[0100] As the erase count increases, the corresponding memory block's degradation level can increase. Memory blocks with erase counts equal to or greater than a reference value can be managed separately as memory regions where reclamation events are expected. Using degradation information MBLK1 to MBLKn stored in the metadata buffer MB, a second memory block BLK2 with a high erase count (e.g., a second erase count EC2) can be managed separately as a memory region where reclamation events are expected.

[0101] Figure 11 This is a flowchart illustrating an operation method of the storage device 100 according to an embodiment, and is... Figure 3 An example of operation S30. Operation S30 may include operations S31 to S37. In one example embodiment, Figure 3 Operation S30 is the part of the reclamation operation performed on the source memory region, which includes the first memory region where a reclamation event has already occurred.

[0102] Reference Figure 1 and Figure 11In operation S31, the storage device 100 may perform a recycling operation on a first memory region where a recycling event has occurred. For example, the storage device 100 may perform a recycling operation on a first memory region having a recycling priority value of a first value. In operation S31, the storage device 100 may also perform a recycling operation on a second memory region where a recycling event is expected to occur (e.g., a memory region having a recycling priority value of a second value).

[0103] In operation S33, storage device 100 can determine whether there is a queue in the command queue (e.g., Figure 2 The command in the command queue (CQ). When a request REQ is received from the host 200, the command corresponding to the request REQ can be queued into the command queue CQ. If there are no commands queued in the command queue CQ, in operation S37, the storage device 100 can perform a reclamation operation on another memory region (e.g., a memory region where no reclamation event has occurred) to complete the reclamation operation on the source memory region.

[0104] If commands are queued in the command queue CQ, storage device 100 can perform operations according to the queued commands in operation S35. For example, when a read request is received from host 200 and thus the read command is queued in the command queue CQ, storage device 100 can perform a read operation before completing a reclamation operation on another memory region of the source memory region (e.g., a memory region where no reclamation event has occurred). Alternatively, for example, when a write request is received from host 200 and thus the write command is queued in the command queue CQ, storage device 100 can perform a write operation before completing a reclamation operation on another memory region of the source memory region (e.g., a memory region where no reclamation event has occurred).

[0105] When the REQ operation requested by the host 200 is completed in operation S35, in operation S37, the storage device 100 may perform a reclamation operation on other memory regions (i.e., third memory regions where no reclamation event has occurred (e.g., memory regions with a reclamation priority value of a third value)).

[0106] The storage device 100 according to the inventive concept can prioritize performing a reclamation operation on memory regions where reclamation events have occurred, then perform an operation according to a request REQ from the host 200, and after the operation according to the request REQ from the host 200, perform a reclamation operation on the remaining memory regions where no reclamation events have occurred, to complete the reclamation operation on the source memory regions. The invention is not limited thereto. In one example embodiment, the storage device 100 can prioritize performing a reclamation operation on memory regions where reclamation events have occurred, then perform an operation according to a request REQ from the host 200, and after the operation according to the request REQ from the host 200 is completed, perform reclamation operations on second and third memory regions different from the first memory region, to complete the reclamation operation on the source memory regions. In one example embodiment, the storage device 100 can prioritize performing reclamation operations on memory regions where reclamation events have occurred and memory regions where reclamation events are expected to occur, then perform an operation according to a request REQ from the host 200, and after the operation according to the request REQ from the host 200 is completed, perform a reclamation operation on the remaining memory regions where no reclamation events have occurred, to complete the reclamation operation on the source memory regions. Therefore, storage device 100 can prevent data from being degraded due to delays in the reclamation operation of memory regions where reclamation events have already occurred, and at the same time prevents the processing of REQ requests from host 200 from being delayed.

[0107] exist Figure 11 The description describes an embodiment in which a command based on a request REQ from host 200 is executed after a reclamation operation is performed on a first memory region and a second memory region; however, the storage device 100 according to the inventive concept is not limited thereto. In one embodiment, the storage device 10 may process a command based on a request REQ from host 200 after a reclamation operation has been performed on a first memory region where a reclamation event has occurred. Subsequently, the storage device 10 may perform a reclamation operation on a second memory region where a reclamation event is expected to occur.

[0108] Figure 12 This is a flowchart illustrating an operation method of the storage device 100 according to an embodiment, and is... Figure 3 Examples of operations S10 and S20.

[0109] Reference Figure 12 In operation S100, the host 200 may send a read request to the storage device 100.

[0110] Figure 3 Operation S10 may include operations S11 to S13. In operation S11, the storage device 100 may read data in response to a read request.

[0111] In operation S13, the storage device 100 may check for errors in the read data to determine whether a recycling event has occurred. In one embodiment, the storage device 100 may determine that a recycling event has occurred when the error bit rate of the read data is greater than or equal to a reference value. Optionally, in one embodiment, the storage device 100 may execute defense code via firmware to perform a read retry due to errors in the read data, and determine that a recycling event has occurred when the previously specified defense code is executed.

[0112] In operation S20', the storage device 100 may set a reclamation priority value for the memory region corresponding to the read request. For example, when it is determined in operation S13 that a reclamation event has occurred, the storage device 100 may set a priority value (e.g., a first value) to prioritize the reclamation operation on the memory region associated with the read request. Otherwise, when it is determined that a reclamation event has not occurred, the storage device 100 may set a later priority value (e.g., a third value) for the memory region corresponding to the read request.

[0113] Figures 13 to 16 This is a flowchart illustrating an operation method of the storage device 100 according to an embodiment, and is... Figure 3 Examples of operations S10 and S20. Figures 13 to 16 This is a diagram illustrating an embodiment of a storage device 100 performing a background read operation. This can be performed periodically regarding... Figures 13 to 16 Each operation is described. In Figures 13 to 16 In the middle, omission and Figure 12 Redundant descriptions using the same reference numerals.

[0114] Reference Figure 1 and Figure 13 Operation S10a may include operations S11a and S13. In operation S11a, the storage device 100 may read data in a memory region of a word line adjacent to the word line to which the read operation (background read operation) is performed. When the read operation is performed, a read voltage may be applied to a specific word line, and stress (read interference) may be generated on the word line adjacent to the specific word line. Therefore, the storage device 100 can determine whether a recycling event has occurred by reading the memory region of the word line adjacent to the word line to which the read operation is performed. In operation S13, the storage device 100 may check for errors in the data to determine whether a recycling event has occurred.

[0115] In operation S20a, the storage device 100 may set a recycling priority value for memory regions connected to adjacent word lines. For example, when it is determined in operation S13 that a recycling event has occurred, the storage device 100 may set a priority value (e.g., a first value) to prioritize recycling operations on memory regions connected to adjacent word lines. Otherwise, when it is determined that a recycling event has not occurred, the storage device 100 may set a later priority value (e.g., a third value) to memory regions connected to adjacent word lines.

[0116] Reference Figure 1 and Figure 14 Operation S10b may include operations S11b and S13. In operation S11b, the storage device 100 may read data from a memory area storing old data. After data is programmed, it may degrade over time. Therefore, when a reference time or longer has elapsed since the data was programmed, the storage device 100 may determine that the data is old data and determine whether a recycling event has occurred by reading the memory area storing the old data. In operation S13, the storage device 100 may check for errors in the data to determine whether a recycling event has occurred.

[0117] In operation S20b, the storage device 100 can set a recycling priority value for the memory region storing old data. For example, when it is determined in operation S13 that a recycling event has occurred in the memory region storing old data, the storage device 100 can set a priority value to prioritize the recycling operation on the memory region storing old data. Otherwise, when it is determined that no recycling event has occurred, the storage device 100 can set a later priority value for the memory region storing old data.

[0118] Reference Figure 1 and Figure 15 Operation S10c may include operations S11c and S13. In operation S11c, the storage device 100 may read data from a previously specified memory region. The previously specified memory region may be an array of memory cells due to non-volatile memory (e.g., ...). Figure 4 The physical structure of memory regions (122) may lead to low data reliability. Information about previously specified memory regions can be stored as degradation information in the metadata buffer MB.

[0119] For example, such as regarding Figure 9B The previously specified memory region may be a page included in the lower-level region BLA or the upper-level region TLA of a memory block. Alternatively, for example, as referenced... Figure 10AThe previously specified memory region can be a memory block located in the first edge region EA1 and the second edge region EA2. In operation S13, the storage device 100 can check for errors in data read from the bottom layer region BLA or the top layer region TLA to determine if a reclamation event has occurred.

[0120] In operation S20c, storage device 100 can set a recycling priority value for a previously specified memory region. For example, when it is determined in operation S13 that a recycling event has occurred, storage device 100 can set a priority value for the priority order, such that the recycling operation is performed on the previously specified memory region first. Otherwise, when it is determined that a recycling event has not occurred, storage device 100 can set a later priority value for the previously specified memory region.

[0121] Reference Figure 1 and Figure 16 Operation S10d may include operations S11d and S13. In operation S11d, the storage device 100 may randomly select a memory region from a plurality of memory regions to read data from the selected memory region. For example, the storage device 100 may read data from... Figure 4 The storage device 100 randomly selects the second page PG2 from the first page PG1 to the m-th page PGm to read data. In operation S13, the storage device 100 can check for errors in the data to determine whether a recycling event has occurred.

[0122] In operation S20d, the storage device 100 can set a recycling priority value for the selected memory region. For example, when it is determined in operation S13 that a recycling event has occurred, the storage device 100 can set a priority value for the order of priority, such that the recycling operation is performed on the selected memory region first. Otherwise, when it is determined that a recycling event has not occurred, the storage device 100 can set a later priority value for the selected memory region.

[0123] Figure 17 This illustrates an embodiment. Figure 1 A block diagram of the grouping of superblocks SPB in non-volatile memory 120.

[0124] Reference Figure 1 and Figure 17 The memory device NVM1, which communicates with the controller 110 via the first channel CH1, may include first memory devices 120_1 to j-th memory devices 120_j (j is an integer greater than or equal to 2). The first memory devices 120_1 to j-th memory devices 120_j may each include n memory blocks BLK_11 to BLK_1n, BLK_21 to BLK_2n, and BLK_j1 to BLK_jn.

[0125] In the first memory devices 120_1 to the j-th memory devices 120_j, blocks allocated with the same address (or located at the same position) can be grouped into a superblock SPB. For example, the second memory blocks BLK_12, BLK_22 and BLK_j2 of the first memory devices 120_1 to the j-th memory devices 120_j can be grouped into a superblock SPB.

[0126] In one embodiment, storage device 100 may perform reclamation operations on a superblock (SPB) basis. For example, when reclamation events have occurred in the second page PG2, the fourth page PG4, and the (m-1)th page PGm-1 of the second memory block BLK_j2 included in the j-th memory device 120_j, the second memory blocks BLK_12 and BLK_22 included in the superblock (SPB) may be registered together with the second memory block BLK_j2 of the j-th memory device 120_j in the reclamation queue (e.g., Figure 7 In the RQ, it is used as the source block.

[0127] Such as about Figure 6A and Figure 7 The physical address of the source block and the corresponding reclamation priority value can be stored in the reclamation queue RQ. For example, the reclamation priority values ​​corresponding to the second memory blocks BLK_12, BLK_22, and BLK_j2 can be set in the reclamation queue RQ. The controller 110 can perform reclamation operations based on the reclamation priority values ​​stored in the reclamation queue RQ.

[0128] For example, the priority value for reclamation (e.g., a first value PV1) can be set to the second memory block BLK_j2 of the j-th memory device 120_j that has already undergone a reclamation event, and the reclamation operation can be performed on the second memory block BLK_j2 with higher priority than other memory blocks of the j-th memory device 120_j. Furthermore, for example, the reclamation priority value PV1 can be set to the second page PG2, the fourth page PG4, and the (m-1)th page PGm-1 of the second memory block BLK_j2 of the j-th memory device 120_j, and the reclamation operation can be performed on the second page PG2, the fourth page PG4, and the (m-1)th page PGm-1 of the second memory block BLK_j2 with higher priority than other pages of the second memory block BLK_j2.

[0129] For example, a later-order recycling priority value (e.g., the third value PV3) can be set to the second memory block BLK_12 of the first memory device 120_1 where no recycling event has occurred, and the first memory device 120_1 can perform a recycling operation after performing an operation in accordance with the request REQ from the host 200.

[0130] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A method of operating a storage device, comprising: Detect whether a reclamation event has occurred in a source memory block comprising multiple memory regions within multiple memory blocks, where each memory block is the unit of the erase operation; Set the recycling priority value to each of the plurality of memory regions in the source memory block; and Based on the reclamation priority value of each of the plurality of memory regions, a reclamation operation is performed on each of the plurality of memory regions in the source memory block. The reclamation operation moves data stored in the source memory block to the destination memory block, and The step of setting the recycling priority value includes: in response to detecting that a recycling event has occurred in a first memory region among the plurality of memory regions, setting a first recycling priority value to the first memory region; in response to detecting that a recycling event is expected to occur in a second memory region among the plurality of memory regions, setting a second recycling priority value to the second memory region; and in response to detecting that no recycling event has occurred in a third memory region among the plurality of memory regions and detecting that no recycling event is expected to occur in the third memory region, setting a third recycling priority value to the third memory region.

2. The operating method according to claim 1 further includes: Generate commands based on the host's request. The steps for performing a reclamation operation on the source memory block include: Before processing the request command from the host, a reclamation operation is performed on the first memory region; and After completing the processing command, a reclamation operation is performed on the third memory region in the source memory block that is different from the first memory region.

3. The operating method according to claim 1, in, The steps for detecting whether a reclamation event has occurred in the source memory block include: Receive a read request from the host for the first memory region of the source memory block; Perform a first read operation to read data from a first memory region according to a read request; and The presence of a reclamation event in the first memory region is determined by examining the data read from the first memory region for errors.

4. The operating method according to claim 1, in, The steps for detecting whether a reclamation event has occurred in the source memory block include: Data is read from a first memory region, wherein the first memory region is connected to an adjacent word line of the word line to which a read operation has been performed; and The presence of a reclamation event in the first memory region is determined by examining the data read from the first memory region for errors.

5. The operating method according to claim 1, in, The steps for detecting whether a reclamation event has occurred in the source memory block include: Data is read from the first memory region of the source memory block, wherein the first memory region is a previously specified memory region based on degradation information; and The presence of a reclamation event in the first memory region is determined by examining the data read from the first memory region for errors.

6. The operating method according to claim 5, in, The storage device includes a plurality of memory cells arranged in a direction perpendicular to the main surface of the substrate. The first memory region corresponds to the memory region of the source memory block, and the memory region is formed by memory cells formed in the bottom layer closest to the substrate.

7. The operating method according to claim 5, in, The storage device includes a plurality of memory cells arranged in a direction perpendicular to the main surface of the substrate. The first memory region corresponds to the memory region of the source memory block, and the memory region is formed by memory cells formed in the top layer furthest from the substrate.

8. The operating method according to claim 1, in, The steps for detecting whether a reclamation event has occurred in the source memory block include: Data is read from a first memory region, which is randomly selected from the plurality of memory regions included in the storage device; and The determination of whether a reclamation event has occurred in the first memory region of the source memory block is made by checking for errors in the data read from the first memory region.

9. The operating method according to any one of claims 1 to 8, in, The steps for performing a recycling operation include moving data from multiple multi-level cells included in the source memory block to multiple single-level cells included in the destination memory block.

10. A storage device, comprising: Non-volatile memory devices; and The controller is configured as follows: Detect whether a reclamation event has occurred in a source memory block among multiple memory blocks in a non-volatile memory device, wherein the source memory block comprises multiple memory regions, and each memory block is a unit of erase operation; Set the reclamation priority value to each of the plurality of memory regions in the source memory block; and Based on the reclamation priority value of each of the plurality of memory regions, a reclamation operation is performed on each of the plurality of memory regions in the source memory block. The controller is configured to: in response to detecting that a recycling event has occurred in a first memory region among the plurality of memory regions, set a first recycling priority value to the first memory region; and in response to detecting that a recycling event is expected to occur in a second memory region among the plurality of memory regions, set a second recycling priority value to the second memory region.

11. The storage device according to claim 10, in, The controller is configured as follows: A first read operation is performed on the first memory region according to a read request received from the host; Read data from a second memory region adjacent to the first memory region that has already performed the first read operation; and The presence of a reclamation event in the second memory region is determined by examining the data read from the second memory region for errors. Each of the first memory region and the second memory region corresponds to a page of the source memory block.

12. The storage device according to claim 10, in, The non-volatile storage device includes a plurality of storage cells arranged in a direction perpendicular to the main surface of the substrate. The controller includes a metadata buffer configured to store row addresses of memory cells formed in the underlying layer closest to the main surface of the substrate as degradation information. The controller is configured to detect whether a reclamation event has occurred in the underlying memory cells of the source memory block, based on degradation information stored in the metadata buffer.

13. The storage device according to claim 10, in, The non-volatile storage device includes a plurality of storage cells arranged in a direction perpendicular to the main surface of the substrate, and The controller includes a metadata buffer configured to store row addresses of memory cells formed in the top layer, furthest from the substrate, as degradation information. The controller is configured to detect whether a reclamation event has occurred in the top-level memory cell of the source memory block, based on degradation information stored in the metadata buffer.

14. The storage device according to claim 10, in, Non-volatile storage devices include memory cell array regions having multiple memory cells. The memory cell array is divided into a central region, a first edge region, and a second edge region, with the first and second edge regions located on opposite sides of the central region. The controller includes a metadata buffer configured to store row addresses of memory cells formed in the first and second edge regions as degradation information. The controller is configured to detect whether a reclamation event has occurred in the first and second edge regions of the source memory block based on degradation information stored in the metadata buffer.

15. The storage device according to claim 10, in, The controller includes: a metadata buffer configured to store erase counts of a first memory region as degradation information, and The controller is configured to detect whether a reclamation event has occurred in the first memory region of the source memory block based on degradation information stored in the metadata buffer.

16. The storage device according to claim 10, in, The controller is configured as follows: Based on the host's request, a command is sent to the non-volatile memory device; Before executing commands on the non-volatile memory device, a reclamation operation is performed on the first memory region; and The command is processed after the reclamation operation of the first memory region is completed and before the reclamation operation of the second memory region is performed.

17. The storage device according to any one of claims 10 to 16, in, The non-volatile memory device includes multiple memory devices configured to communicate with the controller via the same channel. Among these, memory regions with the same address in the plurality of memory devices are grouped into superblocks, and The controller is also configured to control recycling operations in units of superblocks.

18. A memory device, comprising: A memory cell array includes: a plurality of memory blocks, each of the plurality of memory blocks comprising a plurality of pages; and The control logic circuitry is configured to generate control signals for performing reclamation operations on a block-by-block basis. The control logic circuit is configured to perform a reclamation operation by moving the data of each page of the source block among the plurality of memory blocks to the destination block among the plurality of memory blocks, based on the reclamation priority value of each page. The control logic circuit is configured to: in response to detecting that a recycling event has occurred on the first page among the plurality of pages, set a first recycling priority value to the first page; in response to detecting that a recycling event is expected to occur on the second page among the plurality of pages, set a second recycling priority value to the second page; and in response to detecting that a recycling event has not occurred on the third page among the plurality of pages and detecting that a recycling event is not expected to occur on the third page, set a third recycling priority value to the third page.

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