Three-dimensional storage device and method

Abstract

In an embodiment, a device includes: a word line extending in a first direction; a data storage layer located on a sidewall of the word line; a channel layer located on a sidewall of the data storage layer; a back gate spacer located on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region being separated from the channel layer by the back gate spacer, and the bit line extending in a second direction, the second direction being perpendicular to the first direction. Embodiments of the present application provide a three-dimensional memory device and method.

Description

Technical Field

[0001] Embodiments of the present application relate to three-dimensional memory devices and methods. Background Art

[0002] Semiconductor memory is used in integrated circuits for electronic applications including, for example, radios, televisions, cell phones, and personal computer devices. Semiconductor memory includes two main categories. One is volatile memory and the other is non-volatile memory. Volatile memory includes random access memory (RAM), which can also be divided into two subcategories, static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they lose the stored information when power is lost.

[0003] On the other hand, nonvolatile memory can retain data stored therein. One type of nonvolatile semiconductor memory is ferroelectric random access memory (FeRAM). Advantages of FeRAM include fast read / write speeds and small size. Summary of the invention

[0004] An embodiment of the present application provides a device, comprising: a word line extending along a first direction; a data storage layer located on the sidewalls of the word line; a channel layer located on the sidewalls of the data storage layer; a back gate isolation member located on the sidewalls of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region being separated from the channel layer by the back gate isolation member, and the bit line extending along a second direction, the second direction being perpendicular to the first direction.

[0005] An embodiment of the present application provides a device, including: a bit line extending along a first direction, the bit line having a first T-shaped cross-section when viewed from top to bottom; a source line extending along the first direction, the source line having a second T-shaped cross-section when viewed from top to bottom; an isolation region located between the source line and the bit line; a word line extending along a second direction, the second direction being perpendicular to the first direction; a back gate spacer located between the word line and each of the isolation region, the first portion of the bit line and the second portion of the source line; a channel layer located between the back gate spacer and the word line; and a data storage layer located between the channel layer and the word line.

[0006] An embodiment of the present application also provides a method, comprising: forming a word line between a pair of first dielectric layers; depositing a data storage layer on the sidewalls of the first dielectric layer and the sidewalls of the word line; depositing a channel layer on the sidewalls of the data storage layer; depositing a first dielectric layer on the sidewalls of the channel layer; forming a first isolation region on the sidewalls of the first dielectric layer; removing a first portion of the first isolation region, retaining a second portion of the first isolation region after removal; after removing the first portion of the first isolation region, patterning the first dielectric layer to form a back gate isolation member; and forming a bit line and a source line on the opposite side of the second portion of the first isolation region, the back gate isolation member separating the channel layer from the first portion of the bit line and the second portion of the source line. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A , Figure 1B and Figure 1C are various views of the memory array.

[0009] Figures 2 to 19C are various views of intermediate stages in the fabrication of a memory array according to some embodiments.

[0010] FIG. 20A to FIG. 20J is a diagram of an intermediate stage in the fabrication of a staircase structure for a memory array, according to some embodiments.

[0011] FIG. 21A to FIG. 21D is a top view of a memory array according to some embodiments.

[0012] FIG. 22A to FIG. 22C is a top view of a memory array according to some embodiments.

[0013] Fig.23 is a cross-sectional view of a memory array according to some other embodiments.

[0014] Fig.24 is a cross-sectional view of a semiconductor device according to some embodiments.

[0015] Figure 25 to Figure 27 are various views of intermediate stages in the fabrication of a memory array according to some other embodiments. DETAILED DESCRIPTION

[0016] The following disclosure provides a variety of different embodiments or examples to implement different features of the present invention. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are only examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. Moreover, the present invention may repeat reference numbers and / or letters in various examples. This repetition is only for simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0018] According to various embodiments, a three-dimensional memory array is formed by transistors (such as programmable thin film transistors (TFTs)) having bit lines and source lines with extension regions. The extension region serves as a back gate. The data storage layer and the channel layer of the transistor are disposed between the back gate and the word line of the transistor. During a write operation (e.g., an erase or program operation) of the transistor, the back gate can help control (e.g., reduce) the surface potential of the channel layer. Reducing the surface potential of the channel layer can help improve the performance of the memory array.

[0019] Figure 1A , Figure 1B and Figure 1C An example of a memory array 50 is shown in accordance with some embodiments. Figure 1A An example of a portion of a memory array 50 is shown in a three-dimensional view; Figure 1B A circuit diagram showing a memory array 50; Figure 1C A top view of a portion of a memory array 50 is shown. The memory array 50 includes a plurality of memory cells 52, which may be arranged in a grid of rows and columns. The memory cells 52 may be further stacked vertically to provide a three-dimensional memory array, thereby increasing device density. The memory array 50 may be disposed in the back end of line (BEOL) of a semiconductor die. For example, the memory array 50 may be disposed in an interconnect layer of a semiconductor die, such as above one or more active devices (e.g., transistors) formed on a semiconductor substrate.

[0020] In some embodiments, the memory array 50 is a memory array such as a NOR memory array. Each memory cell 52 may include a transistor 54 (such as a TFT) having an insulating memory film 84 as a gate dielectric. In some embodiments, the gate of each transistor 54 is electrically coupled to a corresponding word line (e.g., conductor 72), the first source / drain region of each transistor 54 is electrically coupled to a corresponding bit line (e.g., conductor 64B), and the second source / drain region of each transistor 54 is electrically coupled to a corresponding source line (e.g., conductor 64S), which electrically grounds the second source / drain region. Memory cells 52 in the same horizontal row of the memory array 50 may share a common word line, and memory cells 52 in the same vertical column of the memory array 50 may share a common source line and a common bit line.

[0021] The memory array 50 includes a plurality of vertically stacked conductive lines 72 (eg, word lines), with a dielectric layer 62 disposed between adjacent conductive lines 72. The conductive lines 72 are arranged parallel to the underlying substrate ( Figure 1A and Figure 1B The conductor 72 may be part of a stepped structure, such that the lower conductor 72 is longer than the upper conductor 72 and extends laterally beyond the end point of the upper conductor 72. For example, Figure 1A , a stack of multiple layers of conductive lines 72 are shown, with the topmost conductive line 72 being the shortest and the bottommost conductive line 72 being the longest. The respective lengths of conductive lines 72 may increase in a direction toward the underlying substrate. In this manner, a portion of each conductive line 72 may be accessed from above the memory array 50, and a conductive contact 66 may be made to the exposed portion of each conductive line 72 (see FIG. Figure 1C ). In embodiments where memory array 50 is disposed in an interconnect layer of a semiconductor die, conductive contact 66 may be, for example, interconnect 68 that connects an exposed portion of conductive line 72 to an overlying interconnect layer (see Figure 1C ) through holes.

[0022] The memory array 50 also includes a plurality of conductive lines 64B (e.g., bit lines) and conductive lines 64S (e.g., source lines). The conductive lines 64B and 64S may each extend in a direction D3 perpendicular to the conductive line 72. An isolation region 74 is disposed between the conductive lines 64B and 64S and isolates adjacent conductive lines 64B and 64S. The paired conductive lines 64B and 64S together with the intersecting conductive lines 72 define the boundaries of each memory cell 52, and an isolation region 76 is disposed between and isolates adjacent paired conductive lines 64B and 64S. In some embodiments, the conductive line 64S is electrically grounded. Although Figure 1A A particular placement of conductor 64B relative to conductor 64S is shown, but it should be understood that in other embodiments, the placement of conductors 64B, 64S may be reversed.

[0023] The memory array 50 may further include a semiconductor layer 82. The semiconductor layer 82 may provide a channel region for the transistor 54 of the memory cell 52. For example, when an appropriate voltage (e.g., higher than a corresponding threshold voltage (V th )), the area of ​​semiconductor layer 82 that intersects conductive line 72 may allow current to flow from conductive line 64B to conductive line 64S (eg, in the direction indicated by arrow 56).

[0024] The memory film 84 is disposed between the conductive line 72 and the semiconductor layer 82, and the memory film 84 can provide a gate dielectric for the transistor 54. In some embodiments, the memory film 84 includes a ferroelectric material, such as hafnium oxide, zirconium oxide, silicon-doped hafnium oxide, etc. Therefore, the memory array 50 can also be referred to as a ferroelectric random access memory (FERAM) array. Alternatively, the memory film 84 can be a multi-layer structure including a silicon nitride layer between two silicon oxide layers (e.g., an oxide-nitride-oxide (ONO) structure), different ferroelectric materials, different types of memory layers (e.g., capable of storing bits), etc.

[0025] In an embodiment where the memory film 84 includes a ferroelectric material, the memory film 84 can be polarized in one of two different directions, and the polarization direction can be changed by applying an appropriate voltage difference across the memory film 84 and generating an appropriate electric field. The polarization can be relatively local (e.g., typically contained within each boundary of the memory cell 52), and a continuous region of the memory film 84 can extend across multiple memory cells 52. Depending on the polarization direction of a particular region of the memory film 84, the threshold voltage of the corresponding transistor 54 changes, and a digital value (e.g., 0 or 1) can be stored. For example, when a region of the memory film 84 has a first electrical polarization direction, the corresponding transistor 54 can have a relatively low threshold voltage, and when a region of the memory film 84 has a second electrical polarization direction, the corresponding transistor 54 can have a relatively high threshold voltage. The difference between the two threshold voltages can be referred to as a threshold voltage shift. A larger threshold voltage shift makes it easier (e.g., less prone to error) to read the digital value stored in the corresponding memory cell 52.

[0026] In such an embodiment, in order to perform a write operation on the memory cell 52, a write voltage is applied to the portion of the memory film 84 corresponding to the memory cell 52. The write voltage can be applied by, for example, applying an appropriate voltage to the corresponding conductive line 72 (e.g., word line) and the corresponding conductive lines 64B, 64S (e.g., bit line / source line). By applying a write voltage to a portion of the memory film 84, the polarization direction of the region of the memory film 84 can be changed. As a result, the corresponding threshold voltage of the corresponding transistor 54 can also be switched from a low threshold voltage to a high threshold voltage, and vice versa, and a digital value can be stored in the memory cell 52. Because the conductive line 72 intersects with the conductive lines 64B, 64S, a single memory cell 52 can be selected for a write operation.

[0027] In such an embodiment, to perform a read operation on the memory cell 52, a read voltage (a voltage between the low threshold voltage and the high threshold voltage) is applied to the corresponding conductive line 72 (e.g., a word line). Depending on the polarization direction of the corresponding region of the memory film 84, the transistor 54 of the memory cell 52 may be turned on or off. As a result, the conductive line 64B may be discharged or not discharged through the conductive line 64S (e.g., a grounded source line), and the digital value stored in the memory cell 52 may be determined. Because the conductive line 72 intersects the conductive lines 64B and 64S, a single memory cell 52 may be selected for a read operation.

[0028] Figure 1A Reference cross sections of memory array 50 used in subsequent figures are further illustrated. Cross section BB' is along the longitudinal axis of conductive line 72 and in direction D1, e.g., parallel to the current flow direction of transistor 54. Cross section CC' is perpendicular to cross section BB' and in direction D2, e.g., perpendicular to the longitudinal axis of conductive line 72. For clarity, subsequent figures refer to these reference cross sections.

[0029] Figures 2 to 19C 5 is a diagram of an intermediate stage in the fabrication of a memory array 50 according to some embodiments. Each memory cell 52 of the memory array 50 includes a transistor 54 (see Fig.19B and Fig.19C ). Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 and Fig.19A is a three-dimensional view. Fig.19B It is along Figure 1A A cross-sectional view shown in reference section BB'. Fig.19C It is along Figure 1A The cross-sectional view shown in the reference section CC' in FIG. shows a portion of the memory array 50. For clarity, some components, such as the staircase arrangement of word lines (see FIG. 5 ), are not shown in some figures. Figure 1A ).

[0030] exist Figure 2 In the embodiment of the present invention, a substrate 102 is provided. The substrate 102 may be a doped (e.g., doped with a p-type or n-type dopant) or undoped semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc. The substrate 102 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. For example, the insulator layer may be a buried oxide (BOX) layer, a silicon oxide layer, etc. An insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates such as multilayer or gradient substrates may also be used. In some embodiments, the semiconductor material of the substrate 102 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, potassium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. The substrate 102 may include a dielectric material. For example, substrate 102 may be a dielectric layer, or may include a dielectric layer on a semiconductor substrate. Acceptable dielectric materials for substrate 102 include oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, etc. In some embodiments, substrate 102 is formed of silicon carbide.

[0031] The multilayer stack 104 is formed over the substrate 102. The multilayer stack 104 includes alternating dielectric layers 106 and sacrificial layers 108. The dielectric layers 106 are formed of a first dielectric material, and the sacrificial layers 108 are formed of a second dielectric material. The dielectric materials can each be selected from candidate dielectric materials of the substrate 102. The multilayer stack 104 will be patterned in a subsequent process. In this way, the dielectric materials of the dielectric layers 106 and the sacrificial layers 108 both have a higher etching selectivity than the etching of the material of the substrate 102. The patterned dielectric layer 106 will be used to isolate transistors to be formed subsequently. The patterned sacrificial layer 108 can also be referred to as a dummy layer, and will be selectively replaced by the word line of the transistor in a subsequent process. In this way, the second dielectric material of the sacrificial layer 108 also has a high etching selectivity relative to the etching of the first dielectric material of the dielectric layer 106. In an embodiment where the substrate 102 is formed of silicon carbide, the dielectric layer 106 can be formed of silicon oxide, and the sacrificial layer 108 can be formed of silicon nitride. Other combinations of dielectric materials having acceptable etch selectivities to each other may also be used.

[0032] Each layer of the multilayer stack 104 may be formed by an acceptable deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The thickness of each layer may be in the range of about 40 nm to about 50 nm. In some embodiments, the dielectric layer 106 is formed to have a different thickness than the sacrificial layer 108. For example, the sacrificial layer 108 may be formed to have a thickness greater than the dielectric layer 106. In the illustrated embodiment, the multilayer stack 104 includes five dielectric layers 106 and four sacrificial layers 108. It should be understood that the multilayer stack 104 may include other numbers of dielectric layers 106 and sacrificial layers 108. The multilayer stack 104 may have a total height H1 in the range of about 1000 nm to about 10000 nm.

[0033] As will be discussed in more detail below, Figures 3 to 10 A process is shown in which a multiple patterning process is used to form some components of a transistor. The multiple patterning process may be a double patterning process, a quadruple patterning process, etc. Figures 3 to 10 In the double patterning process, a first etching process is used to pattern the groove 110A in the portion of the multilayer stack 104 (see FIG. Figure 3 ), and components for a first subset of transistors are formed in trench 110A. Trenches 110B are then patterned in other portions of multilayer stack 104 by a second etching process (see Figure 7), and forming a component for a second subset of transistors in trench 110B. Forming the components of the transistors by a multiple patterning process allows each patterning process to be performed at a lower pattern density, which can help reduce defects while still allowing the memory array 50 to have a sufficient memory cell density. In addition, forming the components of the transistors by a multiple patterning process also allows each patterned portion of the multilayer stack 104 to avoid having an excessively large aspect ratio, thereby improving the structural stability of the resulting memory array. As will be discussed in more detail below (see Figure 25 to Figure 27 ), a single patterning process can also be used to form some components of the transistor.

[0034] exist Figure 3 , a trench 110A is patterned in the multilayer stack 104. In the illustrated embodiment, the trench 110A extends through the multilayer stack 104 and exposes the substrate 102. In another embodiment, the trench 110A extends through some but not all layers of the multilayer stack 104. The trench 110A may be patterned using acceptable photolithography and etching techniques, such as using an etching process that is selective to the multilayer stack 104 (e.g., selectively removing the dielectric material of the dielectric layer 106 and the sacrificial layer 108 at a faster rate than the material of the substrate 102). The etching may be any acceptable etching process such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching may be anisotropic. In an embodiment where the substrate 102 is formed of silicon carbide, the dielectric layer 106 is formed of silicon oxide, and the sacrificial layer 108 is formed of silicon nitride, the trench 110A may be formed by dry etching using a fluorine-based gas (e.g., C4F6) mixed with hydrogen (H2) or oxygen (O2). After patterning, the corresponding portion of the multilayer stack 104 is disposed between the corresponding grooves 110A. Each portion of the multilayer stack 104 is disposed between the corresponding grooves 110A in the second direction D2 (see FIG. Figure 1A and Figure 1B ) has a width W1 in the second direction, which may be in the range of about 50 nm to about 500 nm. In addition, each portion of the multilayer stack 104 is separated by a separation distance S1 in the second direction D2, which may be in the range of about 50 nm to about 200 nm.

[0035] exist Figure 4, the trench 110A is expanded to form a sidewall recess 112A. Specifically, the portion of the sidewall of the sacrificial layer 108 exposed by the trench 110A is grooved from the portion of the sidewall of the dielectric layer 106 exposed by the trench 110A to form the sidewall recess 112A. Although the sidewalls of the sacrificial layer 108 are shown as being straight, the sidewalls may be concave or convex. The sidewall recess 112A may be formed by an acceptable etching process, such as an etching process that is selective to the material of the sacrificial layer 108 (e.g., selectively removing the material of the sacrificial layer 108 at a faster rate than the material of the dielectric layer 106 and the substrate 102). The etching may be isotropic. In an embodiment where the substrate 102 is formed of silicon carbide, the dielectric layer 106 is formed of silicon oxide, and the sacrificial layer 108 is formed of silicon nitride, the trench 110A may be expanded by wet etching using phosphoric acid (H3PO4). In another embodiment, a dry etch that is selective to the material of the sacrificial layer 108 may be used.

[0036] After being formed, the side wall recess 112A is Figure 1A and Figure 1B ) has a depth D4 that extends beyond the sidewalls of the dielectric layer 106. The timed etching process can be used to stop etching the sidewall recess 112A after the sidewall recess 112A reaches the desired depth D4. For example, the sidewall recess 112A can have a depth D4 in the range of about 10nm to about 60nm. Forming the sidewall recess 112A can reduce the width of the sacrificial layer 108 by about 5% to about 25%. Continuing with the previous example, after etching, the sacrificial layer 108 can have a width W2 in the second direction D2, which can be in the range of about 50nm to about 450nm.

[0037] exist Figure 5 In the embodiment, conductive features 114A (e.g., metal lines) are formed in sidewall recesses 112A, thereby completing the process for replacing the first portion of sacrificial layer 108. Conductive features 114A may each include one or more layers, such as a seed layer, a glue layer, a barrier layer, a diffusion layer, a filling layer, etc. In some embodiments, conductive features 114A each include a seed layer 114A. S (or barrier layer) and main layer 114A M Each seed layer 114A S Along the corresponding main layer 114A located in the corresponding side wall recess 112A M The seed layer 114A extends from three sides (eg, top surface, sidewall, and bottom surface). S Formed from a first conductive material that can be used to aid growth or adhesion of subsequently deposited materials, such as metal nitrides, such as titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, hafnium nitride, etc. Main layer 114A MThe seed layer 114A may be formed of a second conductive material, such as a metal, such as tungsten, ruthenium, molybdenum, cobalt, aluminum, nickel, copper, silver, gold, alloys thereof, etc. S The material of the main layer 114A is a material having good adhesion to the material of the dielectric layer 106, and M The material of the seed layer 114A is S In the embodiment where the dielectric layer 106 is formed of an oxide such as silicon oxide, the seed layer 114A S The main layer 114A may be formed of titanium nitride or tantalum nitride. M The seed layer 114A may be formed of tungsten. S and main floor 114A M The material of the dielectric layer 106 may be formed by an acceptable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. An acceptable etching process, such as dry etching (e.g., reactive ion etching (RIE), neutral beam etching (NBE), etc.), wet etching, etc., or a combination thereof, may be performed to remove excess material from the sidewalls of the dielectric layer 106 and the top surface of the substrate 102. The etching may be anisotropic. Each conductive feature 114A may have a thickness that is consistent with the sacrificial layer 108 (on the top surface of the conductive feature 114A). Figure 2 ) and may have a similar overall thickness to the sidewall recess 112A (discussed above for Figure 4 The total width of each seed layer 114A is similar to the depth D4 discussed above. S The main layer 114A may have a thickness in the range of about 1 nm to about 10 nm, and each main layer 114A M The seed layer 114A may have a thickness in the range of about 15 nm to about 35 nm. S The thickness is greater than the main layer 114A M Thickness.

[0038] exist Figure 6 In the embodiment, a memory film 116A, a semiconductor layer 118A, a back gate spacer 120A, and an isolation region 122A are formed in the trench 110A. The semiconductor layer 118A and the back gate spacer 120A are formed above the memory film 116A. The isolation region 122A extends through the semiconductor layer 118A, thereby extending in the direction D2 (see FIG. Figure 1A and Figure 1B ) separates the semiconductor layer 118A of the horizontally adjacent transistors. In the illustrated embodiment, the isolation region 122A is formed above the memory film 116A. In another embodiment, the isolation region 122A also extends through the memory film 116A and the substrate 102, thereby separating the memory films 116A of the horizontally adjacent transistors along the direction D2.

[0039] The portion of the memory film 116A provides a data storage layer for the transistor, and the portion of the semiconductor layer 118A provides a channel region for the transistor. As will be discussed in more detail below, the back gate spacer 120A will be patterned and used to help form the T-shaped source / drain region of the transistor. The T-shaped source / drain region has a main region and an extension region. The back gate spacer 120A will be patterned so that the main source / drain region can contact the semiconductor layer 118A, but the source / drain extension region is separated from the portion of the semiconductor layer 118A that provides the channel region, thereby preventing short-circuiting the channel region. The source / drain extension region can be used as a back gate to help control (e.g., reduce) the surface potential of the semiconductor layer 118 (particularly the portion at the far end of the word line 114 of the semiconductor layer 118) during the write operation. Therefore, the window of the write operation can be widened.

[0040] The memory film 116A is formed of an acceptable material for storing digital values. In some embodiments, the memory film 116A is formed of a high-k ferroelectric material, such as hafnium zirconium oxide (HfZrO); zirconium oxide (HfZrO); hafnium oxide (HfO) doped with lanthanum (La), silicon (Si), aluminum (Al), etc.; undoped hafnium oxide (HfO); etc. In some embodiments, the memory film 116A includes one or more low-k dielectric materials, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The material of the memory film 116A can be formed by an acceptable deposition process such as ALD, CVD, physical vapor deposition (PVD), etc. In some embodiments, the memory film 116A is HfZrO deposited by ALD.

[0041] The semiconductor layer 118A is formed of an acceptable material for providing a channel region for a transistor, such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium gallium zinc tin oxide (IGZTO), zinc oxide (ZnO), polycrystalline silicon, amorphous silicon, etc. The material of the semiconductor layer 118A may be formed by an acceptable deposition process such as ALD, CVD, PVD, etc. In some embodiments, the semiconductor layer 118A is formed of IGZTO deposited by ALD.

[0042] The back gate spacer 120A is formed of an acceptable material for electrically insulating the subsequently formed source / drain extension regions from the portion of the semiconductor layer 118A that provides the channel region. In some embodiments, the back gate spacer 120A is formed of a dielectric material. Acceptable dielectric materials for the back gate spacer 120A include: oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; etc.; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, etc. The material of the back gate spacer 120A can be formed by an acceptable deposition process such as ALD, CVD, flowable CVD (FCVD), etc. In some embodiments, the back gate spacer 120A is formed of an oxide such as aluminum oxide deposited by ALD.

[0043] The isolation region 122A is formed of an acceptable material for protecting and electrically isolating the underlying memory film 116A. Acceptable dielectric materials for the isolation region 122A include: oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; etc.; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, etc. The material of the isolation region 122A can be formed by an acceptable deposition process such as ALD, CVD, flowable CVD (FCVD), etc. The isolation region 122A and the back gate spacer 120A are formed of different dielectric materials, so that the material of the isolation region 122A has a high etching selectivity compared to the etching of the material of the back gate spacer 120A. In some embodiments, the isolation region 122A is formed of an oxide such as silicon oxide deposited by FCVD.

[0044] The memory film 116A, the semiconductor layer 118A, the back gate spacer 120A, and the isolation region 122A may be formed by a combination of deposition, etching, and planarization. For example, a tunnel layer may be conformally deposited on the multilayer stack 104 and in the trench 110A (e.g., on the sidewalls of the conductive component 114A and the sidewalls of the dielectric layer 106). The semiconductor layer may then be conformally deposited on the tunnel layer. The dielectric layer may then be conformally deposited on the semiconductor layer. The dielectric layer may then be patterned by an appropriate etching process, such as anisotropic etching using the tunnel layer as an etch stop layer. The semiconductor layer may then be patterned by an appropriate etching process, such as anisotropic etching using the patterned dielectric layer as an etching mask. The isolation material may then be conformally deposited in the remainder of the trench 110A (e.g., on the exposed portions of the patterned semiconductor layer, the patterned dielectric layer, and the tunnel layer). A removal process may then be applied to each layer to remove excess material above the topmost dielectric layer 106 / sacrificial layer 108. The removal process may be a planarization process such as chemical mechanical polishing (CMP), etch back, a combination thereof, etc. Portions of the tunnel layer, semiconductor layer, dielectric layer, and isolation material remaining in the trench 110A form a memory film 116A, a semiconductor layer 118A, a back gate spacer 120A, and an isolation region 122A, respectively. The planarization process exposes the topmost dielectric layer 106 / sacrificial layer 108 so that the top surfaces of the memory film 116A, the semiconductor layer 118A, the back gate spacer 120A, the isolation region 122A, and the topmost dielectric layer 106 / sacrificial layer 108 are coplanar (within process variation) after the planarization process.

[0045] Optionally, the isolation region 122A may be formed to also extend through the memory film 116A and the substrate 102. As will be discussed in more detail below, in some embodiments, the memory array 50 is embedded in another semiconductor device. Specifically, the memory array 50 may be formed in an interconnect structure of a semiconductor device. In such an embodiment, an opening may be formed through the memory film 116A and the substrate 102 before the isolation material of the isolation region 122A is deposited. Portions of the isolation region 122A will subsequently be replaced by source / drain regions of the transistor so that the source / drain regions are connected to the metallization layer of the interconnect structure located below the memory array 50. Using the semiconductor layer 118A and the back gate spacer 120A as an etching mask, a suitable etching process may be performed on the memory film 116A and the substrate 102. The etching process is selective to the memory film 116A and the substrate 102 (e.g., selectively removing the material of the memory film 116A and the substrate 102 at a faster rate than the material of the semiconductor layer 118A and the back gate spacer 120A). The etching may be anisotropic. In some embodiments, the etching process includes multiple etches. For example, a first etch may be performed to extend the opening through the memory film 116A, and a second etch may be performed to extend the opening through the substrate 102. After the opening is formed, the isolation region 122A may be formed in a manner similar to that described above.

[0046] exist Figure 7 , trench 110B is patterned in multilayer stack 104. In the illustrated embodiment, trench 110B extends through multilayer stack 104 and exposes substrate 102. In another embodiment, trench 110B extends through some but not all layers of multilayer stack 104. Acceptable photolithography and etching techniques may be used to pattern trench 110B, such as using an etching process that is selective to multilayer stack 104 (e.g., selectively removes dielectric material of dielectric layer 106 and sacrificial layer 108 at a faster rate than material of substrate 102). The etching process may be any acceptable etching process, and in some embodiments, may be similar to that used to form trench 110A (described above with respect to FIG. 1 ). Figure 3 discussed).

[0047] After patterning, the corresponding portion of the multilayer stack 104 is disposed between the corresponding pairs of grooves 110A, 110B. Each portion of the multilayer stack 104 is disposed in the second direction D2 (see FIG. Figure 1A and Figure 1B) has a width W3 in the second direction D2, which can be in the range of about 50nm to about 500nm. In addition, each portion of the multilayer stack 104 is separated by a separation distance S2 in the second direction D2, which can be in the range of about 50nm to about 200nm. When patterning the groove 110B, misalignment may occur. When misalignment occurs, the patterned portions of the multilayer stack 104 do not all have the same width W3. When misalignment does not occur, the patterned portions of the multilayer stack 104 have the same width W3.

[0048] exist Figure 8 In the embodiment of the present invention, the trench 110B is expanded to form the sidewall recess 112B. Specifically, the remaining portion of the sacrificial layer 108 is removed to form the sidewall recess 112B. Therefore, the sidewall recess 112B exposes the sidewall of the conductive component 114A (eg, the seed layer 114A). S The sidewall recess 112B may be formed by an acceptable etching process, such as an etching process that is selective to the material of the sacrificial layer 108 (e.g., selectively removes the material of the sacrificial layer 108 at a faster rate than the material of the dielectric layer 106 and the substrate 102). The etching process may be any acceptable etching process, and in some embodiments, may be similar to the etching process used to form the sidewall recess 112A (described above with respect to FIG. Figure 4 discussed).

[0049] After being formed, the side wall recess 112B is Figure 1A and Figure 1B ) has a depth D5 that extends beyond the sidewall of the dielectric layer 106. The timed etching process can be used to stop etching the sidewall recess 112B after the sidewall recess 112B reaches the desired depth D5. As described above, when patterning the trench 110B, misalignment may occur. When misalignment occurs, the depth D5 is different from (e.g., greater than or less than) the depth D4 (described above for Figure 4 When no misalignment occurs, depth D5 is similar to depth D4.

[0050] exist Fig. 9 114B is formed in the sidewall recess 112B, thereby completing the process for replacing the second portion of the sacrificial layer 108. The conductive component 114B can be formed of a material selected from the same group of candidate materials as the conductive component 114A, and can be formed using a method selected from the same group of candidate methods for forming the material of the conductive component 114A. The conductive component 114A and the conductive component 114B can be formed of the same material, or can include different materials. In some embodiments, the conductive component 114B includes a seed layer 114B. S (or barrier layer) and main layer 114B M . Seed layer 114BS and main floor 114B M may have respective S and main floor 114A M In some embodiments, the seed layer 114A S and seed layer 114B S Formed of similar materials, in this case, seed layer 114A S and seed layer 114B S The seed layer 114A may be merged during formation so that there is no discernible interface between them. S and seed layer 114B S The seed layer 114A is formed of different materials. S and seed layer 114B S The main layer 114A may not be merged during formation so that there is a discernible interface between them. As described above, when the groove 110B is patterned, misalignment may occur. When misalignment occurs, the main layer 114A M Along the second direction D2 (see Figure 1A and Figure 1B ) has the same M When no misalignment occurs, the main layer 114A M Along the second direction D2, the main layer 114B has M The same width. Each seed layer 114A S , 114B S The part is arranged laterally on the main layer 114A M and main floor 114B M between.

[0051] The conductive features 114A and 114B are collectively referred to as word lines 114 of the memory array 50. Adjacent pairs of conductive features 114A and 114B are in physical contact with each other and are electrically coupled to each other. Thus, each pair of conductive features 114A, 114B functions as a single word line 114.

[0052] exist Fig.10 In the embodiment, a memory film 116B, a semiconductor layer 118B, a back gate spacer 120B, and an isolation region 122B are formed in the trench 110B. The semiconductor layer 118B and the back gate spacer 120B are formed above the memory film 116B. The isolation region 122B extends through the semiconductor layer 118B, thereby extending in the direction D2 (see FIG. Figure 1A and Figure 1B) separates the semiconductor layer 118B of the horizontally adjacent transistors. In the illustrated embodiment, the isolation region 122B is formed above the memory film 116B. In another embodiment, the isolation region 122B also extends through the memory film 116B and the substrate 102, thereby separating the memory films 116B of the horizontally adjacent transistors along the direction D2.

[0053] The memory film 116B may be formed of a material selected from the same group of candidate materials as the memory film 116A, and may be formed using a method selected from the same group of candidate methods for forming the material of the memory film 116A. The memory film 116A and the memory film 116B may be formed of the same material, or may include different materials. The memory film 116A and the memory film 116B are collectively referred to as the memory film 116. The thickness of the memory film 116 may be in the range of about 2 nm to about 20 nm.

[0054] Semiconductor layer 118B may be formed of a material selected from the same group of candidate materials as semiconductor layer 118A, and may be formed using a method selected from the same group of candidate methods as the material of semiconductor layer 118A. Semiconductor layer 118A and semiconductor layer 118B may be formed of the same material, or may include different materials. Semiconductor layer 118A and semiconductor layer 118B are collectively referred to as semiconductor layer 118. The thickness of semiconductor layer 118 may be in the range of about 9 nm to about 11 nm.

[0055] The back gate spacer 120B may be formed of a material selected from the same group of candidate materials as the back gate spacer 120A, and may be formed using a method selected from the same group of candidate methods for forming the material of the back gate spacer 120A. The back gate spacer 120A and the back gate spacer 120B may be formed of the same material, or may include different materials. The back gate spacer 120A and the back gate spacer 120B are collectively referred to as the back gate spacer 120. The thickness of the back gate spacer 120 may be in the range of about 1 nm to about 20 nm.

[0056] The isolation region 122B may be formed of a material selected from the same group of candidate materials as the isolation region 122A, and may be formed using a method selected from the same group of candidate methods as the material of the isolation region 122A. The isolation region 122A and the isolation region 122B may be formed of the same material, or may include different materials. The isolation region 122B and the back gate spacer 120B are formed of different dielectric materials, so that the material of the isolation region 122B has a high etching selectivity compared to the etching of the material of the back gate spacer 120B. The isolation region 122A and the isolation region 122B are collectively referred to as the isolation region 122. The thickness of the isolation region 122 may be in the range of about 42 nm to about 192 nm.

[0057] The memory film 116B, the semiconductor layer 118B, the back gate spacer 120B, and the isolation region 122B may be formed by a combination of deposition, etching, and planarization. For example, the memory film 116B, the semiconductor layer 118B, the back gate spacer 120B, and the isolation region 122B may be formed by steps similar to those used to form the memory film 116A, the semiconductor layer 118A, the back gate spacer 120A, and the isolation region 122A (the above for Figure 6 discussed) formation.

[0058] As will be discussed in more detail below, Figures 11 to 18 1 shows a process in which a portion of the isolation region 122 is replaced with the remaining components of the transistor. Specifically, a portion of the isolation region 122 is replaced by the isolation region 142 (see FIG. Fig.16 ) and bit line 146B and source line 146S (see Fig.18 ) is replaced. The remaining portion of the isolation region 122 is along the direction D1 (see Figure 1A and Figure 1B ) separates components of horizontally adjacent transistors. Bit lines 146B and source lines 146S also serve as source / drain regions for transistors. In a process for replacing portions of isolation regions 122, back gate spacers 120 are patterned. Patterned back gate spacers 120 allow portions of bit lines 146B / source lines 146S to also serve as back gates during write operations.

[0059] exist Fig.11 1, a portion of the isolation region 122 is removed to form an opening 130. The opening 130 can be formed by an etching process that is selective to the isolation region 122 (e.g., selectively removing the material of the isolation region 122 at a faster rate than the material of the memory film 116 and the back gate spacer 120). The etching can be any acceptable etching process such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching can be anisotropic. In an embodiment where the isolation region 122 is formed of silicon oxide, the opening 130 through the isolation region 122 can be formed by dry etching performed using ammonia (NH3) and hydrogen fluoride (HF) gases using an etching mask having a pattern of the opening 130.

[0060] exist Fig.12In the embodiment of the present invention, a sacrificial region 132 is formed in the opening 130. The sacrificial region 132 is formed of a sacrificial material such as a dielectric material, which will be replaced by the bit line and the source line in subsequent processing. In this way, the dielectric material of the sacrificial region 132 has a high etching selectivity compared to the etching of the materials of the memory film 116, the semiconductor layer 118 and the back gate spacer 120. Acceptable dielectric materials for the sacrificial region 132 include: oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; etc.; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon nitride, etc. The material of the sacrificial region 132 can be formed by an acceptable deposition process such as ALD, CVD, flowable CVD (FCVD), etc. In some embodiments, the sacrificial region 132 is formed of a nitride such as silicon nitride deposited by CVD. A removal process can be applied to the material of the sacrificial region 132 to remove excess material above the topmost dielectric layer 106 / sacrificial layer 108. The removal process may be a planarization process such as chemical mechanical polishing (CMP), etch back, a combination thereof, etc. The planarization process exposes the topmost dielectric layer 106 / sacrificial layer 108 so that the top surfaces of the sacrificial region 132 and the topmost dielectric layer 106 / sacrificial layer 108 are coplanar after the planarization process (within process variation).

[0061] exist Fig.13 In the embodiment, the back gate spacer 120 and the sacrificial region 132 are patterned to form an opening 136. The opening 136 can be formed by an etching process that is selective to the back gate spacer 120 and the sacrificial region 132 (for example, the material of the back gate spacer 120 and the sacrificial region 132 is selectively removed at a faster rate than the material of the semiconductor layer 118 and / or the memory film 116). The etching can be any acceptable etching process such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching can be anisotropic. In an embodiment where the back gate spacer 120 is formed of aluminum oxide and the sacrificial region 132 is formed of silicon nitride, the opening 136 through the back gate spacer 120 and the sacrificial region 132 can be formed by dry etching using a fluorine-based gas (for example, C4F6) mixed with hydrogen (H2) or oxygen (O2) and performed using an etching mask having a pattern of the opening 136.

[0062] exist Fig.14, additional material of the sacrificial region 132 is redeposited in the opening 136 to reform the sacrificial region 132. Each sacrificial region 132 thus has a first portion 132A and a second portion 132B. As described above, in subsequent processing, the sacrificial region 132 will be replaced by the bit line and source line, and the bit line / source line will have a main region and an extension region. The first portion 132A of the sacrificial region 132 corresponds to the portion of the sacrificial material that was not removed when the opening 136 was formed, and will be replaced by the extension region of the bit line / source line. The second portion 132B of the sacrificial region 132 corresponds to the portion of the sacrificial material that was redeposited in the opening 136, and will be replaced by the main region of the bit line / source line. The portions 132A, 132B of the sacrificial region 132 may be merged during the redeposition so that there is no discernible interface between them.

[0063] exist Fig.15 , an opening 140 for an isolation region is formed through the sacrificial region 132. The opening 140 divides the sacrificial region 132 into portions that will be replaced by bit lines and source lines in subsequent processing. The opening 140 can be formed by an etching process that is selective to the sacrificial region 132 (e.g., selectively removing the material of the sacrificial region 132 at a faster rate than the material of the memory film 116). The etching can be any acceptable etching process such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching can be anisotropic. In an embodiment where the sacrificial region 132 is formed of silicon nitride, the opening 140 through the sacrificial region 132 can be formed by dry etching using a fluorine-based gas (e.g., C4F6) mixed with hydrogen (H2) or oxygen (O2) and performed using an etching mask having a pattern of the opening 140.

[0064] The semiconductor layer 118 is patterned during processing so that the semiconductor layers 118 of horizontally adjacent transistors are aligned in the direction D1 (see FIG. Figure 1A and Figure 1B ) are separated. As will be discussed in more detail below, the semiconductor layer 118 can be patterned in one of several steps during processing according to the desired width of the divided semiconductor layer 118. In this embodiment, the patterned sacrificial region 132 / opening 140 (see Fig.15 ) and patterning the semiconductor layer 118 at the same time. In another embodiment, patterning the back gate spacer 120 / opening 136 (see Fig.13 ) and patterning the semiconductor layer 118 at the same time. In another embodiment, the patterning of the back gate spacer 120 / opening 136 (see Fig.13 ), but after redeposition of the material in the sacrificial region 132 in the opening 136 (see Fig.14 ) or patterning of the sacrificial region 132 / opening 140 (see Fig.15), the semiconductor layer 118 is patterned in a separate step before being patterned. When patterned separately, the semiconductor layer 118 can be patterned by an etching process that is selective to the semiconductor layer 118 (for example, the material of the semiconductor layer 118 is selectively removed at a faster rate than the material of the memory film 116). The etching can be any acceptable etching process such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching can be anisotropic. In an embodiment where the semiconductor layer 118 is formed of IGZTO, the semiconductor layer 118 can be patterned by dry etching using Cl2, BCl3, CF4, SF6, etc.

[0065] exist Fig.16 , an isolation region 142 is formed in the opening 140. The isolation region 142 thus extends through the sacrificial region 132. The isolation region 142 may be formed of a material selected from the same group of candidate materials as the isolation region 122A, which may be formed using a method selected from the same group of candidate methods for forming the material of the isolation region 122. The isolation region 122 and the isolation region 142 may be formed of the same material, or may include different materials. In some embodiments, the isolation region 142 is formed of silicon oxide deposited by CVD. As an example of forming the isolation region 142, an isolation material is formed in the opening 140. A removal process is then applied to each layer to remove excess isolation material above the topmost dielectric layer 106 / word line 114. The removal process may be a planarization process, such as chemical mechanical polishing (CMP), etch back, a combination thereof, and the like. The remaining isolation material forms the isolation region 142 in the opening 140.

[0066] exist Fig.17 , the sacrificial region 132 is removed to form an opening 144. The opening 144 can be formed by an etching process that is selective to the sacrificial region 132 (e.g., selectively removing the material of the sacrificial region 132 at a faster rate than the material of the isolation region 142, the back gate spacer 120, the isolation region 122, the semiconductor layer 118, and the memory film 116). The etching can be isotropic. In an embodiment where the sacrificial region 132 is formed of silicon nitride, the opening 144 can be formed by wet etching using phosphoric acid (H3PO4). In another embodiment, a dry etch that is selective to the material of the sacrificial region 132 can be used.

[0067] exist Fig.18In the embodiment, conductive lines (including bit lines 146B and source lines 146S) are formed in openings 144. Bit lines 146B and source lines 146S are conductive pillars, which may also be referred to as bit line pillars and source line pillars. Each transistor will include a bit line 146B and a source line 146S, and an isolation region 122 is provided between the bit line 146B and the source line 146S. In this embodiment, the bit line 146B / source line 146S extends through the semiconductor layer 118. In another embodiment, the bit line 146B / source line 146S also extends through the memory film 116 and the substrate 102.

[0068] As an example of forming the bit line 146B / source line 146S, a liner and a main layer such as a diffusion barrier layer, an adhesion layer, etc. are formed in the opening 144. The liner can be formed of a conductive material such as titanium, titanium nitride, tantalum, tantalum nitride, etc., which can be deposited by a conformal deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. In some embodiments, the liner can include an adhesion layer, and at least a portion of the adhesion layer can be processed to form a diffusion barrier layer. The main layer can be formed of a conductive material such as tungsten, cobalt, ruthenium, aluminum, nickel, copper, copper alloy, silver, gold, etc., which can be deposited by ALD, CVD, PVD, etc. In some embodiments, the bit line 146B / source line 146S includes a liner formed of titanium nitride and a main layer formed of tungsten. A removal process is then applied to each layer to remove excess material of the bit line 146B / source line 146S above the topmost dielectric layer 106 / word line 114. The removal process may be a planarization process, such as chemical mechanical polishing (CMP), etch back, a combination thereof, etc. The remaining material in the opening 144 forms the bit line 146B / source line 146S. The planarization process exposes the topmost dielectric layer 106 / word line 114 so that the top surfaces of the bit line 146B / source line 146S, isolation region 142, isolation region 122, back gate spacer 120, semiconductor layer 118, memory film 116, and topmost dielectric layer 106 / word line 114 are coplanar (within process variation) after the planarization process.

[0069] In a top view, the bit line 146B / source line 146S both have a T-shaped cross section. Specifically, the bit line 146B has a main region 146B extending along the sidewall of the semiconductor layer 118. M , and having an extension region 146B extending along the sidewall of the back gate spacer 120 E Similarly, the source line 146S has a main region 146S extending along the sidewall of the semiconductor layer 118. M , and having an extension region 146S extending along the sidewall of the back gate spacer 120 E . Extension area 146B E 、146S Eand the isolation region 122 are both in the second direction D2 (see Figure 1A and Figure 1B ) have the same width. The patterned back gate spacer 120 allows the main region 146B to M 、146S M Contacting semiconductor layer 118, but maintaining extension region 146B E 、146S E The extension region 146B is separated from the portion of the semiconductor layer 118 that provides the channel region. E 、146S E Can be used as a back gate without shorting the channel region.

[0070] exist Fig.19A , Fig.19B and Fig.19C In the embodiment, an interconnect structure 160 is formed above the intermediate structure. The interconnect structure 160 may include, for example, a metallization pattern 162 ( Fig.19A Not shown, see Fig.19B and Fig.19C ). The dielectric material 164 may include one or more dielectric layers, such as one or more layers of low-k (LK) or ultra-low-k (ELK) dielectric materials. The metallization pattern 162 may be a metal interconnect (e.g., a conductive line 162L, a conductive via 162V, etc.) formed in the dielectric material 164. The interconnect structure 160 may be formed by a damascene process (e.g., a single damascene process, a dual damascene process, etc.). The metallization pattern 162 of the interconnect structure 160 is electrically connected to the bit line 146B / source line 146S, and interconnects the transistors 54 to form a functional memory.

[0071] As described above, dielectric layer 106 and word line 114 may be formed into a staircase structure. Dielectric layer 106 and word line 114 may be patterned to form a staircase structure in any suitable step prior to forming interconnect structure 160. Forming interconnect structure 160 includes forming a conductive contact connected to an exposed portion of each word line 114.

[0072] FIG. 20A to FIG. 20J is a diagram of an intermediate stage in the fabrication of a staircase structure of memory array 50 in accordance with some embodiments. FIG. 20A to FIG. 20J is along Figure 1A The cross-sectional view shown in the reference cross section BB' is shown. For the sake of clarity, some components of the transistor are not shown, such as the memory film 116, the semiconductor layer 118, the back gate spacer 120, etc. (see FIG. Figures 6 to 19C ).exist FIG. 20A to FIG. 20J In the embodiment, after replacing the sacrificial layer 108 with the word line 114, the multi-layer stack 104 is patterned to form a staircase structure. It should be understood that the illustrated process may be performed in other suitable processing steps.

[0073] exist Fig. 20A In the process, a mask 202 is formed over the multilayer stack 104. In this process step, the multilayer stack 104 includes alternating dielectric layers 204 (such as the dielectric layers 106 discussed above, labeled 204A, 204B, 204C, 204D) and conductive layers 206 (such as the word lines 114 discussed above, labeled 206A, 206B, 206C). The mask 202 can be a photoresist or the like, which can be formed by a spin coating technique or the like.

[0074] exist Fig. 20B In the embodiment of the present invention, the mask 202 is patterned to expose the multilayer stack 104 in the region 210A while masking the rest of the multilayer stack 104. For example, the topmost layer (e.g., dielectric layer 204D) of the multilayer stack 104 can be exposed in the region 210A. The mask 202 can be patterned using acceptable photolithography techniques.

[0075] exist Fig. 20C In the embodiment of the present invention, the mask 202 is used as an etching mask to etch the exposed portion of the multilayer stack 104 in the region 210A. The etching may be any acceptable etching process such as wet etching, dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching may be anisotropic. The etching may remove portions of the dielectric layer 204D and the conductive layer 206C in the region 210A and define the opening 212. Since the dielectric layer 204D and the conductive layer 206C have different material compositions, the etchants used to remove the exposed portions of these layers may be different. In some embodiments, the conductive layer 206C is used as an etching stop layer when etching the dielectric layer 204D, and the dielectric layer 204C is used as an etching stop layer when etching the conductive layer 206C. As a result, portions of the conductive layer 206C and the dielectric layer 204D may be selectively removed without removing the remaining layers of the multilayer stack 104, and the opening 212 may extend to a desired depth. Alternatively, a timed etching process may be used to stop the etching of opening 212 after opening 212 reaches a desired depth. In the resulting structure, dielectric layer 204C is exposed in region 210A.

[0076] exist Fig.20D In the embodiment of the present invention, the mask 202 is trimmed to expose additional portions of the multilayer stack 104. The mask 202 may be trimmed using acceptable photolithography and / or etching techniques. As a result of the trimming, the width of the mask 202 is reduced, and portions of the multilayer stack 104 in the region 210B may also be exposed. For example, the top surface of the dielectric layer 204C may be exposed in the region 210A, and the top surface of the dielectric layer 204D may be exposed in the region 210B.

[0077] exist Fig.20EIn the embodiment of the present invention, dielectric layer 204D, conductive layer 206C, portions of dielectric layer 204C, and conductive layer 206B in regions 210A and 210B are removed by an acceptable etching process using mask 202 as an etching mask. The etching may be any acceptable etching process such as wet etching, dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching may be anisotropic. The etching may extend opening 212 further into multilayer stack 104. Since dielectric layers 204D / 204C and conductive layers 206C / 206B have different material compositions, the etchants used to remove exposed portions of these layers may be different. In some embodiments, conductive layer 206C is used as an etch stop layer when etching dielectric layer 204D; dielectric layer 204C is used as an etch stop layer when etching conductive layer 206C; conductive layer 206B is used as an etch stop layer when etching dielectric layer 204C; and dielectric layer 204B is used as an etch stop layer when etching conductive layer 206B. As a result, portions of dielectric layers 204D / 204C and conductive layers 206C / 206B may be selectively removed without removing the remaining layers of multilayer stack 104, and opening 212 may extend to a desired depth. In addition, during the etching process, the unetched portions of dielectric layer 204 and conductive layer 206 are used as an etch mask for the underlying layers, and as a result, the previous patterns of dielectric layer 204D and conductive layer 206C (see Fig.20D ) may be transferred to the underlying dielectric layer 204C and conductive layer 206B. In the resulting structure, dielectric layer 204B is exposed in region 210A, and dielectric layer 204C is exposed in region 210B.

[0078] exist Fig.20F In the embodiment of the present invention, mask 202 is trimmed to expose additional portions of multilayer stack 104. The photoresist may be trimmed using acceptable photolithography techniques. As a result of the trimming, the width of mask 202 is reduced, and portions of multilayer stack 104 in region 210C may also be exposed. For example, the top surface of dielectric layer 204B may be exposed in region 210A; the top surface of dielectric layer 204C may be exposed in region 210B; and the top surface of conductive layer 204D may be exposed in region 210C.

[0079] exist Figure 20G, portions of dielectric layers 204D, 204C, 204B in regions 210A, 210B, 210C are removed by an acceptable etching process using mask 202 as an etching mask. The etching may be any acceptable etching process such as wet etching, dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching may be anisotropic. The etching may extend opening 212 further into multilayer stack 104. In some embodiments, conductive layer 206C is used as an etch stop layer when etching dielectric layer 204D; conductive layer 206B is used as an etch stop layer when etching dielectric layer 204C; and conductive layer 206A is used as an etch stop layer when etching dielectric layer 204B. As a result, portions of dielectric layers 204D, 204C, 204B may be selectively removed without removing the remaining layers of multilayer stack 104, and opening 212 may be extended to a desired depth. Furthermore, during the etching process, each conductive layer 206 acts as an etching mask for the underlying layers, and as a result, the previous pattern of the conductive layers 206C / 206B (see Fig.20F ) may be transferred to the underlying dielectric layer 204C / 204B. In the resulting structure, conductive layer 206A is exposed in region 210A; conductive layer 206B is exposed in region 210B; and conductive layer 206C is exposed in region 210C.

[0080] exist Fig. 20H , the mask 202 may be removed, for example, by an acceptable ashing or wet stripping process. Thus, a staircase structure 214 is formed. The staircase structure includes a stack of alternating dielectric layers 204 and conductive layers 206. The lower conductive layer 206 is wider and extends laterally beyond the upper conductive layer 206, and the width of each conductive layer 206 increases in a direction toward the substrate 102. For example, conductive layer 206A may be longer than conductive layer 206B; and conductive layer 206B may be longer than conductive layer 206C. As a result, in subsequent processing steps, a conductive contact may be made from above the staircase structure 214 to each conductive layer 206.

[0081] exist Fig.20I In the embodiment of the present invention, an intermetallic dielectric (IMD) 216 is deposited above the stepped structure 214. The ILD 216 can be formed of a dielectric material and can be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD) or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. The IMD 216 extends along the sidewalls of the dielectric layer 204 and the sidewalls of the conductive layer 206. In addition, the IMD 216 can contact the top surface of each conductive layer 206.

[0082] like Fig.20I As further shown in FIG. 2 , a removal process is then applied to IMD 216 to remove excess dielectric material above step structure 214. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be utilized. The planarization process exposes step structure 214 such that the top surfaces of step structure 214 and IMD 216 are coplanar (within process variation) after the planarization process is completed.

[0083] exist Fig. 20J 216, a portion of the interconnect structure 160 is formed. To simplify the illustration, only one layer of the interconnect structure 160 is shown. In this embodiment, forming the interconnect structure 160 includes forming a conductive contact 166 through the IMD 216. The conductive contact 166 can be formed by a damascene process (e.g., a single damascene process, a dual damascene process, etc.). The conductive contact 166 is connected to an exposed portion of each conductive layer 206 (e.g., the word line 114 discussed above). FIG. 21A to FIG. 21D is a top view of a memory array 50 according to some embodiments. Some components of the interconnect structure are shown. Fig.21A Conductive vias (eg, Fig.19B and Fig.19C The first level conductive vias in 162V 1 ). Fig.21B The conductive lines (eg, Fig.19B and Fig.19C The first level conductor 162L 1 ). Fig. 21C A conductive via (eg, Fig.19B and Fig.19C The second level conductive via 162V 2 ). Fig.21D The conductors (eg, Fig.19B and Fig.19C The second level conductor 162L 2 ).

[0084] refer to Fig.21A , conductive via 162V1 is located above and connected to bit line 146B / source line 146S. In top view, bit lines 146B and source lines 146S are formed in an alternating pattern along the rows and columns of memory array 50. Forming bit lines 146B and source lines 146S in an alternating pattern helps avoid the occurrence of spurious ... Fig.19B and Fig.19C) is activated, the adjacent bit lines 146B / source lines 146S are short-circuited. In this embodiment, the adjacent bit lines 146B and the adjacent source lines 146S are connected along the first direction D1 (see Figure 1A and Figure 1B ) are laterally aligned with each other. In some embodiments, the center of each conductive via 162V1 is laterally aligned with the center of the corresponding underlying bit line 146B / source line 146S.

[0085] refer to Fig.21B , the conductive line 162L1 is located above the conductive via 162V1 and connected thereto. The conductive line 162L1 is arranged in a first direction D1 (see Figure 1A and Figure 1B ) and is laterally offset to the underlying bit line / source line interconnect. In other words, the interconnect connected to bit line 146B (see Fig.21A ) along the second direction D2 (see Figure 1A and Figure 1B ) from the source line 146S (see Fig.21A )'s conductor 162L1 is laterally offset.

[0086] refer to Fig. 21C , conductive via 162V2 is located above and connected to conductive line 162L1. Because conductive line 162L1 is laterally offset from the interconnection with the underlying bit line / source line, the center of each conductive via 162V2 is laterally offset from the center of the corresponding underlying bit line / source line and the center of the corresponding underlying conductive via 162V1. Conductive via 162V2 can be larger (e.g., wider than) conductive via 162V1.

[0087] refer to Fig.21D , the conductive line 162L2 is located above and connected to the conductive via 162V2. The conductive line 162L2 includes a bit line interconnect 162B (which is connected to the bit line 146B, see Fig.21A ) and source line interconnect 162S (which is connected to source line 146S, see Fig.21A ). Because the wire 162L1 (see Fig. 21C ) is laterally offset to the underlying bit line / source line interconnect, the bit line interconnect 162B and the source line interconnect 162S may therefore be in the second direction D2 (see Figure 1A and Figure 1B ) is a straight conductive segment extending on the surface.

[0088] FIG. 22A to FIG. 22C 1 is a top view of a memory cell according to various embodiments. The isolation region 122 may be arranged in a first direction D1 (see Figure 1A and Figure 1B) has a width W4 in the first direction D1, which may be in the range of about 1 nm to about 100 nm. The back gate spacer 120 may have a width W5 in the first direction D1, which may be in the range of about 1 nm to about 100 nm. In each of the illustrated embodiments, the width W5 is greater than the width W4. The semiconductor layer 118 may have a width W6 in the first direction D1, which may be in the range of about 1 nm to about 100 nm.

[0089] Fig.22A The patterned sacrificial area 132 / opening 140 (see Fig.15 ) while patterning the semiconductor layer 118. Therefore, the width W6 is greater than the width W5. In addition, the width W6 may be equal to the combined width W7 of the isolation region 122, the source line 146S, and the bit line 146B. In this embodiment, the main region 146B of the bit line 146B / source line 146S is M 、146S M They are separated from the sidewalls of the memory film 116 .

[0090] Fig. 22B The patterning of the back gate spacer 120 / opening 136 is shown (see Fig.13 ), but after redeposition of the material in the sacrificial region 132 in the opening 136 (see Fig.14 ) or patterning of the sacrificial region 132 / opening 140 (see Fig.15 ) before patterning the semiconductor layer 118 separately. Therefore, the width W6 is greater than the width W5. In addition, the width W6 is less than the combined width W7 of the isolation region 122, the source line 146S, and the bit line 146B. In this embodiment, the main region 146B of the bit line 146B / source line 146S is M 、146S M Both contact the sidewalls of the memory film 116 and the sidewalls of the semiconductor layer 118 .

[0091] Fig. 22C The patterned back gate spacer 120 / opening 136 (see Fig.13 ) while patterning the semiconductor layer 118. Therefore, the width W6 is equal to the width W5. In addition, the width W6 is less than the combined width W7 of the isolation region 122, the source line 146S, and the bit line 146B. In this embodiment, the main region 146B of the bit line 146B / source line 146S is M 、146S M Both contact the sidewalls of the memory film 116 and a single sidewall of the semiconductor layer 118 .

[0092] Fig.23 is a cross-sectional view of a memory array 50 according to some other embodiments. Fig. 20B A similar cross section shows Fig.23. In this embodiment, the memory film 116 is formed of a plurality of low-k dielectric layers. Specifically, each memory film 116 includes a first sublayer 116L1, a second sublayer 116L2 located on the first sublayer 116L1, and a third sublayer 116L3 located on the second sublayer 116L2. In some embodiments, the first sublayer 116L1 and the third sublayer 116L3 are formed of a first dielectric material (e.g., an oxide such as silicon oxide), and the second sublayer 116L2 is formed of a different second dielectric material (e.g., a nitride such as silicon nitride). The low-k dielectric layer allows the transistor to be used as a floating gate transistor.

[0093] In About Figures 2 to 23 In the depicted embodiment, memory array 50 is formed over substrate 102. In some embodiments, memory array 50 is formed as part of a separate device (e.g., a memory die) that is integrated with other devices (e.g., a logic die) via device packaging. In some embodiments, memory array 50 is embedded in another device, such as a logic die. In such embodiments, substrate 102 may be omitted, or may be an underlying layer, such as an underlying dielectric layer, an underlying semiconductor substrate, etc.

[0094] Fig.24 is a cross-sectional view of a semiconductor device 300 according to some embodiments. Fig.24 It is along Figure 1A A cross-sectional view shown in reference section BB'. Fig.24 300L and the memory region 300M. A memory device (e.g., a memory) is formed in the memory region 300M, and a logic device (e.g., a logic circuit) is formed in the logic region 300L. For example, a memory array 50 (see FIG. 1 ) may be formed in the memory region 300M, and a logic device may be formed in the logic region 300L. The memory region 300M may be disposed at the edge of the logic region 300L, or the logic region 300L may surround the memory region 300M.

[0095] The logic region 300L and the memory region 300M are formed over the same semiconductor substrate 302. The semiconductor substrate 302 may be silicon, doped or undoped, or an active layer of a semiconductor on insulator (SOI) substrate. The semiconductor substrate 302 may include: other semiconductor materials such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates such as multilayer or gradient substrates may also be used.

[0096] Device 304 is formed at the active surface of semiconductor substrate 302. Device 304 can be an active device or a passive device. For example, the electrical component can be a transistor, a diode, a capacitor, a resistor, etc. formed by any suitable formation method. Device 304 is interconnected to form a memory device and a logic device of semiconductor device 300.

[0097] One or more interlayer dielectric (ILD) layers 306 are formed on the semiconductor substrate 302, and conductive features (such as contact plugs 308) are formed to be electrically connected to the device 304. The ILD layer 306 can be formed of any suitable dielectric material, for example, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc., a nitride such as silicon nitride, etc. The ILD layer can be formed by any acceptable deposition process, such as spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), etc., or a combination thereof. The conductive features in the ILD layer can be formed by any suitable process, such as deposition, damascene (e.g., single damascene, dual damascene, etc.), or a combination thereof.

[0098] The interconnect structure 310 is formed above the semiconductor substrate 302. The interconnect structure 310 interconnects the devices 304 to form an integrated circuit in each of the logic region 300L and the memory region 300M. The interconnect structure 310 includes a plurality of metallization layers M1-M5. Although five metallization layers are shown, it should be understood that more or fewer metallization layers may be included. Each metallization layer M1-M5 includes a metallization pattern in a dielectric layer. The metallization pattern is connected to the device 304 of the semiconductor substrate 302 and includes metal lines L1-L5 and metal vias V1-V5 formed in one or more intermetallic dielectric (IMD) layers, respectively. The interconnect structure 310 can be formed by a damascene process (e.g., a single damascene process, a dual damascene process, etc.). In some embodiments, the contact plug 308 is also a part of the metallization pattern, such as a part of the bottommost layer of the metal via V1.

[0099] In this embodiment, the memory array 50 is formed in the interconnect structure 310. The memory array 50 can be formed in any of the metallization layers M1-M5, and is shown as being formed in the middle metallization layer M4, but it can also be formed in the lower metallization layers M1-M3 or the upper metallization layer M5. The memory array 50 is electrically connected to the device 304. In this embodiment, the metallization layer above the memory array 50 (e.g., metallization layer M5) includes interconnects to the source lines 146S and the bit lines 146B. The metallization layer above the memory array 50 (e.g., metallization layer M5) can also include interconnects to the word lines 114, such as through conductive contacts 166 (see Fig. 20JIn another embodiment, the metallization layer (eg, metallization layer M3 ) below the memory array 50 includes interconnects to the source lines 146S, the bit lines 146B, and / or the word lines 114 .

[0100] In some embodiments, interconnect structure 310 may be formed by first forming the layers below memory array 50, such as metallization layers M1-M3. Memory array 50 may then be formed on metallization layer M3, wherein substrate 102 is an etch stop layer located on the IMDs of metallization layer M3. After forming memory array 50, the remainder of metallization layer M4 may be formed, such as by depositing and planarizing the IMDs of metallization layer M4, and then forming metal lines M4 and metal vias M4 (which may include forming IMDs 216 and conductive contacts 166, see Fig. 20J ). Layers above the memory array 50 (if any), such as the metallization layer M5, may then be formed.

[0101] Figure 25 to Figure 27 is a diagram of an intermediate stage in the fabrication of memory array 50 according to some other embodiments. Figure 25 to Figure 27 is a three-dimensional view. A portion of the memory array 50 is shown. For clarity, some components, such as the staircase arrangement of word lines (see FIG. 5 ), are not shown in some figures. Figure 1A ).

[0102] exist Fig.25 In the embodiment, a substrate 102 is provided, and a multilayer stack 104 is formed over the substrate 102. Figure 2 The substrate 102 and the multilayer stack 104 are formed in a similar manner as discussed above, but in this embodiment, the multilayer stack 104 includes alternating dielectric layers 106 and conductive layers 168. The conductive features 168 may be formed from a primary layer 114A selected from the conductive features 114A, 114B. M , 114B M The same group of candidate materials as those of the conductive members 114A and 114B may be formed using a main layer 114A selected from the group of candidate materials selected from the main layer 114A selected from the group of candidate materials selected from the main layer 114A selected from the main layer 114B ...A selected from the main layer 11 M , 114B M The same set of candidate methods are used to form the material.

[0103] exist Fig.26 In the embodiment of the present invention, grooves 110 are patterned in the multilayer stack 104. Figure 3 Trenches 110 are formed in a similar manner as discussed above. In this embodiment, trenches 110 are formed to pattern conductive layer 168 to form word lines 114. In this embodiment, word lines 114 may not include multiple layers, but may each be a continuous layer of conductive material (eg, tungsten).

[0104] exist Fig. 27 In the embodiment, a memory film 116, a semiconductor layer 118, a back gate spacer 120 and an isolation region 122 are formed in the trench 110. These components can be formed in the same manner as described above with respect to Figure 6 Thus, the components of the transistor are formed by a single patterning process, wherein only the patterning process is used to form the trench 110 and the layers of the transistor in the multilayer stack 104. After this processing step, as described above with respect to Figures 11 to 18 As discussed above, the isolation region 122 may be replaced by the remaining components of the transistor. Fig.19A , Fig.19B and Fig.19C The interconnect structure is formed in a similar manner as discussed above.

[0105] Embodiments can achieve advantages. The patterned back gate spacer 120 allows the extension region 146B of the bit line 146B / source line 146S to E 、146S E It also acts as a back gate during a write operation. The back gate can help control (e.g., reduce) the surface potential of the semiconductor layer 118 (particularly the portion of the semiconductor layer 118 distal to the word line 114) during a write operation. Thus, the window for the write operation can be widened. Reducing the surface potential of the semiconductor layer 118 during a write operation also helps increase the write voltage applied to the memory film 116 during the write operation. Thus, the performance of the memory array 50 can be improved.

[0106] In an embodiment, a device includes: a word line extending along a first direction; a data storage layer located on the sidewalls of the word line; a channel layer located on the sidewalls of the data storage layer; a back gate isolation member located on the sidewalls of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region being separated from the channel layer by the back gate isolation member, and the bit line extending along a second direction, the second direction being perpendicular to the first direction.

[0107] In some embodiments of the device, the first main region of the bit line is separated from the sidewall of the data storage layer by the channel layer. In some embodiments of the device, the first main region of the bit line contacts the sidewall of the data storage layer and a single sidewall of the channel layer. In some embodiments of the device, the first main region of the bit line contacts the sidewall of the data storage layer and multiple sidewalls of the channel layer. In some embodiments, the device further includes: a source line having a second main region and a second extension region, the second main region contacts the channel layer, the second extension region is separated from the channel layer by a back gate spacer, and the source line extends along a second direction; and an isolation region located between the source line and the bit line. In some embodiments of the device, the isolation region, the first extension region of the bit line, and the second extension region of the source line have the same width along a third direction, and the third direction is perpendicular to the first direction and the second direction. In some embodiments of the device, the isolation region has a first width along the first direction, and the back gate spacer has a second width along the first direction, and the second width is greater than the first width. In some embodiments of the device, the back gate spacer includes aluminum oxide.

[0108] In an embodiment, a device includes: a bit line extending in a first direction, the bit line having a first T-shaped cross-section in a top view; a source line extending in the first direction, the source line having a second T-shaped cross-section in a top view; an isolation region located between the source line and the bit line; a word line extending in a second direction, the second direction being perpendicular to the first direction; a back gate spacer located between the word line and each of the isolation region, the first portion of the bit line, and the second portion of the source line; a channel layer located between the back gate spacer and the word line; and a data storage layer located between the channel layer and the word line.

[0109] In some embodiments of the device, the isolation region has a first width along the second direction, and the back gate spacer has a second width along the second direction, the second width being greater than the first width. In some embodiments of the device, the channel layer has a second width along the second direction. In some embodiments of the device, the channel layer has a third width along the second direction, and the combination of the bit line, the source line, and the isolation region has a fourth width along the second direction, the third width being greater than the second width and less than the fourth width. In some embodiments of the device, the channel layer has a third width along the second direction, and the combination of the bit line, the source line, and the isolation region has a third width along the second direction, the third width being greater than the second width. In some embodiments, the device further includes: a source line interconnect located above the source line and connected to the source line; and a bit line interconnect located above the bit line and connected to the bit line. In some embodiments of the device, the back gate spacer includes aluminum oxide.

[0110] In an embodiment, a method includes: forming a word line between a pair of first dielectric layers; depositing a data storage layer on the sidewalls of the first dielectric layer and the sidewalls of the word line; depositing a channel layer on the sidewalls of the data storage layer; depositing a first dielectric layer on the sidewalls of the channel layer; forming a first isolation region on the sidewalls of the first dielectric layer; removing a first portion of the first isolation region, retaining a second portion of the first isolation region after removal; after removing the first portion of the first isolation region, patterning the first dielectric layer to form a back gate isolation member; and forming a bit line and a source line on the opposite side of the second portion of the first isolation region, the back gate isolation member separating the channel layer from the first portion of the bit line and the second portion of the source line.

[0111] In some embodiments, the method further comprises: patterning the channel layer while patterning the first dielectric layer. In some embodiments, the method further comprises: forming a second isolation region extending through the channel layer; and patterning the channel layer while forming the second isolation region. In some embodiments, the method further comprises: forming a second isolation region extending through the channel layer; and patterning the channel layer after patterning the first dielectric layer and before forming the second isolation region. In some embodiments of the method, the first dielectric layer is formed of aluminum oxide.

[0112] An embodiment of the present application provides a device, comprising: a word line extending in a first direction; a data storage layer located on the sidewall of the word line; a channel layer located on the sidewall of the data storage layer; a back gate spacer located on the sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region being separated from the channel layer by the back gate spacer, the bit line extending in a second direction, the second direction being perpendicular to the first direction. In some embodiments, the first main region of the bit line is separated from the sidewall of the data storage layer by the channel layer. In some embodiments, the first main region of the bit line contacts the sidewall of the data storage layer and a single sidewall of the channel layer. In some embodiments, the first main region of the bit line contacts the sidewall of the data storage layer and a plurality of sidewalls of the channel layer. In some embodiments, it further comprises: a source line having a second main region and a second extension region, the second main region contacting the channel layer, the second extension region being separated from the channel layer by the back gate spacer, the source line extending in the second direction; and an isolation region located between the source line and the bit line. In some embodiments, the isolation region, the first extension region of the bit line, and the second extension region of the source line have the same width along a third direction, and the third direction is perpendicular to the first direction and the second direction. In some embodiments, the isolation region has a first width along the first direction, and the back gate spacer has a second width along the first direction, and the second width is greater than the first width. In some embodiments, the back gate spacer includes aluminum oxide.

[0113] An embodiment of the present application provides a device, comprising: a bit line extending along a first direction, the bit line having a first T-shaped cross section when viewed from top to bottom; a source line extending along the first direction, the source line having a second T-shaped cross section when viewed from top to bottom; an isolation region located between the source line and the bit line; a word line extending along a second direction, the second direction being perpendicular to the first direction; a back gate spacer located between the word line and each of the isolation region, the first portion of the bit line, and the second portion of the source line; a channel layer located between the back gate spacer and the word line; and a data storage layer located between the channel layer and the word line. In some embodiments, the isolation region has a first width along the second direction, and the back gate spacer has a second width along the second direction, the second width being greater than the first width. In some embodiments, the channel layer has the second width along the second direction. In some embodiments, the channel layer has a third width along the second direction, and the combination of the bit line, the source line, and the isolation region has a fourth width along the second direction, the third width being greater than the second width and less than the fourth width. In some embodiments, the channel layer has a third width along the second direction, and the combination of the bit line, the source line and the isolation region has the third width along the second direction, and the third width is greater than the second width. In some embodiments, it also includes: a source line interconnect located above the source line and connected to the source line; and a bit line interconnect located above the bit line and connected to the bit line. In some embodiments, the back gate spacer includes aluminum oxide.

[0114] The embodiment of the present application also provides a method, comprising: forming a word line between a pair of first dielectric layers; depositing a data storage layer on the sidewall of the first dielectric layer and the sidewall of the word line; depositing a channel layer on the sidewall of the data storage layer; depositing a first dielectric layer on the sidewall of the channel layer; forming a first isolation region on the sidewall of the first dielectric layer; removing a first portion of the first isolation region, and retaining a second portion of the first isolation region after removal; patterning the first dielectric layer to form a back gate spacer after removing the first portion of the first isolation region; and forming a bit line and a source line on the opposite side of the second portion of the first isolation region, the back gate spacer separating the channel layer from the first portion of the bit line and the second portion of the source line. In some embodiments, it also includes: patterning the channel layer while patterning the first dielectric layer. In some embodiments, it also includes: forming a second isolation region extending through the channel layer; and patterning the channel layer while forming the second isolation region. In some embodiments, it also includes: forming a second isolation region extending through the channel layer; and patterning the channel layer after patterning the first dielectric layer and before forming the second isolation region. In some embodiments, the first dielectric layer is formed of aluminum oxide.

[0115] The components of several embodiments are discussed above so that those skilled in the art can better understand the various embodiments of the present invention. It should be understood by those skilled in the art that the present invention can be easily used as a basis to design or change other processing and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced in the present invention. It should also be appreciated by those skilled in the art that these equivalent structures do not deviate from the spirit and scope of the present invention, and that various changes, substitutions and modifications may be made without departing from the spirit and scope of the present invention.

Claims

1. A storage device, comprising: A word line extending along a first direction; A data storage layer, located on the sidewalls of the word lines; A channel layer, located on a side wall of the data storage layer; A back gate spacer, located on a sidewall of the channel layer; as well as A bit line has a T-shaped or stepped cross-section in a top-down plane, and the cross-section has a first main region and a first extension region, the first main region contacts the channel layer, the first extension region is separated from the channel layer by the back gate isolation member, and the bit line extends along a second direction, and the second direction is perpendicular to the first direction.

2. The memory device according to claim 1, wherein: A first main region of the bit line is separated from a sidewall of the data storage layer by the channel layer.

3. The memory device according to claim 1, wherein: A first main region of the bit line contacts a sidewall of the data storage layer and a single sidewall of the channel layer.

4. The memory device according to claim 1, wherein: The first main region of the bit line contacts a sidewall of the data storage layer and a plurality of sidewalls of the channel layer.

5. The memory device according to claim 1, further comprising: a source line having a second main region and a second extension region, wherein the second main region contacts the channel layer, the second extension region is separated from the channel layer by the back gate spacer, and the source line extends along the second direction; as well as An isolation region is located between the source line and the bit line.

6. The memory device according to claim 5, wherein: The isolation region, the first extension region of the bit line, and the second extension region of the source line have the same width along a third direction, and the third direction is perpendicular to the first direction and the second direction.

7. The memory device according to claim 5, wherein: The isolation region has a first width along the first direction, and the back gate spacer has a second width along the first direction, the second width being greater than the first width.

8. The memory device according to claim 1, wherein: The back gate spacer includes aluminum oxide.

9. A storage device comprising: A bit line extending along a first direction, wherein the bit line has a first T-shaped cross section when viewed from top to bottom; A source line extending along the first direction, wherein the source line has a second T-shaped cross section when viewed from top to bottom; an isolation region located between the source line and the bit line; A word line extending along a second direction, wherein the second direction is perpendicular to the first direction; a back gate spacer located between the word line and the isolation region, a "-" shaped portion of the first T-shaped cross section of the bit line, and a "-" shaped portion of the second T-shaped cross section of the source line; a channel layer located between the back gate spacer and the word line, wherein a "|"-shaped portion of the first T-shaped cross section of the bit line and a "|"-shaped portion of the second T-shaped cross section of the source line are separated from the channel layer by the back gate spacer; as well as The data storage layer is located between the channel layer and the word line.

10. The memory device according to claim 9, wherein: The isolation region has a first width along the second direction, and the back gate spacer has a second width along the second direction, the second width being greater than the first width.

11. The memory device according to claim 10, wherein: The channel layer has the second width along the second direction.

12. The memory device according to claim 10, wherein: The channel layer has a third width along the second direction, and a combination of the bit line, the source line, and the isolation region has a fourth width along the second direction, the third width being greater than the second width and less than the fourth width.

13. The memory device according to claim 10, wherein: The channel layer has a third width along the second direction, and a combination of the bit line, the source line, and the isolation region has the third width along the second direction, the third width being greater than the second width.

14. The memory device according to claim 10, further comprising: a source line interconnect located above and connected to the source line; as well as A bit line interconnect is located above the bit line and connected to the bit line.

15. The memory device according to claim 10, wherein: The back gate spacer includes aluminum oxide.

16. A method of forming a memory device, comprising: forming a word line between a pair of first dielectric layers; depositing a data storage layer on the sidewalls of the first dielectric layer and the sidewalls of the word lines; depositing a channel layer on the sidewalls of the data storage layer; depositing a first dielectric layer on the sidewalls of the channel layer; forming a first isolation region on a sidewall of the first dielectric layer; removing a first portion of the first isolation region, and retaining a second portion of the first isolation region after the removal; After removing the first portion of the first isolation region, patterning the first dielectric layer to form a back gate isolation member; as well as A bit line and a source line are formed on opposite sides of the second portion of the first isolation region, and the back gate spacer separates the channel layer from the first portion of the bit line and the second portion of the source line.

17. The method for forming a memory device according to claim 16, further comprising: The channel layer is patterned while the first dielectric layer is patterned.

18. The method of forming a memory device according to claim 16, further comprising: forming a second isolation region extending through the channel layer; as well as The channel layer is patterned while forming the second isolation region.

19. The method of forming a memory device according to claim 16, further comprising: forming a second isolation region extending through the channel layer; as well as After patterning the first dielectric layer and before forming the second isolation region, the channel layer is patterned.

20. The method for forming a memory device according to claim 16, wherein: The first dielectric layer is formed of aluminum oxide.

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