Pixel and display device comprising the same

Abstract

A pixel includes a first electrode, a second electrode surrounding at least a portion of the first electrode, a plurality of light emitting elements between the first electrode and the second electrode, a first contact electrode on the first electrode, the first contact electrode electrically connecting the first electrode and the plurality of light emitting elements, a second contact electrode on the second electrode, the second contact electrode electrically connecting the second electrode and the plurality of light emitting elements, and an intermediate electrode on the first electrode and the second electrode, the intermediate electrode including a first region overlapping the first electrode and a second region overlapping the second electrode, the first region and the second region being integrally connected to each other.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0057362, filed on May 13, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to pixels and display devices including such pixels. Background Technology

[0004] With increasing interest in information display and high demand for portable information media, display devices are in high demand, and their commercialization has been strengthened. Summary of the Invention

[0005] One or more embodiments of this disclosure provide pixels having light-emitting units constituting multiple cascaded stages.

[0006] One or more embodiments of this disclosure also provide a pixel capable of improving the light output efficiency of a light-emitting element and a display device including the pixel.

[0007] According to one or more exemplary embodiments of the present disclosure, a pixel is provided, comprising: a first electrode; a second electrode surrounding at least a portion of the first electrode; a plurality of light-emitting elements between the first electrode and the second electrode; a first contact electrode on the first electrode, the first contact electrode being electrically connected to the first electrode and the plurality of light-emitting elements; a second contact electrode on the second electrode, the second contact electrode being electrically connected to the second electrode and the plurality of light-emitting elements; and an intermediate electrode on the first electrode and the second electrode, the intermediate electrode including a first region overlapping the first electrode and a second region overlapping the second electrode, the first region and the second region being integrally connected to each other.

[0008] The first contact electrode, the second contact electrode, and the intermediate electrode can be spaced apart from each other. The intermediate electrode can be disposed in the same layer as the first contact electrode and the second contact electrode, or it can be disposed in a different layer than the first contact electrode and the second contact electrode.

[0009] The first electrode may have a quadrilateral shape including a first side, a second side, a third side, and a fourth side. The second electrode may include a (2-1) electrode adjacent to the first electrode's first side, a (2-2) electrode adjacent to the first electrode's second side, a (2-3) electrode adjacent to the first electrode's third side, and a (2-4) electrode adjacent to the first electrode's fourth side.

[0010] The second electrode may have a quadrilateral ring shape and surround the first electrode from the first side to the fourth side, and at least have an opening.

[0011] Electrode (2-1) and electrode (2-4) can be separated from each other.

[0012] Electrode (2-2) and electrode (2-3) can be separated from each other.

[0013] Electrode (2-1) and electrode (2-2) can be separated from each other, electrode (2-3) and electrode (2-4) can be separated from each other, electrode (2-1) and electrode (2-4) can be connected to each other, and electrode (2-2) and electrode (2-3) can be connected to each other.

[0014] The intermediate electrode may include a first intermediate electrode, a second intermediate electrode, and a third intermediate electrode spaced apart from each other. Each of the first, second, and third intermediate electrodes may overlap with a region of the first electrode and a region of the second electrode.

[0015] The first intermediate electrode may include a first region corresponding to a first side of the first electrode and a second region corresponding to the (2-2) electrode; the second intermediate electrode may include a first region corresponding to a second side of the first electrode and a second region corresponding to the (2-3) electrode; and the third intermediate electrode may include a first region corresponding to a third side of the first electrode and a second region corresponding to the (2-4) electrode.

[0016] In the plan view, the first intermediate electrode may overlap with each of the following: the first side of the first electrode, the first corner where the first and second sides of the first electrode contact each other, and the (2-2)th electrode. In the plan view, the second intermediate electrode may overlap with each of the following: the second side of the first electrode, the second corner where the second and third sides of the first electrode contact each other, and the (2-3)th electrode. In the plan view, the third intermediate electrode may overlap with each of the following: the third side of the first electrode, the third corner where the third and fourth sides of the first electrode contact each other, and the (2-4)th electrode.

[0017] The first contact electrode can overlap with the fourth side of the first electrode, and the second contact electrode can overlap with the (2-1)th electrode.

[0018] The pixel may also include an insulating layer over the first electrode and the second electrode. The insulating layer may include a first opening exposing a region corresponding to a fourth side of the first electrode and a second opening exposing a region of the (2-1)th electrode.

[0019] The insulating layer may cover other areas corresponding to each of the first electrode, the first to third sides of the first electrode, the (2-2) electrode, the (2-3) electrode, and the (2-4) electrode.

[0020] The light-emitting element may include: a plurality of first light-emitting elements located between the first side of the first electrode and the (2-1) electrode; a plurality of second light-emitting elements located between the second side of the first electrode and the (2-2) electrode; a plurality of third light-emitting elements located between the third side of the first electrode and the (2-3) electrode; and a plurality of fourth light-emitting elements located between the fourth side of the first electrode and the (2-4) electrode.

[0021] The first light-emitting element can form a first series stage connected in parallel between the first side of the first electrode and the (2-1) electrode; the second light-emitting element can form a second series stage connected in parallel between the second side of the first electrode and the (2-2) electrode; the third light-emitting element can form a third series stage connected in parallel between the third side of the first electrode and the (2-3) electrode; and the fourth light-emitting element can form a fourth series stage connected in parallel between the fourth side of the first electrode and the (2-4) electrode.

[0022] In a planar view, multiple light-emitting elements can be placed between the first and second electrodes along the periphery of the first electrode.

[0023] The first electrode may have a hexagonal shape including a first side, a second side, a third side, a fourth side, a fifth side, and a sixth side. The second electrode may include: a (2-1) electrode adjacent to the first side of the first electrode; a (2-2) electrode adjacent to the second side of the first electrode; a (2-3) electrode adjacent to the third side of the first electrode; a (2-4) electrode adjacent to the fourth side of the first electrode; a (2-5) electrode adjacent to the fifth side of the first electrode; and a (2-6) electrode adjacent to the sixth side of the first electrode.

[0024] The light-emitting element may include: at least one first light-emitting element between a first side of the first electrode and the (2-1) electrode; at least one second light-emitting element between a second side of the first electrode and the (2-2) electrode; at least one third light-emitting element between a third side of the first electrode and the (2-3) electrode; at least one fourth light-emitting element between a fourth side of the first electrode and the (2-4) electrode; at least one fifth light-emitting element between a fifth side of the first electrode and the (2-5) electrode; and at least one sixth light-emitting element between a sixth side of the first electrode and the (2-6) electrode.

[0025] According to another aspect of this disclosure, a display device is provided, the display device comprising: a substrate including a plurality of pixel regions; and pixels, each of the pixel regions including: a first electrode and a second electrode, the first electrode being on the substrate and the second electrode surrounding at least a portion of the first electrode; a plurality of light-emitting elements between the first electrode and the second electrode; a first contact electrode on the first electrode, the first contact electrode electrically connecting the first electrode and the light-emitting elements; a second contact electrode on the second electrode, the second contact electrode electrically connecting the second electrode and the light-emitting elements; and an intermediate electrode on the first electrode and the second electrode, the intermediate electrode including a first region overlapping the first electrode and a second region overlapping the second electrode, the first region and the second region being integrally connected to each other, and the first contact electrode, the second contact electrode and the intermediate electrode being disposed in the same layer. Attached Figure Description

[0026] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0027] In the accompanying drawings, dimensions may be exaggerated for clarity. It should be understood that when an element is referred to as "between" two elements, it can be the only element between the two elements, or there may be one or more intervening elements. The same reference numerals always denote the same elements.

[0028] Figure 1 This is a perspective view schematically illustrating a light-emitting element according to one or more exemplary embodiments of the present disclosure.

[0029] Figure 2 yes Figure 1 The image shows a cross-sectional view of the light-emitting element.

[0030] Figure 3 This is a perspective view schematically illustrating a light-emitting element according to another exemplary embodiment of the present disclosure.

[0031] Figure 4 yes Figure 3 The image shows a cross-sectional view of the light-emitting element.

[0032] Figure 5 A display device according to one or more exemplary embodiments of the present disclosure is shown, and specifically, it is a display device using... Figures 1 to 4 A schematic plan view of a display device in which any one of the light-emitting elements shown is used as a light source.

[0033] Figures 6A to 6C It is shown Figure 5 Circuit diagrams of various exemplary embodiments of the electrical connections between components included in a pixel are shown.

[0034] Figure 7 It is shown schematically. Figure 5 A planar view of one pixel in the pixel diagram shown.

[0035] Figure 8A Is only shown Figure 7 The diagram shows the first to fourth electrodes, the intermediate electrode, and the first insulating layer.

[0036] Figure 8B It is shown Figure 8A A schematic plan view of another exemplary embodiment of the first and second electrodes shown.

[0037] Figure 9 It is along Figure 7 The sectional view shown is taken by line I-I'.

[0038] Figure 10 It is along Figure 7 The sectional view shown is taken from line II-II'.

[0039] Figure 11 This is a plan view illustrating the drive current flowing through a pixel according to one or more exemplary embodiments of the present disclosure, and illustrating the current flowing through, for example... Figure 7 The driving current of the pixel shown.

[0040] Figure 12 schematically shown Figure 7 The state in which the pixel is bonded to the upper substrate is shown, and corresponds to... Figure 7 The cross-sectional view of line I-I' shown.

[0041] Figure 13 It is shown Figure 7 A schematic plan view of another exemplary embodiment of the first to third intermediate electrodes in the pixel shown.

[0042] Figure 14 It is along Figure 13 The sectional view shown is taken from line III-III'.

[0043] Figure 15A This is a schematic plan view of pixels according to another exemplary embodiment of the present disclosure.

[0044] Figure 15B It is shown Figure 15A A schematic plan view of another exemplary embodiment of the first dike pattern shown.

[0045] Figure 16 It is along Figure 15A The cross-sectional view shown is taken along line IV-IV'.

[0046] Figure 17 It is along Figure 15A The cross-sectional view shown is taken by line V-V'.

[0047] Figure 18 It shows Figure 17 Another exemplary embodiment of the first dike pattern shown, and corresponding to Figure 15A The cross-sectional view of line V-V' shown.

[0048] Figures 19A to 19E It is shown Figure 7 A schematic plan view of another exemplary embodiment of the first and second electrodes shown.

[0049] Figure 20 A pixel is schematically shown according to yet another exemplary embodiment of the present disclosure, and is a schematic plan view of pixels configured only in a portion of the display element layer. Detailed Implementation

[0050] This disclosure can be applied to various variations and different shapes, and therefore is described in detail only by specific examples. However, the embodiments are not limited to certain shapes, but are applicable to all variations as well as equivalent materials and substitutions. The included drawings are shown in such a manner that they have been extended for better understanding.

[0051] The same reference numerals always denote the same elements. In the accompanying drawings, the thickness of certain lines, layers, components, elements, or features may be exaggerated for clarity. It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, the "first" element discussed below may also be referred to as the "second" element without departing from the teachings of this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise.

[0052] It should also be understood that, when used in this specification, the terms "include" and / or "including" specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence and / or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Furthermore, the expression that an element, such as a layer, region, substrate, or plate, is placed "on" or "above" another element indicates not only that the element is placed "directly" on or "just" above another element, but also that another element is interposed between the element and the other element. Conversely, the expression that an element, such as a layer, region, substrate, or plate, is placed "below" or "under" another element indicates not only that the element is placed "directly" below or "just" below another element, but also that another element is interposed between the element and the other element.

[0053] In this disclosure, it will be understood that when an element (e.g., a first element) is "(operably or communicatively) coupled" to or "(operably or communicatively) connected" to another element (e.g., a second element), the element may be directly coupled to or connected to the other element, or an intermediary element (e.g., a third element) may exist between the element and the other element. Conversely, it should be understood that when an element (e.g., a first element) is "directly coupled" to or "directly connected" to another element (e.g., a second element), there is no intermediary element (e.g., a third element) between the element and the other element.

[0054] In the following description, exemplary embodiments of the present disclosure and matters necessary for those skilled in the art to readily understand the contents of the disclosure will be described in detail with reference to the accompanying drawings. In the following description, unless the context clearly indicates otherwise, the singular forms in this disclosure are intended to include the plural forms as well.

[0055] Figure 1 This is a perspective view schematically illustrating a light-emitting element according to one or more exemplary embodiments of the present disclosure. Figure 2 yes Figure 1 The image shows a cross-sectional view of the light-emitting element. Figure 3 This is a perspective view schematically illustrating a light-emitting element according to another exemplary embodiment of the present disclosure. Figure 4 yes Figure 3 The image shows a cross-sectional view of the light-emitting element.

[0056] In one or more exemplary embodiments of this disclosure, the type and / or shape of the light-emitting element are not limited to... Figures 1 to 4 The implementation shown is illustrated.

[0057] Reference Figures 1 to 4 Each light-emitting element (LD) may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. In some exemplary embodiments, the light-emitting element (LD) may implement a light-emitting stack structure, wherein the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are stacked sequentially.

[0058] The light-emitting element (LD) can be configured to extend in one direction. When assuming the extension direction of the LD is the length direction, the LD may include one end (or lower end) and another end (or upper end) along the extension direction. Either the first semiconductor layer 11 or the second semiconductor layer 13 may be disposed at one end (or lower end) of the LD, and the other semiconductor layer 11 or the second semiconductor layer 13 may be disposed at the other end (or upper end) of the LD. In one or more exemplary embodiments, the first semiconductor layer 11 may be disposed at one end (or lower end) of the LD, and the second semiconductor layer 13 may be disposed at the other end (or upper end) of the LD.

[0059] The light-emitting element (LD) can be configured in various shapes. In one or more exemplary embodiments, the LD may have a rod-like or bar-like shape that is long in its longitudinal direction (i.e., its aspect ratio is greater than 1). In some embodiments of this disclosure, the length L of the LD in its longitudinal direction may be greater than the diameter D (or the width of the cross-section) of the LD. The LD may include, for example, a light-emitting diode (LED) manufactured small enough to have a diameter D and / or length L on the micrometer to nanometer scale.

[0060] The diameter D of the light-emitting element (LD) can be from about 0.5 μm to 500 μm, and the length L of the light-emitting element (LD) can be from about 1 μm to 1000 μm. However, the diameter D and length L of the light-emitting element (LD) are not limited to these, and the dimensions of the light-emitting element (LD) can be modified to suit the requirements (or design conditions) of lighting devices or self-emissive display devices that use the light-emitting element (LD).

[0061] The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For instance, the first semiconductor layer 11 may include any semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include an n-type semiconductor layer doped with a first conductive dopant (or an n-type dopant) (such as Si, Ge, or Sn). However, the materials constituting the first semiconductor layer 11 are not limited thereto. In some embodiments, the first semiconductor layer 11 may be configured with various materials. In some embodiments of this disclosure, the first semiconductor layer 11 may include gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or an n-type dopant). Along the length L direction of the light-emitting element LD, the first semiconductor layer 11 may include an upper surface in contact with the active layer 12 and a lower surface exposed to the outside. The lower surface of the first semiconductor layer 11 may be one end (or lower end) of the light-emitting element LD.

[0062] The active layer 12 is formed on the first semiconductor layer 11 and can be formed as a single quantum well structure or a multi-quantum well structure. In one or more exemplary embodiments, when the active layer 12 is formed as a multi-quantum well structure, a barrier layer (not shown), a strain enhancement layer, and a well layer constituting a unit can be periodically and repeatedly stacked in the active layer 12. The strain enhancement layer can have a smaller lattice constant than the barrier layer to further enhance the strain, such as the compressive strain applied to the well layer. However, the structure of the active layer 12 is not limited to the embodiments described above.

[0063] The active layer 12 can emit light with wavelengths from 400 nm to 900 nm and can use a dual heterostructure. In some embodiments of this disclosure, a cladding layer (not shown) doped with a conductive dopant can be formed on the top and / or bottom of the active layer 12 along the length L of the light-emitting element LD. In some exemplary embodiments, the cladding layer can be formed as an AlGaN layer or an InAlGaN layer. In some embodiments, materials such as AlGaN or AlInGaN can be used to form the active layer 12. In some embodiments, the active layer 12 can be configured with various materials. The active layer 12 may include a first surface in contact with the first semiconductor layer 11 and a second surface in contact with the second semiconductor layer 13.

[0064] When an electric field with a certain voltage (e.g., a set or predetermined voltage) or greater is applied between the ends of the light-emitting element (LD), the LD emits light when electron-hole pairs recombine in the active layer 12. By controlling the emission of the LD using this principle, the LD can be used as a light source (or light source) for various light-emitting devices, including pixels of a display device.

[0065] A second semiconductor layer 13 is formed on the second surface of the active layer 12 and may include a semiconductor layer of a different type than the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor material. For example, the second semiconductor layer 13 may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as Mg. However, the materials constituting the second semiconductor layer 13 are not limited thereto. In some embodiments, the second semiconductor layer 13 may be configured with various materials. In some embodiments of this disclosure, the second semiconductor layer 13 may include gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant). Along the length L direction of the light-emitting element LD, the second semiconductor layer 13 may include a lower surface in contact with the second surface of the active layer 12 and an upper surface exposed to the outside. The upper surface of the second semiconductor layer 13 may be the other end (or upper end) of the light-emitting element LD.

[0066] In some embodiments of this disclosure, the first semiconductor layer 11 and the second semiconductor layer 13 may have different thicknesses along the length L of the light-emitting element LD. For example, along the length L of the light-emitting element LD, the first semiconductor layer 11 may have a relatively thicker thickness than the second semiconductor layer 13. Therefore, the active layer 12 of the light-emitting element LD can be positioned closer to the upper surface of the second semiconductor layer 13 than the lower surface of the first semiconductor layer 11.

[0067] Although each of the first semiconductor layer 11 and the second semiconductor layer 13 is shown configured with a single layer, this disclosure is not limited thereto. In some embodiments of this disclosure, each of the first semiconductor layer 11 and the second semiconductor layer 13 may further include at least one layer, such as a cladding layer and / or a tensile strain barrier reducing (TSBR) layer, depending on the material of the active layer 12. The TSBR layer may be a strain reducing layer disposed between semiconductor layers with different lattice structures to perform a buffering function for reducing lattice constant differences. The TSBR may be configured with a p-type semiconductor layer, such as p-GaInP, p-AlInP, or p-AlGaInP, but this disclosure is not limited thereto.

[0068] In some embodiments, in addition to the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 as described above, the light-emitting element LD may further include an additional electrode (not shown) disposed on top of the second semiconductor layer 13 (hereinafter referred to as the "first additional electrode"). In some other embodiments, the light-emitting element LD may further include another additional electrode (not shown) disposed at one end (e.g., the lower end) of the first semiconductor layer 11 (hereinafter referred to as the "second additional electrode").

[0069] Each of the first and second additional electrodes may be an ohmic contact electrode, but this disclosure is not limited thereto. In some embodiments, each of the first and second additional electrodes may be a Schottky contact electrode. The first and second additional electrodes may include conductive materials (or substances). For example, the first and second additional electrodes may include opaque metals using one or a mixture of chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), and any oxides or alloys thereof, but this disclosure is not limited thereto. In some embodiments, the first and second additional electrodes may include transparent conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), or indium tin zinc oxide (ITZO).

[0070] The materials included in the first and second additional electrodes may be the same or different from each other. The first and second additional electrodes may be substantially transparent or translucent. Therefore, light generated in the light-emitting element LD can be emitted to the outside of the light-emitting element LD by passing through the first and second additional electrodes. In some embodiments, when light generated in the light-emitting element LD does not pass through the first and second additional electrodes and is emitted to the outside of the light-emitting element LD through a region other than the two ends of the light-emitting element LD, the first and second additional electrodes may comprise opaque metals.

[0071] In some embodiments of this disclosure, the light-emitting element LD may further include an insulating film 14. However, in some embodiments, the insulating film 14 may be omitted, or the insulating film 14 may be configured to cover only a portion of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0072] The insulating film 14 prevents electrical short circuits that may occur when the active layer 12 comes into contact with conductive materials other than the first semiconductor layer 11 and the second semiconductor layer 13. Furthermore, the insulating film 14 reduces or minimizes surface defects in the light-emitting element (LD), thereby improving the LD's lifetime and luminous efficiency. Additionally, when multiple LDs are densely arranged, the insulating film 14 prevents unwanted short circuits that may occur between the LDs. Whether or not the insulating film 14 is provided is not limited, as long as it prevents short circuits between the active layer 12 and external conductive materials.

[0073] The insulating film 14 can be configured to completely surround the periphery (or outer periphery) of the light-emitting stack structure including the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0074] Although the above embodiments describe an insulating film 14 configured to completely surround the periphery (or outer periphery) of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, this disclosure is not limited thereto. In some embodiments, when the light-emitting element LD includes a first additional electrode, the insulating film 14 may completely surround the periphery (or outer periphery) of each of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the first additional electrode. In some other embodiments, the insulating film 14 may not completely surround the periphery (or outer periphery) of the first additional electrode, or it may surround only a portion of the periphery (or outer periphery) of the first additional electrode and may not surround another portion of the periphery (or outer periphery) of the first additional electrode. In some embodiments, when the first additional electrode is disposed at another end (or upper end) of the light-emitting element LD and the second additional electrode is disposed at one end (or lower end) of the light-emitting element LD, the insulating film 14 may expose at least one region of each of the first and second additional electrodes.

[0075] The insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include materials derived from silicon dioxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiON), aluminum oxide (AlO) x At least one insulating material selected from the group consisting of titanium dioxide (TiO2), etc. However, this disclosure is not limited thereto, and various materials with insulating properties can be used as the material of the insulating film 14.

[0076] In some implementations, such as Figure 3 and Figure 4 As shown, the light-emitting element LD' may include a light-emitting pattern 10' having a core-shell structure. A first semiconductor layer 11' may be located at the core (i.e., the middle (or center) of the light-emitting element LD'), an active layer 12' may be configured and / or formed in a shape surrounding the periphery (or outer periphery) of the first semiconductor layer 11' along the length L direction of the light-emitting element LD', and a second semiconductor layer 13' may be configured and / or formed in a shape surrounding the active layer 12' along the length L direction of the light-emitting element LD'. Furthermore, the light-emitting element LD' may also include an additional electrode 15' surrounding at least one side of the second semiconductor layer 13'. In some embodiments, the light-emitting element LD' may also include an insulating film 14', which is disposed on the periphery (or outer periphery) of the light-emitting pattern 10' having a core-shell structure and comprises a transparent insulating material. The light-emitting element LD' including the light-emitting pattern 10' having a core-shell structure can be manufactured by a growth process.

[0077] The aforementioned light-emitting elements LD or LD' can be used as light sources in various display devices. The light-emitting elements LD or LD' can be manufactured using surface treatment processes. For example, when multiple light-emitting elements LD or LD' to be supplied to each pixel area (e.g., the light-emitting area of ​​each pixel or the light-emitting area of ​​each sub-pixel) are mixed in a liquid solution (or solvent), each light-emitting element LD or LD' can be surface-treated so that the light-emitting elements LD or LD' do not aggregate unevenly in the solution, but are uniformly dispersed in the solution.

[0078] The light-emitting unit (or light-emitting device) including the aforementioned light-emitting elements LD or LD' can be used in various types of devices that require a light source, including display devices. When multiple light-emitting elements LD or LD' are arranged in the light-emitting area of ​​each pixel of a display panel, the light-emitting elements LD or LD' can be used as the light source for the pixel. However, the application areas of light-emitting elements LD or LD' are not limited to the examples above. For example, light-emitting elements LD or LD' can be used in other types of devices that require a light source, such as lighting devices.

[0079] Figure 5 A display device according to one or more exemplary embodiments of the present disclosure is shown, and specifically, it is a display device using... Figures 1 to 4 A schematic plan view of a display device in which any one of the light-emitting elements shown is used as a light source.

[0080] exist Figure 5 For convenience, the structure of the display device is briefly shown based on the display area DA in which the image is displayed.

[0081] Reference Figures 1 to 5 A display device according to one or more exemplary embodiments of the present disclosure may include a substrate SUB, a plurality of pixels PXL (each pixel PXL includes at least one light-emitting element LD) disposed on the substrate SUB, a driving unit disposed on the substrate SUB to drive the pixels PXL, and a line unit connecting the pixels PXL and the driving unit.

[0082] This disclosure can be applied to any electronic device in which a display surface is applied to at least one of its surfaces, such as smartphones, televisions, tablet PCs, mobile phones, video phones, e-book readers, desktop PCs, laptop PCs, netbooks, workstations, servers, personal digital assistants (PDAs), portable multimedia players (PMPs), MP3 players, medical devices, cameras, or wearable devices.

[0083] Based on the method of driving the light-emitting element (LD), display devices can be classified into passive matrix display devices and active matrix display devices. In some exemplary embodiments, when the display device is implemented as an active matrix display device, each of the pixels PXL may include a driving transistor for controlling the amount of current supplied to the light-emitting element (LD), a switching transistor for transmitting data signals to the driving transistor, etc.

[0084] Display devices can be configured in various shapes. In some exemplary embodiments, the display device can be configured as a rectangular plate shape with two pairs of parallel sides, but this disclosure is not limited thereto. When the display device is configured as a rectangular plate shape, either pair of sides can be configured to be longer than the other pair of sides. For convenience, a case is shown where the display device is configured as a rectangle with a pair of long sides and a pair of short sides. The direction of extension of the long side is denoted as the second direction DR2, the direction of extension of the short side is denoted as the first direction DR1, and the direction perpendicular to the direction of extension of the long and short sides is denoted as the third direction DR3. In a display device configured as a rectangular plate shape, the corner where one long side and one short side contact (or intersect) each other can have a rounded shape.

[0085] The substrate SUB may include the display area DA and the non-display area NDA.

[0086] The display area DA can be the area where pixels PXL are configured for displaying images. The non-display area NDA can be the area where driving units for driving pixels PXL and a portion of line units connecting pixels PXL and driving units are configured. For convenience, in Figure 5 Only one pixel PXL is shown, but multiple pixels PXL can be set in the display area DA of the substrate SUB.

[0087] The non-display area NDA can be located at least one side of the display area DA. The non-display area NDA can surround the display area DA along its edge or periphery. The non-display area NDA can be provided with line units connected to the pixel PXL and driving units connected to the line units and driving the pixel PXL.

[0088] The line unit can electrically connect the driving unit and the pixel PXL. The line unit can be a fan-out line that provides a signal to each pixel PXL and is connected to signal lines (e.g., scan lines, data lines, emission control lines, etc. connected to each pixel PXL). Alternatively, the line unit can be a fan-out line connected to signal lines (e.g., control lines, sensing lines, etc. connected to each pixel PXL) to compensate for changes in the electrical characteristics of each pixel PXL in real time.

[0089] The substrate SUB may include a transparent insulating material to allow light to pass through it. The substrate SUB may be a rigid substrate or a flexible substrate.

[0090] One region on the substrate SUB can be designated as a display region DA, where pixel PXL is disposed, and another region on the substrate SUB can be designated as a non-display region NDA. In some exemplary embodiments, the substrate SUB may include a display region DA and a non-display region NDA, where the display region DA includes a pixel region in which the corresponding pixel PXL is disposed, and the non-display region NDA is disposed at the periphery of the display region DA (or adjacent to the display region DA).

[0091] Each of the pixels PXL can be disposed in the display area DA. In some exemplary embodiments of this disclosure, the pixels PXL can be arranged in a stripe arrangement or an RGBG arrangement in the display area DA, but this disclosure is not limited thereto. The RGBG arrangement structure can be referred to as an RGBG matrix structure (e.g., Matrix structure or RGBG structure (e.g., structure)). It is a registered trademark of Samsung Display Co., Ltd. of South Korea.

[0092] Each pixel PXL may include at least one light-emitting element (LD) driven by a corresponding scan signal and a corresponding data signal. The LD may have dimensions ranging from nanometer to micrometer scale and may be connected in parallel with other light-emitting elements disposed nearby. However, this disclosure is not limited thereto. The LD may constitute the light source for each pixel PXL.

[0093] Each pixel PXL may include at least one light source, such as a light-emitting element (LD), driven by a certain signal (e.g., a setting or predetermined signal, such as a scan signal and / or a data signal) and / or a power source (e.g., a setting or predetermined power source, such as a first driving power source and / or a second driving power source). However, in the exemplary embodiments of this disclosure, the types of light-emitting elements (LDs) that can be used as light sources for pixels PXL are not limited thereto.

[0094] The driving unit provides signals (e.g., setting or pre-defined signals) and power (e.g., setting or pre-defined power) to each pixel PXL via line units, and thus can control the driving of the pixel PXL. The driving unit may include a scan driver, a transmit driver, a data driver, and a timing controller.

[0095] Figures 6A to 6C It is shown Figure 5 The circuit diagram shows various implementations of the electrical connection relationships between components contained in a pixel.

[0096] For example, Figures 6A to 6C Different embodiments of the electrical connection relationships between components included in a pixel PXL applicable to an active display device are shown. However, the types of components included in a pixel PXL to which the embodiments of this disclosure are applicable are not limited to these.

[0097] exist Figures 6A to 6C In the middle, the pixel PXL comprehensively includes not only Figure 5 The components included in each of the pixels PXL shown, as well as the areas in which the components are set.

[0098] Reference Figures 1 to 6C A pixel PXL (hereinafter referred to as a "pixel") may include a light-emitting unit EMU that generates light with a brightness corresponding to the data signal. Additionally, the pixel PXL may optionally include pixel circuitry 144 for driving the light-emitting unit EMU.

[0099] The light-emitting unit (EMU) may include a plurality of light-emitting elements (LDs) connected in parallel between a first power line PL1, which is energized by a first driving power supply VDD, and a second power line PL2, which is energized by a second driving power supply VSS. For example, the EMU may include a first electrode EL1 (or "first alignment electrode") connected to the first driving power supply VDD via pixel circuit 144 and the first power line PL1, a second electrode EL2 (or "second alignment electrode") connected to the second driving power supply VSS via the second power line PL2, and a plurality of light-emitting elements (LDs) connected in parallel in the same direction between the first electrode EL1 and the second electrode EL2. In some embodiments of this disclosure, the first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

[0100] Each of the light-emitting elements (LDs) included in the light-emitting unit (EMU) may include one end connected to a first driving power supply VDD via a first electrode EL1 and the other end connected to a second driving power supply VSS via a second electrode EL2. The first driving power supply VDD and the second driving power supply VSS may have different potentials. For example, the first driving power supply VDD may be set to a high potential power supply, and the second driving power supply VSS may be set to a low potential power supply.

[0101] Light-emitting elements (LDs) connected in parallel in the same direction between a first electrode EL1 and a second electrode EL2, which are provided with voltages of different potentials, can each form an effective light source. The effective light sources can constitute the light-emitting unit (EMU) of the pixel PXL.

[0102] Each of the light-emitting elements (LDs) in the light-emitting unit (EMU) can emit light with a brightness corresponding to the driving current provided by the corresponding pixel circuit 144. For example, the pixel circuit 144 can provide the light-emitting unit (EMU) with a driving current corresponding to the grayscale value of the corresponding frame data during each frame period. The driving current provided to the light-emitting unit (EMU) can be distributed to flow through each of the parallel-connected light-emitting elements (LDs). Therefore, the light-emitting unit (EMU) can emit light with a brightness corresponding to the driving current, while each light-emitting element (LD) emits light with a brightness corresponding to the current flowing through it.

[0103] In some embodiments, in addition to the light-emitting element LD connected in the forward direction and forming a corresponding effective light source, the light-emitting unit (EMU) may also include at least one ineffective light source, such as a reverse light-emitting element LDr. The reverse light-emitting element LDr is connected in parallel with the light-emitting element LD forming the effective light source between the first electrode EL1 and the second electrode EL2, and may be connected between the first electrode EL1 and the second electrode EL2 in the opposite direction to the direction in which the light-emitting element LD is connected (e.g., the reverse direction). Although a certain driving voltage (e.g., a set or predetermined driving voltage, such as a forward driving voltage) is applied between the first electrode EL1 and the second electrode EL2, the reverse light-emitting element LDr remains in an ineffective state (e.g., a reverse biased state), and therefore, essentially no current flows through the reverse light-emitting element LDr.

[0104] Pixel circuit 144 can be connected to the scan line Si and data line Dj of the corresponding pixel PXL. In the example, assuming that pixel PXL is arranged in the i-th (i is a natural number) row and j-th (j is a natural number) column of display area DA, pixel circuit 144 of pixel PXL can be connected to the i-th scan line Si and j-th data line Dj of display area DA. In some embodiments, pixel circuit 144 may include a first transistor T1 and a second transistor T2, as well as a storage capacitor Cst. However, the structure of pixel circuit 144 is not limited to... Figures 6A to 6C The implementation shown is illustrated.

[0105] First, refer to Figure 6A The pixel circuit 144 may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0106] The first terminal of the second transistor T2 (e.g., a switching transistor) can be connected to the j-th data line Dj, and the second terminal of the second transistor T2 can be connected to the first node N1. The first and second terminals of the second transistor T2 are different terminals. For example, when the first terminal is the source electrode, the second terminal can be the drain electrode. In some embodiments, the gate electrode of the second transistor T2 can be connected to the i-th scan line Si. When a scan signal with a voltage (e.g., a low-level voltage) that enables the second transistor T2 to conduct is provided from the i-th scan line Si, the second transistor T2 conducts to electrically connect the j-th data line Dj and the first node N1. The data signal of the corresponding frame is provided to the j-th data line Dj. Therefore, the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1 is charged into the storage capacitor Cst (e.g., the storage capacitor Cst can be charged with a voltage corresponding to the data signal).

[0107] The first terminal of the first transistor T1 (e.g., a driving transistor) can be connected to the first driving power supply VDD, and the second terminal of the first transistor T1 can be electrically connected to the first electrode EL1 of the light-emitting unit EMU. The gate electrode of the first transistor T1 can be connected to the first node N1. The voltage of the first transistor T1 corresponds to the voltage of the first node N1, controlling the amount of driving current supplied to the light-emitting element LD.

[0108] One electrode of the storage capacitor Cst can be connected to the first drive power supply VDD, and the other electrode of the storage capacitor Cst can be connected to the first node N1. The storage capacitor Cst is charged with a voltage corresponding to the data signal provided to the first node N1, and the charged voltage is maintained until the data signal of the next frame is provided.

[0109] exist Figure 6A The image shows a pixel circuit 144, which includes a second transistor T2 for transmitting a data signal to the interior of the pixel PXL, a storage capacitor Cst for storing a charge corresponding to the data signal, and a first transistor T1 for providing a drive current corresponding to the data signal to the light-emitting element LD.

[0110] However, this disclosure is not limited thereto, and the structure of the pixel circuit 144 can be modified and implemented differently. In some exemplary embodiments, the pixel circuit 144 may also include at least one transistor element, such as a transistor element for compensating the threshold voltage of the first transistor T1, a transistor element for initializing the first node N1, and / or a transistor element for controlling the emission time of the light-emitting element LD, or other circuit elements such as a boost capacitor for increasing the voltage of the first node N1.

[0111] Despite Figure 6AThe illustration shows a scenario where all transistors (e.g., first transistor T1 and second transistor T2) included in pixel circuit 144 are implemented using P-type transistors, but this disclosure is not limited thereto. For example, at least one of the first transistor T1 and second transistor T2 included in pixel circuit 144 may be implemented using N-type transistors.

[0112] In some implementations, pixel circuitry 144 may also be connected to at least one other scan line. For example, as... Figure 6B As shown, when pixel PXL is positioned in the i-th row of display area DA, the pixel circuit 144 of the corresponding pixel PXL can also be connected to the (i-1)-th scan line Si-1 (e.g., the previous scan line) and / or the (i+1)-th scan line Si+1 (e.g., the next scan line). Furthermore, in some embodiments, in addition to the first driving power supply VDD and the second driving power supply VSS, the pixel circuit 144 can also be connected to a third power supply. For example, the pixel circuit 144 can also be connected to the initialization power supply Vint. The pixel circuit 144 may include first transistors T1 to seventh transistors T7 and a storage capacitor Cst.

[0113] The first terminal (e.g., source electrode) of the first transistor T1 (e.g., a driving transistor) can be connected to the first driving power supply VDD via the fifth transistor T5, and the second terminal (e.g., drain electrode) of the first transistor T1 can be connected to one end of the light-emitting element LD via the sixth transistor T6. The gate electrode of the first transistor T1 can be connected to the first node N1. The voltage of the first transistor T1 and the first node N1 control the amount of driving current flowing between the first driving power supply VDD and the second driving power supply VSS via the light-emitting element LD.

[0114] A second transistor T2 (e.g., a switching transistor) may be connected between the j-th data line Dj connected to pixel PXL and the first terminal of the first transistor T1. In some embodiments, the gate electrode of the second transistor T2 may be connected to the i-th scan line Si connected to pixel PXL. When a scan signal with a gate on-state voltage (e.g., a low-level voltage) is provided from the i-th scan line Si, the second transistor T2 may be turned on to electrically connect the j-th data line Dj to the first terminal of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal provided from the j-th data line Dj is transmitted to the first transistor T1.

[0115] The third transistor T3 can be connected between the second terminal of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 can be connected to the i-th scan line Si. When a scan signal with a gate turn-on voltage is provided from the i-th scan line Si, the third transistor T3 can be turned on to electrically connect the second terminal of the first transistor T1 and the first node N1 to each other.

[0116] A fourth transistor T4 can be connected between the first node N1 and the initialization power line IPL to which the initialization power supply Vint is applied. The gate electrode of the fourth transistor T4 can be connected to the previous scan line, for example, the (i-1)th scan line Si-1. When a scan signal with a gate on-state voltage (e.g., a low-level voltage) is provided to the (i-1)th scan line Si-1, the fourth transistor T4 can be turned on to transfer the voltage of the initialization power supply Vint to the first node N1. The initialization power supply Vint can have a voltage equal to or less than the minimum voltage of the data signal.

[0117] The fifth transistor T5 can be connected between the first drive power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 can be connected to a corresponding emitter control line, such as the i-th emitter control line Ei. The fifth transistor T5 can be turned off when an emitter control signal with a gate cutoff voltage (e.g., a high-level voltage) is provided to the i-th emitter control line Ei, and the fifth transistor T5 can be turned on under other conditions.

[0118] The sixth transistor T6 can be connected between the first transistor T1 and one end of the light-emitting element LD (e.g., the first electrode EL1 of the light-emitting unit EMU). The gate electrode of the sixth transistor T6 can be connected to the i-th emission control line Ei. The sixth transistor T6 can be turned off when an emission control signal with a gate cutoff voltage (e.g., a high-level voltage) is provided to the i-th emission control line Ei, and the sixth transistor T6 can be turned on under other conditions.

[0119] The seventh transistor T7 can be connected between one end of the light-emitting element LD (e.g., the first electrode EL1 or the second node N2 of the light-emitting unit EMU) and the initialization power line IPL. The gate electrode of the seventh transistor T7 can be connected to any of the scan lines in the next row, for example, the (i+1)th scan line Si+1. When a scan signal with a gate on-state voltage (e.g., a low-level voltage) is provided to the (i+1)th scan line Si+1, the seventh transistor T7 can be turned on to provide the voltage of the initialization power supply Vint to one end of the light-emitting element LD (e.g., the first electrode EL1 of the light-emitting unit EMU).

[0120] The storage capacitor Cst can be connected between the first drive power supply VDD and the first node N1. The storage capacitor Cst can be charged with a voltage corresponding to the data signal supplied to the first node N1 and the threshold voltage of the first transistor T1 in each frame period (or store the corresponding charge).

[0121] Despite Figure 6BThe illustration shows a configuration where all transistors (e.g., first transistor T1 through seventh transistor T7) in pixel circuit 144 are implemented using P-type transistors, but this disclosure is not limited thereto. For example, at least one of the first transistors T1 through seventh transistor T7 may be replaced with an N-type transistor.

[0122] In one or more exemplary embodiments of this disclosure, the configuration of the pixel circuitry 144 is not limited to... Figure 6A and Figure 6B The implementation shown is illustrated. For example, pixel circuit 144 can be as follows: Figure 6C The configuration is as shown in the embodiment illustrated.

[0123] like Figure 6C As shown, pixel circuit 144 can also be connected to control line CLI and sensing line SENj. In this example, pixel circuit 144 can be connected to the i-th control line CLI and the j-th sensing line SENj of display area DA. Besides... Figure 6A In addition to the first transistor T1 and the second transistor T2 shown, the pixel circuit 144 may also include a third transistor T3.

[0124] The third transistor T3 can be connected between the first transistor T1 and the j-th sensing line SENj. For example, one electrode of the third transistor T3 can be connected to the first terminal (e.g., the source electrode) of the first transistor T1, which is connected to the first electrode EL1 of the light-emitting unit EMU, and the other electrode of the third transistor T3 can be connected to the j-th sensing line SENj. When the j-th sensing line SENj is omitted, the other electrode of the third transistor T3 can be connected to the j-th data line Dj.

[0125] In some embodiments, the gate electrode of the third transistor T3 may be connected to the i-th control line CLI. When the i-th control line CLI is omitted, the gate electrode of the third transistor T3 may be connected to the i-th scan line Si. The third transistor T3 may be turned on by a control signal having a gate on-state voltage (e.g., a high-level voltage) provided to the i-th control line CLI during a sensing period (e.g., a set or predetermined sensing period) to electrically connect the j-th sensing line SENj and the source electrode of the first transistor T1.

[0126] In some implementations, the sensing period can be a period in which characteristic information (e.g., the threshold voltage of the first transistor T1, etc.) of each of the pixels PXL arranged in the display area DA can be determined. During the sensing period, a reference voltage (e.g., a set or predetermined reference voltage) that can turn on the first transistor T1 can be provided to the first node N1 via the j-th data line Dj and the second transistor T2, or the first transistor T1 can be turned on when each pixel PXL is connected to a current source, etc. When the third transistor T3 turns on in response to a control signal with a gate turn-on voltage provided to the gate electrode of the third transistor T3, the first transistor T1 can be connected to the j-th sensing line SENj via the third transistor T3. Therefore, characteristic information of each pixel PXL, including the threshold voltage of the first transistor T1, etc., can be extracted via the j-th sensing line SENj. The extracted characteristic information can be used to convert image data to compensate for characteristic deviations between pixels PXL.

[0127] Despite Figure 6C The illustration shows an embodiment where all first transistors T1 to third transistors T3 are N-type transistors, but this disclosure is not limited thereto. For example, at least one of the first transistors T1 to third transistors T3 may be replaced with a P-type transistor. Furthermore, although in Figure 6C The diagram shows an embodiment where the light-emitting unit (EMU) is connected between the pixel circuit 144 and the second driving power supply (VSS), but the light-emitting unit (EMU) can be connected between the first driving power supply (VDD) and the pixel circuit 144.

[0128] Despite Figure 6B and Figure 6C The illustration shows an embodiment where all light-emitting elements (LDs) constituting each light-emitting unit (EMU) are connected in parallel, but this disclosure is not limited thereto. In some embodiments, the EMU may be configured to include at least one series stage comprising a plurality of light-emitting elements (LDs) connected in parallel with each other. For example, the EMU may be configured as follows: Figure 6A The series / parallel hybrid structure shown is illustrated.

[0129] Reference Figure 6AThe light-emitting unit (EMU) may include a first series stage SET1 to a fourth series stage SET4 sequentially connected between a first driving power supply VDD and a second driving power supply VSS. Each of the first series stage SET1 to the fourth series stage SET4 may include an electrode pair of the corresponding series stage and a plurality of light-emitting elements (LDs) connected in parallel in the same direction between the two electrodes EL1 and CTE1_1 of the first series stage SET1, the two electrodes CTE1_2 and CTE2_1 of the second series stage SET2, the two electrodes CTE2_2 and CTE3_1 of the third series stage SET3, or the two electrodes CTE3_2 and EL2 of the fourth series stage SET4.

[0130] The first series stage SET1 may include a first electrode EL1 and a (1-1) intermediate electrode CTE1_1, and may also include at least one first light-emitting element LD1 connected between the first electrode EL1 and the (1-1) intermediate electrode CTE1_1. Furthermore, the first series stage SET1 may include a reverse light-emitting element LDr connected in parallel with the first light-emitting element LD1 between the first electrode EL1 and the (1-1) intermediate electrode CTE1_1 in the opposite direction.

[0131] The second series stage SET2 may include a (1-2) intermediate electrode CTE1_2 and a (2-1) intermediate electrode CTE2_1, and may also include at least one second light-emitting element LD2 connected between the (1-2) intermediate electrode CTE1_2 and the (2-1) intermediate electrode CTE2_1. Furthermore, the second series stage SET2 may include a reverse light-emitting element LDr connected in parallel with the second light-emitting element LD2 between the (1-2) intermediate electrode CTE1_2 and the (2-1) intermediate electrode CTE2_1 in the opposite direction.

[0132] The (1-1) intermediate electrode CTE1_1 of the first series stage SET1 and the (1-2) intermediate electrode CTE1_2 of the second series stage SET2 can be integrally configured and connected to each other. For example, the (1-1) intermediate electrode CTE1_1 and the (1-2) intermediate electrode CTE1_2 can constitute a first intermediate electrode CTE1, which is electrically connected to the continuous first series stage SET1 and second series stage SET2. When the (1-1) intermediate electrode CTE1_1 and the (1-2) intermediate electrode CTE1_2 are integrally configured, the (1-1) intermediate electrode CTE1_1 and the (1-2) intermediate electrode CTE1_2 can be different regions of the first intermediate electrode CTE1.

[0133] The third series stage SET3 may include the (2-2) intermediate electrode CTE2_2 and the (3-1) intermediate electrode CTE3_1, and may also include at least one third light-emitting element LD3 connected between the (2-2) intermediate electrode CTE2_2 and the (3-1) intermediate electrode CTE3_1. Furthermore, the third series stage SET3 may include a reverse light-emitting element LDr connected in parallel with the third light-emitting element LD3 between the (2-2) intermediate electrode CTE2_2 and the (3-1) intermediate electrode CTE3_1 in the opposite direction.

[0134] The intermediate electrode CTE2_1 (2-1) of the second series stage SET2 and the intermediate electrode CTE2_2 (2-2) of the third series stage SET3 can be integrally connected to each other. For example, the intermediate electrode CTE2_1 (2-1) and the intermediate electrode CTE2_2 (2-2) can constitute the second intermediate electrode CTE2, which is electrically connected to the continuous second series stage SET2 and the third series stage SET3. When the intermediate electrode CTE2_1 (2-1) and the intermediate electrode CTE2_2 (2-2) are integrally connected, the intermediate electrode CTE2_1 (2-1) and the intermediate electrode CTE2_2 (2-2) can be different regions of the second intermediate electrode CTE2.

[0135] The fourth series stage SET4 may include the (3-2) intermediate electrode CTE3_2 and the second electrode EL2, and may also include at least one fourth light-emitting element LD4 connected between the (3-2) intermediate electrode CTE3_2 and the second electrode EL2. Furthermore, the fourth series stage SET4 may include a reverse light-emitting element LDr connected in parallel with the fourth light-emitting element LD4 between the (3-2) intermediate electrode CTE3_2 and the second electrode EL2 in the opposite direction.

[0136] The (3-1) intermediate electrode CTE3_1 of the third series stage SET3 and the (3-2) intermediate electrode CTE3_2 of the fourth series stage SET4 can be integrally connected to each other. For example, the (3-1) intermediate electrode CTE3_1 and the (3-2) intermediate electrode CTE3_2 can constitute a third intermediate electrode CTE3, which is electrically connected to the continuous third series stage SET3 and fourth series stage SET4. When the (3-1) intermediate electrode CTE3_1 and the (3-2) intermediate electrode CTE3_2 are integrally connected, the (3-1) intermediate electrode CTE3_1 and the (3-2) intermediate electrode CTE3_2 can be different regions of the third intermediate electrode CTE3.

[0137] In the above embodiments, the first electrode EL1 of the first series stage SET1 can be the anode electrode of the light-emitting unit EMU of each pixel PXL, and the second electrode EL2 of the fourth series stage SET4 can be the cathode electrode of the light-emitting unit EMU.

[0138] As described above, the light-emitting unit (EMU) of the pixel PXL, which includes light-emitting elements (LDs) connected in a series / parallel hybrid structure, can easily control the drive current / voltage conditions to specifications suitable for products using the light-emitting unit (EMU).

[0139] For example, compared to an EMU that includes light-emitting elements (LDs) connected in parallel, an EMU that includes pixels (PXLs) with LDs connected in a hybrid series / parallel structure can reduce the drive current. Compared to an EMU that includes all LDs connected in series, an EMU that includes pixels (PXLs) with LDs connected in a hybrid series / parallel structure can reduce the drive voltage applied across the EMU.

[0140] The structure of the pixel PXL applied in this disclosure is not limited to Figures 6A to 6C The embodiments shown are illustrated, and the corresponding pixels PXL can have various structures. For example, each pixel PXL can be configured in a passive type light-emitting display device, etc. Pixel circuit 144 can be omitted, and the two ends of the light-emitting element LD included in the light-emitting unit EMU can be directly connected to the i-th scan line Si, the j-th data line Dj, the first power line PL1 to which the first driving power VDD is applied, the second power line PL2 to which the second driving power VSS is applied, and / or a control line (e.g., a setting or predetermined control line).

[0141] Figure 7 It is shown schematically. Figure 5 A planar view of one pixel in the pixel diagram shown. Figure 8A Is only shown Figure 7 The diagram shows the first to fourth electrodes, the intermediate electrode, and the first insulating layer. Figure 8B It is shown Figure 8A A schematic plan view of another embodiment of the first and second electrodes shown. Figure 9 It is along Figure 7 The sectional view shown is taken by line I-I'. Figure 10 It is along Figure 7 The sectional view shown is taken from line II-II'. Figure 11 This is a plan view illustrating the drive current flowing through a pixel according to one or more exemplary embodiments of the present disclosure, and illustrating the current flowing through, for example... Figure 7 The driving current of the pixel shown. Figure 12 schematically shown Figure 7 The state in which the pixel is bonded to the upper substrate is shown, and corresponds to... Figure 7 The cross-sectional view of line I-I' shown. Figure 13 It is shown Figure 7 A schematic plan view of another embodiment of the first to third intermediate electrodes in the pixel shown. Figure 14 It is along Figure 13 The sectional view shown is taken from line III-III'.

[0142] Figure 7 The pixels shown can be Figure 6A The pixels shown.

[0143] exist Figure 7 For the sake of convenience, the diagrams of the transistors connected to the light-emitting elements and the signal lines connected to the transistors have been omitted.

[0144] exist Figures 7 to 14 In the simplified illustration, a single pixel PXL is shown, such as the case where each electrode is shown as a single-layer electrode and each insulating layer is shown as a single-layer insulating layer. However, this disclosure is not limited thereto.

[0145] In one or more embodiments of this disclosure, the term "formed and / or disposed in the same layer" may refer to being formed in the same process, and the term "formed and / or disposed in different layers" may refer to being formed in different processes.

[0146] In one or more embodiments of this disclosure, the term "connection" between two components may include both electrical connection and physical connection.

[0147] In one or more embodiments of this disclosure, for ease of description, the transverse direction (or horizontal direction) on the plane is referred to as the first direction DR1, the longitudinal direction (or vertical direction) on the plane is referred to as the second direction DR2, and the thickness direction of the substrate SUB on the cross section is referred to as the third direction DR3. The first direction DR1, the second direction DR2, and the third direction DR3 can represent the directions represented by the first direction DR1, the second direction DR2, and the third direction DR3.

[0148] Reference Figures 1 to 6A as well as Figures 7 to 14 A display device according to one or more embodiments of the present disclosure may include a plurality of pixels PXL disposed on a substrate SUB.

[0149] The substrate SUB may include a transparent insulating material to allow light to pass through it. The substrate SUB may be a rigid substrate or a flexible substrate.

[0150] Rigid substrates may include, for example, one of glass substrates, quartz substrates, glass-ceramic substrates, and crystalline glass substrates.

[0151] The flexible substrate can be one of a membrane substrate comprising polymeric organic materials and a plastic substrate. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0152] However, the materials that make up the substrate SUB can be varied. In the manufacturing process of display devices, the materials used in the substrate SUB can have resistance to high processing temperatures (or heat resistance).

[0153] The substrate SUB may include a display area DA and a non-display area NDA. The display area DA includes at least one pixel area PXA in which a pixel PXL is disposed, and the non-display area NDA is disposed at the periphery of the display area DA (or adjacent to the periphery of the display area DA). For example, the non-display area NDA may surround the display area DA along its edge or periphery.

[0154] Pixel PXL can be arranged in a matrix and / or stripe pattern in a display area DA on the substrate SUB along a plurality of pixel rows extending in a first direction DR1 and a plurality of pixel columns extending in a second direction DR2 (e.g., intersecting the first direction DR1) other than the first direction DR1, but this disclosure is not limited thereto. In some embodiments, pixel PXL can be arranged in various configurations in the display area DA on the substrate SUB.

[0155] The pixel region PXA, where each pixel PXL is configured (or provided), may include an emitting region in which light is emitted and a peripheral region adjacent to the emitting region (or surrounding the periphery of the emitting region). In one or more exemplary embodiments of this disclosure, the peripheral region may include a non-emitting region in which no light is emitted.

[0156] Line units electrically connected to pixels PXL may be located on the substrate SUB. The line unit may include multiple signal lines for transmitting signals (e.g., setting or pre-defined signals or voltages) to each pixel PXL. The signal lines may include an i-th scan line Si for transmitting scan signals to each pixel PXL, a j-th data line Dj for transmitting data signals to each pixel PXL, and power lines PL1 and DVL for transmitting drive power to each pixel PXL. In some embodiments, the line unit may also include an transmit control line for transmitting transmit control signals to each pixel PXL. In some other embodiments, the line unit may also include sensing lines and control lines connected to each pixel PXL.

[0157] Each pixel PXL may include a pixel circuit layer PCL and a display element layer DPL. The pixel circuit layer PCL is disposed on the substrate SUB and includes pixel circuitry 144. The display element layer DPL includes multiple light-emitting elements (LDs). The light-emitting elements (LDs) may be located in the pixel region PXA of each pixel PXL.

[0158] For simplicity, the pixel circuit layer PCL will be described first, and the display element layer DPL will be described next.

[0159] The pixel circuit layer PCL may include a buffer layer BFL, pixel circuit 144, and passivation layer PSV.

[0160] The buffer layer BFL prevents impurities from diffusing into the transistors T (e.g., switching transistor Tsw and driving transistor Tdr) included in the pixel circuit 144. The buffer layer BFL can be an inorganic insulating layer comprising an inorganic material. The buffer layer BFL can include, for example, silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiON) and aluminum oxide (AlO) x At least one of the metal oxides of the substrate SUB. The buffer layer BFL can be a single layer, or it can be a multilayer comprising at least two layers. When the buffer layer BFL is multilayered, these layers can be formed of the same material or can be formed of different materials. Depending on the material and process conditions of the substrate SUB, the buffer layer BFL may be omitted.

[0161] Pixel circuit 144 may include at least one transistor T and a storage capacitor Cst. Transistor T may include a driving transistor Tdr for controlling the drive current of the light-emitting element LD and a switching transistor Tsw connected to the driving transistor Tdr. However, this disclosure is not limited thereto, and pixel circuit 144 may include circuit elements other than the driving transistor Tdr and the switching transistor Tsw for performing another function. In the following embodiments, when the driving transistor Tdr and the switching transistor Tsw are explicitly specified, the transistor is referred to as transistor T. The driving transistor Tdr may be a reference... Figure 6A The first transistor T1 is described, and the switching transistor Tsw can be a reference. Figure 6A The second transistor T2 is described.

[0162] Each of the driving transistor Tdr and the switching transistor Tsw may include a semiconductor pattern SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. The first terminal SE may be either the source electrode or the drain electrode, and the second terminal DE may be the other of the source electrode and the drain electrode. In one or more exemplary embodiments, when the first terminal SE is the source electrode, the second terminal DE may be the drain electrode.

[0163] A semiconductor pattern SCL can be disposed and / or formed on a buffer layer BFL. The semiconductor pattern SCL may include a first contact region contacting a first terminal SE and a second contact region contacting a second terminal DE. The region between the first and second contact regions may be a channel region. The channel region may overlap with the gate electrode GE of the corresponding transistor T. The semiconductor pattern SCL may be made of polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. The channel region is an undoped semiconductor pattern and may be intrinsic semiconductor. Each of the first and second contact regions may be a doped semiconductor pattern.

[0164] A gate insulating layer GI may be disposed and / or formed on a semiconductor pattern SCL. The gate insulating layer GI may be an inorganic insulating layer comprising inorganic materials. In some embodiments, the gate insulating layer GI may comprise the same material as the buffer layer BFL, or comprise at least one material selected from those exemplified as constituting the buffer layer BFL. In some embodiments, the gate insulating layer GI may be an organic insulating layer comprising organic materials. The gate insulating layer GI may be a single layer, but may also be a multilayer comprising at least two layers.

[0165] The gate electrode GE can be disposed and / or formed on the gate insulating layer GI to correspond to the channel region of the semiconductor pattern SCL. The gate electrode GE can be disposed on the gate insulating layer GI to overlap with the channel region of the semiconductor pattern SCL. The gate electrode GE can be formed as a single layer comprising one selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and any alloys thereof or mixtures thereof, or formed as a double-layer or multi-layer structure comprising molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag), wherein molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) is a low-resistance material to reduce wiring resistance.

[0166] An interlayer insulating layer (ILD) may be disposed and / or formed on the gate electrode GE. The interlayer insulating layer (ILD) may comprise the same material as the gate insulating layer GI, or may comprise at least one material selected from those exemplified as constituting the gate insulating layer GI.

[0167] The first terminal SE and the second terminal DE may be disposed and / or formed on the interlayer insulating layer ILD, and may contact the first contact region and the second contact region of the semiconductor pattern SCL respectively through contact holes that pass sequentially through the gate insulating layer GI and the interlayer insulating layer ILD. Each of the first terminal SE and the second terminal DE may include the same material as the gate electrode GE, or include at least one material selected from the materials exemplified as constituting the gate electrode GE.

[0168] Although it has been described that the first terminal SE and the second terminal DE of each of the driving transistor Tdr and the switching transistor Tsw are electrically connected to separate electrodes of the semiconductor pattern SCL via contact holes that pass sequentially through the gate insulating layer GI and the interlayer insulating layer ILD, this disclosure is not limited thereto. In some embodiments, the first terminal SE of each of the driving transistor Tdr and the switching transistor Tsw may be a first contact region adjacent to the channel region of the corresponding semiconductor pattern SCL, and the second terminal DE of each of the driving transistor Tdr and the switching transistor Tsw may be a second contact region adjacent to the channel region of the corresponding semiconductor pattern SCL. The first terminal SE of the driving transistor Tdr may be electrically connected to the light-emitting element LD of the corresponding pixel PXL via a separate connection connector (such as a bridging electrode).

[0169] In some embodiments of this disclosure, the transistor T included in the pixel circuit 144 may be implemented using a low-temperature polycrystalline silicon (LTPS) thin-film transistor, but this disclosure is not limited thereto. In some embodiments, the transistor T included in the pixel circuit 144 may be implemented using an oxide semiconductor thin-film transistor. Furthermore, as an example, the case of implementing transistor T using a thin-film transistor with a top-gate structure has been described, but this disclosure is not limited thereto. The structure of transistor T may be modified in various ways.

[0170] In one or more embodiments, the storage capacitor Cst may include a lower electrode disposed on any of the insulating layers included in the pixel circuit layer PCL and an upper electrode disposed on another insulating layer to form a capacitor by overlapping with the lower electrode.

[0171] The pixel circuit layer (PCL) may include drive voltage lines (DVLs) disposed on and / or formed on the interlayer insulating layer (ILD). The drive voltage lines (DVLs) may be references. Figure 6A The second power line PL2 is described. Furthermore, the pixel circuit layer PCL may also include a first power line PL1 connected to the first drive power supply VDD. The first power line PL1 may be disposed in the same layer as the drive voltage line DVL, or it may be disposed in a different layer than the drive voltage line DVL. In one or more embodiments of this disclosure, it has been described that the drive voltage line DVL is disposed in the same layer as the first terminal SE and the second terminal DE of the drive transistor Tdr (and the switching transistor Tsw), but this disclosure is not limited thereto. In some embodiments, the drive voltage line DVL may be disposed in the same layer as any of the conductive layers disposed in the pixel circuit layer PCL. For example, the location of the drive voltage line DVL in the pixel circuit layer PCL may be varied.

[0172] The first power line PL1 can be electrically connected to a component (e.g., the first electrode EL1 of the display element layer DPL), and the drive voltage line DVL can be electrically connected to another component (e.g., the second electrode EL2 of the display element layer DPL). The first power line PL1 and the drive voltage line DVL can transmit alignment signals (or alignment voltages) to the first electrode EL1 and the second electrode EL2 to align the light-emitting element LD in the pixel region PXA of each pixel PXL. Furthermore, each of the first power line PL1 and the drive voltage line DVL can transmit the voltage of a corresponding drive power supply to each pixel PXL after the light-emitting element LD is aligned, thereby driving the light-emitting element LD.

[0173] Each of the first power line PL1 and the drive voltage line DVL may include a conductive material. In an example, each of the first power line PL1 and the drive voltage line DVL may be formed as a single layer, comprising one selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), neodymium aluminum (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and any alloys thereof, or mixtures thereof, or formed as a double-layer or multi-layer structure comprising molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag), wherein molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) is a low-resistance material to reduce wiring resistance. In some exemplary embodiments, each of the first power line PL1 and the drive voltage line DVL may be configured such that a double layer of titanium (Ti) / copper (Cu) is sequentially stacked.

[0174] The passivation layer PSV can be disposed and / or formed on the transistor T and the drive voltage line DVL.

[0175] The passivation layer PSV can be configured to include an organic insulating layer, an inorganic insulating layer, or an organic insulating layer disposed on an inorganic insulating layer. The inorganic insulating layer may include, for example, silicon oxide (SiO₂). x ), silicon nitride (SiN) x ), silicon oxynitride (SiON) and aluminum oxide (AlO) x The organic insulating layer may include at least one of the following metal oxides: polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0176] The passivation layer PSV may include a first contact hole CH1 that exposes the first terminal SE of the drive transistor Tdr and a second contact hole CH2 that exposes the drive voltage line DVL.

[0177] The display element layer DPL can be set on the passivation layer PSV.

[0178] The display element layer (DPL) may include a dam (BNK), a first electrode (EL1) and a second electrode (EL2), a light-emitting element (LD), a first contact electrode (CNE1) and a second contact electrode (CNE2), intermediate electrodes (CTE1, CTE2, and CTE3), and first insulating layers (INS1) to third insulating layers (INS3).

[0179] The embankment BNK can be located in the peripheral region on at least one side of the emission region surrounding the corresponding pixel PXL. The peripheral region may include non-emission regions.

[0180] A dam BNK is a structure that defines (or divides) a pixel region PXA (or emission region) of a corresponding pixel PXL and each of its adjacent pixels PXL, and may be, for example, a pixel defining layer. The dam BNK may include at least one light-blocking material and / or at least one reflective material to prevent light (or beams) from leaking between each pixel PXL and its adjacent pixels PXL due to light leakage defects. In some embodiments, the dam BNK may include a transparent material (or substance). Transparent materials may include, for example, polyamide resins, polyimide resins, etc., but this disclosure is not limited thereto. In other embodiments, a reflective material layer may be formed on the dam BNK to further improve the efficiency of light emitted from each pixel PXL. The dam BNK may be disposed on and / or formed on a first insulating layer INS1, but this disclosure is not limited thereto. In some embodiments, the dam BNK may be disposed on and / or formed on a passivation layer PSV.

[0181] The first electrode EL1 can be electrically connected via the first contact hole CH1 to a component in the pixel circuit layer PCL of the corresponding pixel PXL, such as the driving transistor Tdr. The second electrode EL2 can be electrically connected via the second contact hole CH2 to a component included in the pixel circuit layer PCL of the corresponding pixel PXL, such as the driving voltage line DVL.

[0182] The first electrode EL1 and the second electrode EL2 may be disposed on the same surface (e.g., one surface (or upper surface) of the passivation layer PSV) and may be spaced apart from each other. In the following description and / or claims, as will be understood by those skilled in the art, the terms first electrode and second electrode may be used interchangeably. In other words, electrode EL1 may be referred to as the second electrode, and electrode EL2 may be referred to as the first electrode, without limitation. Similarly, any portion or part of electrode EL1 may be referred to as a portion or part of the second electrode, and any portion or part of electrode EL2 may be referred to as a portion or part of the first electrode, without limitation. Furthermore, throughout the description and / or claims, the designations first and second may be used interchangeably with respect to other components (e.g., contact electrodes).

[0183] Each of the first electrode EL1 and the second electrode EL2 may be made of a material with constant reflectivity to allow light emitted from each of the light-emitting elements LD to propagate in the image display direction (or forward direction) of the display device. Each of the first electrode EL1 and the second electrode EL2 may be made of a conductive material (or substance) with constant reflectivity. The conductive material (or substance) may include an opaque metal adapted to reflect light emitted from the light-emitting element LD in the image display direction of the display device. The opaque metal may include, for example, metals such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys thereof. In some embodiments, each of the first electrode EL1 and the second electrode EL2 may include a transparent conductive material (or substance). Transparent conductive materials (or substances) may include conductive oxides (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), or indium tin zinc oxide (ITZO)) and conductive polymers (such as poly(3,4-ethylenedioxythiophene) (PEDOT). When each of the first electrode EL1 and the second electrode EL2 comprises a transparent conductive material, a separate conductive layer made of an opaque metal may be additionally included for reflecting light emitted from the light-emitting element LD in the image display direction of the display device. However, the material of each of the first electrode EL1 and the second electrode EL2 is not limited to the materials described above.

[0184] Furthermore, each of the first electrode EL1 and the second electrode EL2 may be configured and / or formed as a single layer, but this disclosure is not limited thereto. In some embodiments, each of the first electrode EL1 and the second electrode EL2 may be configured and / or formed as a multilayer, wherein two or more materials selected from metals, alloys, conductive oxides, and conductive polymers are stacked in the multilayer. Each of the first electrode EL1 and the second electrode EL2 may be configured as a multilayer comprising at least two layers to reduce or minimize distortion caused by signal delay when a signal (or voltage) is transmitted to both ends of each of the light-emitting elements LD. In some exemplary embodiments, each of the first electrode EL1 and the second electrode EL2 may be configured as a multilayer in which indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO) is sequentially stacked.

[0185] In some embodiments of this disclosure, the second electrode EL2 may have a quadrilateral shape located in the middle (or core) of the pixel region PXA of the corresponding pixel PXL, and may have a first side S1 to a fourth side S4. In some exemplary embodiments, the second electrode EL2 may have a square shape in which the first side S1 to the fourth side S4 are of the same length, or a rectangular shape in which two opposing sides of the first side S1 to the fourth side S4 (e.g., the second side S2 and the fourth side S4) are of the same length and two non-opposing sides (e.g., the first side S1 and the second side S2) are of different lengths. Furthermore, the second electrode EL2 may have, for example, […]. Figure 8B The rhombus shape shown.

[0186] The first electrode EL1 may have a quadrilateral ring shape or a rhombus ring shape and may surround the second electrode EL2 along its periphery (e.g., periphery (or edge)). The first electrode EL1 may have a specific shape and may not completely surround the second electrode EL2; for example, the first electrode EL1 may have a quadrilateral ring shape or a rhombus ring shape having an opening portion A (e.g., region A). The second electrode EL2 may be isolated from the first electrode EL1 and may be surrounded by the first electrode EL1, but this disclosure is not limited thereto. The first electrode EL1 and the second electrode EL2 may be disposed on the passivation layer PSV in a spaced-apart manner.

[0187] The first electrode EL1 may include electrodes EL1_1 (1-1) to EL1_4 (1-4). Electrodes EL1_1 (1-1) to EL1_4 (1-4) may be integrally connected to each other and are different regions of the first electrode EL1. In some exemplary embodiments, electrode EL1_1 (1-1) may be a region of the first electrode EL1 adjacent to the first side S1 of the second electrode EL2, electrode EL1_2 (1-2) may be a region of the first electrode EL1 adjacent to the second side S2 of the second electrode EL2, electrode EL1_3 (1-3) may be a region of the first electrode EL1 adjacent to the third side S3 of the second electrode EL2, and electrode EL1_4 (1-4) may be a region of the first electrode EL1 adjacent to the fourth side S4 of the second electrode EL2.

[0188] One end of electrode EL1_1 (1-1) may contact electrode EL1_2 (1-2), and the other end of electrode EL1_1 (1-1) may not contact electrode EL1_4 (1-4). One end of electrode EL1_2 (1-2) may contact electrode EL1_1 (1-1), and the other end of electrode EL1_2 (1-2) may contact electrode EL1_3 (1-3). One end of electrode EL1_3 (1-3) may contact electrode EL1_2 (1-2), and the other end of electrode EL1_3 (1-3) may contact electrode EL1_4 (1-4). One end of electrode EL1_4 (1-4) may contact electrode EL1_3 (1-3), and the other end of electrode EL1_4 (1-4) may not contact electrode EL1_1 (1-1).

[0189] In the pixel region PXA of each pixel PXL, multiple light-emitting elements (LDs) can be aligned and / or positioned between a region including the first side S1 of the (1-1) electrode EL1_1 and the second electrode EL2, between a region including the second side S2 of the (1-2) electrode EL1_2 and the second electrode EL2, between a region including the third side S3 of the (1-3) electrode EL1_3 and the second electrode EL2, and between a region including the fourth side S4 of the (1-4) electrode EL1_4 and the second electrode EL2. The first electrode EL1, the second electrode EL2, and the light-emitting elements (LDs) can constitute the light-emitting unit (EMU) of each pixel PXL.

[0190] The first electrode EL1 and the second electrode EL2 can receive alignment signals (or alignment voltages) to serve as alignment electrodes (or alignment lines) for aligning the light-emitting element LD. In some exemplary embodiments, the first electrode EL1 can receive a first alignment signal (or a first alignment voltage) from a first power line PL1 to serve as a first alignment electrode (or a first alignment line), and the second electrode EL2 can receive a second alignment signal (or a second alignment voltage) from a drive voltage line DVL to serve as a second alignment electrode (or a second alignment line). The first alignment signal (or alignment voltage) and the second alignment signal (or alignment voltage) can be signals having a voltage difference and / or a phase difference sufficient to allow the light-emitting element LD to be aligned between the first electrode EL1 and the second electrode EL2. At least one of the first alignment signal (or alignment voltage) and the second alignment signal (or alignment voltage) can be an AC signal (or voltage), but this disclosure is not limited thereto.

[0191] As described above, when the second electrode EL2 is located in the middle of the pixel region PXA of each pixel PXL and the first electrode EL1 surrounds the peripheral region of the second electrode EL2, an alignment signal (or alignment voltage) is applied to each of the first electrode EL1 and the second electrode EL2. An electric field can then be formed between the first electrode EL1 and the second electrode EL2 in the same direction along the periphery (e.g., the periphery) of the second electrode EL2. The light-emitting element LD provided to the pixel region PXA can be arranged in the same direction between the first electrode EL1 and the second electrode EL2. For example, one end of the light-emitting element LD can face the first electrode EL1, and the other end of the light-emitting element LD can face the second electrode EL2.

[0192] Each of the light-emitting elements (LDs) can be a light-emitting diode with a micrometer-sized structure, made using a material with an inorganic crystal structure, for example, with a size as small as the micrometer to nanometer scale. For example, each of the light-emitting elements (LDs) can be a micro-light-emitting element manufactured by an etching process or a micro-light-emitting element manufactured by a growth process.

[0193] At least two or dozens of light-emitting elements (LDs) can be aligned and / or arranged in the pixel region PXA of each pixel PXL, but the number of LDs is not limited to this. In some embodiments, the number of LDs aligned and / or arranged in the pixel region PXA can be varied.

[0194] Each of the light-emitting elements (LDs) can emit either colored light or white light. Each of the LDs can be aligned on a first insulating layer INS1 between a first electrode EL1 and a second electrode EL2, such that the extension direction (or length L direction) of the LD is parallel to either a first direction DR1 or a second direction DR2. The LDs can be provided in the form of being dispersed in a solution for injection into the pixel region PXA of each pixel PXL.

[0195] The light-emitting element (LD) can be mixed with a volatile solvent to be supplied to the pixel region PXA via inkjet printing or slot coating. When an alignment signal corresponding to each of the first electrode EL1 and the second electrode EL2 disposed in the pixel region PXA is applied, an electric field can be formed between the first electrode EL1 and the second electrode EL2. Therefore, the light-emitting element (LD) can self-align between the first electrode EL1 and the second electrode EL2.

[0196] After the light-emitting element (LD) is aligned, the solvent is evaporated or removed through another process, so that the LD can be finally aligned and / or set in the pixel area PXA of each pixel PXL.

[0197] In one or more embodiments of this disclosure, the light-emitting element LD may include a plurality of first light-emitting elements LD1, a plurality of second light-emitting elements LD2, a plurality of third light-emitting elements LD3, and a plurality of fourth light-emitting elements LD4.

[0198] The first light-emitting element LD1 can be disposed between the first side S1 of the (1-1) electrode EL1_1 and the second electrode EL2. The second light-emitting element LD2 can be disposed between the second side S2 of the (1-2) electrode EL1_2 and the second electrode EL2. The third light-emitting element LD3 can be disposed between the third side S3 of the (1-3) electrode EL1_3 and the second electrode EL2. The fourth light-emitting element LD4 can be disposed between the fourth side S4 of the (1-4) electrode EL1_4 and the second electrode EL2.

[0199] The first light-emitting element LD1 can be aligned in the same direction between a region including the first side S1 of the (1-1) electrode EL1_1 and the second electrode EL2. In some exemplary embodiments, one end of each of the first light-emitting elements LD1 can be connected to the (1-1) electrode EL1_1, and the other end of the first light-emitting element LD1 can be connected to a region including the first side S1 of the second electrode EL2. In some embodiments of this disclosure, a region including the first side S1 of the (1-1) electrode EL1_1 and the second electrode EL2, together with the first light-emitting elements LD1 connected in parallel between them in the same direction, can constitute a first series stage SET1.

[0200] The second light-emitting element LD2 can be aligned in the same direction between a region including the second side S2 of the first (1-2) electrode EL1_2 and the second electrode EL2. In some exemplary embodiments, one end of each of the second light-emitting elements LD2 can be connected to the first (1-2) electrode EL1_2, and the other end of the second light-emitting element LD2 can be connected to a region including the second side S2 of the second electrode EL2. The region including the second side S2 of the first (1-2) electrode EL1_2 and the second electrode EL2, together with the second light-emitting elements LD2 connected in parallel between them in the same direction, can constitute a second series stage SET2.

[0201] The third light-emitting element LD3 can be aligned in the same direction between a region including the third side S3 of the first (1-3) electrode EL1_3 and the second electrode EL2. In some exemplary embodiments, one end of each of the third light-emitting elements LD3 can be connected to the first (1-3) electrode EL1_3, and the other end of the third light-emitting element LD3 can be connected to a region including the third side S3 of the second electrode EL2. The regions including the third side S3 of the first (1-3) electrode EL1_3 and the second electrode EL2, together with the third light-emitting elements LD3 connected in parallel between them in the same direction, can constitute a third series stage SET3.

[0202] The fourth light-emitting element LD4 can be aligned in the same direction between a region including the fourth side S4 of the first (1-4) electrode EL1_4 and the second electrode EL2. In some exemplary embodiments, one end of each of the fourth light-emitting elements LD4 can be connected to the first (1-4) electrode EL1_4, and the other end of the fourth light-emitting element LD4 can be connected to a region including the fourth side S4 of the second electrode EL2. The regions including the fourth side S4 of the first (1-4) electrode EL1_4 and the second electrode EL2, together with the fourth light-emitting elements LD4 connected in parallel between them in the same direction, can constitute a fourth series stage SET4.

[0203] The first light-emitting element LD1 to the fourth light-emitting element LD4 can be disposed and / or formed on the first insulating layer INS1.

[0204] The first insulating layer INS1 may comprise an inorganic insulating layer made of inorganic materials or an organic insulating layer made of organic materials. In some embodiments of this disclosure, the first insulating layer INS1 may be configured as an inorganic insulating layer adapted to protect the light-emitting element LD from the pixel circuit layer PCL of each pixel PXL. In some exemplary embodiments, the first insulating layer INS1 may comprise silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiON) and aluminum oxide (AlO) x The first insulating layer INS1 may be an organic insulating layer suitable for planarizing the support surface of the light-emitting element LD, but this disclosure is not limited thereto. In some embodiments, the first insulating layer INS1 may be configured as an organic insulating layer suitable for planarizing the support surface of the light-emitting element LD.

[0205] The first insulating layer INS1 may include a first opening OPN1 exposing a region of the first electrode EL1 and a second opening OPN2 exposing a region of the second electrode EL2. The first insulating layer INS1 may cover regions other than the region of the first electrode EL1 and the region of the second electrode EL2.

[0206] A second insulating layer INS2 may be disposed and / or formed on each of the light-emitting elements LD. The second insulating layer INS2 may be disposed and / or formed on the light-emitting elements LD to partially cover the outer peripheral surface (e.g., the outer circumferential surface) of each of the light-emitting elements LD and expose both ends of each of the light-emitting elements LD to the outside.

[0207] The second insulating layer INS2 can be configured as a single layer or multiple layers, and includes an inorganic insulating layer containing at least one inorganic material or an organic insulating layer containing at least one organic material. The second insulating layer INS2 allows each of the light-emitting elements LD to be further fixed. The second insulating layer INS2 may include an inorganic insulating layer adapted to protect the active layer 12 of each of the light-emitting elements LD from external oxygen, moisture, etc. However, this disclosure is not limited thereto. Depending on the design conditions of the display device using the light-emitting elements LD, the second insulating layer INS2 may include an organic insulating layer containing organic materials.

[0208] In some embodiments of this disclosure, after the light-emitting element LD is fully aligned in the pixel region PXA of each pixel PXL, a second insulating layer INS2 is formed on the light-emitting element LD to prevent the light-emitting element LD from separating from its aligned position. When a gap (or space) exists between the first insulating layer INS1 and the light-emitting element LD before the formation of the second insulating layer INS2, this gap can be filled with the second insulating layer INS2 during the process of forming the second insulating layer INS2. Therefore, the light-emitting element LD can be configured with an organic insulating layer suitable for filling the gap between the first insulating layer INS1 and the light-emitting element LD.

[0209] The first contact electrode CNE1, the second contact electrode CNE2, and the intermediate electrode CTE may be disposed on and / or formed on the first electrode EL1 and the second electrode EL2.

[0210] The first contact electrode CNE1 and the second contact electrode CNE2 can be components that more stably connect each of the first electrode EL1 and the second electrode EL2 to the light-emitting element LD.

[0211] The first contact electrode CNE1 may be disposed on and / or formed on the (1-1) electrode EL1_1. The first contact electrode CNE1 can be connected to the (1-1) electrode EL1_1 by direct contact via the first opening OPN1. Furthermore, the first contact electrode CNE1 may be disposed on and / or formed on one end of each of the first light-emitting elements LD1 to connect to one end of each of the first light-emitting elements LD1. The signal applied to the driving transistor Tdr of the (1-1) electrode EL1_1 can be transmitted to one end of each of the first light-emitting elements LD1 through the first contact electrode CNE1.

[0212] The second contact electrode CNE2 may be disposed and / or formed on a region of the second electrode EL2 including the fourth side S4. The second contact electrode CNE2 can be connected to the second electrode EL2 by direct contact with the second electrode EL2 via the second opening OPN2. Furthermore, the second contact electrode CNE2 may be disposed and / or formed on the other end of each of the fourth light-emitting elements LD4 to be connected to the other end of each of the fourth light-emitting elements LD4.

[0213] The first contact electrode CNE1 and the second contact electrode CNE2 can be made of various transparent conductive materials (or substances) to allow light emitted from each of the light-emitting elements LD and then reflected by the first electrode EL1 and the second electrode EL2 to travel in the image display direction of the display device without light loss. In some exemplary embodiments, the first contact electrode CNE1 and the second contact electrode CNE2 may include at least one of various transparent conductive materials, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO), and the first contact electrode CNE1 and the second contact electrode CNE2 may be substantially transparent or translucent to meet the transmittance (e.g., set or predetermined transmittance or transmittance ratio). However, the materials of the first contact electrode CNE1 and the second contact electrode CNE2 are not limited to the embodiments described above. In some embodiments, the first contact electrode CNE1 and the second contact electrode CNE2 may be made of various opaque conductive materials. Opaque conductive materials may include, for example, titanium (Ti), aluminum (Al), silver (Ag), etc., but this disclosure is not limited thereto. Furthermore, the first contact electrode CNE1 and the second contact electrode CNE2 can be formed as a single layer or multiple layers.

[0214] When viewed in a plane, each of the first contact electrode CNE1 and the second contact electrode CNE2 may have a rod-like shape extending in one direction, but this disclosure is not limited thereto. In some embodiments, the shape of each of the first contact electrode CNE1 and the second contact electrode CNE2 may vary differently within the range where each of the first contact electrode CNE1 and the second contact electrode CNE2 is stably electrically connected to each of the light-emitting elements LD. Furthermore, the shape of each of the first contact electrode CNE1 and the second contact electrode CNE2 can be varied differently by taking into account the connection relationship with the electrode disposed on its bottom.

[0215] When viewed in a plane, the intermediate electrode CTE may overlap with each of a region of the first electrode EL1 and a region of the second electrode EL2. The intermediate electrode CTE may be an electrode to which signals (e.g., setting or pre-setting signals or voltages) are not transmitted from the outside. In some exemplary embodiments of this disclosure, the intermediate electrode CTE may include a first intermediate electrode CTE1, a second intermediate electrode CTE2, and a third intermediate electrode CTE3.

[0216] The first intermediate electrode CTE1 can be disposed on a region of the second electrode EL2 including the first side S1 and each of the (1-2) electrodes EL1_2, so as to overlap with the region of the second electrode EL2 and the (1-2) electrodes EL1_2. Furthermore, the first intermediate electrode CTE1 can be disposed on the first corner portion CON1 of the second electrode EL2 to overlap with the first corner portion CON1, at which the first side S1 and the second side S2 are in contact with (or intersect) each other.

[0217] The first intermediate electrode CTE1 can be divided into a first region A1 and a second region A2. The first region A1 can be a region of the first intermediate electrode CTE1 that corresponds to or overlaps with the (1-2) electrode EL1_2, and the second region A2 can be a region of the first intermediate electrode CTE1 that corresponds to (or overlaps with) a region of the second electrode EL2 that includes the first side S1. The first region A1 and the second region A2 can be integrally configured to be connected to each other.

[0218] The first intermediate electrode CTE1 can be disposed on a first insulating layer INS1 above the first electrode EL1 and the second electrode EL2 to be electrically insulated from the first electrode EL1 and the second electrode EL2. That is, the first region A1 of the first intermediate electrode CTE1 can be electrically insulated from the (1-2) electrode EL1_2 through the first insulating layer INS1 disposed on its bottom, and the second region A2 of the first intermediate electrode CTE1 can be electrically insulated from a region of the second electrode EL2 including the first side S1.

[0219] In some embodiments of this disclosure, the second region A2 of the first intermediate electrode CTE1 may be disposed on the other end of each of the first light-emitting elements LD1 for electrical and / or physical connection to the first light-emitting element LD1. The first region A1 of the first intermediate electrode CTE1 may be disposed on one end of each of the second light-emitting elements LD2 for electrical and / or physical connection to the second light-emitting element LD2. The first intermediate electrode CTE1 may serve as a first bridging electrode (or a first connecting electrode) connecting the first light-emitting element LD1 and the second light-emitting element LD2. In an example, the first intermediate electrode CTE1 may be a first bridging electrode (or a first connecting electrode) connecting the first series stage SET1 and the second series stage SET2.

[0220] The first intermediate electrode CTE1 can be configured to extend over a region of the first electrode EL1 (e.g., the (1-2) electrode EL1_2) and a region of the second electrode EL2 (e.g., a region of the second electrode EL2 including the first side S1), to have a rod-like shape with at least one bend. The shape of the first intermediate electrode CTE1 is not limited to the above-described embodiments. In some embodiments, the first intermediate electrode CTE1 can be varied in shape within the range where the first intermediate electrode CTE1 is stably connected to the continuous first series stage SET1 and the second series stage SET2.

[0221] The second intermediate electrode CTE2 can be disposed on each of the regions including the second side S2 of the first (1-3) electrode EL1_3 and the second electrode EL2, so as to overlap with the region of the second electrode EL2 and the first (1-3) electrode EL1_3. Furthermore, the second intermediate electrode CTE2 can be disposed on the second corner portion CON2 of the second electrode EL2, so as to overlap with the second corner portion CON2, at which the second side S2 and the third side S3 are in contact with (or intersect) each other.

[0222] The second intermediate electrode CTE2 may include a first region A1 corresponding to (or overlapping with) the first electrode EL1_3 and a second region A2 corresponding to (or overlapping with) a region of the second electrode EL2 including the second side S2. The first region A1 and the second region A2 may be different regions of the second intermediate electrode CTE2. The first region A1 and the second region A2 may be integrally configured to be connected to each other.

[0223] The second intermediate electrode CTE2 can be disposed on the first insulating layer INS1 to electrically insulate it from the first electrode EL1 and the second electrode EL2. In some exemplary embodiments, the first region A1 of the second intermediate electrode CTE2 can be electrically insulated from the (1-3) electrode EL1_3 through the first insulating layer INS1 disposed on its bottom, and the second region A2 of the second intermediate electrode CTE2 can be electrically insulated from a region of the second electrode EL2 including the second side S2 through the first insulating layer INS1.

[0224] In some exemplary embodiments of this disclosure, the second region A2 of the second intermediate electrode CTE2 may be disposed on the other end of each of the second light-emitting elements LD2 for electrical and / or physical connection to the second light-emitting element LD2. The first region A1 of the second intermediate electrode CTE2 may be disposed on one end of each of the third light-emitting elements LD3 for electrical and / or physical connection to the third light-emitting element LD3. The second intermediate electrode CTE2 may be used as a second bridging electrode (or a second connecting electrode) connecting the second light-emitting element LD2 and the third light-emitting element LD3. In the example, the second intermediate electrode CTE2 may be a second bridging electrode (or a second connecting electrode) connecting the second series stage SET2 and the third series stage SET3.

[0225] The second intermediate electrode CTE2 can be configured to extend over a region of the first electrode EL1 (e.g., the (1-3)th electrode EL1_3) and a region of the second electrode EL2 (e.g., a region of the second electrode EL2 including the second side S2), to have a rod-like shape with at least one bend. The shape of the second intermediate electrode CTE2 is not limited to the above-described embodiments. In some embodiments, the second intermediate electrode CTE2 can be varied in shape within the range where the second intermediate electrode CTE2 stably connects to the continuous second series stage SET2 and the third series stage SET3.

[0226] The third intermediate electrode CTE3 can be disposed on each of the regions including the third side S3 of the first (1-4) electrode EL1_4 and the second electrode EL2, so as to overlap with the region of the second electrode EL2 and the first (1-4) electrode EL1_4. Furthermore, the third intermediate electrode CTE3 can be disposed on the third corner CON3 of the second electrode EL2, at which the third side S3 and the fourth side S4 are in contact with each other (or intersect). Additionally, the second electrode EL2 may also include a fourth corner CON4, at which the fourth side S4 and the first side S1 are in contact with each other (or intersect).

[0227] The third intermediate electrode CTE3 may include a first region A1 corresponding to the (1-4) electrode EL1_4 and a second region A2 corresponding to a region of the second electrode EL2 including the third side S3. The first region A1 and the second region A2 may be different regions of the third intermediate electrode CTE3. The first region A1 and the second region A2 may be integrally configured to be connected to each other.

[0228] The third intermediate electrode CTE3 can be disposed on the first insulating layer INS1 to electrically insulate it from the first electrode EL1 and the second electrode EL2. In some exemplary embodiments, the first region A1 of the third intermediate electrode CTE3 can be electrically insulated from the (1-4) electrode EL1_4 through the first insulating layer INS1 disposed on its bottom, and the second region A2 of the third intermediate electrode CTE3 can be electrically insulated from a region of the second electrode EL2 including the third side S3 through the first insulating layer INS1.

[0229] In some embodiments of this disclosure, the second region A2 of the third intermediate electrode CTE3 may be disposed on the other end of each of the third light-emitting elements LD3 for electrical and / or physical connection to the third light-emitting element LD3. The first region A1 of the third intermediate electrode CTE3 may be disposed on one end of each of the fourth light-emitting elements LD4 for electrical and / or physical connection to the fourth light-emitting element LD4. The third intermediate electrode CTE3 may be used as a third bridging electrode (or third connecting electrode) connecting the third light-emitting element LD3 and the fourth light-emitting element LD4. For example, the third intermediate electrode CTE3 may be a third bridging electrode (or third connecting electrode) connecting the third series stage SET3 and the fourth series stage SET4.

[0230] The third intermediate electrode CTE3 can be configured to extend over a region of the first electrode EL1 (e.g., the (1-4) electrode EL1_4) and a region of the second electrode EL2 (e.g., a region of the second electrode EL2 including the third side S3), to have a rod-like shape with at least one bend. The shape of the third intermediate electrode CTE3 is not limited to the above-described embodiments. In some embodiments, the third intermediate electrode CTE3 can be varied in shape within the range where the third intermediate electrode CTE3 is stably connected to the continuous third series stage SET3 and fourth series stage SET4.

[0231] In each pixel region PXA of pixel PXL, the first contact electrode CNE1, the second contact electrode CNE2, and the first intermediate electrode CTE1 to the third intermediate electrode CTE3 can be arranged to be spaced apart from each other in the plane and cross section.

[0232] The first contact electrode CNE1 may face the second region A2 of the first intermediate electrode CTE1 and extend in the same direction as the second region A2 of the first intermediate electrode CTE1 (e.g., the first direction DR1). The first contact electrode CNE1 and the second region A2 of the first intermediate electrode CTE1 may be spaced apart from each other in the second direction DR2.

[0233] The first region A1 of the first intermediate electrode CTE1 may face the second region A2 of the second intermediate electrode CTE2 and extend in the same direction as the second region A2 of the second intermediate electrode CTE2 (e.g., the second direction DR2). The first region A1 of the first intermediate electrode CTE1 and the second region A2 of the second intermediate electrode CTE2 may be spaced apart from each other in the first direction DR1.

[0234] The first region A1 of the second intermediate electrode CTE2 may face the second region A2 of the third intermediate electrode CTE3 and extend in the same direction as the second region A2 of the third intermediate electrode CTE3 (e.g., the first direction DR1). The first region A1 of the second intermediate electrode CTE2 and the second region A2 of the third intermediate electrode CTE3 may be spaced apart from each other in the second direction DR2.

[0235] The first region A1 of the third intermediate electrode CTE3 may face the second contact electrode CNE2 and extend in the same direction as the second contact electrode CNE2 (e.g., the second direction DR2). The first region A1 of the third intermediate electrode CTE3 and the second contact electrode CNE2 may be spaced apart from each other in the first direction DR1.

[0236] The first intermediate electrodes CTE1 to the third intermediate electrodes CTE3 can be made of various transparent conductive materials (or substances) to allow light emitted from each of the light-emitting elements LD and then reflected by the first electrode EL1 and the second electrode EL2 to travel in the image display direction of the display device without light loss. The first intermediate electrodes CTE1 to the third intermediate electrodes CTE3 may include the same material as the first contact electrode CNE1 and the second contact electrode CNE2, and are formed by the same process as the first contact electrode CNE1 and the second contact electrode CNE2.

[0237] The first intermediate electrode CTE1 to the third intermediate electrode CTE3 can be disposed in the same layer as the first contact electrode CNE1 and the second contact electrode CNE2 formed by the same process. In the example, the first intermediate electrode CTE1 to the third intermediate electrode CTE3 and the first contact electrode CNE1 and the second contact electrode CNE2 can be disposed and / or formed on the second insulating layer INS2. However, this disclosure is not limited thereto. In some embodiments, the first intermediate electrode CTE1 to the third intermediate electrode CTE3 can be disposed in a layer different from the layer of the first contact electrode CNE1 and the second contact electrode CNE2, and can be formed by a process different from the process of the first contact electrode CNE1 and the second contact electrode CNE2. When the first contact electrode CNE1 and the second contact electrode CNE2 and the first intermediate electrode CTE1 to the third intermediate electrode CTE3 are disposed in different layers and formed by different processes, such as Figure 13 and Figure 14 As shown, an auxiliary insulating layer AUINS may be disposed and / or formed between the first contact electrode CNE1 and the first intermediate electrode CTE1, and between the third intermediate electrode CTE3 and the second contact electrode CNE2. The auxiliary insulating layer AUINS may be disposed on each of the first contact electrode CNE1 and the second contact electrode CNE2 to cover both the first contact electrode CNE1 and the second contact electrode CNE2. The auxiliary insulating layer AUINS may comprise the same material as the first insulating layer INS1 and the second insulating layer INS2, or may comprise at least one material selected from the materials exemplified as constituting the first insulating layer INS1 and the second insulating layer INS2. In some exemplary embodiments, the auxiliary insulating layer AUINS may be an inorganic insulating layer comprising inorganic materials or an organic insulating layer comprising organic materials. As described above, when the auxiliary insulating layer AUINS is disposed on the first contact electrode CNE1 and the second contact electrode CNE2, the first intermediate electrodes CTE1 to the third intermediate electrodes CTE3 may be disposed on the auxiliary insulating layer AUINS.

[0238] The third insulating layer INS3 may be disposed and / or formed on the first contact electrode CNE1, the second contact electrode CNE2, and the first intermediate electrode CTE1 to the third intermediate electrode CTE3. The third insulating layer INS3 may be an inorganic insulating layer comprising inorganic materials or an organic insulating layer comprising organic materials. In some exemplary embodiments, the third insulating layer INS3 may have a structure in which at least one inorganic insulating layer and at least one organic insulating layer are alternately stacked. The third insulating layer INS3 may be an encapsulation layer that completely covers the display element layer DPL to prevent moisture, humidity, etc., from being introduced into the display element layer DPL, including the light-emitting element LD.

[0239] In some implementations, such as Figure 12 As shown, the upper substrate U_SUB can be disposed on the third insulating layer INS3.

[0240] The upper substrate U_SUB can be disposed on the display element layer DPL to cover the display area DA in which pixels PXL are arranged. The upper substrate U_SUB can constitute the encapsulation substrate (or thin film encapsulation layer) and / or window member of the display device. The intermediate layer CTL can be disposed between the upper substrate U_SUB and the display element layer DPL. The intermediate layer CTL can be a transparent adhesive layer (or bonding layer), for example, an optically transparent adhesive for enhancing the adhesion between the display element layer DPL and the upper substrate U_SUB, but this disclosure is not limited thereto.

[0241] The upper substrate U_SUB may include a base layer BSL and an optical conversion patterning layer LCP.

[0242] The base layer (BSL) can be a rigid substrate or a flexible substrate, and the material or properties of the base layer (BSL) are not particularly limited. The base layer (BSL) can be made of the same material as the substrate (SUB), or it can be made of a different material than the substrate (SUB).

[0243] The light conversion pattern layer LCP can be disposed on one surface of the base layer BSL to face the pixel PXL of the substrate SUB. The light conversion pattern layer LCP may include a color conversion layer CCL and a color filter CF corresponding to an appropriate color (e.g., a predetermined color).

[0244] A color conversion layer (CCL) may include color conversion particles (QDs) corresponding to a specific color. A color filter (CF) may allow light of a specific color to selectively pass through it. A color conversion layer (CCL) may be disposed on one surface of a base layer (BSL) facing a pixel (PXL) (or a sub-pixel) and may include color conversion particles (QDs) for converting light of a specific color emitted from a light-emitting element (LD) disposed in a pixel (PXL) into light of that specific color. In some exemplary embodiments, when a pixel (PXL) is a red pixel, the color conversion layer (CCL) may include color conversion particles (QDs) of red quantum dots for converting light emitted from the light-emitting element (LD) into red light. In another example embodiment, when a pixel (PXL) is a green pixel, the color conversion layer (CCL) may include color conversion particles (QDs) of green quantum dots for converting light emitted from the light-emitting element (LD) into green light. In yet another example embodiment, when a pixel (PXL) is a blue pixel, the color conversion layer (CCL) may include color conversion particles (QDs) of blue quantum dots for converting light emitted from the light-emitting element (LD) into blue light.

[0245] A color filter CF can be disposed between the color conversion layer CCL and the base layer BSL, and can include a color filter material for selectively transmitting light of a specific color converted by the color conversion layer CCL through it. The color filter CF can include a red color filter, a green color filter, and a blue color filter.

[0246] A first light-blocking pattern LBP1 may be disposed between a color filter CF corresponding to a pixel PXL and a color filter (not shown) corresponding to a pixel adjacent to a pixel PXL. The first light-blocking pattern LBP1 may be disposed on a base layer BSL to overlap with a dam BNK disposed in the pixel region PXA of the corresponding pixel PXL. In some embodiments, a second light-blocking pattern LBP2 may be disposed on the first light-blocking pattern LBP1. The first light-blocking pattern LBP1 and the second light-blocking pattern LBP2 may comprise the same material. In some exemplary embodiments, the first light-blocking pattern LBP1 and the second light-blocking pattern LBP2 may correspond to a black matrix.

[0247] like Figures 11 to 12 As shown, when assuming that the driving current flows from the first power line PL1 to the driving voltage line DVL through the driving transistor Tdr of the pixel circuit layer PCL included in each pixel PXL, the driving current can be introduced into the light-emitting unit EMU of each pixel PXL through the first contact hole CH1.

[0248] In some exemplary embodiments, a driving current is supplied to a region of the first electrode EL1, such as the (1-1) electrode EL1_1, through the first contact hole CH1, and flows through the first contact electrode CNE1, which is in direct contact with (or directly connected to) the (1-1) electrode EL1_1, via the first light-emitting element LD1 in a second region A2 of the first intermediate electrode CTE1. Therefore, the first light-emitting element LD1 in the first series stage SET1 can emit light with a brightness corresponding to the current distributed and applied to each of them.

[0249] The driving current flowing in the second region A2 of the first intermediate electrode CTE1 flows through the first region A1 of the first intermediate electrode CTE1 and the second light-emitting element LD2 in the second region A2 of the second intermediate electrode CTE2. Therefore, the second light-emitting element LD2 in the second series stage SET2 can emit light with a brightness corresponding to the current distributed and applied to each of them.

[0250] The driving current flowing in the second region A2 of the second intermediate electrode CTE2 flows through the first region A1 of the second intermediate electrode CTE2 and the third light-emitting element LD3 in the second region A2 of the third intermediate electrode CTE3. Therefore, the third light-emitting element LD3 in the third series stage SET3 can emit light with a brightness corresponding to the current distributed and applied to each of them.

[0251] The driving current flowing in the second region A2 of the third intermediate electrode CTE3 flows through the first region A1 of the third intermediate electrode CTE3 and the fourth light-emitting element LD4 in the second contact electrode CNE2. Therefore, the fourth light-emitting element LD4 in the fourth series stage SET4 can emit light with a brightness corresponding to the current distributed and applied to each of them.

[0252] In the manner described above, the driving current of each pixel PXL can flow simultaneously through the first light-emitting element LD1 of the first series stage SET1, the second light-emitting element LD2 of the second series stage SET2, the third light-emitting element LD3 of the third series stage SET3, and the fourth light-emitting element LD4 of the fourth series stage SET4. Therefore, each pixel PXL can emit light with a brightness corresponding to the data signal provided during each frame period.

[0253] The second region A2 of the first contact electrode CNE1 and the first intermediate electrode CTE1, together with the first light-emitting element LD1, the (1-1) electrode EL1_1 and the second electrode EL2, including a region of the first side S1, can form the first series stage SET1.

[0254] The first region A1 of the first intermediate electrode CTE1 and the second region A2 of the second intermediate electrode CTE2, together with the second light-emitting element LD2, the (1-2) electrode EL1_2 and the region of the second electrode EL2 including the second side S2, can form the second series stage SET2.

[0255] The first region A1 of the second intermediate electrode CTE2 and the second region A2 of the third intermediate electrode CTE3, together with the third light-emitting element LD3, the (1-3) electrode EL1_3 and a region of the second electrode EL2 including the third side S3, can form the third series stage SET3.

[0256] The first region A1 of the third intermediate electrode CTE3 and the second contact electrode CNE2, together with the fourth light-emitting element LD4, the (1-4) electrode EL1_4 and a region including the fourth side S4 of the second electrode EL2, can form the fourth series stage SET4.

[0257] In some embodiments of this disclosure, during the process of forming the first contact electrode CNE1 of the first series stage SET1 and the second contact electrode CNE2 of the fourth series stage SET4, the first intermediate electrode CTE1 connecting the first series stage SET1 and the second series stage SET2, the second intermediate electrode CTE2 connecting the second series stage SET2 and the third series stage SET3, and the third intermediate electrode CTE3 connecting the third series stage SET3 and the fourth series stage SET4 can be formed in parallel (e.g., simultaneously). Therefore, the manufacturing process for each pixel PXL and the display device including the pixel PXL is simplified, and thus the yield rate of the product can be improved.

[0258] According to the above embodiment, when the second electrode EL2, including the first side S1 to the fourth side S4, is disposed in the middle of the pixel region PXA of each pixel PXL, and the first electrode EL1 is disposed around (or surrounds) the second electrode EL2 along its periphery (e.g., the periphery), the light-emitting element LD can be arranged radially between the first electrode EL1 and the second electrode EL2 along the first side S1 to the fourth side S4 of the second electrode EL2. For example, the light-emitting element LD can be arranged in the same direction between the first electrode EL1 and the second electrode EL2, such that one end or the other end of the light-emitting element LD faces the second electrode EL2. When the second electrode EL2 is disposed in the middle of the pixel region PXA, the light-emitting element LD can be aligned to concentrate in the middle of the pixel region PXA. Light emitted from the light-emitting element LD and then reflected by the first electrode EL1 and the second electrode EL2 can be concentrated on the color conversion layer CCL located on top of the corresponding pixel PXL (or propagating toward the color conversion layer CCL) without light loss. Therefore, a larger amount of light propagates toward the color conversion layer CCL, and thus the amount (or intensity) of the final light emitted from the color conversion layer CCL increases. Therefore, the light output efficiency of each pixel PXL can be improved.

[0259] Furthermore, when the light-emitting element LD is radially aligned along the periphery (e.g., the periphery) of the second electrode EL2, the alignment area of ​​the light-emitting element LD can be further ensured, and the light-emitting element LD in the pixel region PXA can be aligned to concentrate in the desired area (or the area to be desired). Therefore, abnormal alignment failures that cause the light-emitting element LD to be aligned in an unwanted area can be prevented.

[0260] Furthermore, according to the above embodiment, the second electrode EL2, having a quadrilateral shape, is disposed in the middle (or center) of the pixel region PXA of each pixel PXL, and the first electrode EL1 is disposed around the second electrode EL2 along its periphery (e.g., the periphery). The first intermediate electrodes CTE1 to the third intermediate electrodes CTE3 are configured such that four consecutive series stages SET1 to SET4 are electrically connected in the pixel region PXA. The light-emitting elements LD included in each of the four consecutive series stages SET1 to SET4 can be electrically connected to each other via corresponding intermediate electrodes CTE (e.g., CTE1, CTE2, CTE3). In some exemplary embodiments, the first light-emitting element LD1 included in the first series stage SET1, the second light-emitting element LD2 included in the second series stage SET2, the third light-emitting element LD3 included in the third series stage SET3, and the fourth light-emitting element LD4 included in the fourth series stage SET4 can be electrically connected to each other via corresponding intermediate electrodes CTE (e.g., CTE1, CTE2, CTE3). In this way, the light-emitting elements (LDs) aligned in the pixel region PXA of each pixel PXL are connected in a series / parallel hybrid structure to form the light-emitting unit (EMU) of each pixel PXL. Therefore, the light-emitting unit (EMU) can be configured to include a series / parallel hybrid structure with four series stages, while reducing or minimizing the area occupied by the first electrode EL1 and the second electrode EL2 (alignment electrodes) (or without increasing the number of alignment electrodes), and thus a display device with high resolution and fine pitch can be easily realized.

[0261] According to the above embodiment, an EMU with a series / parallel hybrid structure is configured to stably drive each pixel PXL. Therefore, the driving current flowing in the display panel of the display device is reduced, thereby improving power efficiency.

[0262] Figure 15A This is a schematic plan view of pixels according to another embodiment of the present disclosure. Figure 15B It is shown Figure 15A A schematic plan view of another embodiment of the first embankment pattern shown. Figure 16 It is along Figure 15A The cross-sectional view shown is taken along line IV-IV'. Figure 17 It is along Figure 15A The cross-sectional view shown is taken by line V-V'. Figure 18 It shows Figure 17 Another embodiment of the first dike pattern shown, and corresponding to Figure 15A The cross-sectional view of line V-V' shown.

[0263] about Figures 15A to 18The embodiments shown will primarily describe the parts that differ from the embodiments described above to avoid redundancy. Parts not specifically described in this disclosure follow the parts described in the embodiments above. Components similar to and / or identical to those in the embodiments described above are indicated by the same reference numerals.

[0264] Reference Figures 1 to 6A as well as Figures 15A to 18 The substrate SUB, pixel circuit layer PCL, and display element layer DPL can be set in the pixel area PXA of each pixel PXL.

[0265] In some embodiments of this disclosure, the display element layer DPL may include a first dam pattern BNK1 and a second dam pattern BNK2, a first electrode EL1 and a second electrode EL2, a dam BNK, a light-emitting element LD, a first contact electrode CNE1 and a second contact electrode CNE2, a first intermediate electrode CTE1 to a third intermediate electrode CTE3, and a first insulating layer INS1 to a third insulating layer INS3.

[0266] The first dam pattern BNK1 and the second dam pattern BNK2 can be located in the emission region of the pixel area PXA of each pixel PXL, from which light is emitted. The first dam pattern BNK1 and the second dam pattern BNK2 can correspond to the support member used to support each of the first electrode EL1 and the second electrode EL2, so as to change the surface profile (or shape) of each of the first electrode EL1 and the second electrode EL2, thereby guiding the light emitted from the light-emitting element LD in the image display direction of the display device.

[0267] The first dam pattern BNK1 can be disposed between the passivation layer PSV and the first electrode EL1 in the emission region of the corresponding pixel PXL. The first dam pattern BNK1 can include a (1-1) dam pattern BNK1_1, a (1-2) dam pattern BNK1_2, a (1-3) dam pattern BNK1_3, and a (1-4) dam pattern BNK1_4. The (1-1) dam pattern BNK1_1 can be disposed between a region of the first electrode EL1 (e.g., the (1-1) electrode EL1_1) and the passivation layer PSV. The (1-2) dam pattern BNK1_2 can be disposed between a region of the first electrode EL1 (e.g., the (1-2) electrode EL1_2) and the passivation layer PSV. The (1-3) dam pattern BNK1_3 can be disposed between a region of the first electrode EL1 (e.g., the (1-3) electrode EL1_3) and the passivation layer PSV. The (1-4) embankment pattern BNK1_4 can be disposed between a region of the first electrode EL1 (e.g., the (1-4) electrode EL1_4) and the passivation layer PSV.

[0268] When viewed on a plane, each of the (1-1)th dam pattern BNK1_1 to the (1-4)th dam pattern BNK1_4 can be configured such that each of the (1-1)th dam pattern BNK1_1 to the (1-4)th dam pattern BNK1_4 is separated from the adjacent first dam pattern BNK1 in the (1-1)th dam pattern BNK1_1 to the (1-4)th dam pattern BNK1_4. In some exemplary embodiments, the (1-1)th dike pattern BNK1_1 may be separated from each of the (1-2)th dike patterns BNK1_2 to (1-4)th dike patterns BNK1_4, the (1-2)th dike pattern BNK1_2 may be separated from each of the (1-1)th dike pattern BNK1_1, the (1-3)th dike patterns BNK1_3 and (1-4)th dike patterns BNK1_4, the (1-3)th dike pattern BNK1_3 may be separated from each of the (1-1)th dike pattern BNK1_1, the (1-2)th dike pattern BNK1_2 and (1-4)th dike patterns BNK1_4, and the (1-4)th dike pattern BNK1_4 may be separated from each of the (1-1)th dike patterns BNK1_1 to (1-3)th dike patterns BNK1_3.

[0269] However, this disclosure is not limited thereto. In some embodiments, such as Figure 15BAs shown, the (1-1)th dam pattern BNK1_1 to the (1-4)th dam pattern BNK1_4 can be connected to each other to form a quadrilateral ring shape, which forms a closed loop around the second electrode EL2 along its periphery (e.g., circumference). One end of the (1-1)th dam pattern BNK1_1 can contact the (1-2)th dam pattern BNK1_2, and the other end of the (1-1)th dam pattern BNK1_1 can contact the (1-4)th dam pattern BNK1_4. One end of the (1-2)th dam pattern BNK1_2 can contact the (1-1)th dam pattern BNK1_1, and the other end of the (1-2)th dam pattern BNK1_2 can contact the (1-3)th dam pattern BNK1_3. One end of the (1-3) dike pattern BNK1_3 can contact the (1-2) dike pattern BNK1_2, and the other end of the (1-3) dike pattern BNK1_3 can contact the (1-4) dike pattern BNK1_4. One end of the (1-4) dike pattern BNK1_4 can contact the (1-3) dike pattern BNK1_3, and the other end of the (1-4) dike pattern BNK1_4 can contact the (1-1) dike pattern BNK1_1. As described above, the first dam pattern BNK1 includes dam patterns BNK1_1 to BNK1_4 (1-1) and BNK1_4 (1-4) integrally connected to each other to overlap with the first electrode EL1 in the plane and cross section, and is realized as a quadrilateral ring shape, which forms a closed loop around the second electrode EL2 along the periphery (e.g., the periphery).

[0270] The second dam pattern BNK2 can be disposed in the emission region between the passivation layer PSV and the second electrode EL2.

[0271] The first dam pattern BNK1 and the second dam pattern BNK2 can be inorganic insulating layers comprising inorganic materials or organic insulating layers comprising organic materials. In some embodiments, the first dam pattern BNK1 and the second dam pattern BNK2 may comprise a single layer of organic insulating layer and / or a single layer of inorganic insulating layer, but this disclosure is not limited thereto. However, the materials of the first dam pattern BNK1 and the second dam pattern BNK2 are not limited to the embodiments described above. In some embodiments, the first dam pattern BNK1 and the second dam pattern BNK2 may comprise conductive materials.

[0272] Each of the first dam pattern BNK1 and the second dam pattern BNK2 may have a cross-section with a trapezoidal shape, the width of which narrows from one surface (e.g., the upper surface) of the passivation layer PSV along the third direction DR3 toward its top, but this disclosure is not limited thereto. In some embodiments, such as Figure 18As shown, the first dam pattern BNK1 and the second dam pattern BNK2 may include curved surfaces having a cross-section with a semi-elliptical shape, a semi-circular shape (or a hemispherical shape), etc., whose width narrows from one surface of the passivation layer PSV along the third direction DR3 toward its top. When viewed in cross-section, the shapes of the first dam pattern BNK1 and the second dam pattern BNK2 are not limited to the embodiments described above, and can be varied to improve the efficiency of light emitted from each of the light-emitting elements LD. The first dam pattern BNK1 and the second dam pattern BNK2 adjacent to each other in the first direction DR1 may be disposed on the same surface of the passivation layer PSV and may have the same height (or thickness) in the third direction DR3.

[0273] The dam BNK can be set and / or formed in the peripheral region of the pixel region PXA of each pixel PXL. The dam BNK can be relative to a reference... Figures 7 to 14 The components described are the same as those in the BNK dike.

[0274] The second electrode EL2 can be disposed on the second embankment pattern BNK2 and can be located in the middle of the pixel region PXA of each pixel PXL. The second electrode EL2 can have a quadrilateral shape having a first side S1 to a fourth side S4. The first electrode EL1 can be disposed on the first embankment pattern BNK1 and can have a shape that surrounds the second electrode EL2 along its periphery (or periphery). The first electrode EL1 can have a ring shape that does not completely surround the second electrode EL2, but has a portion A with any one of the openings.

[0275] The first electrode EL1 and the second electrode EL2 can be disposed on the passivation layer PSV at a distance (e.g., a set or predetermined distance) from each other. Because each of the first electrode EL1 and the second electrode EL2 has a surface profile corresponding to the shape of the first dam pattern BNK1 and the second dam pattern BNK2 disposed on its bottom, light emitted from each of the light-emitting elements LD can be reflected by the first electrode EL1 and the second electrode EL2 to further propagate in the image display direction of the display device. The first dam pattern BNK1 and the second dam pattern BNK2, as well as the first electrode EL1 and the second electrode EL2, can serve as reflective members that improve the light efficiency of the display device by guiding the light emitted from the light-emitting element LD in a desired direction.

[0276] A first insulating layer INS1 may be disposed on the first electrode EL1 and the second electrode EL2. The first insulating layer INS1 may include a first opening OPN1 that exposes a region of the first electrode EL1 (e.g., a portion of the (1-1) electrode EL1_1) to the outside and a second opening OPN2 that exposes a region of the second electrode EL2 to the outside. Furthermore, the first insulating layer INS1 may completely cover all regions except for the portion of the (1-1) electrode EL1_1 and the aforementioned region of the second electrode EL2.

[0277] The first contact electrode CNE1 can be disposed on the first insulating layer INS1 above the (1-1) electrode EL1_1, and can be electrically connected to the (1-1) electrode EL1_1 through the first opening OPN1.

[0278] The first intermediate electrode CTE1 may include a first region A1 and a second region A2. The second region A2 may be a region of the first intermediate electrode CTE1 located on the first insulating layer INS1 above a region of the second electrode EL2 including the first side S1, and the first region A1 may be a region of the first intermediate electrode CTE1 located on the first insulating layer INS1 above the (1-2) electrode EL1_2.

[0279] The second region A2 of the first contact electrode CNE1 and the first intermediate electrode CTE1 can be disposed on the second insulating layer INS2 above the first light-emitting element LD1, and spaced apart from each other. The first light-emitting element LD1 can be a light-emitting element LD disposed between a region including the first side S1 of the first electrode EL1_1 and the second electrode EL2.

[0280] The second intermediate electrode CTE2 may include a first region A1 and a second region A2. The second region A2 may be a region of the second intermediate electrode CTE2 located on the first insulating layer INS1 above a region of the second electrode EL2 including the second side S2, and the first region A1 may be a region of the second intermediate electrode CTE2 located on the first insulating layer INS1 above the (1-3) electrode EL1_3.

[0281] The first region A1 of the first intermediate electrode CTE1 and the second region A2 of the second intermediate electrode CTE2 can be disposed on the second insulating layer INS2 above the second light-emitting element LD2, spaced apart from each other. The second light-emitting element LD2 can be a light-emitting element LD disposed between a region including the second side S2 of the first (1-2) electrode EL1_2 and the second electrode EL2.

[0282] The third intermediate electrode CTE3 may include a first region A1 and a second region A2. The second region A2 may be a region of the third intermediate electrode CTE3 located on the first insulating layer INS1 above a region of the second electrode EL2 including the third side S3, and the first region A1 may be a region of the third intermediate electrode CTE3 located on the first insulating layer INS1 above the (1-4) electrode EL1_4.

[0283] The first region A1 of the second intermediate electrode CTE2 and the second region A2 of the third intermediate electrode CTE3 can be separated from each other on the second insulating layer INS2 above the third light-emitting element LD3. The third light-emitting element LD3 can be a light-emitting element LD disposed between a region including the third side S3 of the (1-3) electrode EL1_3 and the second electrode EL2.

[0284] The second contact electrode CNE2 can be disposed on the first insulating layer INS1 above a region of the second electrode EL2 including the fourth side S4, and electrically connected to a region of the second electrode EL2 through the second opening OPN2.

[0285] The first region A1 of the third intermediate electrode CTE3 and the second contact electrode CNE2 can be disposed on the second insulating layer INS2 above the fourth light-emitting element LD4. The fourth light-emitting element LD4 can be a light-emitting element LD disposed between a region including the fourth side S4 of the (1-4) electrode EL1_4 and the second electrode EL2.

[0286] The first light-emitting element LD1 and the second light-emitting element LD2 can be electrically connected to each other through the first intermediate electrode CTE1, the second light-emitting element LD2 and the third light-emitting element LD3 can be electrically connected to each other through the second intermediate electrode CTE2, and the third light-emitting element LD3 and the fourth light-emitting element LD4 can be electrically connected to each other through the third intermediate electrode CTE3. The first light-emitting element LD1 to the fourth light-emitting element LD4 can be radially arranged between the first electrode EL1 and the second electrode EL2 along the first side S1 to the fourth side S4 of the second electrode EL2, so as to be positioned concentrated in the middle (or center) of the pixel region PXA of each pixel PXL.

[0287] As described above, intermediate electrodes CTE (e.g., CTE1, CTE2, CTE3) are disposed between consecutive series stages, second electrode EL2 is disposed in the middle of pixel region PXA, and first electrode EL1 is disposed around second electrode EL2 along the periphery of second electrode EL2, such that the light-emitting unit EMU of each pixel PXL can be configured as a series / parallel hybrid structure including four series stages, while reducing or minimizing the area occupied by alignment electrodes.

[0288] Figures 19A to 19E It is shown Figure 7 A schematic plan view of another embodiment of the first and second electrodes shown.

[0289] about Figures 19A to 19E The first and second electrodes shown will be described primarily for the parts that differ from those described in the above embodiments, in order to avoid redundancy.

[0290] Reference Figures 1 to 6A , Figure 7 as well as Figures 19A to 19E The first electrode EL1 and the second electrode EL2, the first contact electrode CNE1 and the second contact electrode CNE2, and the first intermediate electrode CTE1 to the third intermediate electrode CTE3 can be disposed in the pixel area PXA of each pixel PXL.

[0291] The second electrode EL2 can be located in the middle of the pixel region PXA and can have a quadrilateral shape including the first side S1 to the fourth side S4.

[0292] The first electrode EL1 can be configured to surround the first side S1 to the fourth side S4 of the second electrode EL2. The first electrode EL1 may include the (1-1)th electrode EL1_1 adjacent to the first side S1 of the second electrode EL2, the (1-2)th electrode EL1_2 adjacent to the second side S2 of the second electrode EL2, the (1-3)th electrode EL1_3 adjacent to the third side S3 of the second electrode EL2, and the (1-4)th electrode EL1_4 adjacent to the fourth side S4 of the second electrode EL2.

[0293] The first electrode EL1 surrounds the second electrode EL2 from the first side S1 to the fourth side S4, but as Figure 19A As shown, a portion of the first electrode EL1 may be removed between electrodes (1-3) EL1_3 and (1-4) EL1_4 to avoid completely surrounding the periphery (e.g., the periphery) of the second electrode EL2. The first electrode EL1 may have a quadrilateral ring shape with an opening in one of its regions B. Electrodes (1-3) EL1_3 and (1-4) EL1_4 may not contact each other (or may be spaced apart from each other).

[0294] In some embodiments, the first electrode EL1 surrounds the second electrode EL2 from the first side S1 to the fourth side S4, but as... Figure 19BAs shown, a portion of the first electrode EL1 may be removed between the (1-2) electrodes EL1_2 and (1-3) electrodes EL1_3, so as not to completely surround the periphery (e.g., the periphery) of the second electrode EL2. The first electrode EL1 may have a quadrilateral ring shape with an opening in one of its regions C. The (1-2) electrodes EL1_2 and (1-3) electrodes EL1_3 may not contact each other (or may be separated from each other by a predetermined distance).

[0295] In another embodiment, the first electrode EL1 surrounds the second electrode EL2 from the first side S1 to the fourth side S4, but as... Figure 19C As shown, a portion of the first electrode EL1 may be removed between electrode (1-1) EL1_1 and electrode (1-4) EL1_4, and a portion of the first electrode EL1 may be removed between electrode (1-2) EL1_2 and electrode (1-3) EL1_3, instead of completely surrounding the periphery (or periphery) of the second electrode EL2. For example, the first electrode EL1 may have a quadrilateral ring shape with openings in two regions A and C. Electrodes (1-1) EL1_1 and (1-4) EL1_4 may not contact each other (or may be spaced apart by a predetermined distance), electrodes (1-2) EL1_2 and (1-3) EL1_3 may not contact each other (or may be spaced apart by a predetermined distance), electrodes (1-1) EL1_1 and (1-2) EL1_2 may contact each other, and electrodes (1-3) EL1_3 and (1-4) EL1_4 may contact each other. Electrode EL1_1 (1-1) can be electrically connected to the pixel circuit layer through the first contact hole CH1 (see...). Figure 9 Some components of the 'PCL' shown, such as the driving transistor (see... Figure 9 (as shown in 'Tdr'). The (1-3) electrode EL1_3 can be electrically connected to the driving transistor Tdr through the third contact hole CH3.

[0296] In another embodiment, the first electrode EL1 surrounds the second electrode EL2 from the first side S1 to the fourth side S4, but as... Figure 19DAs shown, a portion of the first electrode EL1 may be removed between electrode (1-1) EL1_1 and electrode (1-2) EL1_2, and a portion of the first electrode EL1 may be removed between electrode (1-3) EL1_3 and electrode (1-4) EL1_4, instead of completely surrounding the periphery (e.g., the periphery) of the second electrode EL2. The first electrode EL1 may have a quadrilateral ring shape with openings in two regions D and B. Electrodes (1-1) EL1_1 and (1-2) EL1_2 may not contact each other (or may be spaced apart by a predetermined distance), electrodes (1-3) EL1_3 and (1-4) EL1_4 may not contact each other (or may be spaced apart by a predetermined distance), electrodes (1-2) EL1_2 and (1-3) EL1_3 may contact each other, and electrodes (1-1) EL1_1 and (1-4) EL1_4 may contact each other. Electrode EL1_2 (1-2) can be electrically connected to the driving transistor Tdr through the first contact hole CH1, and electrode EL1_4 (1-4) can be electrically connected to the driving transistor Tdr through the third contact hole CH3.

[0297] In another embodiment, the first electrode EL1 surrounds the second electrode EL2 from the first side S1 to the fourth side S4, but as... Figure 19EAs shown, portion D of the first electrode EL1 can be removed between electrode (1-1) EL1_1 and electrode (1-2) EL1_2, portion C of the first electrode EL1 can be removed between electrode (1-2) EL1_2 and electrode (1-3) EL1_3, portion B of the first electrode EL1 can be removed between electrode (1-3) EL1_3 and electrode (1-4) EL1_4, and portion A of the first electrode EL1 can be removed between electrode (1-4) EL1_4 and electrode (1-1) EL1_1, so as not to completely surround the periphery (e.g., the periphery) of the second electrode EL2. The first electrode EL1 can have a quadrilateral ring shape in which four regions A, B, C, and D are open. Electrode (1-1) EL1_1 and electrode (1-2) EL1_2 may not contact each other (or may be separated by a predetermined distance), electrode (1-2) EL1_2 and electrode (1-3) EL1_3 may not contact each other (or may be separated by a predetermined distance), electrode (1-3) EL1_3 and electrode (1-4) EL1_4 may not contact each other (or may be separated by a predetermined distance), and electrode (1-4) EL1_4 and electrode (1-1) EL1_1 may not contact each other (or may be separated by a predetermined distance). Electrode (1-1) EL1_1 can be electrically connected to a portion of the pixel circuit layer PCL via the first contact hole CH1; electrode (1-2) EL1_2 can be electrically connected to a portion of the pixel circuit layer PCL via the second contact hole CH2; electrode (1-3) EL1_3 can be electrically connected to a portion of the pixel circuit layer PCL via the third contact hole CH3; and electrode (1-4) EL1_4 can be electrically connected to a portion of the pixel circuit layer PCL via the fourth contact hole CH4. The portion of the pixel circuit layer PCL may be a driving transistor Tdr.

[0298] The shape of the first electrode EL1 is not limited to the embodiments described above. In some embodiments, the first electrode EL1 can be changed in various shapes within such a range that the alignment area of ​​the light-emitting element LD located between the first electrode EL1 and the second electrode EL2 can be further ensured, while surrounding at least a portion of the second electrode EL2.

[0299] Figure 20 A pixel is schematically shown according to another embodiment of the present disclosure, and is a schematic plan view of pixels configured only in a portion of the display element layer.

[0300] Reference Figures 1 to 6A as well as Figure 20 The first electrode EL1, the second electrode EL2, the intermediate electrode CTE, and the light-emitting element LD can be set in the pixel area PXA of each pixel PXL.

[0301] The second electrode EL2 may have a hexagonal shape, located in the middle (or center) of the pixel region PXA and surrounded by first sides S1 to sixth sides S6. In some exemplary embodiments, the second electrode EL2 may have a regular hexagonal shape, wherein the first sides S1 to sixth sides S6 have the same length. The second electrode EL2 can be electrically connected to the second contact electrode CNE2 through the second opening OPN2 of the first insulating layer INS1. Furthermore, the second electrode EL2 can be electrically connected to the pixel circuit layer (see [link to relevant documentation]) through the second contact hole CH2. Figure 9 Some components of the “PCL” shown, such as the drive voltage line (see Figure 9 (as shown in "DVL").

[0302] The first electrode EL1 may have a specific shape (e.g., a hexagonal ring shape) and may surround the second electrode EL2 along its periphery (e.g., its edge). In some exemplary embodiments, the first electrode EL1 may have a shape that does not completely surround the periphery (e.g., its edge) of the second electrode EL2; for example, it may form a hexagonal ring shape with any part E of an opening rather than a complete hexagonal ring shape. However, this disclosure is not limited thereto, and the first electrode EL1 may be modified to have a shape corresponding to the shape of the second electrode EL2. For example, when the second electrode EL2 has a pentagonal shape with five sides, the first electrode EL1 may have a pentagonal ring shape such as having an open portion while surrounding the periphery (e.g., its edge) of the second electrode EL2. When the second electrode EL2 has an octagonal shape with eight sides, the first electrode EL1 may have an octagonal ring shape such as having an open portion while surrounding the periphery (e.g., its edge) of the second electrode EL2.

[0303] The first electrode EL1 and the second electrode EL2 can be spaced apart from each other by a predetermined distance. The first electrode EL1 can be electrically connected to the first contact electrode CNE1 through the first opening OPN1 of the first insulating layer INS1. Furthermore, the first electrode EL1 can be electrically connected to the driving transistor of the pixel circuit layer PCL through the first contact hole CH1 (see...). Figure 9 (as shown in "Tdr").

[0304] The first electrode EL1 may include (1-1) electrode EL1_1 to (1-6) electrode EL1_6. The (1-1) electrode EL1_1 to (1-6) electrode EL1_6 may be integrally connected to each other and may be different regions of the first electrode EL1. In the example, the (1-1) electrode EL1_1 can be a region of the first electrode EL1 adjacent to the first side S1 of the second electrode EL2, the (1-2) electrode EL1_2 can be a region of the first electrode EL1 adjacent to the second side S2 of the second electrode EL2, the (1-3) electrode EL1_3 can be a region of the first electrode EL1 adjacent to the third side S3 of the second electrode EL2, the (1-4) electrode EL1_4 can be a region of the first electrode EL1 adjacent to the fourth side S4 of the second electrode EL2, the (1-5) electrode EL1_5 can be a region of the first electrode EL1 adjacent to the fifth side S5 of the second electrode EL2, and the (1-6) electrode EL1_6 can be a region of the first electrode EL1 adjacent to the sixth side S6 of the second electrode EL2.

[0305] In the pixel region PXA, multiple light-emitting elements (LDs) can be aligned and / or disposed between a region including the first side S1 of the (1-1) electrode EL1_1 and the second electrode EL2, between a region including the second side S2 of the (1-2) electrode EL1_2 and the second electrode EL2, between a region including the third side S3 of the (1-3) electrode EL1_3 and the second electrode EL2, between a region including the fourth side S4 of the (1-4) electrode EL1_4 and the second electrode EL2, between a region including the fifth side S5 of the (1-5) electrode EL1_5 and the second electrode EL2, and between a region including the sixth side S6 of the (1-6) electrode EL1_6 and the second electrode EL2.

[0306] When the second electrode EL2 is located in the middle of the pixel region PXA and the first electrode EL1 surrounds the second electrode EL2 along its periphery, an alignment signal (or alignment voltage) is applied to each of the first electrode EL1 and the second electrode EL2. An electric field can then be formed between the first electrode EL1 and the second electrode EL2 in the same direction along the periphery (e.g., the circumference) of the second electrode EL2. Light-emitting elements (LDs) provided to the pixel region PXA can be arranged in the same direction between the first electrode EL1 and the second electrode EL2. For example, one end of each of the light-emitting elements LDs can face the first electrode EL1, and the other end of each of the light-emitting elements LDs can face the second electrode EL2.

[0307] The light-emitting element LD may include at least one first light-emitting element LD1 aligned between a region including a first side S1 of the first electrode EL1_1 and the second electrode EL2, at least one second light-emitting element LD2 aligned between a region including a second side S2 of the second electrode EL1_2 and the second electrode EL2, at least one third light-emitting element LD3 aligned between a region including a third side S3 of the second electrode EL1_3 and the second electrode EL2, at least one fourth light-emitting element LD4 aligned between a region including a fourth side S4 of the second electrode EL1_4 and the second electrode EL2, at least one fifth light-emitting element LD5 aligned between a region including a fifth side S5 of the second electrode EL1_5 and the second electrode EL2, and at least one sixth light-emitting element LD6 aligned between a region including a sixth side S6 of the second electrode EL1_6 and the second electrode EL2.

[0308] The region including the first side S1 of the first electrode EL1_1 and the second electrode EL2, together with the first light-emitting element LD1 aligned (or connected) between them, can constitute the first cascade stage SET1 of the light-emitting unit EMU of each pixel PXL.

[0309] The region including the second side S2 of the first (1-2) electrode EL1_2 and the second electrode EL2, together with the second light-emitting element LD2 aligned (or connected) between them, can constitute the second series stage SET2 of the light-emitting unit EMU.

[0310] The region including the third side S3 of the first (1-3) electrode EL1_3 and the second electrode EL2, together with the third light-emitting element LD3 aligned (or connected) between them, can constitute the third series stage SET3 of the light-emitting unit EMU.

[0311] The region of the (1-4) electrode EL1_4 and the second electrode EL2, including the fourth side S4, together with the fourth light-emitting element LD4 aligned (or connected) between them, can constitute the fourth series stage SET4 of the light-emitting unit EMU.

[0312] The region of the (1-5) electrodes EL1_5 and the second electrode EL2, including the fifth side S5, together with the fifth light-emitting element LD5 aligned (or connected) between them, can constitute the fifth series stage of the light-emitting unit EMU.

[0313] The region of the (1-6) electrodes EL1_6 and the second electrode EL2, including the sixth side S6, together with the sixth light-emitting element LD6 aligned (or connected) between them, can constitute the sixth series stage of the light-emitting unit EMU.

[0314] The first contact electrode CNE1 can be disposed on each of the (1-1) electrode EL1_1 and one end of the first light-emitting element LD1. The first contact electrode CNE1 can be electrically connected to each of the (1-1) electrode EL1_1 and the first light-emitting element LD1.

[0315] The second contact electrode CNE2 can be disposed on each of the regions of the second electrode EL2 including the sixth side S6 and the other end of the sixth light-emitting element LD6. The second contact electrode CNE2 can be electrically connected to each of the regions of the second electrode EL2 including the sixth side S6 and the sixth light-emitting element LD6.

[0316] In some exemplary embodiments of this disclosure, the intermediate electrode CTE may include a first intermediate electrode CTE1 to a fifth intermediate electrode CTE5. The intermediate electrode CTE may be disposed in the same layer as the first contact electrode CNE1 and the second contact electrode CNE2, comprise the same material as the first contact electrode CNE1 and the second contact electrode CNE2, and be formed by the same process as the first contact electrode CNE1 and the second contact electrode CNE2. However, this disclosure is not limited thereto. In some embodiments, the intermediate electrode CTE may be disposed in a layer different from the layers of the first contact electrode CNE1 and the second contact electrode CNE2, and may be formed by a process different from the process used for the first contact electrode CNE1 and the second contact electrode CNE2.

[0317] The first intermediate electrode CTE1 can be disposed on a region of the second electrode EL2 including the first side S1 and each of the (1-2) electrodes EL1_2, so as to overlap with a region of the second electrode EL2 and the (1-2) electrodes EL1_2. The first intermediate electrode CTE1 can be disposed on a first corner of the second electrode EL2 to overlap with the first corner, at which the first side S1 and the second side S2 are in contact with each other (or intersect). Furthermore, the first intermediate electrode CTE1 can be disposed on the other end of the first light-emitting element LD1 and one end of the second light-emitting element LD2. The first intermediate electrode CTE1 can be used as a first bridging electrode (or a first connecting electrode) for electrically connecting the first light-emitting element LD1 and the second light-emitting element LD2. The first intermediate electrode CTE1 can also be a first bridging electrode (or a first connecting electrode) for connecting the first series stage SET1 and the second series stage SET2.

[0318] The second intermediate electrode CTE2 can be disposed on a region of the second electrode EL2 including the second side S2 and each of the (1-3) electrodes EL1_3, so as to overlap with a region of the second electrode EL2 and the (1-3) electrodes EL1_3. The second intermediate electrode CTE2 can be disposed on the second corner of the second electrode EL2 to overlap with the second corner, where the second side S2 and the third side S3 are in contact with each other (or intersect). Furthermore, the second intermediate electrode CTE2 can be disposed on each of the other end of the second light-emitting element LD2 and one end of the third light-emitting element LD3. The second intermediate electrode CTE2 can be used as a second bridging electrode (or a second connecting electrode) electrically connecting the second light-emitting element LD2 and the third light-emitting element LD3. The second intermediate electrode CTE2 can also be a second bridging electrode (or a second connecting electrode) connecting the second series stage SET2 and the third series stage SET3.

[0319] The third intermediate electrode CTE3 can be disposed on a region of the second electrode EL2 including the third side S3 and each of the (1-4) electrodes EL1_4, so as to overlap with a region of the second electrode EL2 and the (1-4) electrodes EL1_4. The third intermediate electrode CTE3 can be disposed on the third corner of the second electrode EL2 so as to overlap with the third corner, at which the third side S3 and the fourth side S4 are in contact with each other (or intersect). In addition, the third intermediate electrode CTE3 can be disposed on each of the other end of the third light-emitting element LD3 and one end of the fourth light-emitting element LD4. The third intermediate electrode CTE3 can be used as a third bridging electrode (or a third connecting electrode) for electrically connecting the third light-emitting element LD3 and the fourth light-emitting element LD4. The third intermediate electrode CTE3 can be a third bridging electrode (or a third connecting electrode) for connecting the third series stage SET3 and the fourth series stage SET4.

[0320] The fourth intermediate electrode CTE4 can be disposed on a region of the second electrode EL2 including the fourth side S4 and each of the (1-5) electrodes EL1_5, so as to overlap with a region of the second electrode EL2 and the (1-5) electrodes EL1_5. The fourth intermediate electrode CTE4 can be disposed on the fourth corner of the second electrode EL2 to overlap with the fourth corner, where the fourth side S4 and the fifth side S5 are in contact with each other (or intersect). Furthermore, the fourth intermediate electrode CTE4 can be disposed on each of the other end of the fourth light-emitting element LD4 and one end of the fifth light-emitting element LD5. The fourth intermediate electrode CTE4 can be used as a fourth bridging electrode (or fourth connecting electrode) for electrically connecting the fourth light-emitting element LD4 and the fifth light-emitting element LD5. The fourth intermediate electrode CTE4 can also be a fourth bridging electrode (or fourth connecting electrode) for connecting the fourth series stage SET4 and the fifth series stage.

[0321] The fifth intermediate electrode CTE5 can be disposed on a region of the second electrode EL2 including the fifth side S5 and each of the (1-6) electrodes EL1_6, so as to overlap with a region of the second electrode EL2 and the (1-6) electrodes EL1_6. The fifth intermediate electrode CTE5 can also be disposed on the fifth corner of the second electrode EL2, overlapping with the fifth corner, where the fifth side S5 and the sixth side S6 are in contact with each other (or intersect). Furthermore, the fifth intermediate electrode CTE5 can be disposed on each of the other end of the fifth light-emitting element LD5 and one end of the sixth light-emitting element LD6. The fifth intermediate electrode CTE5 can serve as a fifth bridging electrode (or a fifth connecting electrode) electrically connecting the fifth light-emitting element LD5 and the sixth light-emitting element LD6. The fifth intermediate electrode CTE5 can also be a fifth bridging electrode (or a fifth connecting electrode) connecting the fifth series stage and the sixth series stage.

[0322] The sixth corner of the second electrode EL2, where the sixth side S6 and the first side S1 are in contact (or intersect), may not overlap with the first intermediate electrode CTE1 to the fifth intermediate electrode CTE5.

[0323] In the pixel region PXA of each pixel PXL, the first contact electrode CNE1, the second contact electrode CNE2, and the first intermediate electrode CTE1 to the fifth intermediate electrode CTE5 can be arranged to be spaced apart from each other when viewed on a plane.

[0324] When it is assumed that the driving current flows from the first power line PL1 to the driving voltage line DVL through the driving transistor Tdr of the pixel circuit layer PCL included in each pixel PXL, the driving current can be introduced into the light-emitting unit EMU of each pixel PXL through the first contact hole CH1.

[0325] In the example, the driving current is supplied to the (1-1) electrode EL1_1 through the first contact hole CH1, and flows through the first contact electrode CNE1 via the first light-emitting element LD1 in the first intermediate electrode CTE1. Therefore, the first light-emitting element LD1 in the first series stage SET1 can emit light with a brightness corresponding to the current distributed and applied thereto.

[0326] The driving current flowing in the first intermediate electrode CTE1 flows through the second light-emitting element LD2 in the second intermediate electrode CTE2. Therefore, the second light-emitting element LD2 in the second series stage SET2 can emit light with a brightness corresponding to the current distributed and applied thereto.

[0327] The driving current flowing in the second intermediate electrode CTE2 flows through the third light-emitting element LD3 in the third intermediate electrode CTE3. Therefore, the third light-emitting element LD3 in the third series stage SET3 can emit light with a brightness corresponding to the current distributed and applied thereto.

[0328] The driving current flowing in the third intermediate electrode CTE3 flows through the fourth light-emitting element LD4 in the fourth intermediate electrode CTE4. Therefore, the fourth light-emitting element LD4 in the fourth series stage SET4 can emit light with a brightness corresponding to the current distributed and applied thereto.

[0329] The driving current flowing in the fourth intermediate electrode CTE4 flows through the fifth light-emitting element LD5 in the fifth intermediate electrode CTE5. Therefore, the fifth light-emitting element LD5 in the fifth series stage can emit light with a brightness corresponding to the current distributed and applied to it.

[0330] The driving current flowing in the fifth intermediate electrode CTE5 flows through the sixth light-emitting element LD6 in the second contact electrode CNE2. Therefore, the sixth light-emitting element LD6 in the sixth series stage can emit light with a brightness corresponding to the current distributed and applied to it.

[0331] In the manner described above, the driving current of each pixel PXL flows sequentially through the first light-emitting element LD1 of the first series stage SET1, the second light-emitting element LD2 of the second series stage SET2, the third light-emitting element LD3 of the third series stage SET3, the fourth light-emitting element LD4 of the fourth series stage SET4, the fifth light-emitting element LD5 of the fifth series stage, and the sixth light-emitting element LD6 of the sixth series stage. Therefore, each pixel PXL can emit light with a brightness corresponding to the data signal provided during each frame period.

[0332] According to this disclosure, a pixel can be provided in which a first electrode having a quadrilateral shape is disposed in the middle (or center) of the pixel region of each pixel, and a second electrode is disposed around the first electrode, thereby ensuring sufficient alignment area of ​​the light-emitting elements between the first electrode and the second electrode.

[0333] Furthermore, according to this disclosure, a pixel and a display device including the pixel can be provided, wherein a plurality of cascaded light-emitting units are configured by providing an intermediate electrode that overlaps with each of a region of a first electrode and a region of a second electrode, thereby improving the light output efficiency of the light-emitting element.

[0334] Exemplary embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments at the time of filing this application, unless specifically stated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. Pixel, including: First electrode; A second electrode surrounds at least a portion of the first electrode; Multiple light-emitting elements are located between the first electrode and the second electrode; A first contact electrode is provided, wherein the first contact electrode is electrically connected to the first electrode and the plurality of light-emitting elements; The second contact electrode is electrically connected to the second electrode and the plurality of light-emitting elements. as well as An intermediate electrode, located on the first electrode and the second electrode, includes a first region overlapping the first electrode and a second region overlapping the second electrode. The first region and the second region are integrally connected to each other.

2. The pixel of claim 1, wherein, The first contact electrode, the second contact electrode, and the intermediate electrode are spaced apart from each other. The intermediate electrode is located in the same layer as the first contact electrode and the second contact electrode, or it is located in a different layer than the first contact electrode and the second contact electrode.

3. The pixel according to claim 2, wherein, The first electrode has a quadrilateral shape including a first side, a second side, a third side, and a fourth side. The second electrode includes a (2-1) electrode adjacent to the first side of the first electrode, a (2-2) electrode adjacent to the second side of the first electrode, a (2-3) electrode adjacent to the third side of the first electrode, and a (2-4) electrode adjacent to the fourth side of the first electrode.

4. The pixel according to claim 3, wherein, The second electrode has a quadrilateral ring shape and surrounds the first electrode from the first side to the fourth side, and has at least an opening.

5. The pixel according to claim 4, wherein, The (2-1) electrode and the (2-4) electrode are separated from each other.

6. The pixel according to claim 4, wherein, The (2-2) electrode and the (2-3) electrode are spaced apart from each other.

7. The pixel according to claim 4, wherein, The (2-1) electrode and the (2-2) electrode are spaced apart from each other. The (2-3) electrode and the (2-4) electrode are spaced apart from each other. The (2-1)th electrode and the (2-4)th electrode are connected to each other, and The (2-2) electrode and the (2-3) electrode are connected to each other.

8. The pixel according to claim 3, wherein, The intermediate electrode includes a first intermediate electrode, a second intermediate electrode, and a third intermediate electrode that are spaced apart from each other. Each of the first intermediate electrode, the second intermediate electrode, and the third intermediate electrode overlaps with a region of the first electrode and a region of the second electrode.

9. The pixel according to claim 8, wherein, The first intermediate electrode includes a first region corresponding to the first side of the first electrode and a second region corresponding to the (2-2)th electrode. The second intermediate electrode includes a first region corresponding to the second side of the first electrode and a second region corresponding to the (2nd-3rd) electrode, and The third intermediate electrode includes a first region corresponding to the third side of the first electrode and a second region corresponding to the (2-4)th electrode.

10. The pixel according to claim 9, wherein, In the plan view, the first intermediate electrode overlaps with each of the first edge of the first electrode, the first corner portion where the first edge and the second edge of the first electrode contact each other, and the first (2-2) electrode. In the plan view, the second intermediate electrode overlaps with each of the second corner portions of the first electrode, the second side of the first electrode, and the third side of the first electrode, which are in contact with each other, and the second corner portion of the (2nd-3rd) electrodes. In the plan view, the third intermediate electrode overlaps with each of the third corner portions of the first electrode, the third and fourth sides of the first electrode, and the (2-4) electrodes.

11. The pixel according to claim 9, wherein, The first contact electrode overlaps with the fourth side of the first electrode, and the second contact electrode overlaps with the (2-1)th electrode.

12. The pixel of claim 11, further comprising an insulating layer over the first electrode and the second electrode. in, The insulating layer includes a first opening exposing a region of the first electrode corresponding to the fourth side of the first electrode and a second opening exposing a region of the (2-1)th electrode.

13. The pixel according to claim 12, wherein, The insulating layer covers the other regions corresponding to each of the first electrode and the first to third sides of the first electrode, the (2-2) electrode, the (2-3) electrode, and the (2-4) electrode.

14. The pixel according to claim 12, wherein, The light-emitting element includes: Multiple first light-emitting elements are located between the first side of the first electrode and the (2-1)th electrode; Multiple second light-emitting elements are located between the second side of the first electrode and the (2-2)th electrode; A plurality of third light-emitting elements are located between the third side of the first electrode and the (2nd-3rd) electrode; and Multiple fourth light-emitting elements are located between the fourth side of the first electrode and the (2-4)th electrode.

15. The pixel according to claim 14, wherein: The first light-emitting element forms a first series stage connected in parallel between the first side of the first electrode and the (2-1)th electrode. The second light-emitting element forms a second series stage connected in parallel between the second side of the first electrode and the (2-2)th electrode. The third light-emitting element constitutes a third series stage connected in parallel between the third side of the first electrode and the (2nd-3rd) electrode, and The fourth light-emitting element constitutes a fourth series stage connected in parallel between the fourth side of the first electrode and the (2-4)th electrode.

16. The pixel according to claim 1, wherein, In the plan view, the plurality of light-emitting elements are placed between the first electrode and the second electrode along the periphery of the first electrode.

17. The pixel according to claim 16, wherein, The first electrode has a hexagonal shape including a first side, a second side, a third side, a fourth side, a fifth side, and a sixth side. The second electrode includes: The (2-1)th electrode is adjacent to the first side of the first electrode; The (2-2)th electrode is adjacent to the second side of the first electrode; The (2nd-3rd) electrode is adjacent to the third side of the first electrode; The (2nd-4th) electrode is adjacent to the fourth side of the first electrode; The (2nd-5th) electrode is adjacent to the fifth side of the first electrode; and The (2nd-6th) electrode is adjacent to the sixth side of the first electrode.

18. The pixel according to claim 17, wherein, The light-emitting element includes: At least one first light-emitting element is located between the first side of the first electrode and the (2-1)th electrode; At least one second light-emitting element is located between the second side of the first electrode and the (2-2)th electrode; At least one third light-emitting element is located between the third side of the first electrode and the (2nd-3rd) electrode; At least one fourth light-emitting element is located between the fourth side of the first electrode and the (2-4)th electrode; At least one fifth light-emitting element is located between the fifth side of the first electrode and the (2-5)th electrode; and At least one sixth light-emitting element is located between the sixth side of the first electrode and the (2-6)th electrode.

19. A display device, including: The substrate includes multiple pixel regions; as well as Pixel, in each of the pixel regions, The pixels include: A first electrode and a second electrode, the first electrode being on the substrate and the second electrode surrounding at least a portion of the first electrode; Multiple light-emitting elements are located between the first electrode and the second electrode; A first contact electrode is provided, wherein the first contact electrode is electrically connected to the first electrode and the light-emitting element; A second contact electrode, wherein the second contact electrode is electrically connected to the second electrode and the light-emitting element; and An intermediate electrode, located on the first electrode and the second electrode, includes a first region overlapping the first electrode and a second region overlapping the second electrode. The first region and the second region are integrally connected to each other, and The first contact electrode, the second contact electrode, and the intermediate electrode are located in the same layer.

20. The display device according to claim 19, wherein, The first electrode has a quadrilateral shape including a first side, a second side, a third side, and a fourth side. The second electrode includes a (2-1) electrode adjacent to the first side of the first electrode, a (2-2) electrode adjacent to the second side of the first electrode, a (2-3) electrode adjacent to the third side of the first electrode, and a (2-4) electrode adjacent to the fourth side of the first electrode.

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