Flexible display device

Abstract

A flexible display device comprising: a flexible substrate; a semiconductor layer over the flexible substrate, the semiconductor layer comprising a polycrystalline semiconductor; a gate insulating layer over the semiconductor layer; and a gate electrode over the gate insulating layer, the gate electrode overlapping a channel region of the semiconductor layer in plan view, wherein the semiconductor layer includes a source region and a drain region located on opposite sides of the channel region, wherein the channel region includes a first region in contact with the source region and a second region in contact with the drain region, and wherein a channel width of the first region is greater than a channel width of the second region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0057649, filed with the Korean Intellectual Property Office (KIPO) on May 14, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a flexible display device, and more specifically, to a display device that includes light-emitting diodes and can be folded and unfolded by having flexible properties. Background Technology

[0004] Display devices are image display devices, and recently, self-emissive display devices such as organic light-emitting diode displays have attracted attention.

[0005] Unlike LCDs, OLEDs are self-emissive and do not require a separate light source, allowing for reductions in thickness and weight. Furthermore, OLEDs offer superior characteristics such as low power consumption, high brightness, and fast response times.

[0006] Because the light-emitting display device emits its own light, each pixel's light-emitting diode can emit light individually or independently. For this purpose, a light-emitting driver and a scan driver can be included, and a light-emitting signal is transmitted to each pixel to allow the organic light-emitting diode to emit light.

[0007] The light-emitting display device can also be a flexible display device in which the display device can be bent.

[0008] The information disclosed in this background section is intended only to enhance the understanding of the background technology of this disclosure, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0009] One or more exemplary embodiments relate to a flexible display device including a transistor whose output current does not decrease even when mechanical or electrical stress occurs while the display device is folded or unfolded or held in the folded state.

[0010] A flexible display device according to an exemplary embodiment includes: a flexible substrate; a semiconductor layer on the flexible substrate, the semiconductor layer comprising a polycrystalline semiconductor; a gate insulating layer on the semiconductor layer; and a gate electrode on the gate insulating layer, the gate electrode overlapping a channel region of the semiconductor layer in a plan view, wherein the semiconductor layer includes a source region and a drain region located on opposite sides of the channel region, wherein the channel region includes a first region contacting the source region and a second region contacting the drain region, and wherein the channel width of the first region is greater than the channel width of the second region.

[0011] The width of the drain region can be greater than the channel width of the second region, and the width of the source region can be less than the channel width of the first region.

[0012] The width of the drain region can be equal to the channel width of the second region, and the width of the source region can be less than the channel width of the first region.

[0013] The width of the drain region can be equal to the channel width of the second region, and the width of the source region can be equal to the channel width of the first region.

[0014] The semiconductor layer and the gate electrode may each have a bent structure.

[0015] The width of the drain region can be equal to the channel width of the second region, and the width of the source region can be equal to the channel width of the first region.

[0016] The channel region may include the intermediate region between the first region and the second region.

[0017] The width of the channel in the intermediate region changes along the intermediate region of the channel area.

[0018] The flexible substrate may include a display area and a non-display area, a plurality of pixels located in the display area, and a driver located in the non-display area to apply driving signals to the plurality of pixels; wherein the driver includes a transistor, the transistor including the source region, the channel region, the drain region and the gate electrode.

[0019] The driver may include a light-emitting driver to provide light-emitting signals to the plurality of pixels, and the light-emitting driver includes multiple stages.

[0020] The plurality of stages of the light-emitting driver may include: a high-level output section for outputting a high voltage of the light-emitting signal according to the voltage of a first node; a low-level output section for outputting a low voltage of the light-emitting signal according to the voltage of a second node; a first node controller for controlling the first node, the first node controller including a first node_first controller and a first node_second controller; a second node controller for controlling the second node, the second node controller including a second node_first controller and a second node_second controller; and a third node controller for controlling the voltage of a third node, the third node controlling the first node_second controller.

[0021] At least one of the second node controller and the third node controller includes the transistor.

[0022] The second node_first controller may include a first transistor, the first transistor including a control electrode connected to a first clock input terminal, an input electrode connected to a control terminal, and an output electrode connected to the second node. The second node_second controller may include: the transistor as a second transistor, further including a control electrode connected to the third node and an input electrode receiving the high voltage of the light emission signal; and a third transistor, including a control electrode connected to a second clock input terminal, an input electrode connected to the output electrode of the second transistor, and an output electrode connected to the second node. The third node controller may include: a fourth transistor, including a control terminal connected to the second node, an input terminal connected to the first clock input terminal, and an output terminal connected to the third node; and a fifth transistor, including a control terminal connected to the first clock input terminal, a low voltage input terminal receiving the light emission signal, and an output terminal connected to the third node.

[0023] A flexible display device according to an exemplary embodiment includes: a flexible substrate; a semiconductor layer on the flexible substrate, the semiconductor layer including a polycrystalline semiconductor; a gate insulating layer on the semiconductor layer; and a gate electrode on the gate insulating layer, wherein the semiconductor layer may include a channel region, a source region, and a drain region, the source region and the drain region being located on opposite sides of the channel region, wherein the gate electrode may include a linear portion extending in a direction intersecting the semiconductor layer and a protruding portion protruding from the linear portion, and wherein the protruding portion may overlap with the channel region of the semiconductor layer in a plan view.

[0024] The drain region, the source region, and the channel region may have the same width.

[0025] The drain region, the source region, and the channel region may have the same width.

[0026] The channel region may include a portion that overlaps with the linear portion and a portion that overlaps with the protruding portion of the gate electrode.

[0027] A flexible display device according to an exemplary embodiment includes: a flexible substrate; a semiconductor layer on the flexible substrate, the semiconductor layer including a polycrystalline semiconductor; a gate insulating layer on the semiconductor layer; and a gate electrode on the gate insulating layer, wherein the semiconductor layer includes a channel region, a source region, and a drain region, the source region and the drain region being located on opposite sides of the channel region, wherein the semiconductor layer and the gate electrode each have a bent structure, wherein the channel region and the gate electrode overlap each other in a plan view, and wherein the channel region is located at a bent portion of the semiconductor layer.

[0028] The channel region may include a first region in contact with the source region and a second region in contact with the drain region, and the channel width of the first region may be greater than the channel width of the second region.

[0029] The semiconductor layer may further include a non-channel region in contact with the channel region, the non-channel region being separate from the source region and the drain region, and the non-channel region may be doped and does not overlap with the gate electrode in a planar view.

[0030] According to the exemplary embodiment, in the semiconductor layer of the transistor formed in the flexible display device, the channel width of the channel region contacting the source region can be greater than the channel width of the channel region contacting the drain region, so that even if a large mechanical or electrical stress is applied, the output current of the transistor will not decrease. Furthermore, according to the exemplary embodiment, the driver for the flexible display device includes a thin-film transistor whose output current does not decrease, thereby eliminating display problems such as flickering caused by a reduction in the drive signal. Attached Figure Description

[0031] Figure 1 This is a block diagram of a light-emitting display device according to an exemplary embodiment.

[0032] Figure 2 This is a block diagram of a light-emitting driver according to an exemplary embodiment.

[0033] Figure 3 This is a circuit diagram of one stage of a light-emitting driver according to an exemplary embodiment.

[0034] Figure 4It is a waveform diagram of the signal applied to the stage according to an exemplary embodiment and the emission signal according to the signal.

[0035] Figure 5 A graph showing the simulation results of the characteristics of each transistor included in the stage of the light-emitting driver according to the comparative example is shown.

[0036] Figure 6 This is a waveform diagram showing the characteristics of the second transistor in the stage according to the comparison example.

[0037] Figure 7 This is a top view of an asymmetric structure of a transistor according to an exemplary embodiment.

[0038] Figure 8 It is a section taken along line VIII-VIII. Figure 7 Cross-sectional view.

[0039] Figure 9 It is a top view of the transistor in the comparative example, and Figure 10 This is a top view of an asymmetric structure of a transistor according to an exemplary embodiment, to describe from Figure 7 Does the output current generated by the transistor in the exemplary embodiment decrease?

[0040] Figures 11 to 13 The features generated from the edge portion of the transistor's channel are shown.

[0041] Figure 14 It shows the basis Figure 9 and Figure 10 A graph showing the simulation results of the change in the output current.

[0042] Figures 15 to 19 This is a top view of an asymmetric transistor structure according to another exemplary embodiment. Detailed Implementation

[0043] The present disclosure will be described more fully below with reference to the accompanying drawings, in which exemplary embodiments of the invention are illustrated. As those skilled in the art will recognize, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure.

[0044] The accompanying drawings and description should be considered illustrative rather than restrictive in nature. Throughout the specification, the same reference numerals denote the same elements.

[0045] Furthermore, since the dimensions and thicknesses of each component shown in the accompanying drawings are arbitrarily illustrated for better understanding and ease of description, this disclosure is not necessarily limited to what is shown. In the drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Additionally, in the accompanying drawings, the thicknesses of some layers and regions are enlarged for better understanding and ease of description.

[0046] As used herein, the singular forms “a,” “one,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0047] It will be further understood that, when used in this specification, the terms “includes” and / or “comprises” indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0048] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0049] Furthermore, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure".

[0050] It will be understood that when an element is referred to as being "on" another element, "connected to" or "coupled to" another element, it can be directly on, directly connected to or coupled to the other element, or there may be one or more intermediate elements. When an element is referred to as being "directly on" another element, "directly connected to" or "directly coupled to" another element, there are no intermediate elements.

[0051] As used herein, the terms “substantially,” “approximately,” and similar terms are used as terms of approximation rather than terms of degree, and are intended to describe the inherent bias of measured or calculated values ​​that would be readily accepted by one of ordinary skill in the art.

[0052] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly on" another element, there are no intermediate elements present. Furthermore, throughout the specification, the phrase "on" the target element will be understood as being located above or below the target element, and may not necessarily be based on being located "on the upper side" in a direction opposite to the direction of gravity.

[0053] Furthermore, throughout the instruction manual, the phrase "on a cross section" or "cross-sectional view" refers to observing a cross-sectional view formed on a plane that cuts through the target object.

[0054] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms, such as those defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0055] In the following text, reference will be made to Figure 1 A light-emitting display device according to an exemplary embodiment is described.

[0056] Figure 1 This is a block diagram of a light-emitting display device according to an exemplary embodiment.

[0057] A light-emitting display device according to an exemplary embodiment includes a display panel comprising a flexible substrate such as polyimide (PI) or a film, and thus possessing bendable properties. In one or more embodiments, the display panel may have a curved structure or may be both foldable and non-foldable. Additionally, the display panel may be divided (e.g., broadly divided) into a display area 300 and a non-display area.

[0058] Multiple pixels PX are formed in the display area 300, and various suitable drivers for driving the pixels PX are provided in the non-display area. Figure 1 In the display area 300, scan drivers 410 and 420 are respectively arranged in pairs on the right and left sides, and light-emitting drivers 510 and 520 are respectively arranged in pairs on the right and left sides, respectively. In one or more embodiments, a data driver for applying a data voltage to the pixel PX is also provided in the non-display area. Additionally, voltages such as driving voltage, driving low voltage, and / or initialization voltage can be applied to the pixel PX.

[0059] Multiple pixels PX are arranged in the display area 300 along the column direction and the row direction. In one or more embodiments, the pixels PX of the light-emitting display device include a pixel circuit portion formed on a substrate and a light-emitting element portion formed on the pixel circuit portion.

[0060] The light-emitting element portion includes a light-emitting diode (LED) and receives current from the pixel circuit portion. In one or more embodiments, the light-emitting element portion emits light having a brightness level that varies according to the current intensity (e.g., the magnitude or amount of current supplied to the LED). Here, the LED may include an organic emitting layer or an inorganic emitting layer.

[0061] The reference pixel circuit section shows a portion with Figure 1 The pixel PX shown is quadrilateral in shape. The pixel circuitry includes multiple transistors and capacitors, and is connected to scan line 121, previous scan line 123, and light-emitting signal line 151. The multiple transistors according to this exemplary embodiment may include polycrystalline semiconductors. The pixel circuitry is formed in a quadrilateral shape and arranged in a matrix format in the row and column directions. The light-emitting element portion may have a quadrilateral shape such as a rhombus, or may have a shape other than a quadrilateral, and the arrangement may also be configured in various suitable structures.

[0062] Pixel PX is connected to scan line 121, previous scan line 123, and light-emitting signal line 151. Scan line 121, previous scan line 123, and light-emitting signal line 151 extend in a first direction (e.g., row direction). In one or more embodiments, pixel PX is connected to a data line that transmits data voltage from a data driver to pixel PX. The data line extends in a direction perpendicular to the first direction (e.g., column direction).

[0063] The non-display area is the peripheral area of ​​the display area 300. In one or more embodiments, scan drivers 410 and 420 are respectively disposed on the right and left sides of the display area 300 in the non-display area, and light-emitting drivers 510 and 520 are respectively disposed on the right and left sides of the display area 300 in the non-display area. Scan drivers 410 and 420 are disposed near the display area 300 in the non-display area, and light-emitting drivers 510 and 520 are disposed outside the scan drivers 410 and 420. For example, each of the light-emitting drivers 510 and 520 may be farther from the display area 300 than each of the scan drivers 410 and 420.

[0064] The scan drivers 410 and 420 include a first scan driver 410 disposed on the right side of the display area 300 and a second scan driver 420 disposed on the left side of the display area 300.

[0065] Each of scan drivers 410 and 420 includes multiple scan signal stages GD. Each scan signal stage GD generates and outputs a gate signal, and transmits the output gate signal to the pixels included in the current pixel row via scan line 121, and applies the output gate signal to the pixels PX included in the next pixel row via the previous scan line 123. Additionally, each scan signal stage GD applies the gate signal as a carry signal to the next scan signal stage GD. A scan line 121 and a previous scan line 123 can receive the same gate signal from both the first scan driver 410 and the second scan driver 420. Gate on-voltage and gate off-voltage of the gate signal are applied alternately, and at least one gate on-voltage is included during a frame. Depending on the exemplary embodiment, the gate on-voltage and gate off-voltage may be applied multiple times (i.e., more than once) during a frame.

[0066] Scan drivers 410 and 420 may further include a 0th scan signal stage GD[0] to apply a gate signal to the preceding scan line 123 of the pixel PX connected to the first pixel row.

[0067] Light-emitting drivers 510 and 520 are located outside of scan drivers 410 and 420. The first light-emitting driver 510 is located on the right side of the display area 300, and the second light-emitting driver 520 is located on the left side of the display area 300.

[0068] Each of the light-emitting drivers 510 and 520 includes multiple light-emitting signal levels (EMs). A light-emitting signal line 151 is connected to only one corresponding light-emitting signal level EM and receives a light-emitting signal from that EM. Therefore, in the second light-emitting driver 520, there may not be a light-emitting signal level EM corresponding to the light-emitting signal line 151 controlled by the light-emitting signal level EMs provided in the first light-emitting driver 510.

[0069] exist Figure 1 In an exemplary embodiment, a light emission signal output from a light emission signal level EM can be simultaneously (e.g., concurrently) applied to pixels PX in two pixel rows. That is, in Figure 1 The emission signal levels labeled EM[1,2] indicate that emission signals are applied simultaneously (e.g., concurrently) to the first pixel row and the second pixel row. However, according to an exemplary embodiment, the emission signals may be applied to only one pixel row, or simultaneously (e.g., concurrently) to three or more pixel rows. That is, an emission signal level EM may be connected to n emission signal lines 151 and apply emission signals simultaneously (e.g., concurrently) to pixels PX included in n pixel rows. Here, n is a natural number of 1 or greater.

[0070] When a light emission signal is applied, a low-level voltage (corresponding to a light emission period) and a high-level voltage (corresponding to a write period) are applied alternately. A frame contains one high-level voltage portion (write period). Furthermore, the light emission period and write period, distinguished by the light emission signal, are longer than the sustain period (also referred to as 1H) of the gate on-state voltage applied to a pixel PX. Due to this characteristic, the light emission signal can be applied simultaneously (e.g., concurrently) to multiple light emission signal lines 151. However, the gate on-state voltage sustains a very short 1H period, and therefore for each scan signal level GD, the gate signal is applied only to one scan line 121 and one previous scan line 123.

[0071] Additionally, light-emitting signal levels (EMs) can be formed in corresponding light-emitting drivers 510 and 520. In one or more embodiments, two adjacent light-emitting signal levels (EMs) can be located in the same light-emitting drivers 510 and 520. However, depending on the exemplary embodiment, the light-emitting signal levels (EMs) can be alternately located on opposite sides. For example, consecutive light-emitting signal levels can be alternately formed in the respective light-emitting drivers, such that two adjacent or consecutive light-emitting signal levels are not located in the same light-emitting driver.

[0072] In addition, Figure 1 In an exemplary embodiment, scan drivers 410 and 420 are formed on opposite sides of the display area 300, and light-emitting drivers 510 and 520 are formed on opposite sides of the display area 300. However, according to an exemplary embodiment, scan drivers 410 and 420 may be formed on only one side of the display area 300, and light-emitting drivers 510 and 520 may be formed on only one side of the display area 300.

[0073] Furthermore, during the process of forming the transistors and light-emitting diodes included in the pixels PX in the display area 300, the scan drivers 410 and 420 and the light-emitting drivers 510 and 520 are formed together. That is, the scan drivers 410 and 420 and the light-emitting drivers 510 and 520 are formed by the same process as the pixels PX in the display panel and have the same layers, and the scan drivers 410 and 420 and the light-emitting drivers 510 and 520 include transistors comprising polysilicon semiconductors as semiconductors.

[0074] Reference Figure 2 A more detailed description Figure 1 The connection structure of the light-emitting drivers 510 and 520.

[0075] Figure 2 This is a block diagram of a light-emitting driver according to an exemplary embodiment.

[0076] Figure 2Multiple light-emitting signal levels (EMs) located in the first light-emitting driver 510 and the second light-emitting driver 520 are shown. Additionally, as... Figure 1 As shown, in Figure 2 In an exemplary embodiment, two light-emitting signal lines 151 are connected to each light-emitting signal level EM.

[0077] The respective light emission signal stages EM of the light emission drivers 510 and 520 include: a first clock input terminal In1 and a second clock input terminal In2 that receive two clock signals respectively, a control terminal ACL_FLM that receives the control signal FLM or the light emission signal of the previous stage, and an output terminal Out that outputs the light emission signal.

[0078] The connection relationships of each emitting signal level (EM) will now be described.

[0079] The light emission level EM[1,2] (hereinafter also referred to as the first light emission level) that applies the light emission signal to the first light emission signal line EM line 1 and the second light emission signal line EM line 2 is set in the first light emission driver 510 located on the right side of the display area 300. Pixels PX connected to the first pixel row and the second pixel row receive the light emission signal through the first light emission level EM[1,2]. Therefore, all pixels PX connected to the first pixel row and the second pixel row have light emission cycles and write cycles in the same or substantially the same timing sequence, and emit light simultaneously (e.g., concurrently) when the light emission cycle begins.

[0080] In the first light-emitting signal level EM[1,2], the control signal FLM is applied to the control terminal ACL_FLM from the outside, the first clock signal EM_CLK1 is applied to the first clock input terminal In1, and the second clock signal EM_CLK2 is applied to the second clock input terminal In2. In addition, the light-emitting signal is applied to the first light-emitting signal line EM line 1 and the second light-emitting signal line EM line 2 through the output terminal Out.

[0081] Meanwhile, the light emission signal output from the first light emission signal level EM[1,2] is transmitted as a carry signal to the second light emission driver 520, and then applied to the control terminal ACL_FLM of the next light emission signal level EM[3,4].

[0082] The light emission level EM[3,4] (also referred to as the second light emission level) that applies the light emission signal to the third light emission signal line EM line 3 and the fourth light emission signal line EM line 4 is set in the second light emission driver 520 located on the left side of the display area 300. The light emission signal is applied to the pixels PX connected to the third pixel line and the fourth pixel line through the second light emission level EM[3,4]. Therefore, all pixels PX connected to the third pixel line and the fourth pixel line have light emission cycles and write cycles in the same or substantially the same timing sequence, and emit light simultaneously (e.g., concurrently) when the light emission cycle begins.

[0083] The light emission signal, acting as a carry signal, is applied from the first light emission signal level EM[1,2] to the second light emission signal level EM[3,4] and then to the control terminal ACL_FLM. The second clock signal EM_CLK2 is applied to the first clock input terminal In1, and the first clock signal EM_CLK1 is applied to the second clock input terminal In2. In addition, the light emission signal is applied to the third light emission signal line EM line 3 and the fourth light emission signal line EM line 4 through the output terminal Out.

[0084] Meanwhile, the light emission signal output from the second light emission signal level EM[3,4] is applied to the control terminal ACL_FLM of the third light emission signal level EM[5,6] in the second light emission driver 520 as a carry signal.

[0085] The light emission level EM[5,6] (also called the third light emission level) that applies the light emission signal to the fifth light emission signal line EM line 5 and the sixth light emission signal line EM line 6 is located below the second light emission level EM[3,4] in the second light emission driver 520 located on the left side of the display area 300. That is, two adjacent light emission levels are located in the same light emission driver. The third light emission level EM[5,6] applies the light emission signal to the pixels PX connected to the fifth pixel line and the sixth pixel line. Therefore, all pixels PX connected to the fifth pixel line and the sixth pixel line have light emission cycles and write cycles in the same or substantially the same timing sequence, and emit light simultaneously (e.g., concurrently) at the beginning of the light emission cycle.

[0086] The third light-emitting signal level EM[5,6] receives the light-emitting signal from the second light-emitting signal level EM[3,4] via the control terminal ACL_FLM as a carry signal. The first clock signal EM_CLK1 is applied to the first clock input terminal In1, and the second clock signal EM_CLK2 is applied to the second clock input terminal In2. In addition, the light-emitting signal is applied to the fifth light-emitting signal line EM line 5 and the sixth light-emitting signal line EM line 6 via the output terminal Out.

[0087] Meanwhile, the light emission signal output from the third light emission signal level EM[5,6] is applied to the control terminal ACL_FLM of the fourth light emission signal level EM[7,8] in the first light emission driver 510 as a carry signal.

[0088] The light emission level EM[7,8] (hereinafter referred to as the fourth light emission level) that applies light emission signals to the seventh light emission signal line EM line 7 and the eighth light emission signal line EM line 8 is located in the first light emission driver 510 located on the right side of the display area 300, below the first light emission level EM[1,2]. Light emission signals are applied to the pixels connected to the seventh and eighth pixel rows via the fourth light emission level EM[7,8] (i.e., the pixels connected to the seventh and eighth pixel rows receive light emission signals via the fourth light emission level EM[7,8]). Therefore, all pixels PX connected to the seventh and eighth pixel rows have light emission and write cycles in the same or substantially the same timing sequence, and emit light simultaneously (e.g., concurrently) at the beginning of the light emission cycle.

[0089] The fourth light-emitting signal level EM[7,8] receives the light-emitting signal from the third light-emitting signal level EM[5,6] as a carry signal through the control terminal ACL_FLM. The second clock signal EM_CLK2 is applied to the first clock input terminal In1, and the first clock signal EM_CLK1 is applied to the second clock input terminal In2. In addition, the light-emitting signal is applied to the seventh light-emitting signal line EM line 7 and the eighth light-emitting signal line EM line 8 through the output terminal Out.

[0090] Meanwhile, the light emission signal output from the fourth light emission signal level EM[7,8] is applied as a carry signal to the control terminal ACL_FLM of the fifth light emission signal level EM[9,10] in the first light emission driver 510.

[0091] The light emission signal level EM[9,10] (hereinafter also referred to as the fifth light emission signal level) that applies the light emission signal to the ninth light emission signal line EM line 9 and the tenth light emission signal line EM line 10 is located in the first light emission driver 510 located on the right side of the display area 300, and is located below the fourth light emission signal level EM[7,8]. That is, the two adjacent light emission signal levels are located in the same light emission driver.

[0092] The fifth emission signal level EM[9,10] applies an emission signal to the pixels PX connected to the ninth and tenth pixel rows. Therefore, all pixels PX connected to the ninth and tenth pixel rows have emission and write cycles in the same or substantially the same timing, and emit light simultaneously (e.g., concurrently) at the beginning of the emission cycle.

[0093] The control terminal ACL_FLM applies the light emission signal from the fourth light emission signal level EM[7,8] as a carry signal to the fifth light emission signal level EM[9,10]. The first clock signal EM_CLK1 is applied to the first clock input terminal In1, and the second clock signal EM_CLK2 is applied to the second clock input terminal In2. Additionally, the light emission signal is applied to the ninth light emission signal line EM line9 and the tenth light emission signal line EM line 10 through the output terminal Out.

[0094] Meanwhile, the light emission signal output from the fifth light emission signal level EM[9,10] is applied as a carry signal to the control terminal ACL_FLM of the sixth light emission signal level in the second light emission driver 520.

[0095] In the same manner as described above, light emission signal levels EM are formed in the first light emission driver 510 and the second light emission driver 520, and pixels PX in two pixel rows of each light emission signal level EM emit light.

[0096] According to an exemplary embodiment, an EM (Emitting Signal Level) can be connected to any suitable number of pixel rows. For example, an EM can be connected to three or more pixel rows, or an EM can be connected to a single pixel row.

[0097] In this exemplary embodiment, two light-emitting signal level EMs (e.g., two adjacent or consecutive light-emitting signal level EMs) are continuously positioned in one light-emitting driver 510 or 520. However, according to the exemplary embodiment, an even number of light-emitting signal level EMs (e.g., four or six light-emitting signal level EMs) may be continuously formed in one of the light-emitting drivers 510 or 520. Additionally, according to the exemplary embodiment, a light-emitting signal level EM may be alternately arranged in the light-emitting drivers 510 and 520 on both sides. For example, consecutive light-emitting signal level EMs may be alternately formed in the corresponding light-emitting drivers 510 and 520, such that two adjacent or consecutive light-emitting signal level EMs are not located in the same light-emitting driver 510 or 520.

[0098] As described above, when an even number of light-emitting signal levels EM are formed in a light-emitting driver 510 or 520, two pairs of clock signal wirings 171 and 172, as well as 171-1 and 172-1, which apply two clock signals EM_CLK1 and EM_CLK2, are alternately connected to the first clock input terminal In1 and the second clock input terminal In2 of the light-emitting signal level EM.

[0099] In other words, reference Figure 2In the two clock signal wirings 171 and 172 located on the left side of the display area 300, in the second light-emitting signal level EM[3,4], the first clock signal wiring 171 is connected to the second clock input terminal In2, and the second clock signal wiring 172 is connected to the first clock input terminal In1. However, in the third light-emitting signal level EM[5,6] located below the second light-emitting signal level EM[3,4], the first clock signal wiring 171 is connected to the first clock input terminal In1, and the second clock signal wiring 172 is connected to the second clock input terminal In2. Therefore, even when the two clock input terminals In1 and In2 of the light-emitting signal level EM have significantly different capacitance values, no load difference will occur between the two clock signal wirings 171 and 172 located on the left side of the display area 300.

[0100] As a result, even when static electricity flows from the outside, it will not be transmitted solely through specific wiring, and therefore, the specific input side of the luminous signal level EM will not be damaged by static electricity. Furthermore, there will be no delay in the specific clock signal due to the load difference between the two clock signal wirings 171 and 172.

[0101] Figure 3 This is a circuit diagram of one stage of a light-emitting driver according to an exemplary embodiment.

[0102] Each light-emitting signal level (EM) included in the light-emitting drivers 510 and 520 of this exemplary embodiment includes a high-level output section 551, a low-level output section 552, a first node-first controller 553, a first node-second controller 554, a second node-first controller 555, a second node-second controller 556, and a third node controller 557. Here, the first node-first controller 553 and the first node-second controller 554 can be referred to as the first node controller, and the second node-first controller 555 and the second node-second controller 556 can be referred to as the second node controller.

[0103] The high-level output section 551 outputs a high voltage VGH for the light emission signal, while the low-level output section 552 outputs a low voltage VGL for the light emission signal. Both the high-level output section 551 and the low-level output section 552 are connected to the output terminal Out. When the high-level output section 551 outputs a high voltage VGH, the low-level output section 552 has no output; conversely, when the low-level output section 552 outputs a low voltage VGL, the high-level output section 551 has no output.

[0104] The high-level output section 551 is controlled according to the voltage of the first node N1, and the voltage of the first node N1 is controlled by the first node_first controller 553 and the first node_second controller 554.

[0105] The low-level output section 552 is controlled based on the voltage of the second node N2, and the voltage of the second node N2 is controlled by the second node_first controller 555 and the second node_second controller 556. Figure 3 In the middle, the second node_first controller 555 is divided into (or includes) the first second node_first controller 555-1 and the second second node_first controller 555-2.

[0106] The first node_second controller 554 is controlled by the voltage of the third node N3, and the voltage of the third node N3 is controlled by the third node controller 557.

[0107] exist Figure 3 In the luminous signal level EM, such as Figure 2 Similar to the odd-numbered LED signal levels EM, the first clock signal wiring 171 is connected to the first clock input terminal In1 and thereby applies the first clock signal EM_CLK1, and the second clock signal wiring 172 is connected to the second clock input terminal In2 and thereby applies the second clock signal EM_CLK1. However, the even-numbered LED signal levels EM can be applied with a clock signal that is opposite to the clock signal applied to the odd-numbered LED signal levels EM.

[0108] The details of each part are as follows.

[0109] The high-level output section 551 includes a sixth transistor T6. The control electrode of the sixth transistor T6 is connected to the first node N1, the input electrode of the sixth transistor T6 is connected to the high voltage VGH terminal, and the output electrode of the sixth transistor T6 is connected to the output terminal Out. Therefore, when the voltage of the first node N1 is low, the high voltage VGH is output to the output terminal Out, and when the voltage of the first node N1 is high, the sixth transistor T6 does not output anything.

[0110] The low-level output section 552 includes a seventh transistor T7, whose control electrode is connected to the second node N2, whose input electrode is connected to the low voltage VGL terminal, and whose output electrode is connected to the output terminal Out. Therefore, when the voltage at the second node N2 is low, the low voltage VGL is output to the output terminal Out, and when the voltage at the second node N2 is high, the seventh transistor T7 outputs nothing (e.g., the low voltage VGL is not output to the output terminal Out).

[0111] The voltage of the first node N1 is controlled by the first node_first controller 553 and the first node_second controller 554.

[0112] The first node_first controller 553 includes a transistor (e.g., an eighth transistor T8) and a capacitor (e.g., a first capacitor C1). The control electrode of the eighth transistor T8 is connected to the second node N2, the input electrode of the eighth transistor T8 is connected to the high voltage VGH terminal, and the output electrode of the eighth transistor T8 is connected to the first node N1. Simultaneously, the two electrodes of the first capacitor C1 are connected to the input and output electrodes of the eighth transistor T8, respectively, and thus, the first capacitor C1 is connected between the first node N1 and the high voltage VGH terminal. When the voltage of the second node N2 is low, the eighth transistor T8 transmits the high voltage VGH to the first node N1, and the first capacitor C1 stores and maintains the voltage of the first node N1. That is, the first node_first controller 553 is used to change the voltage of the first node N1 to the high voltage VGH.

[0113] Simultaneously, the first node_second controller 554 includes two transistors (e.g., a ninth transistor T9 and a tenth transistor T10) and a capacitor (e.g., a second capacitor C2). The control electrode of the ninth transistor T9 is connected to the first clock input terminal In1, the output electrode of the ninth transistor T9 is connected to the first node N1, and the input electrode of the ninth transistor T9 is connected to the fourth node N4. The control electrode of the tenth transistor T10 is connected to the third node N3, the output electrode of the tenth transistor T10 is connected to the fourth node N4, and the input electrode of the tenth transistor T10 is connected to the first clock input terminal In1. Here, depending on the magnitude of the connected voltage, the input and output electrodes can have opposite inputs and outputs. The first node_second controller 554 is used to change the voltage of the first node N1 to a low voltage of the clock signal.

[0114] Meanwhile, the second capacitor C2 is connected between the third node N3 and the fourth node N4, and the voltage of the fourth node N4 can be increased by utilizing the voltage difference between the two nodes N3 and N4.

[0115] The voltage of the second node N2 is controlled by the second node_first controller 555 and the second node_second controller 556.

[0116] The second node_first controller 555 is formed by the first second node_first controller 555-1 and the second second node_first controller 555-2. The first second node_first controller 555-1 is formed by a transistor (e.g., first transistor T1), and the second second node_first controller 555-2 is formed by a capacitor (e.g., third capacitor C3). The control electrode of the first transistor T1 is connected to the second clock input terminal In2, the input electrode of the first transistor T1 is connected to the control terminal ACL_FLM, and the output electrode of the first transistor T1 is connected to the second node N2. One electrode of the third capacitor C3 is connected to the second node N2, and the other electrode is connected to the first clock input terminal In1.

[0117] Due to the structure of the third capacitor C3, the voltage at the second node N2 will also change due to the variable clock signal applied to the first clock input terminal In1. Therefore, the capacitance of the third capacitor C3 can be set to a very high value to reduce the fluctuation of the second node N2. Thus, even if the clock signal applied to one electrode of the third capacitor C3 changes, the voltage at the other electrode of the third capacitor C3, i.e., the voltage at the second node N2, will not change significantly. Because of the third capacitor C3, the capacitance at the first clock input terminal In1 has a very high value compared to the capacitance at the second clock input terminal In2.

[0118] When the third clock signal EM_CLK3 is applied to the second clock input terminal In2 (see...) Figure 4 When the voltage is low, the first transistor T1 included in the second node_first controller 555 changes the voltage of the second node N2 to the voltage of the control signal FLM or light emission signal of the previous stage, and the third capacitor C3 stores and maintains the voltage. That is, the second node_first controller 555 is used to change the voltage of the second node N2 to a high voltage or a low voltage according to the carry signal (e.g., the control signal FLM or light emission signal of the previous stage).

[0119] The second node / second controller 556 is formed by two transistors (e.g., second transistor T2 and third transistor T3). The control electrode of the second transistor T2 is connected to the third node N3, the input electrode of the second transistor T2 is connected to the high voltage VGH terminal, and the output electrode of the second transistor T2 is connected to the input electrode of the third transistor T3. The control electrode of the third transistor T3 is connected to the first clock input terminal In1, the input electrode of the third transistor T3 is connected to the output electrode of the second transistor T2, and the output electrode of the third transistor T3 is connected to the second node N2. That is, the second node / second controller 556 prevents or substantially prevents the high voltage VGH from being connected to the second node N2, so that the voltage of the second node N2 does not change to a low voltage.

[0120] The third node controller 557 is formed by two transistors (e.g., a fourth transistor T4 and a fifth transistor T5). The control terminal of the fourth transistor T4 is connected to the second node N2, the input terminal of the fourth transistor T4 is connected to the second clock input terminal In2, and the output terminal of the fourth transistor T4 is connected to the third node N3. The control electrode of the fifth transistor T5 is connected to the second clock input terminal In2, the input terminal of the fifth transistor T5 is connected to the low voltage VGL terminal, and the output terminal of the fifth transistor T5 is connected to the third node N3. The fifth transistor T5 is used to make the voltage of the third node N3 low voltage VGL, and the fourth transistor T4 makes the voltage of the third node N3 the voltage of the second clock input terminal In2, thereby changing the voltage of the third node N3 to a high voltage (e.g., the high voltage of the clock signal).

[0121] Based on the signals applied to the first clock input In1, the second clock input In2, and the control terminal ACL_FLM, the luminous signal level EM with this configuration is determined, and this will be referenced. Figure 4 A more detailed description.

[0122] Figure 4 It is a waveform diagram of the signal applied to the stage according to an exemplary embodiment and the emission signal according to the signal.

[0123] First, refer to Figure 4 The signals applied to the first clock input In1, the second clock input In2, and the control terminal ACL_FLM of the light-emitting signal level EM are described in more detail.

[0124] In this exemplary embodiment, a first clock signal EM_CLK1 is applied to a first clock input terminal In1, and a third clock signal EM_CLK3 is applied to a second clock input terminal In2. The first clock signal EM_CLK1 and the third clock signal EM_CLK3 are clock signals that repeat between high and low voltages and have opposite phase characteristics. For example, when a low-voltage third clock signal EM_CLK3 is applied, a high-voltage first clock signal EM_CLK1 is applied, and vice versa.

[0125] Simultaneously, the externally applied control signal FLM is transmitted as a carry signal to the control terminal ACL_FLM of the first emission signal level EM[1,2], and the output signal of the previous emission signal level, i.e., the emission signal, is transmitted as a carry signal to the second emission signal level EM[3,4]. The control signal FLM and the emission signal have a high voltage portion during a frame, and are applied as low voltages for the remainder of the frame. The high voltage portion is the portion where the data voltage is applied to the pixel PX, and the pixel PX emits light during the low voltage portion (e.g., the emission period).

[0126] exist Figure 4 In the process, for each stage, the voltage applied to the light-emitting signal stage EM is divided into (a), (b), (c), (d), (e), and (f), and the operation of each part is as follows.

[0127] First, the operation of the luminous signal level EM in section (a) will be described.

[0128] In part (a), a low voltage is applied to the control signal FLM, a high voltage first clock signal EM_CLK1 is applied to the first clock input In1, and a low voltage third clock signal EM_CLK3 is applied to the second clock input In2. The third transistor T3 and the ninth transistor T9 are turned off due to the high voltage first clock signal EM_CLK1, and the first transistor T1 and the fifth transistor T5 are turned on due to the low voltage third clock signal EM_CLK3.

[0129] A low-voltage control signal FLM is applied to the second node N2 through the first transistor T1, and thus the low voltage at the second node N2 is stored in the third capacitor C3. The seventh transistor T7 is turned on due to the low voltage at the second node N2, and thus the low voltage VGL is output to the output terminal Out. Additionally, the eighth transistor T8 is turned on due to the low voltage at the second node N2, and thus the first node N1 becomes a high voltage VGH, and the opposite terminal of the first capacitor C1 becomes a high voltage VGH. Therefore, the sixth transistor T6 is turned off.

[0130] Additionally, the fourth transistor T4 is turned on by the low voltage of the second node N2, and thus applies a low voltage value to the third clock signal EM_CLK3, causing the voltage of the third node N3 to be low. Furthermore, a low voltage VGL is applied through the fifth transistor T5.

[0131] The tenth transistor T10 is turned on due to the low voltage VGL of the third node N3, and therefore the high voltage first clock signal EM_CLK1 is applied to the fourth node N4. Thus, the high voltage (e.g., applied to the fourth node N4) and the low voltage (e.g., applied to the third node N3) are applied to the opposite ends of the capacitor C2.

[0132] In addition, the second transistor T2 is turned on due to the low voltage VGL of the third node N3, but the third transistor T3 is turned off, and therefore the high voltage VGH is not transmitted to the second node N2 but only to the input electrode of the third transistor T3.

[0133] In summary, in part (a), the first node N1 has a high voltage, the second node N2 has a low voltage, the third node N3 has a low voltage, the fourth node N4 has a high voltage, and as the main operation, the seventh transistor T7 is turned on by the low voltage of the second node N2, and thus a low voltage VGL is applied to the output terminal Out.

[0134] The operation of the luminous signal level EM in section (b) will be described below.

[0135] In part (b), the control signal FLM remains unchanged, the first clock signal EM_CLK1 goes low and is then applied to the first clock input In1, and the third clock signal EM_CLK3 goes high and is then applied to the second clock input In2. The third transistor T3 and the ninth transistor T9 are turned on by the low-voltage first clock signal EM_CLK1, and the first transistor T1 and the fifth transistor T5 are turned off by the high-voltage third clock signal EM_CLK3.

[0136] Because the first transistor T1 is in the off state, the low voltage stored in the third capacitor C3 remains unchanged, thus keeping the voltage at the second node N2 low. Therefore, the seventh transistor T7 remains continuously on, causing the low voltage VGL to be output to the output terminal Out.

[0137] In addition, the eighth transistor T8 is also turned on due to the low voltage of the second node N2, and thus the first node N1 becomes a high voltage VGH, the sixth transistor T6 remains in the off state, and the opposite end of the first capacitor C1 becomes a high voltage VGH.

[0138] Furthermore, the fourth transistor T4 is turned on due to the low voltage of the second node N2, and therefore the high-voltage third clock signal EM_CLK3 is applied to the third node N3, causing the voltage of the third node N3 to become high. In this case, because the fifth transistor T5 is turned off, the third node N3 becomes high-voltage due to the fourth transistor T4.

[0139] The tenth transistor T10 is turned off due to the high voltage at the third node N3, and the ninth transistor T9 is turned on due to the low voltage of the first clock signal EM_CLK1, connecting the first node N1 and the fourth node N4. In this situation, the voltage at the third node N3, connected to the second capacitor C2, changes from low to high, and therefore the voltages at the fourth node N4 and the first node N1 connected to the fourth node N4 increase (e.g., boost to a high voltage). Thus, the voltage at the first node N1 can have a value higher than the high voltage VGH. Simultaneously, due to the high voltage at the third node N3, the second transistor T2 remains off, and the third transistor T3 is turned on by the low voltage of the first clock signal EM_CLK1.

[0140] In summary, in part (b), the first node N1 and the fourth node N4 are given a boosted high voltage, the second node N2 is given a low voltage, and the third node N3 is given a high voltage. As the main operation, the seventh transistor T7 is turned on due to the low voltage of the second node N2, so that the low voltage VGL is continuously applied to the output terminal Out.

[0141] Comparing parts (a) and (b), the clock signal is inverted and then applied, but the voltage of the first node N1 remains high and the voltage of the second node N2 remains low, so that the low voltage VGL is continuously output to the output terminal Out.

[0142] The operation of the luminescent signal level EM in section (c) will then be described.

[0143] In part (c), the control signal FLM goes high, the first clock signal EM_CLK1 goes high and is then applied to the first clock input In1, and the third clock signal EM_CLK3 goes low and is then applied to the second clock input In2.

[0144] The third transistor T3 and the ninth transistor T9 are turned off due to the high voltage of the first clock signal EM_CLK1, while the first transistor T1 and the fifth transistor T5 are turned on due to the low voltage of the third clock signal EM_CLK3. The high voltage control signal FLM is applied to the second node N2 through the first transistor T1, thus making the voltage of the second node N2 high and then stored in the third capacitor C3. The seventh transistor T7 is turned off due to the high voltage of the second node N2. Additionally, the eighth transistor T8 and the ninth transistor T9 are turned off due to the high voltage of the second node N2.

[0145] Simultaneously, because the fifth transistor T5 is turned on, a low voltage VGL is applied to the third node N3. In this situation, because the second node N2 has a high voltage, the fourth transistor T4 is turned off. Therefore, the voltage at the third node N3 is controlled by the fifth transistor T5 and becomes a low voltage VGL.

[0146] The second transistor T2 and the tenth transistor T10 are turned on by the low voltage of the third node N3. Because the tenth transistor T10 is turned on, the high voltage first clock signal EM_CLK1 is applied to the fourth node N4. Therefore, the high voltage (e.g., applied to the fourth node N4) and the low voltage (e.g., applied to the third node N3) are applied to the opposite ends of the second capacitor C2.

[0147] Because the ninth transistor T9 and the eighth transistor T8 are turned off, the voltage of the first node N1 is kept high by maintaining the voltage in section (b).

[0148] In summary, in part (c), a high voltage is applied to the first node N1, a high voltage is applied to the second node N2, a low voltage is applied to the third node N3, and a high voltage is applied to the fourth node N4. The seventh transistor T7 and the sixth transistor T6 are both in the off state and can therefore float without outputting a voltage to the output terminal Out. The low voltage VGL is output until the voltage of the second node N2 becomes the off voltage of the seventh transistor T7, and then the seventh transistor T7 is turned off and thus floated.

[0149] The operation of the luminous signal level EM in section (d) will be described below.

[0150] In part (d), the control signal FLM remains high, the first clock signal EM_CLK1 goes low and is then applied to the first clock input In1, and the third clock signal EM_CLK3 goes high and is then applied to the second clock input In2.

[0151] The third transistor T3 and the ninth transistor T9 are turned on by the low-voltage first clock signal EM_CLK1, while the first transistor T1 and the fifth transistor T5 are turned off by the high-voltage third clock signal EM_CLK3.

[0152] Because the first transistor T1 is in the off state, it maintains the high voltage stored in the third capacitor C3, resulting in a high voltage value at the second node N2. Therefore, the seventh transistor T7 remains in the off state. Additionally, the eighth transistor T8 and the fourth transistor T4 also remain in the off state due to the high voltage at the second node N2.

[0153] The fifth transistor T5 is turned off by the high-voltage third clock signal EM_CLK3. Because both the fourth transistor T4 and the fifth transistor T5 are turned off, the voltage of the third node N3 remains unchanged and remains low, which is the voltage of the third node N3 in part (c).

[0154] The tenth transistor T10 is kept on by the low voltage of the third node N3, and the ninth transistor T9 is turned on by the low voltage of the first clock signal EM_CLK1, thus connecting the first node N1, the fourth node N4, and the low voltage of the first clock signal EM_CLK1. Therefore, the voltages of the first node N1 and the fourth node N4 become low. The sixth transistor T6 is turned on by the low voltage of the first node N1, and therefore, the high voltage VGH is output to the output terminal Out.

[0155] Simultaneously, the second transistor T2 is turned on by the low voltage of the third node N3, and the third transistor T3 is also turned on by the low voltage of the first clock signal EM_CLK1, thus connecting the high voltage VGH terminal to the second node N2. Therefore, the voltage of the second node N2 remains at the high voltage VGH, and the seventh transistor T7 cannot be turned on.

[0156] In summary, in part (d), a low voltage is applied to the first node N1 and the fourth node N4, a high voltage is applied to the second node N2, and a low voltage is applied to the third node N3. As the main operation, the sixth transistor T6 is turned on by the low voltage of the first node N1, causing the high voltage VGH to be output to the output terminal Out. The pixel PX with the applied high voltage VGH can be in a write cycle, during which the data voltage is stored in the capacitor of the pixel PX.

[0157] The operation of the luminescent signal level EM in section (e) will be described below.

[0158] In part (e), the control signal FLM remains high, the first clock signal EM_CLK1 becomes high and is then applied to the first clock input In1, and the third clock signal EM_CLK3 becomes low and is then applied to the second clock input In2.

[0159] The third transistor T3 and the ninth transistor T9 are turned off due to the high voltage of the first clock signal EM_CLK1, while the first transistor T1 and the fifth transistor T5 are turned on due to the low voltage of the third clock signal EM_CLK3.

[0160] A high-voltage control signal is applied to the second node N2 through the first transistor T1, thus maintaining a high voltage at the second node N2. The seventh transistor T7 is turned off due to the high voltage at the second node N2. Additionally, the eighth transistor T8 and the fourth transistor T4 also remain off due to the high voltage at the second node N2.

[0161] The fifth transistor T5 is turned on, and therefore a low voltage VGL is applied to the third node N3. In this situation, the fourth transistor T4 is turned off, and therefore the fourth transistor T4 cannot change the voltage of the third node N3.

[0162] Because the third node N3 has a low voltage VGL, the second transistor T2 and the tenth transistor T10 are turned on. The tenth transistor T10 is turned on, and thus a high voltage, the first clock signal EM_CLK1, is applied to the fourth node N4. Therefore, a high voltage (e.g., applied to the fourth node N4) and a low voltage (e.g., applied to the third node N3) are applied to opposite ends of the second capacitor C2.

[0163] In addition, the second transistor T2 is turned on while the third transistor T3 is turned off, and therefore the high voltage VGH is only transmitted to the input electrode of the third transistor T3, and not to the second node N2.

[0164] Because the ninth transistor T9 is turned off due to the high voltage of the first clock signal EM_CLK1, the voltage stored in the first capacitor C1 remains unchanged, and the voltage of the first node N1 remains low. Therefore, the sixth transistor T6 turns on, causing the high voltage VGH to be continuously output to the output terminal Out.

[0165] In summary, in part (e), a low voltage is applied to the first node N1, a high voltage is applied to the second node N2, a low voltage is applied to the third node N3, and a high voltage is applied to the fourth node N4, while the sixth transistor T6 remains on, so that the high voltage VGH is continuously output to the output terminal Out.

[0166] Comparing parts (d) and (e), the clock signal is inverted and then applied, but the voltage of the first node N1 remains low, and therefore the high voltage VGH is continuously output to the output terminal Out. Additionally, the voltage of the second node N2 remains high, and therefore the low voltage VGL is not transmitted to the output terminal Out.

[0167] Parts (d) and (e) are repeated several times, and then part (f) begins as the control signal FLM goes low. Part (f) begins after a part has the same state as part (d).

[0168] The operation of the luminous signal level EM in section (f) will be described below.

[0169] In part (f), the control signal FLM goes low, the first clock signal EM_CLK1 goes high and is then applied to the first clock input In1, and the third clock signal EM_CLK3 goes low and is then applied to the second clock input In2.

[0170] The third transistor T3 and the ninth transistor T9 are turned off due to the high voltage of the first clock signal EM_CLK1, and the first transistor T1 and the fifth transistor T5 are turned on due to the low voltage of the third clock signal EM_CLK3.

[0171] A low-voltage control signal is applied to the second node N2 through the first transistor T1, causing the voltage at the second node N2 to become low, and the tenth transistor T10 turns on. Therefore, the low voltage VGL is output to the output terminal Out. Due to the low voltage at the second node N2, the eighth transistor T8 and the fourth transistor T4 are also turned on.

[0172] Because the eighth transistor T8 is turned on, a high voltage VGH is applied to the first node N1, and the sixth transistor T6 is turned off due to the high voltage at the first node N1, so the high voltage VGH is no longer output to the output terminal Out.

[0173] When the fourth transistor T4 is turned on, a low-voltage third clock signal EM_CLK3 is applied to the third node N3. Additionally, a low-voltage VGL is applied to the third node N3 through the turned-on fifth transistor T5. Therefore, the third node N3 has a low voltage.

[0174] The second transistor T2 and the tenth transistor T10 are turned on by the low voltage of the third node N3. The tenth transistor T10 is turned on, and therefore the high voltage of the first clock signal EM_CLK1 is applied to the fourth node N4. Thus, the high voltage (e.g., applied to the fourth node N4) and the low voltage (e.g., applied to the third node N3) are applied to the opposite ends of the second capacitor C2.

[0175] In addition, the second transistor T2 is turned on but the third transistor T3 is turned off, and therefore the high voltage VGH is only transmitted to the input electrode of the third transistor T3, and the high voltage VGH is not transmitted to the second node N2.

[0176] Because the ninth transistor T9 is turned off due to the high voltage of the first clock signal EM_CLK1, the voltage of the first node N1 is unaffected. Therefore, the voltage of the first node N1 is controlled by the eighth transistor T8, and the high voltage VGH is transmitted through the eighth transistor T8, thus keeping the voltage of the first node N1 high.

[0177] In summary, in part (f), a high voltage is applied to the first node N1, a low voltage is applied to the second node N2, a low voltage is applied to the third node N3, and a high voltage is applied to the fourth node N4. The sixth transistor T6 is turned off and the seventh transistor T7 is turned on, and thus the voltage at the output terminal Out changes from a high voltage VGH to a low voltage VGL and is then output.

[0178] Part (f) is followed by the part corresponding to part (b), and then the operation is repeated as described above.

[0179] Therefore, the output of the light emission signal stage is a light emission signal delayed by half a clock cycle from the control signal. That is, because the carry signal applied to the next light emission signal stage is delayed by half a clock cycle, the application timing of the high voltage VGH in the output light emission signal is also delayed by half a clock cycle.

[0180] In the following text, see references Figure 5 and Figure 6 This will describe the characteristics of each transistor included in the stage according to the comparison example.

[0181] First, refer to Figure 5 This will describe the characteristics of each transistor included in the stage of the light-emitting driver according to the comparative example.

[0182] Figure 5 A graph showing the simulation results of the characteristics of each transistor included in the stage of the light-emitting driver according to the comparative example is shown.

[0183] exist Figure 5 In the graph, the x-axis represents the gate-source voltage Vgs value, and the y-axis represents the output current Ids value.

[0184] It can be determined that most of the transistors included in the stage of the light-emitting driver according to the comparative example maintain a constant output current, but the second transistor T2 outputs a reduced output current.

[0185] To determine the reason for the decrease in output current of the second transistor T2, the characteristics of the second transistor T2 according to the comparative example were simulated, and the simulation results were... Figure 6 As shown in the image.

[0186] Figure 6 This is a waveform diagram showing the characteristics of the second transistor in the stage according to the comparison example.

[0187] exist Figure 6The diagram shows the gate-source voltage Vgs, drain-source voltage Vds, and output current (e.g., the output current of T2) to determine the voltage and output current in the second transistor T2 included in the stage of the light-emitting driver according to the comparative example. The diagram also shows the transmit signal output from the output terminal Out of the corresponding stage. Figure 6 The output current shown only indicates a change in intensity and is independent of direction.

[0188] refer to Figure 3 The gate-source voltage Vgs in the second transistor T2 has a value obtained by subtracting the high voltage VGH from the voltage of the third node N3, and the drain-source voltage Vds has a value obtained by subtracting the high voltage VGH from the voltage of the node where the third transistor T3 connects to the second transistor T2 (e.g., the node between the third transistor T3 and the second transistor T2).

[0189] exist Figure 6 In the text, part (g) and part (i) correspond to Figure 4 Parts (d), (h), and (j) in the text correspond to Figure 4 Part (e), and part (k) corresponds to Figure 4 Part (f).

[0190] As per the above reference Figure 4 As described above, a low voltage is applied to the third node N3 in parts (d), (e), and (f), but the level of this low voltage fluctuates due to the clock signal at its periphery. Therefore, Figure 6 The gate-source voltage Vgs and drain-source voltage Vds shown also have oscillating voltage levels.

[0191] In particular, Figure 6 In parts (h) and (j), the applied electric stress is further reduced as part of the gate-source voltage Vgs value of the second transistor T2, and a strong electric field is generated.

[0192] exist Figure 6 The diagram illustrates how the current of the second transistor T2 changes before and after the portions (h) and (j) where the gate-source voltage Vgs of the second transistor T2 decreases. Specifically, the output current changes when the gate-source voltage Vgs of the second transistor T2 further decreases, and when the gate-source voltage Vgs increases again. Figure 6 As shown, when the gate-source voltage Vgs of the second transistor T2 is further reduced, the output current value changes even more.

[0193] This change in the output current of the second transistor T2 occurs four times in each write cycle, and repeats in each write cycle, and therefore, as Figure 5 As shown, the output current of the second transistor T2 decreases overall as stress increases during long-term use.

[0194] The decrease in the output current of the second transistor T2 may cause problems for the light-emitting driver to provide a constant output.

[0195] As described, in Figure 6 The results showed that the output current of the second transistor T2 decreased due to electrical stress.

[0196] However, in the case of flexible display devices, mechanical stress exists when the channel layer is folded while the display device is folded or unfolded, or while it remains folded. Therefore, due to mechanical stress, the characteristics of the transistors may change when electrons or holes are located at specific positions in the semiconductor layer. Thus, the reduction in transistor output current due to mechanical stress may need to be considered.

[0197] Therefore, in this disclosure, the output current in at least one transistor included in the light-emitting driver suddenly changes due to at least one of the changes in the characteristics of the semiconductor layer caused by the compressive force generated when folding in the flexible display device (hereinafter referred to as mechanical stress) and the changes in the characteristics of the transistor caused by the accumulation of hot carriers due to the high level electric field in the transistor channel (hereinafter referred to as electrical stress).

[0198] As described, in order to overcome the output current problem in a transistor caused by mechanical or electrical stress, according to an exemplary embodiment, it includes, as described above... Figure 7 and Figure 8 The transistor shown is an asymmetric channel structure. In the following text, "asymmetric structure" may also be referred to as "asymmetric channel structure" or "asymmetric transistor structure".

[0199] Figure 7 This is a top view of an asymmetric structure of a transistor according to an exemplary embodiment, and Figure 8 It is a section taken along line VIII-VIII. Figure 7 Cross-sectional view.

[0200] exist Figure 7 and Figure 8 The diagram only shows the structure of the transistor, and illustrates a semiconductor layer formed of polycrystalline semiconductor and including a drain region D, a source region S, and a channel region C, as well as a gate electrode G overlapping the channel region C. Gate insulating layer 113 (as shown) Figure 8 (As shown in the figure) is disposed between the semiconductor layer and the gate electrode G.

[0201] First, refer to Figure 7 A more detailed description of the planar structure of the asymmetric channel structure in which the channel width is not uniform in the channel region C.

[0202] In the semiconductor layer of the transistor according to an exemplary embodiment, the source region S and the drain region D have approximately the same or identical widths (Ws = Wd), but the channel region C has a width different from that of the source region S and the drain region D. Furthermore, in the channel region C, the channel width W1 of the first region ① that contacts the source region S is wider than (i.e., greater than) the channel width W2 of the second region ② that contacts the drain region D.

[0203] The channel width W1 of the first region ① is wider than the widths Ws and Wd of the source region S and drain region D, respectively, and the channel width W2 of the second region ② is narrower than (i.e., less than) the widths Ws and Wd of the source region S and drain region D, respectively. Figure 7 In an exemplary embodiment, the first region ① and the second region ② are connected to each other (e.g., directly connected), causing the channel width at the periphery of the center of the channel region C to change abruptly. For example, the channel region C may include the first region ① and the second region ②, which are directly connected to each other, such that the first region ① and the second region ② form a T-shape. However, according to an exemplary embodiment, an intermediate region between the first region ① and the second region ② may be further included at the periphery of the center of the channel region C, and the intermediate region may have a channel width between the channel width W1 of the first region ① and the channel width W2 of the second region ② (i.e., the intermediate channel width) or a gradually changing channel width (e.g., a channel width that gradually changes from the channel width W1 of the first region ① to the channel width W2 of the second region ②).

[0204] In the semiconductor layer, the channel region C is a polycrystalline semiconductor layer that overlaps with the gate electrode G on a plane or in a planar diagram and may not be doped with impurities, and the source region S and the drain region D are polycrystalline layers and may have the same properties as conductors or have increased conductivity by doping (e.g., highly doped) with impurities.

[0205] exist Figure 7 In an exemplary embodiment, the semiconductor layer extends in a horizontal direction (e.g., a first direction) at the portion where the transistor is located, and the gate electrode G extends in a vertical direction (e.g., a second direction) that intersects the first direction at the portion where the transistor is located.

[0206] In the following text, reference will be made to Figure 8 A cross-sectional view describing the structure of a transistor in more detail.

[0207] According to an exemplary embodiment, the flexible display device includes a flexible substrate 110 formed of a flexible material such as a film or polyimide (PI).

[0208] Barrier layer 111 and buffer layer 112 may be disposed on flexible substrate 110. Barrier layer 111 and buffer layer 112 may include inorganic insulating materials such as silicon oxide, silicon nitride, and aluminum oxide, and according to exemplary embodiments, they may include organic insulating materials such as polyimide and polyacrylate (with added epoxy resin). When the subsequently formed semiconductor layer is crystallized, barrier layer 111 and buffer layer 112 serve to prevent or substantially prevent impurities from being supplied from flexible substrate 110 to semiconductor layer.

[0209] The semiconductor layer includes an undoped channel region C, a source region S, and a drain region D. The source region S and drain region D are doped on opposite sides of the channel region C. Figure 8 In the diagram, the source region S is not shown because, as Figure 7 As shown, line VIII-VIII does not intersect with the source region S. The semiconductor layer is formed of polycrystalline semiconductor, and after laminating amorphous silicon, the semiconductor layer is formed into a polycrystalline structure through a crystallization process. A doping process can be performed after forming the gate electrode G.

[0210] A gate insulating layer 113 is formed on the semiconductor layer, and a gate electrode G is formed on the gate insulating layer 113. Figure 8 In this embodiment, the gate insulating layer 113 completely covers the semiconductor layer; however, according to an exemplary embodiment, the gate insulating layer 113 may have the same width as the gate electrode G. When the gate insulating layer 113 and the gate electrode G have the same width, the drain region D and the source region S of the semiconductor layer are covered by the upper insulating layer 114. In one or more embodiments, the gate insulating layer 113 may cover the channel region C of the semiconductor layer, but not the drain region D and the source region S of the semiconductor layer. The gate insulating layer 113 may comprise an inorganic insulating material such as silicon oxide, silicon nitride, and / or aluminum oxide.

[0211] When a semiconductor layer is doped using a gate electrode G as a mask, a channel region C is formed in a portion of the semiconductor, overlapping the gate electrode G in the thickness direction (e.g., a third direction perpendicular to the first and second directions) or in a plan view and thus remaining undoped, and a doped source region S and a doped drain region D are disposed on opposite sides of the channel region C.

[0212] An upper insulating layer 114 is disposed on and covers the gate electrode G and the gate insulating layer 113. The upper insulating layer 114 may include an inorganic insulating material, such as silicon oxide, silicon nitride, and / or aluminum oxide.

[0213] Additional wiring and an insulating layer may be formed on the upper insulating layer 114. As a representative structure, it may include source and drain electrodes connected (e.g., electrically connected) to the source region S and the drain region D, and light-emitting diodes may also be formed in the display area 300.

[0214] In this exemplary embodiment, having Figure 7 and Figure 8 The transistor structure is formed as a second transistor T2 included in the stage of the light-emitting driver to prevent or substantially prevent a decrease in output current due to electrical and mechanical stress.

[0215] Specifically, will refer to Figures 9 to 14 A more detailed description based on Figure 7 and Figure 8 Features of a transistor in an exemplary embodiment.

[0216] In the following text, Figure 7 and Figure 8 The structural features shown are similar to Figure 9 Comparative examples are used to illustrate the improvements in electrical and mechanical stress. Figure 7 and Figure 8 The structural characteristics.

[0217] Figure 9 It is a top view of the transistor in the comparative example, and Figure 10 This is a top view of an asymmetric structure of a transistor according to an exemplary embodiment, to describe from Figure 7 Does the output current generated by the transistor in the exemplary embodiment decrease?

[0218] Figure 9 The diagram illustrates a structure comprising a semiconductor layer of constant width, based on a comparative example. Figure 10 It shows something similar to Figure 7 Asymmetric channel structure with planar structure.

[0219] exist Figure 9 and Figure 10 In this context, the portion of holes captured is denoted as H, and the portion of electrons captured is denoted as M.

[0220] Here, the hole-collecting trapping portion H is adjacent to the drain region D, and the size of the transverse electric field (e.g., reference) varies with the size of the transverse electric field. Figure 12 As the electrical stress increases, the amount of holes collected also increases. The more accumulated electrical stress, the more holes are collected. In addition, the hole-trapping portion H has the following characteristics: structurally, as the boundary of the semiconductor layer increases, the electric field in the horizontal direction disperses and decreases.

[0221] Figure 9 and Figure 10 The portion marked with an "H" represents the area with the maximum electric field in the horizontal direction, and where holes can converge to the greatest extent. (Compare) Figure 9 and Figure 10 Even if it is the part where the holes converge, in Figure 10 In this case, there are many boundaries of the semiconductor layer around it, and therefore the lateral electric field (E field) in the horizontal direction is dispersed and the degree of collection is reduced.

[0222] To confirm the phenomenon of hole collection based on the transverse electric field (E field) in the horizontal direction, refer to Figures 11 to 13 Examine the characteristics of the transverse E-field in the horizontal direction.

[0223] Figures 11 to 13 The features generated from the edge portion of the transistor's channel are shown.

[0224] exist Figure 11 and Figure 12 In a transistor, the channel is divided into two types. One type is the channel edge W located at the opposite edge in the width direction. edge And the other is the channel center W, which corresponds to the center of the channel. center The edge of the trench (W) edge It is formed in two parts located on opposite sides of the channel, while the center of the channel, W center It is positioned in a section between these two parts, thus dividing the channel into a total of three sections. The width of the entire channel can be equal to the channel edge W. edge Twice the width and the center of the channel W center The sum of their widths is the same.

[0225] exist Figure 11 In the planar diagram of the semiconductor layer, the channel edge W edge and the center of the channel W center Separate, and Figure 12 This division is shown as a circuit diagram.

[0226] exist Figure 12 In the middle, with the center of the channel W center The corresponding transistor is shown as T. center And with the edge of the channel W edge The corresponding transistor is shown as T. edge .

[0227] The electric field characteristics at the edge of these three different parts Figure 13 As shown in the image.

[0228] exist Figure 13 The image shows a magnified view of the channel region C of the semiconductor layer, the gate insulating layer 113, and the gate electrode G.

[0229] Because the gate electrode G is formed to cover one side of the channel region C, therefore... Figure 13 As indicated by the arrows, an electric field with a component in the horizontal direction is generated, and holes are collected by a strong electric field in the edge portion of the channel region C.

[0230] exist Figure 9 In the comparative example, the edge adjacent to the hole-trapping portion H includes the edge of the upper or lower edge of the semiconductor layer and only one edge extending in the vertical direction (e.g., the second direction) of the gate electrode G. Conversely, in Figure 10 In an exemplary embodiment, in addition to Figure 9 In addition to the edges described, the edges adjacent to the hole-collecting trapping portion H also include edges in the vertical direction (e.g., the second direction) of the drain region D and edges in the vertical direction (e.g., the second direction) of the first region ① of the channel region C. Therefore, the electric field in the horizontal direction is dispersed, and the number of holes collected at the trapping portion H is reduced. Thus, compared to the comparative example, in... Figure 7 In an exemplary embodiment, the reduction in output current caused by the portion H that collects holes is mitigated.

[0231] Now return to the reference Figure 9 and Figure 10 The electron-collecting trapping portion M is described in more detail. The electron-collecting trapping portion M is adjacent to the source region S, and electrons tend to be collected at the outer edge or boundary portion of the first region ① in the channel region C of the semiconductor layer. In particular, when the channel region C is partially bent while the flexible display device is folded, the accumulation of electrons at the corresponding location further increases. Therefore, the electron-collecting trapping portion M is related to mechanical stress, and more electrons (e.g., many more electrons) accumulate in the portion with strong mechanical stress.

[0232] refer to Figure 9 The electron-collecting trapping portion M occupies a portion of the relatively narrow channel width and reduces the output current, while also reducing the flow area of ​​holes in the channel region C and the hole-collecting trapping portion H.

[0233] On the contrary, in relation to Figure 9 The structure corresponding Figure 10 In this exemplary embodiment, the electron-collecting trapping portion M in the first region ① is located at the edge and thus far from the region where holes actually flow. Therefore, the effect of the electron-collecting trapping portion M decreases as the output current decreases. Even when the electron concentration in the electron-collecting trapping portion M increases due to the folding of the flexible display device, this reduction in effect does not decrease the output current due to distance.

[0234] As described, according to Figure 7 The exemplary embodiment of the asymmetric channel structure prevents or substantially prevents the reduction of output current due to electrical and mechanical stress.

[0235] At the same time, in having Figure 9 In the case of the transistor with the structure of the comparative example, another comparative example can be provided, in which the length or width of the channel is increased to prevent or reduce the decrease in output current. In the case of the transistor of this additional comparative example, by increasing the length or width of the channel, the electric field in the horizontal direction is positioned away from the center of the channel region, and thus the overall effect of the channel is reduced, which can have the effect of preventing or substantially preventing the output current from decreasing to a certain extent. However, when the length or width of the channel is increased as in the additional comparative example, in exemplary embodiments where the area of ​​the high-resolution display device or the non-display area is small, the channel with the increased length or width may be difficult to form (e.g., due to size limitations).

[0236] Additionally, in the following description, such as via Figure 14 The simulation results show that when stress accumulates due to long-term use, such as when there is... Figure 9 In the structure where the channel width is increased, the reduction in output current is greater than that of an additional comparison example with a structure having Figure 7 The output current is reduced in an exemplary embodiment of an asymmetric channel structure that does not increase the channel width.

[0237] Figure 14 It shows the basis Figure 9 and Figure 10 A graph showing the simulation results of the change in the output current.

[0238] Figure 14 The graph shows the retention rate of the output current over time and the output current retention rate of the two objects.

[0239] One is that its channel width W is 4.0 μm and its channel length L is 2.0 μm, while also possessing Figure 9 As an additional comparative example, a transistor with a channel structure is shown. Another example has a channel width W of 1.0 μm and a channel length L of 2.0 μm, while also possessing... Figure 7 Similar channel structures do not have transistors that increase the channel width; that is, another transistor has a constant width smaller than the width of the source region and the width of the drain region. Although specific widths and lengths are provided relative to asymmetric channel structures according to one or more embodiments, this disclosure is not limited thereto. In other embodiments, asymmetric channel structures may provide any suitable length and / or width.

[0240] As in Figure 14As shown in the graph, when the channel width W is increased as in the additional comparative example, the output current does not decrease over a constant time period, but it suddenly decreases with increasing stress due to prolonged use. However, it can be determined that by not increasing the channel width, a transistor with an asymmetric channel structure can be formed in a smaller area, and the output current can be maintained even with prolonged use.

[0241] As mentioned above, when having Figure 7 When transistors with asymmetric channel structures are used in flexible display devices using polycrystalline semiconductors, the output current can remain constant even when strong electrical or mechanical stress is applied.

[0242] The above, in view of Figure 7 The change in the asymmetric channel structure shown has been accompanied by the description of the second transistor T2 in the stage of the light-emitting driver in the flexible display device.

[0243] However, due to the folding and unfolding operations, and in the folded state, all transistors formed in the flexible display device are forced to endure mechanical stress.

[0244] Mechanical stress can cause greater electrical stress, and in particular, transistors located near the input terminals to which periodically applied clock signals are input may receive stronger electrical stress.

[0245] Therefore, in the stage of the light-emitting driver, except for the second transistor T2, an asymmetric channel structure can be applied to the first transistor T1, the third transistor T3, the fourth transistor T4, the ninth transistor T9, or the tenth transistor T10. Additionally, the transistors included in the high-level output section 551, the first node-second controller 554, the second node-second controller 556, and the third node controller 557 can also employ an asymmetric channel structure.

[0246] Furthermore, the transistors in other drivers of the flexible display device can have asymmetric channel structures. Specifically, the scan driver receives a clock signal like the light-emitting driver and receives the previous scan signal as a carry signal, which may reduce the output current due to some transistors. Therefore, some transistors included in the scan driver can be formed with asymmetric channel structures.

[0247] As described above, the transistors included in the driver share the common characteristic of high electrical stress. However, according to an exemplary embodiment, the transistors located at the folded portion of the flexible display device may experience a decrease in output current due to mechanical stress. Therefore, in addition to the aforementioned transistors in the driver, asymmetric channel structures can be applied to various transistors (e.g., transistors included in pixels or other drivers) to prevent or reduce the decrease in output current due to mechanical stress.

[0248] The following text will describe various variations of the asymmetric channel structure.

[0249] Figures 15 to 19 This is a top view of an asymmetric transistor structure according to another exemplary embodiment.

[0250] For reference only. Figures 15 to 19 The cross-sectional view of the structure and Figure 8 The cross-sectional views of the structures are the same or substantially similar, and therefore no repeated descriptions are included.

[0251] First, the description Figure 15 The asymmetric channel structure.

[0252] and Figure 7 Unlike the exemplary embodiments, in Figure 15 In an exemplary embodiment, the width Wd of the drain region D in the semiconductor layer is narrower than the width Ws of the source region S. The width Wd of the drain region D is the same as the channel width W2 of the second region ② of the channel region C.

[0253] That is, according to Figure 15 In the semiconductor layer of the transistor in an exemplary embodiment, such as Figure 15 As shown, the width of the source region S is greater than the width of the drain region D (Ws > Wd), the width Wd of the drain region D is the same as the channel width W2 of the second region ② of the channel region C, and the channel width W1 of the first region ① that contacts the source region S of the channel region C has the largest width.

[0254] The channel width W1 of the first region ① is wider than the widths Ws and Wd of the source region S and drain region D, and the channel width W2 of the second region ②. The channel width W2 of the second region ② is narrower than the width Ws of the source region S, but has the same width as the width Wd of the drain region D. Figure 15In an exemplary embodiment, the first region ① and the second region ② are connected (e.g., directly connected), and therefore the channel width changes abruptly near the center of the channel region C. However, according to an exemplary embodiment, the intermediate region / area (i.e., the intermediate area) may be further included between the first region and the second region near the center of the channel region C, and the intermediate area may have a channel width between the channel width of the first region and the channel width of the second region (i.e., the intermediate channel width) or may have a gradually changing channel width (e.g., a channel width that gradually changes from the channel width W1 of the first region ① to the channel width W2 of the second region ②).

[0255] exist Figure 15 In an exemplary embodiment, the semiconductor layer extends in a horizontal direction (e.g., a first direction) at the portion where the transistor is located, and the gate electrode G extends in a vertical direction (e.g., a second direction) intersecting the horizontal direction at the portion where the transistor is located. Additionally, according to... Figure 15 In an exemplary embodiment, the semiconductor layer is formed as a polycrystalline semiconductor layer, the channel region C overlaps with the gate electrode G in a planar or planar diagram and is therefore undoped with impurities, and the source region S and drain region D are polycrystalline semiconductor layers and are doped with a high concentration of impurities, and therefore they can have the same properties as conductors or have higher conductivity.

[0256] like Figure 15 As shown, in Figure 15 In the asymmetric channel structure, the electron-collecting trapping portion M in the first region ① is located at the edge of the region far from the actual hole flow region, and therefore the effect of the electron-collecting trapping portion M on the reduction of output current is reduced. Thus, the reduction in output current caused by mechanical stress is mitigated.

[0257] At the same time, with Figure 7 Compared to the structure, in Figure 15 In the asymmetric channel structure, the number of edges adjacent to the trapping portion H of the collecting cavity is reduced by one. That is, in Figure 15 In an exemplary embodiment, the drain region D and the second region ② have the same width, and therefore are... Figure 7 Compared to the structure of [other structure], the drain region D has no edge in the vertical direction (e.g., the second direction). However, compared to [other structure], Figure 9 In contrast, an edge is formed along the vertical direction (e.g., the second direction) of the first region ①, thus dispersing the transverse electric field and reducing hole collection. Therefore, compared to the example shown... Figure 9 In comparison, it reduces the decrease in output current caused by electrical stress.

[0258] In other words, Figure 15Exemplary embodiments can prevent or reduce the reduction in output current due to strong electrical or mechanical stress.

[0259] In the following text, it will be described Figure 16 The asymmetric channel structure.

[0260] Figure 16 This is an exemplary embodiment, in which, except Figure 15 In addition to the exemplary embodiment, the width of the source region S is formed to be the same as the channel width of the first region ① (W1 = Ws).

[0261] Therefore, in Figure 16 In asymmetric channel structures, with Figure 7 Unlike the exemplary embodiment, the width Wd of the drain region D in the semiconductor layer is formed to be narrower than the width Ws of the source region S. The width Wd of the drain region D is the same as the channel width W2 of the second region ②, and the width Ws of the source region S is the same as the channel width W1 of the first region ①. That is, Figure 16 The exemplary embodiment of the semiconductor layer has only two widths, and the width of the semiconductor layer can change abruptly near the center of the channel region C.

[0262] Meanwhile, according to an exemplary embodiment, an intermediate region may be further included between the first region ① and the second region ② near the center of the channel region C, and the intermediate region may have a channel width between the channel width of the first region ① and the channel width of the second region ② (i.e., the intermediate channel width) or a gradually changing channel width (e.g., a channel width that gradually changes from the channel width W1 of the first region ① to the channel width W2 of the second region ②).

[0263] exist Figure 16 In asymmetric channel structures, such as Figure 16 As shown, the electron-collecting trapping portion M is located at the edge of the first region ①, far from the region where holes actually flow, and therefore the effect of the electron-collecting trapping portion M on the reduction of the output current is reduced. Thus, the reduction in output current caused by mechanical stress is mitigated.

[0264] At the same time, with Figure 7 Compared to the structure, in Figure 16 In the asymmetric channel structure, the number of edges adjacent to the trapping portion H of the collecting cavity is reduced by one. That is, as in Figure 15 In an exemplary embodiment, in Figure 16 In an exemplary embodiment, the drain region D and the second region ② also have the same width, and therefore are the same as... Figure 7 Compared to the structure in the drain region D, there is no vertical edge (e.g., in the second direction). However, with Figure 9In contrast, an edge is formed along the vertical direction (e.g., the second direction) of the first region ①, and thus disperses the transverse electric field, thereby reducing the hole collection rate. Therefore, compared to the example provided... Figure 9 In comparison, it reduces the decrease in output current caused by electrical stress.

[0265] In other words, even if strong electrical or mechanical stress is applied, Figure 16 The exemplary embodiments can prevent or substantially prevent a decrease in output current.

[0266] In the following text, it will be described Figure 17 The asymmetric channel structure.

[0267] Unlike other exemplary embodiments, in Figure 17 In an exemplary embodiment, the semiconductor layer has a constant width, but the gate electrode G has a protrusion corresponding to the channel region C, thereby forming an asymmetric structure.

[0268] Now the description will be based on Figure 17 An exemplary embodiment of the asymmetric structure.

[0269] Figure 17 In an exemplary embodiment, the semiconductor layer extends along a horizontal direction (e.g., a first direction) while having a constant width in the portion where the transistor is located. Therefore, the width Ws of the source region S, the width Wd of the drain region D, the channel width W1 of the first region ①, and the channel width W2 of the second region ② can be the same. In this case, the width of the semiconductor layer can be like... Figure 7 The second region ② in the exemplary embodiment has a narrower channel width W2, just like the other regions.

[0270] The gate electrode G, overlapping the semiconductor layer, extends along a direction perpendicular to the semiconductor layer (e.g., a second direction) at the portion where the transistor is located, and includes a protruding portion P at the portion intersecting the semiconductor layer. That is, according to Figure 17 An exemplary embodiment of the gate electrode G includes a linear portion extending in a direction intersecting the semiconductor layer (e.g., a vertical direction (e.g., a second direction)) and a protruding portion P projecting from the linear portion. In one or more embodiments, the protruding portion P may project from the linear portion in a horizontal direction (e.g., a first direction) such that the protruding portion P overlaps with the semiconductor layer.

[0271] The protruding portion P of the gate electrode G overlaps with the first region ① of the semiconductor layer. Furthermore, the three edge sides of the protruding portion P can match the vertical edge sides of the first region ① and the boundary of the source region S. In this case, the width of the protruding portion P can be the same as the channel width W1 of the first region ①. Additionally, the width of the gate electrode G in the horizontal direction (e.g., the first direction) of the portion extending in the vertical direction (e.g., the second direction) can be the same as... Figure 17 The semiconductor layers in the exemplary embodiments have the same width.

[0272] In the semiconductor layer, the channel region C includes a portion that overlaps with the linear portion of the gate electrode G and a portion that overlaps with the protruding portion P of the gate electrode G.

[0273] The channel region C of the semiconductor layer is a region that is a polycrystalline semiconductor layer and is an area that overlaps with the gate electrode G on a plane or in a planar diagram and is therefore not doped with impurities. The source region S and the drain region D are polycrystalline semiconductor layers and can have conductor-like properties or increased conductivity by doping with high concentrations of impurities.

[0274] Meanwhile, according to an exemplary embodiment, the width of the protrusion P extending from the gate electrode G is greater than the width of the semiconductor layer, rather than having the same width as the semiconductor layer. Additionally, the protrusion P may have a structure in which its vertical edge is inclined relative to the horizontal direction (e.g., a first direction) rather than horizontally parallel.

[0275] As with other exemplary embodiments, in Figure 17 In an asymmetric structure, a transistor can operate without reducing the output current, as will be described below.

[0276] and Figure 9 Compared to the structure of the comparison example, in Figure 17 In the asymmetric structure, the number of edges adjacent to the trapping portion H of the collecting cavity increases by one. That is, in Figure 17 In an exemplary embodiment, the two edges of the gate electrode G extending in the vertical direction (e.g., the second direction) are arranged adjacent to the hole-trapping portion H, but in Figure 9 In this configuration, only one edge of the gate electrode G, extending in the vertical direction (e.g., the second direction), is positioned adjacent to the trapping portion H. Therefore, with... Figure 9 Comparison examples, in Figure 17 In the asymmetric structure, the transverse electric field (E field) is dispersed, thus reducing the collection degree of holes at the trapped portion H. Therefore, compared with Figure 9 Compared to the comparative example, the reduction in output current caused by electrical stress is mitigated.

[0277] At the same time, comparison Figure 17Exemplary embodiments and Figure 9 A comparative example, in terms of mechanical stress, Figure 17 An exemplary embodiment may have the same as Figure 9 Similar characteristics to the comparison examples. That is, in Figure 17 In an exemplary embodiment, the electron-collecting trapping portion M in the first region ① can be positioned relatively close to the region where holes actually flow, and therefore, the effect of the electron-collecting trapping portion M on the reduction of the output current can be compared with... Figure 9 The effects of the comparative examples are similar.

[0278] when Figure 17 In the exemplary embodiment, the channel width of the channel region C is... Figure 9 When the channel width of the comparative example is greatly reduced, the output current may decrease due to the trapping portion M that collects electrons.

[0279] However, this only considers mechanical stress, and takes into account the relative stress. Figure 17 The advantage of the exemplary embodiment of the electrical stress is that the overall output current of the transistor does not decrease. When the output current of the transistor decreases, Figure 17 The channel width of the channel region C is formed too narrow, and thus the width of the semiconductor layer (e.g., the channel width) is increased to prevent or reduce the reduction in output current.

[0280] In other words, Figure 17 An exemplary embodiment can prevent or reduce the reduction in output current due to strong electrical or mechanical stress.

[0281] In the following text, it will be described Figure 18 The asymmetric channel structure.

[0282] exist Figure 18 In an exemplary embodiment, the gate electrode G and the semiconductor layer are bent, and the gate electrode G maintains the same width even when bent. However, in the case of the semiconductor layer, the widths of the source region S and the first region ① become wider, and then the widths of the source region S and the first region ① become narrower when the semiconductor layer is bent, such that the width of the drain region D and the width of the second region ② are narrower than the widths of the source region S and the first region ①. That is, in the semiconductor layer, the width Ws of the source region S is wider than the width Wd of the drain region D, and the channel width W1 of a portion of the first region ① in the channel region C that contacts the source region S1 is formed to be wider than the channel width W2 of the second region ②. In addition, the channel width W1 of the first region ① is the same as the width Ws of the source region S, and the channel width W2 of the second region ② is the same as the width Wd of the drain region D.

[0283] exist Figure 18In an exemplary embodiment, the first region ① and the second region ② are connected to each other while being bent. In the portion forming the transistor, the first region ① and the source region S of the semiconductor layer extend in a vertical direction (e.g., a second direction), and the drain region D and the second region ② extend in a horizontal direction (e.g., a first direction).

[0284] The gate electrode G also has a bent structure and includes a portion extending in a horizontal direction (e.g., a first direction) and a portion extending in a vertical direction (e.g., a second direction). In the gate electrode G, the portion extending in the horizontal direction (e.g., the first direction) and the portion extending in the vertical direction (e.g., the second direction) may have the same width.

[0285] In the semiconductor layer, the source region S and the drain region D do not overlap with the gate electrode G, and only the channel region C overlaps with the gate electrode G in a planar or planar diagram and is therefore undoped.

[0286] In addition, Figure 18 In an exemplary embodiment, a non-channel region NC, which is doped on the outside of the channel region C and does not overlap with the gate electrode G, can be formed.

[0287] The non-channel region NC contacts the channel region C, and simultaneously contacts the first region ① and / or the second region ②. However, the non-channel region NC is separated from the source region S and the drain region D. Therefore, the non-channel region NC passes through the channel region C and then connects to the source region S and the drain region D.

[0288] like Figure 18 As shown, the shape of the non-channel region NC can be a quadrilateral structure, but it can have various suitable shapes, such as triangles and circles.

[0289] When a hole moves from the first region ① to the second region ②, it can pass through the non-channel region NC. That is, after a hole moves vertically (e.g., in the second direction) in the first region ① adjacent to the source region S and thus reaches the non-channel region NC, the hole enters the second region ② horizontally (e.g., in the first direction) in the non-channel region NC and can then be transported to the drain region D. When a hole is transported after passing through the non-channel region NC, Figure 18 A transistor can be represented as two transistors in a circuit diagram, and this can correspond to Figure 12 The circuit structure is shown, with only two transistors.

[0290] Additionally, some holes can move from the first region ① to the second region ② without crossing the non-channel region NC.

[0291] exist Figure 18In the asymmetric channel structure, the transistor does not reduce the output current, as in other exemplary embodiments, and this will now be described.

[0292] like Figure 18 As shown, the electron-capturing portion M in the first region ① is located only at the right edge, not the left edge. This is because the main migration path of holes is primarily formed on the right side of the first region ①, as... Figure 18 As indicated by the arrows in the diagram. Therefore, even if the region of the electron-capturing section M is relatively small, and even if it is close to the region of hole flow, the influence on holes can be reduced. Thus, the reduction in output current due to mechanical stress can be mitigated.

[0293] In addition, with Figure 9 Compared to the comparison examples, in Figure 18 In the asymmetric channel structure, the number of edges adjacent to the trapping portion H of the collecting cavity increases by one. That is, in Figure 18 In an exemplary embodiment, the two edges of the gate electrode G extending in the vertical direction (e.g., the second direction) are arranged adjacent to the hole-trapping portion H, but in Figure 9 In this configuration, only one edge of the gate electrode G, extending in the vertical direction (e.g., the second direction), is positioned adjacent to the trapping portion H. Therefore, with... Figure 9 Compared to the comparison examples, in Figure 18 In the asymmetric structure, the transverse electric field (E field) in the horizontal direction is dispersed, and the collection degree of holes in the trapped part H is reduced. Therefore, compared with Figure 9 Compared to the comparative example, the reduction in output current caused by electrical stress is mitigated.

[0294] As described, Figure 18 Exemplary embodiments can prevent or reduce output current caused by strong electrical or mechanical stress.

[0295] exist Figure 18 In an exemplary embodiment, the semiconductor layer and the gate electrode G are bent once at 90 degrees, and can be bent multiple times at various angles.

[0296] In the following text, reference will be made to Figure 19 An exemplary embodiment is described in more detail, wherein an intermediate region ③ is further included between the first region ① and the second region ② near the center of the channel region C.

[0297] The width of the intermediate region ③ can have a constant value, and its channel width (i.e., the intermediate channel width) is between the channel width W1 of the first region ① and the channel width W2 of the second region ②, or it can have a value that gradually changes from the channel width W1 of the first region ① to the channel width W2 of the second region ②.

[0298] exist Figure 19 The image shows an exemplary embodiment in which the width of the middle region ③ gradually changes. Figure 7 Exemplary variations of exemplary embodiments.

[0299] The intermediate region ③ is the middle part of the channel region C and is independent of the electron-trapping portion M that collects electrons in the first region ① of the contact source region S or the hole-trapping portion H that collects holes in the second region ② of the contact drain region D. Therefore, it is possible to maintain the... Figure 7 The exemplary embodiment mitigates the effect of reduced output current.

[0300] like Figure 19 As shown, it can also be further deformed. Figure 17 and Figure 18 An exemplary embodiment further includes an intermediate region ③. However, this disclosure is not limited thereto. For example, with Figure 19 In different embodiments, the width of the intermediate region ③ can have a constant value, and its channel width (i.e., the intermediate channel width) is between the channel width W1 of the first region ① and the channel width W2 of the second region ②.

[0301] Although this disclosure has been described in conjunction with exemplary embodiments now considered to be practical, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims and their equivalents.

Claims

1. A flexible display device comprising: a flexible substrate; a semiconductor layer over the flexible substrate, the semiconductor layer including a polycrystalline semiconductor; a gate insulating layer over the semiconductor layer; and a gate electrode over the gate insulating layer, the gate electrode overlapping a channel region of the semiconductor layer in a plan view, wherein the semiconductor layer includes a source region and a drain region on opposite sides of the channel region, wherein the channel region includes a first region in direct contact with and extending from the source region and a second region in direct contact with and extending from the drain region, and wherein a channel width of the first region is greater than a channel width of the second region and a width of the source region.

2. The flexible display device according to claim 1, wherein a width of the drain region is greater than the channel width of the second region.

3. The flexible display device according to claim 1, wherein a width of the drain region is equal to the channel width of the second region.

4. The flexible display device according to claim 1, wherein each of the semiconductor layer and the gate electrode has a bent structure.

5. The flexible display device according to claim 4, wherein a width of the drain region is equal to the channel width of the second region.

6. The flexible display device according to claim 1, wherein the channel region includes an intermediate region between the first region and the second region.

7. The flexible display device according to claim 6, wherein the intermediate region has a channel width changing structure.

8. The flexible display device according to claim 1, wherein the flexible substrate includes a display region and a non-display region, a plurality of pixels at the display region, and a driver at the non-display region to apply a driving signal to the plurality of pixels; wherein the driver includes one transistor including the source region, the channel region, the drain region, and the gate electrode.

9. The flexible display device according to claim 8, wherein the driver includes a light emitting driver to supply a light emitting signal to the plurality of pixels, the light emitting driver including a plurality of stages, the driver in which the one transistor is formed is a light emitting driver.

10. The flexible display device according to claim 9, wherein the plurality of stages of the light emitting driver includes: a high level output portion to output a high voltage of the light emitting signal according to a voltage of a first node; a low level output portion to output a low voltage of the light emitting signal according to a voltage of a second node; a first node controller to control the first node, the first node controller including a first node_first controller and a first node_second controller; a second node controller to control the second node, the second node controller including a second node_first controller and a second node_second controller; and a third node controller to control a voltage of a third node, the third node controlling the first node_second controller. ​ 11. The flexible display device according to claim 10, wherein, At least one of the second node controller, which includes the second node_first controller, and the second node_second controller, and the third node controller includes the transistor.

12. The flexible display device according to claim 11, wherein, The second node_first controller includes a first transistor, the first transistor including a control electrode connected to a first clock input terminal, an input electrode connected to a control terminal, and an output electrode connected to the second node. The second node, the second controller, includes: As the second transistor, one of the transistors further includes a control electrode connected to the third node and an input electrode for receiving the high voltage of the light-emitting signal; and The third transistor includes a control electrode connected to the second clock input, an input electrode connected to the output electrode of the second transistor, and an output electrode connected to the second node. The third node controller includes: The fourth transistor includes a control terminal connected to the second node, an input terminal connected to the first clock input terminal, and an output terminal connected to the third node; and The fifth transistor includes a control terminal connected to the first clock input, a low-voltage input terminal that receives the light emission signal, and an output terminal connected to the third node.

13. A flexible display device, comprising: Flexible substrate; A semiconductor layer on the flexible substrate, the semiconductor layer comprising a polycrystalline semiconductor; Gate insulating layer on the semiconductor layer; as well as Gate electrode on the gate insulating layer, The semiconductor layer includes a channel region, a source region, and a drain region, wherein the source region and the drain region are located on opposite sides of the channel region in a first direction. The gate electrode includes a linear portion that intersects the semiconductor layer and extends in a second direction perpendicular to the first direction, passing through both ends of the semiconductor layer in the second direction, and a protruding portion that protrudes only on one side of the linear portion in the first direction. In the plan view, the protruding portion overlaps with the channel region of the semiconductor layer.

14. The flexible display device according to claim 13, wherein, The drain region, the source region, and the channel region have the same width.

15. The flexible display device according to claim 14, wherein, The protruding portion has the same width as the channel region.

16. The flexible display device according to claim 13, wherein, The channel region includes a portion that overlaps with the linear portion and a portion that overlaps with the protruding portion of the gate electrode.

17. A flexible display device, comprising: Flexible substrate; A semiconductor layer on the flexible substrate, the semiconductor layer comprising a polycrystalline semiconductor; Gate insulating layer on the semiconductor layer; as well as Gate electrode on the gate insulating layer, The semiconductor layer includes a channel region, a source region, and a drain region, with the source region and the drain region located on opposite sides of the channel region. The semiconductor layer and the gate electrode each have an asymmetric bending structure. The bending direction of the semiconductor layer is different from that of the gate electrode. Wherein, the channel region and the gate electrode overlap each other in the planar view, and The channel region is located at the portion of the semiconductor layer that is asymmetrically bent.

18. The flexible display device according to claim 17, wherein, The channel region includes a first region that contacts the source region and a second region that contacts the drain region. The channel width of the first region is greater than the channel width of the second region.

19. The flexible display device according to claim 18, wherein, The semiconductor layer further includes a non-channel region in contact with the channel region, the non-channel region being separate from the source region and the drain region, and The non-channel region is doped and does not overlap with the gate electrode in the plan view.

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