Iii-v structure integration on group iv substrates

Abstract

A method for forming a III-V configuration on a Group IV substrate (1), the method comprising: a. providing an assembly comprising a Group IV substrate (1) and a dielectric (2) thereon, the dielectric layer comprising a trench exposed at the bottom to the Group IV substrate (1), b. starting growth of a first III-V structure in the trench, c. continuing growth outside the trench at a top portion (4) of the first III-V structure, d. epitaxially growing a second III-V sacrificial structure (6) on a top portion (5) of the first III-V structure, e. epitaxially growing a third III-V structure (7, 7', 7", 8) on the second III-V sacrificial structure (6), the third III-V structure (7, 7', 7", 8) comprising: ii. a top III-V layer, f. physically disconnecting a first portion (8') of the top layer from a second portion (8') thereof, and g. contacting the second III-V sacrificial structure (6) with a liquid etching medium.

Description

Technical Field

[0001] This invention relates to the field of III-V semiconductors. More specifically, this invention relates to a method for integrally integrating III-V structures onto a group IV substrate. Background Technology

[0002] III-V materials (e.g., GaAs, InGaAs, or InP) typically exhibit higher electron mobility and saturation velocity than Si. They also offer higher power at higher frequencies compared to Si. Therefore, they are widely used in radio frequency (RF) applications. Si devices are not efficient when targeting very high frequencies (GHz or higher). Currently, devices using III-V materials are built on small-size III-V wafers. However, these wafers are very expensive compared to Si wafers. Therefore, there is interest in finding methods to integrate III-V devices monolithically on silicon substrates.

[0003] However, this is difficult due to the lattice mismatch between the III-V material and the silicon substrate, as this can lead to defects in the grown III-V material.

[0004] Using selective region growth, III-V materials can be deposited on silicon substrates through a variety of methods. These methods ensure that materials without threading dislocations are located on top of the structure that builds the III-V device by confining defects caused by large lattice mismatches between the III-V material and Si to the lower portion of the III-V material.

[0005] One of these methods is to utilize nanoridges.

[0006] The nanoridge is a semiconductor structure having a first width at the bottom and a second width at the top, the second width being greater than the first width. The first portion is grown in a dielectric trench, and a second portion is formed as growth continues beyond the trench. The width of the second portion substrate increases as it moves away from the interface between the first and second portions, thus forming a funnel-shaped substrate. The top of this substrate is the upper portion of the second portion, which can have a constant width and a flat top surface, the width of which is equal to the width of the upper surface of the second portion substrate. Kuner et al. have described this structure (Applied Physics Letters, 109, 091101 (2016)).

[0007] Because the bottom portion grows within narrow grooves, it benefits from aspect ratio trapping, and its top surface has few or no defects. Therefore, the top portion also has few or no defects.

[0008] Besides defects, the background doping level of the layers constituting the III-V structure is also important. For example, the background doping level in the layer beneath the transistor channel can lead to unwanted leakage paths.

[0009] Therefore, there remains a need in the field for improved methods and devices with very low background doping levels. Summary of the Invention

[0010] One object of the present invention is to provide a good apparatus or method for integrating III-V structures on Si substrates.

[0011] The above-mentioned objectives are achieved by the methods and devices described in this invention.

[0012] In a first aspect, the present invention relates to a method for forming a III-V semiconductor structure on a group IV substrate, the method comprising:

[0013] a. Providing an assembly in an epitaxial growth chamber, the assembly comprising a single-crystal group IV substrate and a first dielectric layer thereon, the first dielectric layer comprising a trench with its bottom exposed to the group IV substrate.

[0014] b. The first III-V structure begins to grow in the trench, thereby forming the bottom portion of the first III-V structure within the trench.

[0015] c. Growth continues outside the trench at the top of the bottom portion, thereby forming the top portion of the first III-V structure.

[0016] d. A second III-V sacrificial structure is epitaxially grown on the top portion of the first III-V structure. The second III-V sacrificial structure is selectively etchable in the liquid etching medium relative to the first III-V structure.

[0017] e. Epitaxially growing a third III-V structure on the second III-V sacrificial structure, the third III-V structure comprising:

[0018] i. A bottom III-V layer on the second III-V sacrificial structure (6), wherein, relative to the bottom layer, the second III-V sacrificial structure is selectively etchable in the liquid etching medium.

[0019] ii. Top III-V layers,

[0020] f. Physically disconnect the first part of the third III-V structure from the second part of the third III-V structure, and

[0021] g. The second III-V sacrificial structure is brought into contact with a liquid etching medium, thereby selectively etching the second III-V sacrificial structure relative to the first III-V structure and the bottom layer to form a chamber.

[0022] In a second aspect, the present invention relates to a III-V semiconductor structure comprising:

[0023] a. An assembly comprising a single-crystal group IV substrate and a first dielectric layer thereon, the first dielectric layer including a trench with its bottom exposed to the group IV substrate.

[0024] b. A first III-V structure, comprising a bottom portion within a trench and a top portion outside the trench on top of the bottom portion.

[0025] c. A cavity or dielectric structure on the top portion of the first III-V structure.

[0026] d. A third III-V structure on a chamber or dielectric structure, the third III-V structure comprising a bottom III-V layer and a top III-V layer on the chamber or dielectric structure, the top III-V layer comprising a first portion physically disconnected from the second portion.

[0027] The advantage of the first aspect of the implementation is that it allows III-V devices to be integrated on a group IV substrate.

[0028] The advantage of the first aspect of the implementation is that it allows devices for RF applications to be formed on a group IV substrate.

[0029] The advantage of the first aspect of the implementation is that it allows devices for RF applications to be formed on a group IV substrate.

[0030] The advantage of the first aspect of the implementation is that it allows for the formation of devices exhibiting high electron mobility and saturation rate on group IV substrates.

[0031] The advantage of the first aspect of the implementation is that it allows for the formation of devices on group IV substrates that can provide high power at high frequencies.

[0032] The advantage of the first aspect of the implementation is that it allows for the formation of III-V devices at low cost.

[0033] The advantage of the first aspect of the implementation is that it allows the formation of III-V devices with low defect rates on group IV substrates.

[0034] The advantage of the first aspect of the implementation is that it allows the formation of III-V transistor devices on a group IV substrate, wherein the background doping level in the layer below the transistor channel is very low.

[0035] The advantage of the first aspect of the implementation is that it allows for the formation of III-V structures and devices with low parasitic capacitance coupling to the substrate.

[0036] Therefore, there remains a need in the field for improved methods and devices with very low background doping levels.

[0037] Specific and preferred aspects of the invention are set forth in the appended independent and dependent claims. Features in the dependent claims may be appropriately combined with features in the independent and other dependent claims, and are not limited to those expressly stated in the claims.

[0038] While improvements, modifications, and developments in the apparatus have been ongoing in the art, the concepts of the present invention are considered to represent sufficiently new and novel improvements, including deviations from existing practice, resulting in a more efficient, stable, and reliable apparatus that provides this property.

[0039] The above and other features, characteristics, and advantages of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, which illustrate the principles of the invention by way of example. This specification is for illustrative purposes only and is not intended to limit the scope of the invention. The references to the drawings cited below refer to the accompanying drawings. Attached Figure Description

[0040] Figure 1-4 Figures 7 and 8 are schematic diagrams of the vertical cross-section of an intermediate in a method according to an embodiment of the present invention.

[0041] Figure 5 yes Figure 4 A perspective view of the intermediate structure shown.

[0042] Figure 6 yes Figure 4 and Figure 7 A perspective diagram of the intermediate structure obtained between these steps.

[0043] Figure 9 and 10 The illustration schematically shows the layout strategy of HEMT according to some embodiments of the present invention.

[0044] In different figures, the same reference numerals denote the same or similar elements. Detailed Implementation

[0045] The invention will be described with reference to specific embodiments and certain accompanying drawings, but is not limited thereto; it is defined only by the claims. The described drawings are illustrative only and not restrictive. In the drawings, the dimensions of some elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and relative dimensions described do not correspond to actual reductions in practice.

[0046] Furthermore, the terms first, second, third, etc., used in the specification and claims are used to distinguish similar elements and are not necessarily used to describe a temporal, spatial, hierarchical, or any other order. It should be understood that such terms are used interchangeably where appropriate, and embodiments of the invention can operate in orders other than those described or shown herein.

[0047] Furthermore, in the specification and claims, terms such as top, bottom, above, and below are used for descriptive purposes and not necessarily to describe relative positions. It should be understood that such terms are used interchangeably where appropriate, and embodiments of the invention can operate in orientations other than those described or shown herein.

[0048] It should be noted that the term "comprising" as used in the claims should not be construed as being limited to the portion listed thereafter, and does not exclude other elements or steps. Therefore, it should be understood to indicate the presence of the stated feature, integral, step, or component or assembly, but does not exclude the presence or addition of one or more other features, integrals, steps, or components or combinations thereof. Thus, the term "comprising" covers the case where only the stated feature is present, as well as the case where these features are present along with one or more other features. Therefore, the term "comprising" according to the invention also includes an embodiment where no other components are present. Therefore, the scope of the expression "a device comprising components A and B" should not be construed as limiting the device to components A and B alone. It indicates that, for the present invention, the only relevant components of the device are A and B.

[0049] The phrase "one embodiment" or "one implementation" mentioned in the specification means that the relevant specific features, structures, or characteristics described in the embodiment are included in at least one embodiment of the invention. Therefore, the phrases "in one embodiment" or "in one implementation" appearing throughout the specification do not necessarily all refer to the same embodiment, but may all refer to the same embodiment. Furthermore, specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments, as will be apparent to those skilled in the art.

[0050] Similarly, it should be understood that in the description of exemplary embodiments of the invention, different features of the invention are sometimes grouped together in a single embodiment, drawing, or description thereof in order to simplify the disclosure and aid in understanding one or more different aspects of the invention. However, the methods in this disclosure should not be construed as reflecting an intention that the claimed invention needs to have more features than expressly described in the claims. Rather, as reflected in the appended claims, inventive aspects may include fewer features than all the features of a single embodiment of the foregoing disclosure. Therefore, the detailed description of the preceding claims will be explicitly incorporated into this detailed description, and each claim in itself represents an independent embodiment of the invention.

[0051] Furthermore, when some embodiments described herein include, but are not included in, other features included in other embodiments, combinations of features from different embodiments are intended to be included within the scope of the invention and to form different embodiments, as will be understood by those skilled in the art. For example, any embodiment claimed in the appended claims may be used in any combination.

[0052] Furthermore, certain embodiments described herein are methods or combinations of method elements implemented by a processor of a computer system or by other means of implementing functionality. Thus, a processor having instructions required for implementing the method or method elements forms an apparatus for implementing the method or method elements. Furthermore, the elements of the device embodiments described herein are examples of apparatuses for performing functions performed by elements for implementing the objectives of the present invention.

[0053] Numerous specific details are set forth in this description. However, it should be understood that embodiments of the invention may be implemented without these specific details. In other instances, well-known methods, steps, and techniques have not been shown in detail to avoid obscuring the understanding of this specification.

[0054] The following terminology is provided merely to aid in understanding the invention.

[0055] As used herein, unless otherwise stated, when the term "III-V" is applied to materials, it refers to materials composed of at least one Group III (Group 13 in IUPAC) element and at least one Group V (Group 15 in IUPAC) element. This includes binary compounds as well as more advanced compounds, such as ternary compounds.

[0056] The present invention will now be described in detail by way of several embodiments thereof. It will be apparent that other embodiments of the invention can be constructed based on the knowledge of those skilled in the art without departing from the true technical teachings of the invention, which are limited only by the appended claims.

[0057] Reference transistors. These transistors are three-terminal devices having a first main electrode (e.g., drain), a second main electrode (e.g., source), and a control electrode (e.g., gate) for controlling the charge flow between the first and second main electrodes.

[0058] In a first aspect, the present invention relates to a method for forming a III-V group semiconductor structure.

[0059] This structure typically comprises multiple distinct III-V semiconductor layers. It is usually a III-V semiconductor device or an intermediate in the construction of a semiconductor device.

[0060] Group IV substrates are typically Si or Ge substrates (e.g., wafers), but Si substrates are the most common.

[0061] Figure 1 A single-crystal group IV substrate (1) (e.g., Si) is shown, wherein fins have been patterned using a hard mask (3) and covered with a dielectric layer (e.g., SiO2), the top surface of which is coplanar with the top surface of the hard mask (3). Then, Figure 1 The structure can be removed by a hard mask (3), and the single-crystal group IV substrate (1) can be selectively etched relative to the dielectric layer (3) to form the trenches of the component provided in step a. For example, if the substrate (1) is a Si substrate (1), the etching can be performed with tetramethylammonium hydroxide (TMAH). This has the advantage of forming the bottom of the V-shaped trench.

[0062] Figure 2 An example of the construction obtained in the implementation is shown after steps a to e.

[0063] Step a of the method in the first aspect includes: providing an assembly in an epitaxial growth chamber, the assembly comprising a single-crystal group IV substrate (1) and a first dielectric layer (2) thereon, the first dielectric layer comprising a trench with its bottom exposed to the group IV substrate (1).

[0064] To form this structure, the components are placed in an epitaxial growth chamber where growth conditions can be controlled. For example, a metal-organic vapor phase epitaxy (MOVPE) chamber can be used.

[0065] The first dielectric layer (2) on the single-crystal group IV substrate (1) is preferably an oxide layer. Preferably, it is a layer of oxide of the group IV material constituting the substrate (1). For example, if the substrate (1) is a Si substrate (1), the first dielectric layer (2) is preferably a silicon oxide layer, and the assembly comprises a Si substrate (1) and a silicon oxide layer thereon.

[0066] For example, the thickness of the first dielectric layer (2) can be 200 nm to 500 nm, such as 250 nm to 450 nm.

[0067] The first dielectric layer (2) includes trenches.

[0068] The component can be formed using a shallow trench isolation process, thereby creating one or more trenches in the dielectric layer. Defects are trapped within the trenches. Therefore, the trench width is preferably smaller than the trench depth. For example, the trench width is 1 / 6 to 1 / 2 of the thickness of the dielectric layer in which the trenches are located. For instance, if the dielectric layer thickness is 300 nm, the trench width can be 50 nm to 150 nm.

[0069] Preferably, the aspect ratio (trench depth relative to trench width) is greater than 1.43. This is advantageous because it allows for the capture of all defects caused by mismatch. The trench is fabricated via a dielectric layer, meaning it can be fabricated through direct physical contact between the trench and the group IV substrate (1). In some embodiments of the invention, the dielectric trench may have a V-shaped group IV bottom. This is advantageous because it avoids anti-phase disorder in the III / V layer. However, the invention is not limited thereto. For example, the bottom may also be flat.

[0070] The advantage of this embodiment of the invention is that strain-induced defects caused by lattice mismatch between the III-V material and the IV substrate (1) are trapped near the sidewalls of the trench at the III-V to IV interface. Therefore, the defect density at the overgrown top of the first III-V structure is significantly reduced, which is highly advantageous for device integration.

[0071] Step b of the method includes: initiating the growth of a first III-V structure in a trench, thereby forming the bottom portion (4) of the first III-V structure within the trench.

[0072] In some embodiments, in order to initiate the growth of the first III-V structure in the trench, precursors of the group III and group V elements of the III-V material constituting the first III-V structure can be introduced into the chamber.

[0073] The composition of each III-V structure in the first aspect (especially the first, second and third III-V structures (7, 7', 7'', 8)) and the composition of each layer constituting the third III-V structure (7, 7', 7'', 8) are as follows: they contain 50 atomic percent of group V atoms and 50 atomic percent of group III atoms.

[0074] In some implementations, the first III-V structure may include In x Ga1-x As z E 1-z , where 0≤x≤1, 0≤z≤1, and E is selected from P, Sb, and N.

[0075] In some implementations, 0.5 ≤ z ≤ 1. In a preferred implementation, z can be equal to 1.

[0076] In some implementations, the first III-V structure may include In x Ga 1-x As, where x is 0 to 1. The entire range from GaAs to InAs is suitable.

[0077] In some embodiments, 0.51 ≤ x ≤ 0.55, and z = 1. This is particularly suitable when the top III-V layer of the third III-V structure (7, 7', 7'', 8) is InP, as it allows for a good match between the lattice constant of the first structure and the lattice constant of InP. In this case, preferably 0.52 ≤ x ≤ 0.54, and z = 1, more preferably x = 0.53, and z = 1.

[0078] Preferably, the material of the first III-V structure is selected in such a way that the lattice constant of the material in the unstrained (i.e., relaxed) state is mismatched with the lattice of the top III-V layer material of the third III-V structure (7, 7', 7'', 8) in the unstrained (i.e., relaxed) state by a maximum of 1%, preferably a maximum of 0.5%.

[0079] Preferably, the material of the first III-V structure is selected in such a way that the lattice constant of the material in the unstrained (i.e., relaxed) state has a maximum mismatch of 1%, preferably a maximum of 0.5%, with respect to the lattice constant of the material of the top III-V layer and all layers in between of the third III-V structure (7, 7', 7'', 8).

[0080] Examples of precursors used to form the various III-V structures of the first aspect (especially the first, second, and third III-V structures (7, 7', 7'', 8)) and the layers of the third III-V structure (7, 7', 7'', 8) are: trialkyl gallium, such as triethyl gallium (TEGa) and trimethyl gallium (TMGa); trialkyl indium (e.g., trimethyl indium (TMIn)), alkylarsine (e.g., tert-butylarsine (TBA)), arsine (AsH3), trialkyl antimony (e.g., triethyl antimony (TESb) or trimethyl antimony (TMSb)), trialkyl aluminum (e.g., trimethyl aluminum (TMAl)), tert-alkylphosphine (e.g., tert-butylphosphine (TBP)), phosphine (PH3), and dialkylhydrazine (e.g., 1,1-dimethylhydrazine).

[0081] For example, when the first III-V structure can contain In x Ga 1-x When As (where x is from 0 to 1), the following precursor combinations can be used:

[0082] - TMGa, TMIn, TBAs;

[0083] - TMGa, TMIn, AsH3;

[0084] - TEGa, TMIn, TBAs; and

[0085] - TEGa, TMIn, AsH3.

[0086] The applied molar flux can, for example, be within the range of the following values:

[0087] For example, the molar flux of TMGa can be from 1.0E-5 to 2.0E-4 [mol / min], or more preferably from 1.5E-5 to 1E-4 [mol / min], or, for example, the molar flux of TEGa can be from 0.2E-5 to 2.0E-4 [mol / min], or more preferably from 1.0E-5 to 1E-4 [mol / min].

[0088] For example, the molar flux of TMIn can be 1.9E-5 to 1.9E-4 [mol / min], or more preferably 3.8E-5 to 1.5E-4 [mol / min].

[0089] The flux of TBA can be adjusted according to the flux of Ga + In moles per minute to meet a specific TBA / (TMGa+TMIn) or TBA / (TEGa+TMIn) ratio. This ratio is preferably 5 to 200, or even more preferably 10 to 80.

[0090] The flux of AsH3 can be adjusted according to the flux of Ga + In moles per minute to meet a specific AsH3 / (TMGa+TMIn) or AsH3 / (TEGa+TMIn) ratio. This ratio is preferably 50 to 1000, or even more preferably 50 to 500.

[0091] In some embodiments, step b can be performed in two stages. In the first stage, seed layer nucleation of the first III-V structure material can be achieved on the group IV surface, while in the second stage, the remaining trenches can be filled, thereby completing the bottom portion (4) of the first III-V structure. In some embodiments, the seed layer and the filling of the remaining trenches are performed under different growth conditions. The thickness of the seed layer can range from 5 nm to 30 nm.

[0092] In some embodiments, the seed layer (III-V nucleation on a group IV surface) can be carried out, for example, at 300°C to 450°C.

[0093] In some embodiments, filling the remaining trenches can be done, for example, at 350°C to 700°C, preferably 350°C to 500°C.

[0094] Typically, step b can be carried out at a temperature between 300°C and 500°C. Step c is typically carried out at a temperature at least equal to that used in step b to initiate growth.

[0095] The seed layer is advantageous because it provides good wettability to the next layer of the group IV (e.g., Si) substrate (1) and, together with the filler layer, compensates for the group IV substrate (1) (Si) and the first III-V structure (e.g., In). x Ga 1-x The lattice mismatch between As) does not affect the shape of the top portion of the first III-V structure.

[0096] In step c, the growth that begins in the trench continues to the outside of the trench located at the top of the bottom portion (4), thereby forming the top portion (5) of the first III-V structure.

[0097] In some implementations, the temperature in the chamber can be set to be at least 50°C higher during step c than during step b.

[0098] In some embodiments, the temperature in the chamber can be set to 400°C or higher when the top portion (5) of the first III-V structure grows outside the trench.

[0099] In some embodiments, at least one surfactant may be added to the chamber as the top portion (5) of the first III-V structure grows outside the trench. Preferably, no surfactant is added if penetrating dislocations are still present on the top surface of the growing III-V structure. Typically, surfactant is added only after the top surface of the growing III-V structure is free of penetrating dislocations. This is typically the case during step c. Therefore, it is preferable to add surfactant as the first III-V structure grows outside the trench. In some embodiments of the invention, surfactant may also be added in step b while the growth front of the first III-V structure is still within the trench. The optimal time to add surfactant is when the first III-V structure is fully relaxed and all penetrating dislocations are trapped in the trench sidewalls. In some embodiments, this may occur within the trench during step b. Depending on the trench depth, the moment when the first III-V structure is fully relaxed may be when the filler layer is still within the trench. For deeper trenches, the point where the III-V layer is fully relaxed and free of penetrating dislocations will be deeper within the trench.

[0100] Surfactants alter surface energy, thereby changing the migration length of atoms involved in the growth process of the first III-V structure. Surfactants change the properties of the crystal surface and thus alter the growth characteristics. An advantage of some embodiments of the invention is that, by using surfactants, first III-V structures with flat (001) surfaces can be obtained at higher temperatures than without surfactants. Therefore, funnel-shaped or box-shaped first III-V structures can be formed at high growth temperatures. Temperatures can be, for example, above 400°C, for example, above 500°C. Temperatures can be, for example, above 525°C. And temperatures can be, for example, from 500°C to 700°C or preferably from 525°C to 625°C. By increasing the temperature, not only can the relaxation degree of the trenches be improved, but also the migration rate of atoms and molecules on the surface can be improved. Without being limited to theory, it is speculated that adding a surfactant in step c reduces the migration rate of group III- and group V atoms already incorporated into the first III-V structure.

[0101] In embodiments of the present invention, at least one surfactant may be selected from a list of surfactants consisting of the following substances: gallium precursors (e.g., trialkylgallium, such as triethylgallium (TEGa) and trimethylgallium (TMGa)), indium precursors (e.g., trialkylindium, such as trimethylindium (TMIn)), arsenic precursors (e.g., alkylarsene, such as tert-butylarsene (TBAs) or arsene (AsH3)), antimony precursors (e.g., trialkylantimony, such as triethylantimony (TESb) or trimethylantimony (TMSb)), bismuth precursors (e.g., triphenylbismuth or trimethylbismuth), tellurium precursors (e.g., diethyltellurium), zinc precursors (e.g., dimethylzinc or diethylzinc), magnesium precursors (e.g., magnesia), manganese precursors (e.g., dicyclopentadienylmanganese), tin precursors (e.g., tin chloride), hydrogen chloride, carbon tetrabromide, chlorine, bromochloromethane (e.g., CCl3Br, CCl2Br2 and CClBr3), and carbon tetrachloride. The surfactant may not contain the group III or group V element used in step b to grow the first III-V structure. Preferably, the surfactant contains a group III or group V element different from the group III or group V element used in step b to grow the first III-V structure.

[0102] In some implementations, when the first III-V structure contains In x Ga 1-x As, where x is 0 to 1, the surfactant can be an Sb precursor, such as a trialkylantimony (e.g., TESb or TMSb). In this case, for example, for TESb or TMSb, the molar flux can range from 1.0E-5 to 6.5E-4, preferably 3.3E-5 to 3.2E-4 [mol / min].

[0103] In some embodiments, the amount of surfactant can be adjusted to be below 1E19cm. -3 And preferably below 1E20cm -3 The concentration is incorporated into the top portion of the first III-V structure. Preferably, no surfactant is incorporated into the first III-V structure. This is advantageous because it allows the surfactant to alter the growth characteristics without significantly changing the chemical properties of the III-V structure.

[0104] In some embodiments, the exposure time of the first III-V structure to the surfactant can be adjusted so that no surfactant is incorporated into the first III-V structure. This is advantageous because it allows the surfactant to alter the growth characteristics without changing the chemical properties of the III-V structure.

[0105] Preferably, the first III-V structure obtained at the end of step c has a flat (001) surface. Although a first III-V structure with a flat (001) surface can be grown at a low growth temperature, this tends to produce an inhomogeneous structure with a rough top (001) surface due to the low-temperature growth. This is detrimental to device integration. Therefore, it is advantageous to increase the growth temperature by adding a surfactant while still forming a flat (001) surface.

[0106] In some implementations, a plurality of first III-V structures are grown during steps b and c, and steps d to g are performed on each of the plurality of first III-V structures.

[0107] In some embodiments, the resulting plurality of first III-V structures all have the same shape and size. In other words, they can be uniform. Typically, the top surfaces of the plurality of III-V structures are coplanar. Therefore, an advantage of embodiments of the present invention is that it enables heteroepitaxial integration of coplanar and uniform III-V structures on a Si substrate (1) with a flat (001) surface for device integration.

[0108] In a preferred embodiment, the III-V semiconductor structure is grown using metal-organic vapor phase epitaxy (MOVPE). However, hydride vapor phase epitaxy or molecular beam epitaxy can also be used to implement the invention.

[0109] In hydride vapor-phase epitaxy, HCl reacts with Group III metals to produce gaseous chlorides, which then enter the deposition chamber. For Group V metals, hydrides and H2 are used as the carrier gas.

[0110] MBE primarily uses solid metal sources (such as Ga and As), but other types of sources are also possible. It is an ultra-high vacuum evaporation technique, therefore no carrier gas is required.

[0111] In some implementations, the carrier gas used to introduce the precursor in the chamber (e.g., the MOVPE chamber) can be, for example, N2 or H2. H2 is the preferred option.

[0112] In some embodiments, the pressure range in the chamber (e.g., the MOVPE chamber) can be, for example, from 5 tor to 450 tor, more preferably from 10 to 150 tor.

[0113] In some embodiments, during any of steps b to e, the total carrier gas flow rate can range from 10 liters / minute to 30 liters / minute, more preferably from 15 liters / minute to 25 liters / minute.

[0114] In some implementations, the first III-V structure can be a nanoridge.

[0115] Although the present invention has been described in terms of the formation of HEMT, the implementation of this method can be used to form other types of devices, such as silicon photonic devices, analog RF devices, imagers, etc.

[0116] In step d, a second III-V sacrificial structure (6) is grown on the top portion (5) of the first III-V structure. The second III-V sacrificial structure (6) is selectively etched relative to the first III-V structure in a liquid etching medium.

[0117] The second III-V sacrificial structure (6) is typically made of a material whose relaxed (i.e., unstrained) lattice parameters differ from those of the first III-V structure by ±1%, preferably ±0.5%.

[0118] Preferably, the second III-V sacrificial structure (6) is lattice-matched with the first III-V structure. The first III-V structure is composed of In... x Ga 1-x In embodiments made of As (wherein 0.51 ≤ x ≤ 0.55, preferably 0.52 ≤ x ≤ 0.54, and more preferably x = 0.53), the second III-V sacrificial structure can be InP. This is advantageous because InP can be relative to In x Ga 1-x As (where 0.51 ≤ x ≤ 0.55) is selectively etched, and because InP and In x Ga 1-x As (where x = 0.53) lattice matching.

[0119] Examples of precursors used to form InP are TMI and TBP or PH3.

[0120] For example, the flux of TMIn can range from 1.9E-5 to 1.9E-4 [mol / min], or more preferably from 2.9E-5 to 1.6E-4 [mol / min]. The flux of TBP can be adjusted to meet a specific TBP / TMIn ratio. This ratio is preferably from 5 to 400, or even more preferably from 10 to 200.

[0121] The flux of pH3 can be adjusted to achieve a specific pH3 / TMIn ratio. This ratio is preferably 50 to 1000, or even more preferably 50 to 600.

[0122] For example, InP can be grown at temperatures ranging from 400°C to 700°C, preferably from 475°C to 625°C.

[0123] The liquid etching medium is selected such that it can etch the second III-V structure (6) without etching the bottom III-V layer (7) of the first III-V structure or the third III-V structure (7, 7', 7'', 8).

[0124] For example, concentrated HCl can be used to selectively etch InP relative to InGaAs.

[0125] In step e, a third III-V structure (7,7',7'',8) is epitaxially grown on the second III-V sacrificial structure (6), wherein the third III-V structure (7,7',7'',8) comprises:

[0126] i. A bottom III-V layer (7) on the second III-V sacrificial structure (6), wherein the second III-V sacrificial structure (6) is selectively etched relative to the bottom layer in a liquid etching medium; and

[0127] ii. Top III-V layer.

[0128] The bottom III-V layer (7) is typically made of a material whose relaxed (i.e., unstrained) lattice parameters differ from those of the second III-V sacrificial structure (6) by ±1%, preferably ±0.5%.

[0129] In some implementations, the bottom III-V layer (7) may contain In y Al 1-y As, where y is from 0.51 to 0.53, preferably y is 0.52. In other embodiments, the bottom III-V layer (7) may contain In. w Ga 1-w As, where w is 0.52 to 0.54, preferably w is 0.53. When the sacrificial layer is InP, the bottom III-V layer (7) is In. y Al 1-y As or In w Ga 1-w These embodiments of As are particularly advantageous because the lattice constants of these materials are close to or even match those of InP. Furthermore, InP can be selectively removed relative to these layers using a liquid etching medium.

[0130] In some embodiments, the lattice constants of the materials constituting the first III-V structure, the materials constituting the second III-V sacrificial structure (6), and the materials constituting the layers of the third III-V structure (7, 7', 7'', 8) differ from each other by ±1%, preferably ±0.5%. Preferably, all the materials constituting the first III-V structure, the materials constituting the second III-V sacrificial structure (6), and the materials constituting the layers of the third III-V structure (7, 7', 7'', 8) are lattice-matched.

[0131] In some implementations, the top III-V layer may comprise InP. This is particularly advantageous because InP has electron mobility and saturation velocity compatible with ultra-high frequency device applications operating at 1 GHz or higher.

[0132] In some implementations, the third III-V structure (7, 7', 7'', 8) may include the bottom first In y Al 1- y As layer, bottom first In y Al 1-y In on the As layer w Ga 1-w As layer, in In w Ga 1-w The second In above and above the As layer y Al 1-y As layer (therefore In) w Ga 1-w As layer sandwiched between two In layers y Al 1-y Between As layers), and in the second In y Al 1-y A top InP layer on top of the As layer, wherein y is 0.51 to 0.53, and preferably y is 0.52, and w is 0.52 to 0.54, and preferably w is 0.53. These embodiments are particularly suitable for forming HEMTs. y Al 1-y As has a higher band gap than In. w Ga 1-w As. (In) w Ga 1-w As layer sandwiched in In y Al 1- y The As layers are connected using In w Ga 1-w As layers form quantum wells. As a result, In w Ga 1-w The As layer is used as a high-mobility channel layer that can carry most of the charge carriers.

[0133] In some implementations, In can be at the top and / or bottom y Al 1-y Delta doping is performed in the As layer. This is advantageous because, during quantum well formation, carriers supplied by the dopant fall into the In channel. w Ga 1-w An As layer is formed, creating a 2D electron gas that can be used for carrier conduction. Because the channels remain undoped, they can provide very high carrier mobility.

[0134] Figure 3 An example of the construction according to an embodiment of the present invention is shown after step f11.

[0135] In step f, the first portion (8') of the top layer (8) of the third III-V structure (7, 7', 7'', 8) is physically disconnected from its second portion (8''). In other words, by creating a gap between the first portion (8) and its second portion (8'') of the top layer (8), the top layer (8) of the third III-V structure (7, 7', 7'', 8) can be made discontinuous. For this purpose, typically, the first portion of the entire third III-V structure (7, 7', 7'', 8) can be physically disconnected from its second portion.

[0136] In some implementations, step f may include the following steps:

[0137] f1. A passivation layer (10) is formed on the exposed surface of the component and the top III-V layer (8);

[0138] f2. The passivated third III-V structure (7, 7', 7'', 8) is embedded in the second dielectric layer (9) so that the top surface of the second dielectric layer (9) is coplanar with the passivation layer (10).

[0139] f3. The top portion of the top III-V layer (8) is exposed by etching away the top portion of the passivation layer (10) using a dielectric layer as a mask.

[0140] f4. Cover the exposed top portion of the top III-V layer (8) and the exposed portion of the second dielectric layer (9) with the third dielectric layer (12).

[0141] f5. A mask element (e.g., photoresist) is formed on the first portion (8') of the top III-V layer (8).

[0142] f6. The third dielectric layer (12) is etched using a mask element as a mask until a portion of the top III-V layer (8) and a portion of the passivation layer (10) are exposed, and

[0143] f7. The third III-V structure (7, 7', 7'', 8) is etched using a mask element, a passivation layer (10), and a third dielectric layer (12) as a mask, thereby physically separating the first portion (8') of the top layer (8) from its second portion (8''). At the end of step f7, a trench (11) is present, which separates the first portion (8') from the second portion (8'').

[0144] At this stage, the first part (8') of the third III-V structure (7, 7', 7'', 8) is usually physically disconnected from its second part (8'').

[0145] Other steps aimed at preparing step f' could be:

[0146] f8. Remove mask elements

[0147] f9. A second passivation layer (13) is conformally formed on the structure obtained after step f.

[0148] f10. Another dielectric layer is formed on the second passivation layer (13).

[0149] f11. Planarize the top surface of the structure obtained in g2 (e.g., by chemical mechanical planarization) until the top surface of the second passivation layer (13) is exposed.

[0150] f12. Further planarize until the first part (8') of the top III-V layer (8) is exposed.

[0151] In some embodiments, the III-V semiconductor structure may be a field-effect transistor (e.g., a HEMT), and the method may include step f', performed between or after step g: exposing a first portion (8') of the third III-V structure (7,7', 7'', 8) and forming thereon a source (20), a drain (21), and a gate stack (14, 16). The gate stack typically includes a gate dielectric (14) and a gate metal (16). Spacers (15) are typically present on either side of the gate stack.

[0152] Figure 4 and Figure 5 An example of the construction according to an embodiment of the present invention is shown after step f' and before step g.

[0153] In some implementations, step f' may include the following steps:

[0154] f'1. A dummy gate is formed on the first portion of the top III-V layer.

[0155] f'2. Spacers are formed on the sidewalls of the dummy gate.

[0156] f'3. On the first part of the top layer, a source (20) is grown on one side of the dummy gate, and a drain (21) is grown on the other side of the dummy gate.

[0157] f'4. Replacing the dummy gate with a metal gate, and

[0158] f'5. Form a contact (17) with the source (20), drain (21) and metal gate.

[0159] Step f' is usually performed after step f and before step g.

[0160] When step f' is performed only after step h, it is preferable to perform step f' after step g (see below). In fact, it is advantageous to form the source (20) / drain (21) and gate when the mechanical stability of the structure is improved by first filling the cavity (23) with dielectric material (24).

[0161] In some implementations, the gate may have a T-shape.

[0162] exist Figure 4 and Figure 5 In this process, an additional passivation layer (18) and an additional dielectric layer (19) are used to pattern the top gate and obtain a “T-shape”.

[0163] In step g, the second III-V sacrificial structure (6) is brought into contact with a liquid etching medium, thereby selectively etching the second III-V sacrificial structure (6) relative to the first III-V structure and the bottom layer, thereby forming a chamber (23).

[0164] In some implementations, step g may include the following steps:

[0165] g1. Expose the second III-V sacrificial structure (6), and

[0166] g2. The second III-V sacrificial structure (6) is brought into contact with a liquid etching medium, thereby selectively etching the second III-V sacrificial structure (6) relative to the first III-V structure and the bottom layer, thereby forming a chamber (23).

[0167] An example of the structure obtained from step g1 can be found in Figure 6 Found it.

[0168] An example of the structure obtained from step g2 can be found in Figure 7 Found it.

[0169] In some embodiments, the method may further include step h after step g: filling the cavity (23) with a dielectric material (24). This is advantageous because it improves the mechanical stability of the device.

[0170] An example of the structure obtained from step h can be found in Figure 8 Found it.

[0171] Figure 9 and Figure 10 It is shown that, in the case of forming multiple transistors (e.g., HEMT) by this method, two different layout strategies are able to enter the second III-V sacrificial structure (6) to make it contact the liquid etching medium. Many other possible layers exist. Typically, the entry point into the second III-V sacrificial structure (6) is formed outside the transistor, for example, in the region between the transistors. In these figures, the entry point (22) and the gate exposing the second III-V sacrificial structure (6) are identified.

[0172] In a second aspect, the present invention relates to a III-V semiconductor structure comprising:

[0173] a. An assembly comprising a single-crystal group IV substrate (1) and a first dielectric layer (2) thereon, the first dielectric layer (2) comprising a trench with its bottom exposed to the group IV substrate (1),

[0174] b. A first III-V structure, comprising a bottom portion (4) within a trench and a top portion (5) on top of the bottom portion (4) outside the trench.

[0175] c. A cavity (23) or dielectric structure on the top portion (5) of the first III-V structure,

[0176] d. A third III-V III-V structure (7,7',7'',8) on the chamber (23) or dielectric structure, the third III-V structure (7,7',7'',8) comprising a bottom III-V layer (7) and a top III-V layer on the chamber (23) or dielectric structure, the top III-V layer comprising a first portion (8') physically disconnected from the second portion (8'').

[0177] In some implementations, the top portion (5) may be wider than the bottom portion (4).

[0178] In some embodiments, the III-V semiconductor structure can be obtained through any of the embodiments of the first aspect.

[0179] Similarly, any feature of the second aspect described in the first aspect can also be described accordingly.

[0180] It should be understood that while preferred embodiments, specific constructions and configurations, and materials have been discussed for the apparatus of the present invention, various changes or modifications in form and detail may be made without departing from the scope of the invention. Steps may be added to or reduced from the methods described within the scope of the invention.

Claims

1. A method for forming a III-V semiconductor structure on a single-crystal group IV substrate (1), the method comprising: a. Providing an assembly in an epitaxial growth chamber, the assembly comprising a single-crystal group IV substrate (1) and a first dielectric layer (2) thereon, the first dielectric layer (2) comprising a trench with its bottom exposed to the group IV substrate (1), b. The first III-V structure begins to grow in the trench, thereby forming the bottom portion (4) of the first III-V structure within the trench. c. Growth continues outside the groove located at the top of the bottom portion (4), thereby forming the top portion (5) of the first III-V structure. d. A second III-V sacrificial structure (6) is epitaxially grown on the top portion (5) of the first III-V structure. The second III-V sacrificial structure (6) is selectively etchable in the liquid etching medium relative to the first III-V structure (4, 5). e. Epitaxially growing a third III-V structure (7,7',7'',8) on the second III-V sacrificial structure (6), wherein the third III-V structure (7,7',7'',8) comprises: i. A bottom III-V layer (7) on the second III-V sacrificial structure (6), wherein the second III-V sacrificial structure (6) is selectively etchable in a liquid etching medium relative to the bottom III-V layer (7). ii. Top III-V layers, f. Physically disconnect the first part (8') of the top layer of the third III-V structure (7, 7', 7'', 8) from its second part (8''), and g. The second III-V sacrificial structure (6) is brought into contact with a liquid etching medium, thereby selectively etching the second III-V sacrificial structure (6) relative to the first III-V structure (4,5) and the bottom layer (7) to form a chamber (23).

2. The method as described in claim 1, wherein, The single-crystal group IV substrate (1) is a single-crystal silicon substrate (1).

3. The method as claimed in claim 1 or claim 2, wherein, The exposed group IV substrate (1) at the bottom of the trench is V-shaped.

4. The method as claimed in claim 1 or claim 2, wherein, The first III-V structure (4, 5) contains In x Ga 1- x As z E 1-z , where 0≤x≤1, 0≤z≤1, and E is selected from P, Sb, and N.

5. The method as claimed in claim 1 or claim 2, wherein, The second III-V sacrificial structure (6) contains InP.

6. The method as claimed in claim 1 or claim 2, wherein, The bottom III-V layer (7) comprises: In y Al 1-y As, where y is between 0.51 and 0.53; or In w Ga 1-w As, where w is between 0.52 and 0.

54.

7. The method as claimed in claim 1 or claim 2, wherein, The top III-V layer (8) contains InP.

8. The method of claim 6, wherein, The third III-V structure (7, 7', 7'', 8) includes a bottom first In y Al 1-y As layer (7), bottom first In y Al 1-y In on the As layer w Ga 1-w As layer (7'), in In w Ga 1-w The second In above and above the As layer y Al 1-y As layer (7''), and in the second In y Al 1-y The top InP layer (8) on the As layer (7''), thus In w Ga 1- w As layer (7') sandwiched between two In layers y Al 1-y Between layers (7, 7'') of As.

9. The method of claim 7, wherein, The third III-V structure (7, 7', 7'', 8) includes a bottom first In y Al 1-y As layer (7), bottom first In y Al 1-y In on the As layer w Ga 1-w As layer (7'), in In w Ga 1-w The second In above and above the As layer y Al 1-y As layer (7''), and in the second In y Al 1-y The top InP layer (8) on the As layer (7''), thus In w Ga 1- w As layer (7') sandwiched between two In layers y Al 1-y Between layers (7, 7'') of As.

10. The method of claim 1 or claim 2, wherein, The III-V semiconductor structure is a field-effect transistor, and the method includes step f', performed between or after step f: exposing a first portion (8') of the top layer (8) of the third III-V structure (7,7', 7'', 8) and forming a source (20), a drain (21) and a gate stack (16, 14) thereon.

11. The method of claim 10, wherein, Field-effect transistors are high electron mobility transistors.

12. The method as claimed in claim 1 or claim 2, wherein, The method further includes step h after step g: filling the chamber (23) with dielectric material (24).

13. The method as claimed in claim 1 or claim 2, wherein, When the top portion (5) grows outside the groove, the temperature in the chamber is set to 400°C or higher.

14. The method as claimed in claim 1 or claim 2, wherein, When the top portion (5) grows outside the trench, at least one surfactant is added to the chamber.

15. A III-V semiconductor structure comprising: a. An assembly comprising a single-crystal group IV substrate (1) and a first dielectric layer (2) thereon, the first dielectric layer (2) comprising a trench with its bottom exposed to the group IV substrate (1), b. A first III-V structure (4, 5), comprising a bottom portion (4) within the trench and a top portion (5) on top of the bottom portion (4) outside the trench. c. A cavity (23) or dielectric structure (24) on the top portion (5) of the first III-V structure. d. A third III-V structure (7,7',7'',8) on the chamber (23) or dielectric structure (24), the third III-V structure (7,7',7'',8) comprising a bottom III-V layer (7) and a top III-V layer on the chamber (23) or dielectric structure, the top III-V layer comprising a first portion (8') physically disconnected from the second portion (8'').

16. The III-V semiconductor structure as described in claim 15, wherein, The top part (5) is wider than the bottom part (4).

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