Device and method for controlling word line discharge

Abstract

Disclosed herein are apparatus and methods for driving word driver lines in a progressive manner. A word driver line may be driven to an intermediate potential between a high and a low potential. In some examples, the word driver line may be driven in a stepwise manner. In some examples, the intermediate potential may be a bias voltage. The bias voltage may be provided by a bias voltage generator. One or more enable signals may be used to control the driving of the word driver line. In some examples, an address signal may be used to control the driving of the word driver line. In some examples, driving the word driver line in a progressive manner may cause the word line to discharge in a progressive manner.

Description

Background Art

[0001] A semiconductor memory device represented by a DRAM (dynamic random access memory) includes a memory cell array having memory cells disposed at intersections between word lines and bit lines. The semiconductor memory device may include a hierarchically structured main word line and a sub-word line. The main word line is a word line located at an upper level and is selected by a first portion of a row address. The sub-word line is a word line located at a lower level and is selected based on a corresponding main word line (MWL) and a word driver line (FXL) selected by a second portion of a row address.

[0002] A memory cell array included in a semiconductor memory device such as a DRAM can be divided into a plurality of memory pads to reduce wiring capacitance of sub-word lines and bit lines. Each memory pad includes a corresponding main word line, so that when the main word line is selected using the first part of a row address, the memory pad to be selected is also determined at the same time.

[0003] The driving process of the sub-word line is implemented by the sub-word driver, and when the sub-word line is driven to a high potential, the memory cell is coupled to the corresponding bit line. On the other hand, during the period in which the sub-word line is driven to a low potential, the memory cell and the bit line remain in a cut-off state. As used herein, a low potential is a potential associated with a low logic level and / or an inactive state. When the sub-word line is driven to a high potential, a relatively high voltage is provided to the sub-word driver of the memory pad. As used herein, a high potential is a potential associated with a high logic level and / or an active state. Conversely, when the sub-word line is driven to a low potential, a relatively low voltage is provided to the sub-word driver of the memory pad.

[0004] Repeated access to a particular sub-wordline (commonly referred to as "row hammer") can cause an increased rate of data degradation for nearby sub-wordlines. It is desirable to reduce the effects of row hammer events. Summary of the invention

[0005] As described herein, the discharge of the sub-word line can be controlled by driving the word driver line FXL in a progressive manner (e.g., in a stepwise manner). The sub-word line may be discharged at a slower rate than when FXL is driven directly between active and inactive states. The discharge rate of the sub-word line may be based at least in part on the value of the intermediate potential of FXL between active and inactive states. As described herein, the word driver line FXL may include multiple drive lines for providing multiple drive signals. The drive signal of FXL may be driven to active and inactive states at different times. The timing of driving the FX signal may provide control over the discharge of the word line. Driving the word line FXL in a progressive manner may be used in combination with activating and deactivating the drive signal at different times to control the discharge of the sub-word line. Controlling the discharge of the sub-word line may reduce the impact of a row hammering event.

[0006] According to at least one example disclosed herein, an apparatus may include: a sub-word driver configured to drive a sub-word line; and a word driver configured to provide a first drive signal to the sub-word driver, wherein the word driver is further configured to drive the first drive signal to an intermediate potential when driving the first drive signal between an active state and an inactive state, wherein the intermediate potential has a value between a high potential and a low potential.

[0007] According to at least one example disclosed herein, an apparatus may include: a control circuit configured to receive a first enable signal and output an intermediate voltage in response to the first enable signal; a plurality of word drivers coupled to the control circuit, each of the plurality of word drivers being configured to receive an address signal, receive a second enable signal, and provide a first drive signal, wherein when the address signal, the first enable signal, and the second enable signal are in an active state, the first drive signal is provided in an active state, and wherein when the address signal and the second enable signal are in an active state and the first enable signal is in an inactive state, the first drive signal is provided at the intermediate voltage. The apparatus may include a plurality of sub-word drivers configured to receive the first drive signal from respective ones of the plurality of word drivers, each of the plurality of sub-word drivers being configured to drive a corresponding sub-word line.

[0008] According to at least one example disclosed herein, an apparatus may include: a sub-word driver configured to drive a sub-word line; and a word driver configured to provide a first drive signal and a second drive signal to the sub-word driver, wherein in response to activation of the first drive signal and the second drive signal, the sub-word line is driven to a high potential, and in response to deactivation of the first drive signal, the sub-word line is discharged to an intermediate sub-word line voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 2 is a diagram of a layout of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 3 is a diagram showing a configuration of a bank of a memory cell array of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 4 is a schematic diagram of a portion of a memory bank of a memory cell array according to an embodiment of the present disclosure.

[0013] Figure 5 is a circuit diagram of a word driver according to an embodiment of the present disclosure.

[0014] Figure 6 is a timing diagram of various signals during operation of a driver circuit according to an embodiment of the present disclosure.

[0015] Figure 7 is a circuit diagram of a word driver according to an embodiment of the present disclosure.

[0016] Figure 8 is a timing diagram of various signals during operation of a driver circuit according to an embodiment of the present disclosure.

[0017] Fig. 9 is a block diagram of a plurality of word drivers according to an embodiment of the present disclosure.

[0018] Fig.10 is a circuit diagram of a bias voltage generator according to an embodiment of the present disclosure.

[0019] Fig.11 is a circuit diagram of a bias voltage generator according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] Certain details are set forth below to provide a full understanding of the examples of various embodiments of the present disclosure. However, it will be clear to those skilled in the art that the examples described herein can be practiced without these specific details. In addition, the specific examples of the present disclosure described herein should not be interpreted as limiting the scope of the present disclosure to these specific examples. In other examples, in order to avoid unnecessarily obscuring the embodiments of the present disclosure, known circuits, control signals, timing protocols, and software operations are not shown in detail. In addition, terms such as "coupled" and "coupled" mean that two components can be electrically coupled directly or indirectly. Indirect coupling may mean that two components are coupled through one or more intermediate components.

[0021] A semiconductor memory device may include hierarchically structured main word lines and sub-word lines. The main word line is a word line located at an upper level and is selected by a first portion of a row address. The sub-word line is a word line located at a lower level and is selected based on a corresponding main word line (MWL) and a word driver line (FXL), which is selected by a second portion of a row address. The MWL may be driven by a main word driver (MWD), and the word driver line FXL may be driven by a word driver (FXD). Both the MWL and FXL must be driven to an active state to select a desired sub-word line in the memory device.

[0022] Some studies have shown that data degradation due to row hammering events may be caused by free electrons generated in the back gate region when the channel of the transistor disappears. Without being bound by a particular theory, in some applications, the row hammering effect can be mitigated by reducing the channel dissipation rate. As described herein, the discharge of the sub-word line can be controlled. For example, the discharge rate and / or the voltage to which the sub-word line is discharged can be controlled. As described herein, in some embodiments, the discharge of the sub-word line can be controlled by driving the word driver line FXL in a progressive manner (e.g., in a stepwise manner). The sub-word line may be discharged at a slower rate than when FXL is driven directly between active and inactive states. In some embodiments, the discharge rate of the sub-word line may be based at least in part on the value of the intermediate potential of FXL between active and inactive states. As described herein, the word driver line FXL may include multiple drive lines for providing multiple drive signals. In some embodiments, the drive signal of FXL may be driven to active and inactive states at different times. In some embodiments, the timing of driving the FX signal can provide control over the discharge of the word line. In some embodiments, driving the word line FXL in a gradual manner can be used in conjunction with activating and deactivating the drive signal at different times to control the discharge of the sub-word lines. In some applications, controlling the discharge of the sub-word lines can reduce the effects of row hammering events.

[0023] Figure 1 1 is a block diagram of a semiconductor device 10 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the semiconductor device 10 may be a dynamic random access memory (DRAM). The semiconductor device 10 includes a memory cell array 11. The memory cell array 11 includes a plurality of sub-word lines SWL and a plurality of bit lines BL intersecting each other, wherein memory cells MC are disposed at the intersections. SWL may be driven by a sub-word driver SWD. For clarity, Figure 1 1 and 12. Only one SWL, SWD, BL and MC is shown in FIG. 1. A plurality of main word lines MWL and word driver lines FXL are coupled between the row decoder circuit 12 and SWD. The selection of the main word lines MWL and word driver lines FXL is performed by the row decoder circuit 12, and the selection of the bit lines BL is performed by the column decoder circuit 13. The sense amplifier 18 is coupled to the corresponding bit line BL and to the local I / O line pair LIOT / B. The local IO line pair LIOT / B is coupled to the main IO line pair MIOT / B via the transfer gate TG 19, which serves as a switch for the read / write amplifier and buffer 15.

[0024] Turning to the explanation of the plurality of external terminals included in the semiconductor device 10 , the plurality of external terminals include an address terminal 21 , a command terminal 22 , a clock terminal 23 , a data terminal 24 , and power supply terminals 25 and 26 .

[0025] The address terminal 21 is supplied with an address signal ADD. The address signal ADD is supplied to the address terminal 21 and is transmitted to the address decoder circuit 32 via the command / address input circuit 31. The address decoder circuit 32 receives the address signal ADD and supplies a decoded row address signal XADD to the row decoder circuit 12 and a decoded column address signal YADD to the column decoder circuit 13.

[0026] The command terminal 22 is provided with a command signal COM. The command signal COM may include one or more separate signals. The command signal COM input to the command terminal 22 is input to the command decoder circuit 34 via the command / address input circuit 31. The command decoder circuit 34 decodes the command signal COM to provide various internal command signals. For example, the command decoder circuit 34 may activate the activation signal ACT in response to an activation command and / or activate the refresh signal REF in response to a refresh command. For example, the internal command may include a row command signal for selecting a word line and a column command signal for selecting a bit line, such as a read command or a write command.

[0027] When a row activation command is issued and the row address is provided with an activation command in a timely manner and the column address is provided with a read command in a timely manner, read data is read from the memory cell MC specified by these row addresses and column addresses in the memory cell array 11. More specifically, the row decoder circuit 12 selects the main word line MWL, the word driver line FXL and the sub-word line SWL indicated by the row address RA indicated by XADD, so that the associated memory cell MC is then coupled to the bit line BL. The read data DQ is output from the outside of the data terminal 24 via the read / write amplifier 15 and the input / output circuit 17. Similarly, when a row activation command is issued and the row address is provided with an activation command in a timely manner and the column address is provided with a write command in a timely manner, the input / output circuit 17 can receive the write data DQ at the data terminal 24. The write data DQ is provided to the memory cell array 11 via the input / output circuit 17 and the read / write amplifier 15, and is written into the memory cell MC specified by the row address and the column address.

[0028] In some embodiments, row decoder circuit 12 may include enable signal circuit 40. Enable signal circuit 40 may receive activation signal ACT from command decoder circuit 34. In response to activation signal ACT, enable signal circuit 40 may provide one or more enable signals to one or more word drivers (not shown) included in row decoder circuit 12. As will be explained in more detail, the enable signals may be used to drive word driver line FXL in a progressive manner. In some applications, this may provide control over the discharge of sub-word line SWL.

[0029] The device 10 may include a refresh control circuit 16 for performing a refresh operation. The refresh operation may be an auto-refresh operation and / or other refresh operations. In some embodiments, a refresh command may be issued externally to the device 10 and provided to the command decoder circuit 34, which provides the command to the refresh control circuit 16 and the row decoder circuit 12. In some embodiments, the refresh command may be provided periodically by a component of the device 10 (e.g., provided internally by the refresh control circuit 16 or the command decoder circuit 34). The refresh control circuit 16 may provide a refresh address R_ADD to the row decoder circuit 12, which may indicate a row address for performing a refresh operation.

[0030] The clock terminals 23 are provided with external clock signals CK and / CK, respectively. These external clock signals CK and / CK are complementary to each other and are provided to the clock input circuit 35. The clock input circuit 35 receives the external clock signals CK and / CK and provides an internal clock signal ICLK. The internal clock signal ICLK is provided to the internal clock generator 36, and thus a phase-controlled internal clock signal LCLK is provided based on the received internal clock signal ICLK and the clock enable signal CKE from the command / address input circuit 31. Although not limited to this, a DLL circuit can be used as the internal clock generator 36. The phase-controlled internal clock signal LCLK is provided to the input / output circuit 17 and used as a timing signal for determining the output timing of the read data DQ.

[0031] The power supply terminal 25 is provided with power supply voltages VDD1, VDD2 and VSS. These power supply voltages VDD1, VDD2 and VSS are provided to the internal voltage generator circuit 39. The internal voltage generator circuit 39 provides various internal voltages VPP, VOD, VARY, VPERI, VEQ, VCCP, VDRV and VKK.

[0032] The internal potentials VCCP, VDRV, and VKK are potentials to be mainly used in the row decoder circuit 12. For example, in some embodiments, VKK may be used as a low potential, and VCCP may be used as a high potential. Although a detailed description thereof will be given later, the row decoder circuit 12 drives the main word line MWL and the sub word line SWL selected based on the address signal ADD to a VCCP level corresponding to a high potential (e.g., 3.1V), so that the cell transistors of the memory cells MC are turned on.

[0033] The internal potentials VARY and VEQ are potentials to be used by the sense amplifier 18, the transfer gate 19, and / or the read / write amplifier 15. When the sense amplifier 18 is activated, the read data read out is amplified by driving one of the paired bit lines to the VARY level and the other to the VSS level. The internal potential VPERI is used as a power supply potential for most peripheral circuits (such as the command / address input circuit 31). By using the internal potential VPERI having a potential lower than the external potential VDD as the power supply potential for these peripheral circuits, it is possible to reduce the power consumption of the semiconductor device 10.

[0034] The power supply terminal 26 is provided with power supply voltages VDDQ and VSSQ. These power supply voltages VDDQ and VSSQ are provided to the input / output circuit 17. The power supply voltages VDDQ and VSSQ may be the same voltages as the power supply voltages VDD2 and VSS respectively provided to the power supply terminal 25. However, dedicated power supply voltages VDDQ and VSSQ may be used for the input / output circuit 17 so that power supply noise generated by the input / output circuit 17 is not propagated to other circuit blocks of the device 10.

[0035] Figure 2 is a diagram of an example layout of a memory cell array of a semiconductor device according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the memory cell array may include Figure 1 In the memory cell array 11 of the semiconductor device 10 shown in FIG.

[0036] Figure 2 The memory cell array 200 of the example shown in FIG. 1 is divided into 16 memory banks BK0 to BK15. The row decoder circuit (eg, Figure 1 The row decoder circuit 12; not in Figure 2 The peripheral circuit region PE may be arranged between adjacent memory cells and / or in the peripheral circuit region PE. In the peripheral circuit region PE, various peripheral circuits and external terminals ( Figure 2 not shown).

[0037] Figure 3 3 is an example configuration diagram of a memory bank 300 of a memory cell array according to an embodiment of the present disclosure. In some embodiments of the present disclosure, Figure 2 Each of the memory banks BK0 to BK15 may include Figure 3 In some embodiments, the memory bank 300 may include Figure 1 In the memory cell array 11 of the semiconductor device 10 shown in FIG.

[0038] like Figure 3 As shown in FIG. 1 , the memory bank 300 includes a plurality of memory pad areas MAT0 to MAT3. Figure 3 In the example shown in FIG. 3 , the memory bank 300 has four memory mat areas, but in other examples, the memory bank 300 may include more or fewer memory mat areas. As indicated by the dotted lines in the memory mat area MAT1, each memory mat area may be divided into a plurality of sub-areas SUBMAT1-0 to 3. Although Figure 3 The example shown in FIG. 1 includes four sub-regions, but in other examples, the memory pad regions MAT0-3 may include more or fewer sub-regions. Each sub-region SUBMAT1-0-3 may include multiple memory pads (e.g., 32, 64, 128) aligned in the Y direction. In some embodiments, the multiple memory pads in a sub-region may be further subdivided into groups. For example, SUBMAT1-0 may include 64 memory pads, and the memory pads may be organized into eight groups of eight. For clarity, Figure 3 Individual memory pads are not shown in FIG. 1. In some embodiments, the memory pads of each sub-area SUBMAT1-0 to 3 may be associated with corresponding IOs (eg, DQ pads).

[0039] The sub-word driver operation is performed by the row decoder circuit ( Figure 3 not shown) (e.g. Figure 1 When a row address RA is inputted thereto, the row decoder selects a sub-word line by activating the appropriate main word driver (MWD) and the appropriate word driver (FXD) indicated by the row address RA. Figure 3 In the example shown in , one block is shown for the main word drivers MWD, however, the main word driver MWD block may include multiple main word drivers MWD. ​​Similarly, two blocks are shown for the word drivers FXD, but each word driver FXD block may include multiple word drivers FXD. For example, if each memory pad area MAT includes four sub-areas and each sub-area includes 64 memory pads, then the main word driver MWD block may include 128 MWDs, each of which is configured to activate a corresponding main word line (MWL). Continuing with this example, each word driver FXD block may include eight word drivers FXD, each of which is configured to activate a corresponding word driver line (FXL). In Figure 3 In the example shown in FIG. 1 , bits 3 to 15 of the row address RA encode the main word line MWL, and bits 0 to 2 of the row address RA encode the word driver line FXL. However, other encoding schemes may be used.

[0040] Figure 4 is a schematic diagram of a portion of a storage body 400 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, Figure 4 The portion of memory bank 400 shown in FIG. 4 may be included in Figure 3 The storage body 300, Figure 2 The memory cell array 200 and / or Figure 1In the memory cell array 11.

[0041] The sub-word lines are adjacent to each other and driven by sub-word drivers SWD0 to 7 of different sub-word driver groups. Corresponding main word signals (not shown), drive signals FX, and low potentials VKK / Gnd (not shown) are provided to the sub-word drivers SWD0 to 7. In some embodiments, the main word signals and drive signals FX may be respectively provided by a row decoder circuit (e.g., Figure 1 The main word drivers MWD0 to N and the word driver FXD 404 in the row decoder circuit 12) shown in FIG. Figure 3 The row address RA described above provides the signal. The main word signal is transmitted through the main word line ( Figure 4 4 ) is provided to the sub-word drivers SWD0 to 7, and the driving signal FX is provided to the sub-word drivers SWD0 to 7 through the word driver line 402.

[0042] The main word line MWL may be located at a corresponding memory pad (eg, Figure 3 The main word driver MWD 404 extends over the array area of ​​the memory pads (in the memory pads SUBMAT1-0 in the memory pads) to provide a main word signal to the sub-word driver group of the memory pads to activate the sub-word drivers SWD0 to 7 of the memory pads. That is, when the main word driver MWD is activated, it can provide an active main word signal to all the sub-word drivers SWD0 to 7 of the pad. As will be described below, the drive signal FX includes complementary signals FXT and FXF. Each word driver line 402 of the word driver FXD 404 provides a drive signal FX to at least one sub-word driver SWD in each pad. In Figure 4 In the example shown in FIG. 4 , word driver FXD 404 includes an even word driver 406 and an odd word driver 408. Even word driver 406 provides corresponding drive signals to even-numbered sub-word drivers SWD0, SWD2, SWD4, and SWD6 of each memory pad, and odd word driver 408 provides corresponding drive signals to odd-numbered sub-word drivers SWD1, SWD3, SWD5, and SWD7 of each memory pad. However, other arrangements may be used in other examples. Figure 4 In the example shown in , each line of word driver FXD can be coupled to a corresponding sub-word driver SWD0 to 7 in each memory mat. For example, FXL5 can be coupled to sub-word driver SWD5 of each memory mat.

[0043] exist Figure 4, the row address RA has indicated that MWD1 should be activated (e.g., selected), and the odd word driver FXD 408 associated with word driver line FXL5 should be activated (e.g., selected). As shown by the shaded area 412, the sub-word lines 410 associated with the main word drivers MWD0, MWDn (even the sub-word line associated with word driver line FXL5) remain inactive. However, the sub-word line 414 driven by the sub-word driver SWD5 416 associated with the activated MWD1 and FXL5 is activated to allow access to memory cells along the sub-word line 414. Therefore, the selected sub-word line SWL of the selected memory pad associated with MWD1 is driven to a high potential by the corresponding activated sub-word driver SWD5. In some examples, the other sub-word drivers SWD of the selected memory pad drive the corresponding unselected sub-word lines SWL to a low potential to remain inactive. The sub-word drivers SWD of the unselected memory pads (e.g., memory pads associated with MWD0 and MWDn) remain deactivated, and in some examples, no voltage is provided to the sub-word lines SWL of the unselected memory pads MAT. That is, although the sub-word drivers SWD may be enabled by the active main word driver MWD or the active word driver FXD, in order to be activated, the sub-word lines SWL must be associated with the sub-word drivers SWD coupled to the activated word driver FXD and the activated main word driver MWD. ​​After the memory cells of the selected sub-word line SWL have been accessed, the selected sub-word line SWL is then discharged to a low potential by deactivating MWD and / or FXD, as described herein.

[0044] According to some embodiments of the present disclosure, the sub-word line SWL is discharged in a controlled manner. For example, the discharge rate of the sub-word line SWL can be controlled. In some embodiments, the discharge of the sub-word line SWL can be controlled by activating the word driver FXD (e.g. Figure 3 and 4 Displayed and referenced in Figure 1 In some embodiments, the word driver line FXL may be controlled by a word driver (e.g., a word driver discussed above) for driving the word driver line FXL in a progressive manner (e.g., in a stepwise manner). Driving the word driver line FXL in a progressive manner may include driving FX to an intermediate potential between an active and a low potential. For example, the intermediate potential may be between Gnd and VCCP. In other examples, the intermediate potential may be between VKK and VCCP. In another example, the voltage to which the sub-word line SWL is discharged may be controlled. In some embodiments, the drive signal FX may be activated and deactivated at different times to discharge the sub-word line to an intermediate sub-word line voltage. The intermediate sub-word line voltage may be a voltage between a high potential (e.g., VCCP) and a low potential (e.g., Gnd, VKK). Driving the word driver line FXL in a progressive manner and / or changing the timing of activation of the drive signal FX may cause the sub-word line SWL to discharge at a slower rate than directly driving the drive signal FX between active and inactive states at the same time.

[0045] Figure 5 FIG. 5 is a circuit diagram of a word driver FXD 500 according to an embodiment of the present disclosure. In some embodiments, FXD 500 may be included in Figure 3 The word driver FXD and / or Figure 4 FXD 500 may be included in a row decoder, such as Figure 1 In some embodiments, FXD 500 may be included in a peripheral region of a memory array, such as Figure 3 500. For context, sub-word driver SWD 502 and enable signal circuit 504 associated with FXD 500 are also shown. In some embodiments, SWD 502 may be used to implement Figure 4 In some embodiments, the enable signal circuit 503 can be used to implement the sub-word drivers SWD0 to 7 shown in FIG. Figure 1 The enable signal circuit 40 is shown in FIG.

[0046] exist Figure 5 , SWD 502 includes a P-channel field effect transistor P1 and N-channel field effect transistors N1 and N2. Transistors P1 and N1 are coupled in series to each other at nodes 505 and 507, respectively, and the main word signal MWS is provided to gate electrodes 503 and 509, respectively. A drive signal FXT is provided to a node 501 (e.g., drain or source) of transistor P1, and a low potential is provided to a node 511 (e.g., drain or source) of transistor N1. Although the examples herein describe the low potential as Gnd, other potentials (e.g., a negative voltage, VKK) may also be used. The nodes (e.g., drain or source) of transistors P1 and N1 are coupled to a sub-word line SWL. A drive signal FXF is provided to a gate 515 of transistor N2, wherein its node 513 (e.g., drain or source) is coupled to the sub-word line SWL, and a low potential is provided to a node 517 (e.g., drain or source). As previously described, the main word signal MWS is provided by the main word driver MWD, and the drive signals FXT and FXF are provided by FXD 500 on the word driver line FXL.

[0047] The main word signal MWS is a signal that becomes a low level when selected, and the drive signals FXT and FXF are signals that become a high level and a low level, respectively, when selected. The drive signals FXT and FXF are complementary signals. When the main word signal MWS and the drive signals FXT and FXF are activated (for example, MWS and FXF are low and FXT is high), transistors N1 and N2 are not activated, but transistor P1 is activated to provide the FXT signal, and the corresponding sub-word line SWL is activated. On the contrary, when the main word signal MWS is in an inactive state and either of the drive signals FXT and FXF is also in an inactive state, the corresponding sub-word line SWL is deactivated. For active and inactive states, the potential to which the sub-word line SWL is driven may be based at least in part on the potential of the FXT and / or FXF signals. For example, when FXT is driven to VCCP and FXF is driven to Gnd, the sub-word line SWL may be driven to VCCP when activated by MWS.

[0048] Returning to the FX driver (e.g., FXD 500), various control signals may be provided to control the operation of FXD 500. FXD 500 may receive an address signal ADD, and enable signals En1, En2, and En3. The address signal ADD may be decoded by an address decoder circuit (e.g., Figure 1 The address decoder circuit 32 shown in FIG. 1 ) or the refresh control circuit (eg Figure 1 The refresh control circuit 16 shown in FIG. Figure 3 and 4 , row address bits RA0-2 may be used to indicate one of the eight FX drivers to be selected (e.g., activated). In some examples, FXD 500 may be one of the eight FX drivers. Enable signals En1, En2, En3 may be provided by enable signal circuit 504. Enable signal circuit 504 may activate one or more of enable signals En1, En2, En3 in response to active activation signal ACT. In some embodiments, the activation signal may be provided by a command decoder circuit, such as Figure 1 The command decoder circuit 34 in.

[0049] The address signal ADD and the second enable signal En2 may be provided as inputs to a NAND gate 506. The output of the NAND gate 506 may be provided as inputs to an inverter 508. The address signal ADD and the first enable signal En1 may be provided to a second NAND gate 510. The output of the second NAND gate 510 may be provided to a second inverter 512. The third enable signal En3 may be provided as input to an inverter 514.

[0050] The word driver may include a P-channel transistor P2. A node (e.g., source or drain) 519 of P2 may be coupled to a potential VCCP. A gate 521 of P2 may receive the output of inverter 508. A node 523 of P2 may be coupled to a node 529 of a P-channel transistor P3 and a node 531 of a P-channel transistor P4. A node 525 of P3 may be coupled to a bias voltage V bias . Gate 527 of P3 can receive the output of NAND gate 506. Gate 533 of P4 can receive the output of inverter 512. Node 535 of P3 can be coupled to node 537 of N-channel transistor N3. A drive signal FXF can be provided between nodes 535 and 537. Gate 539 of N3 can also receive the output of inverter 512. Node 541 of N3 can be coupled to a low potential. Figure 5 In the example shown in , ground Gnd is used as the low potential.

[0051] P-channel transistor P5 may have a node 543 coupled to potential VCCP. The gate of P5 may receive the output of inverter 514. Node 547 of P5 may be coupled to node 549 of P-channel transistor P6. Gate 551 of P6 may receive drive signal FXF. Node 553 of P6 may be coupled to node 555 of N-channel transistor N4 and node 561 of N-channel transistor N5. Drive signal FXT may be provided between nodes 553 and 561. Gate 557 of N4 may receive the output of inverter 514. Node 559 of N4 may be coupled to a low potential, such as Gnd. Gate 563 of N5 may receive drive signal FXF. Node 565 of N5 may be coupled to low potential Gnd.

[0052] When the address signal ADD is inactive (e.g., low), indicating that FXD 500 is not selected (e.g., not activated), the outputs of NAND gates 506, 510 are high regardless of the states of enable signals En1, En2, En3. Therefore, transistors P2 and P4 are activated, and transistors P3 and N3 are not activated. Therefore, FXF is driven to an inactive (e.g., high) state, which is Figure 5 , VCCP in the example shown in . When FXF is inactive, transistor N5 is activated and transistor P6 is not activated. This drives FXT to an inactive (e.g., low) state. The inactive drive signal FXF further deactivates transistor N2, thereby driving the sub-word line SWL to an inactive state. Therefore, when FXD 500 is not selected by the address signal ADD (e.g., the address signal ADD is inactive), the corresponding sub-word line SWL is in an inactive state. Similarly, when the enable signals En1 and En2 are inactive, FXF and FXT remain in an inactive state regardless of the states of the address signal ADD and the enable signal En3.

[0053] When the address signal ADD is active (e.g., high), indicating that FXD 500 is selected, the state of FXT and FXF may vary depending on the state of the enable signals En1, En2 and En3. The potential of the state may also depend on the enable signal. The state of the enable signals En1, En2, and En3 may be determined based at least in part on the state of the activation signal ACT. When the enable signal En1 is active (e.g., high) and the enable signals En2 and En3 are inactive (e.g., low), the output of the NAND gate 510 is low. Therefore, transistor N3 is activated and transistor P4 is not activated, thereby driving FXF to an active state. However, because the enable signal En3 is low, transistor N4 is activated and transistor P5 is not activated. Therefore, FXT is driven to an inactive state. When both the enable signals En1 and En3 are active, transistor P5 is activated and transistor N4 is not activated, thereby allowing FXT to reach an active state. Therefore, in some embodiments, FXT may be active only when the enable signal En3 is active.

[0054] Continuing with the example where the address signal ADD is active, when both enable signals En1 and En2 are active, in response to the active enable signal En2, transistor P3 may be activated and transistor P2 may be inactivated. However, because transistor N3 is activated and transistor P4 is inactivated in response to the enable signal En1, the drive signal FXF remains active low. When the enable signal En3 is inactive and both En1 and En2 are active, transistor P5 is inactive and transistor N4 is active, causing FXT to be at the low potential Gnd. With transistor P1 activated by the active (low) main word signal MWS, the sub-word line SWL begins to discharge from the high potential VCCP through transistor P1 to an intermediate sub-word line voltage, which may be greater than the low potential Gnd. For example, the sub-word line SWL may discharge from VCCP to a potential related to the threshold voltage of transistor P1. Subsequently, when the enable signal En3 becomes inactive, when the enable signal En1 is inactive and the enable signal En2 is active, transistor P4 is activated and transistor N3 is inactivated. Therefore, FXF is driven to the bias voltage V bias In some embodiments, V bias It may be a potential having a value between the low potential Gnd and the high potential VCCP.

[0055] Driving FXF to an intermediate potential can allow for an increased discharge time of the sub-word line SWL. For example, when the drive signal FXT is in an inactive state (e.g., at a low potential Gnd) and FXF is also in an inactive state (e.g., at a high potential VCCP), the sub-word line is driven to a low potential Gnd. However, when FXT is driven to a low potential, Gnd and FXF are driven to a bias voltage V bias, transistor N2 can provide resistance through which the sub-word line SWL discharges. Therefore, by driving FXF from Gnd to V bias , and then to VCCP, the sub-word line SWL can be discharged from VCCP to the low potential at a slower rate compared to the case where FXF is driven directly from the low potential to VCCP.

[0056] Figure 6 600 is a timing diagram of various signals during operation of a driver circuit according to an embodiment of the present disclosure. In some embodiments of the present disclosure, Figure 5 The driver circuit may operate according to the example operation of timing diagram 600. Timing diagram 600 will refer to Figure 5 However, Figure 6 The examples are not limited to a specific embodiment of FXD 500 .

[0057] Timing diagram 600 shows enable signals En1, En2, and En3, drive signals FXT and FXF, sub-word line SWL, and P_source (coupled to V bias A node of a P-channel field effect transistor (for example, Figure 5 The voltage at the node 529 of P3 in FIG. Figure 6 It is not shown, but it is assumed that the address signal ADD is active during the operation shown in timing diagram 600.

[0058] At some time before T0, an activation command 602 is received by a memory device including a word driver. An internal activation signal ACT may be converted to an active state. The activation signal ACT may be received by an enable signal circuit 504, which may activate enable signals En1, En2, and En3 in response to the activated activation signal ACT. Near T0, the enable signal circuit 504 may convert En1 to an active (e.g., high) state. As previously mentioned, this may cause the output of the NAND gate 510 to be converted to a low logic state. The output of the NAND gate 510 is inverted by an inverter 512, which activates transistor N3 and does not activate transistor P4. Because En2 remains low at T0, transistor P2 is activated and P3 is not activated. Therefore, FXF is driven to an active (e.g., low) state, and P_Source remains at a potential equal to VCCP.

[0059] Around T1, the enable signal circuit 504 turns En3 to an active (e.g., high) state. En3 may be inverted by the inverter 514, which activates transistor P5 and deactivates transistor N4. Because FXF is active low, transistor P6 is also activated and transistor N5 is deactivated. Therefore, FXT is driven to an active (e.g., high) state. Therefore, SWL is driven to an active (e.g., high) state.

[0060] Around T2, enable signal circuit 504 transitions En2 to an active (e.g., high) state. The active En2 signal may cause the output of NAND gate 510 to transition to a low logic state. This may activate transistor P3 and deactivate transistor P2. This may cause P_source to transition to equal V bias The electric potential. Figure 6 In the example shown in bias Has a potential greater than Gnd and lower than VCCP.

[0061] Before T3, a precharge command 604 may be received by the memory device. In response to the precharge command 604, the activation signal ACT may be turned to an inactive state. In response to the inactive activation signal ACT, the enable signal circuit 504 may deactivate (eg, turn to an inactive state) the enable signals En1, En2, En3.

[0062] At around T3, the enable signal circuit 504 may transition En3 to an inactive state. Figure 5 As discussed, when En3 is inactive, FXT may be driven to an inactive (e.g., low) state. Due to the inactive FXT, the sub-word line SWL is no longer coupled to VCCP (through FXT) via transistor P1, but is instead coupled to a low potential via transistor P1. As a result, SWL begins to discharge from VCCP through transistor P1 to an intermediate sub-word line voltage, which may be a potential less than VCCP but greater than the low potential. For example, SWL begins to discharge from VCCP until the potential of SWL is equal to the potential of the main word line MWL plus the threshold voltage V of transistor P1. tp Because FXF is still active low, transistor N2 is inactive, so the discharge rate of SWL is limited by P1.

[0063] Around T4, the enable signal circuit 504 may turn En1 to an inactive state. This may activate transistor P4 and deactivate transistor N3. FXF is driven to V via transistors P3 and P4. bias . V bias can be applied to the gate 515 of transistor N2. The voltage applied to N2 is increased to V bias The sub-word line SWL may be allowed to discharge through N2, thereby allowing SWL to continue to charge from above a low potential (eg, MWL plus V tp ) is discharged toward Gnd. The discharge rate may be based at least in part on V bias The value of .

[0064] Around T5, the enable signal circuit 504 may transition En2 to an inactive state. This may activate transistor P2 and deactivate transistor P3, driving FXF to an inactive (e.g., high) state and driving P_source to VCCP. The inactive FXF signal may activate N2, which may allow SWL to discharge to Gnd with a small resistance.

[0065] refer to Figure 5 The described word driver embodiments utilize P-channel transistors (e.g., Figure 5 The transistor P4 in the drive signal FXF is driven to V bias However, in other embodiments, the drive signal FXF may be driven to V via an N-channel transistor. bias .

[0066] Figure 7 FIG. 7 is a circuit diagram of a word driver FXD 700 according to an embodiment of the present disclosure. In some embodiments, FXD 700 may be included in Figure 3 The word driver FXD and / or Figure 4 FXD 700 may be included in a row decoder, such as Figure 1 In some embodiments, FXD 700 may be included in a peripheral region of a memory array, such as Figure 3 700. For context, sub-word driver SWD 702 and enable signal circuit 704 associated with FXD 700 are also shown. In some embodiments, SWD 702 may be used to implement Figure 4 In some embodiments, the enable signal circuit 704 can be used to implement the sub-word drivers SWD0 to 7 shown in FIG. Figure 1 The enable signal circuit 40 is shown in FIG.

[0067] Various control signals may be provided to control the operation of FXD 700. FXD 700 may receive an address signal ADD and enable signals En1, En2, and En3. The address signal ADD may be generated by an address decoder circuit (e.g., Figure 1 The address decoder circuit 32 shown in FIG. 1 ) or the refresh control circuit (eg Figure 1 The refresh control circuit 16 shown in FIG. Figure 3 and 4, row address bits RA0-2 may be used to indicate one of the eight FX drivers to be selected (e.g., activated). In some examples, FXD 700 may be one of the eight FX drivers. Enable signals En1, En2, En3 may be provided by enable signal circuit 704. Enable signal circuit 704 may activate one or more of enable signals En1, En2, En3 in response to active activation signal ACT. In some embodiments, the activation signal may be provided by a command decoder circuit, such as Figure 1 The command decoder circuit 34 in.

[0068] The address signal ADD and the enable signal En1 may be provided as inputs to the NAND gate 706. The output of the NAND gate 706 may be provided to the inverter 708. The enable signal En3 may be provided as input to the inverter 710. The FXD 700 may include a P-channel transistor P2 having a node 719 coupled to VCCP and a node 723 coupled to a node 725 of an N-channel transistor N3. A drive signal FXF may be provided between nodes 723 and 725. The gate 721 of P2 and the gate 727 of N3 may both receive the output of the inverter 708. The node 729 of N3 may be coupled to a node 735 of the P-channel transistor P3 and a node 737 of the N-channel transistor N4. The node 731 of P3 may be coupled to a bias voltage V bias Node 741 of N4 may be coupled to a low potential, such as Gnd. Gate 733 of P3 and gate 739 of N4 may both receive enable signal En2.

[0069] FXD 700 may include a P-channel transistor P4. A node 743 of P4 may be coupled to VCCP and a node 747 of P3 may be coupled to a node 749 of a P-channel transistor P5. A gate 745 of P4 may receive an output from an inverter 710. A gate 751 of P5 may receive a drive signal FXF. A node 753 of P5 may be coupled to a node 755 of an N-channel transistor N5 and a node 761 of an N-channel transistor N6. A drive signal FXT may be provided between nodes 753 and 761. A gate 757 of N5 may receive an output of the inverter 710, and a node 759 of N5 may be coupled to a low potential Gnd. A gate 763 of N6 may receive a drive signal FXF, and a node 765 of N6 may be coupled to a low potential Gnd.

[0070] Similar to Figure 5 , FXT is only driven to an active (e.g., high) state when FXF is active and enable signal En3 is active. When enable signal En3 is active, transistor P4 is activated and N5 is not activated. When FXF is active, transistor P5 is activated and transistor N6 is not activated, and FXT is driven to VCCP.

[0071] When En3 is inactive and En1 and En2 are active, FXT may be inactive and FXF may remain active. Thus, transistor N5 may be active and transistor N2 may be inactive. When transistor P1 is activated by an active (low) main word signal MWS, sub-word line SWL begins to discharge from active potential VCCP through transistor P1 to an intermediate sub-word line voltage, which may be greater than low potential Gnd. The intermediate sub-word line voltage may be based at least in part on a threshold voltage of P1.

[0072] Similar to Figure 5 , FXF may only be driven to an active (eg, low) state when address signal ADD is active (eg, FXD 700 is selected). Figure 5 Unlike the embodiment in FIG. 1 , the enable signal En2 may also be enabled to drive FXF to an active state. When both the address signal ADD and the enable signal En1 are active, the transistor P2 is not activated and the transistor N3 is activated. When the enable signal En2 is active, the transistor P3 is not activated and the N4 is activated. Therefore, FXF is driven to an inactive state via the transistors N3 and N4.

[0073] When the address signal ADD and the enable signals En1 and En2 are active, FXF can be driven to the low potential Gnd. On the contrary, when the address signal ADD and the enable signal En1 are active and the enable signal En2 is inactive, the transistor N4 is not activated and the transistor P3 is activated. Therefore, FXF is driven to the bias voltage V via the transistors P3 and N3. bias In some embodiments, V bias It may be a potential having a value between the low potential Gnd and the high potential VCCP.

[0074] Driving FXF to an intermediate potential may allow for an increase in the discharge time of the sub-word line SWL. For example, when the drive signal FXT is in an inactive state (e.g., at a low potential Gnd) and FXF is also in an inactive state (e.g., at a high potential VCCP), the sub-word line SWL is driven to the low potential Gnd. However, when FXT is driven to the low potential Gnd and FXF is driven to the bias voltage V bias When FXF is driven directly to VCCP, transistor N2 may present a resistance through which sub-word line SWL discharges. Thus, sub-word line SWL may be discharged to a low potential at a slower rate than when FXF is driven directly to VCCP. The discharge rate may be based at least in part on V bias .

[0075] Figure 8 800 is a timing diagram of various signals during operation of a driver circuit according to an embodiment of the present disclosure. In some embodiments of the present disclosure, Figure 7The driver circuit may operate according to the example operation of the timing diagram 800. The timing diagram 800 will refer to Figure 7 However, Figure 8 The examples shown in are not limited to a specific embodiment of FXD 700.

[0076] Timing diagram 800 shows enable signals En1, En2, and En3, drive signals FXT and FXF, sub-word line SWL, and N_source (coupled to V bias A node of a P-channel field effect transistor (for example, Figure 7 The voltage at the node 735) of P3 in FIG. Figure 8 Not shown, but assumed, during the operation shown in timing diagram 800 that address signal ADD is active.

[0077] At some time before T0, an activation command 802 is received by a memory device including a word driver. The internal activation signal ACT may transition to an active state. The activation signal ACT may be received by an enable signal circuit 704, which may activate enable signals En1, En2, and En3 in response to the activated activation signal ACT. Before any enable signals are activated, transistors P2 and P3 may be active, while transistors N3 and N4 are inactive. Thus, FXF may be inactive (e.g., high), and N_source may be at a voltage equal to the bias voltage V bias Under the potential of Figure 8 As shown in FIG. 1 , in some embodiments, V bias Can have a potential between VCCP and Gnd.

[0078] Around T0, enable signal circuit 704 may transition enable signals En1 and En2 to an active (e.g., high) state. Active enable signals En1 and En2 activate transistors N3 and N4 and deactivate transistors P2 and P3. This drives FXF to an active (e.g., low) state and drives N_source to a low potential (e.g., Gnd).

[0079] Around T1, the enable signal circuit 704 may transition the enable signal En3 to an active (e.g., high) state. The active enable signal En3 may activate transistor P4 and deactivate transistor N5. FXT may be driven to an active (e.g., high) state. When both FXF and FXT are in their active states, SWL is driven to an active state (e.g., high state).

[0080] Before T2, a precharge command 804 may be received by the memory device. In response to the precharge command 804, the activation signal ACT may be turned to an inactive state. In response to the inactive activation signal ACT, the enable signal circuit 704 may deactivate (eg, turn to an inactive state) the enable signals En1, En2, En3.

[0081] Around T2, the enable signal circuit 704 may transition the enable signal En3 to an inactive (e.g., low) state. The inactive enable signal En3 may deactivate transistor P4 and activate transistor N5, thereby driving FXT to an inactive state. Due to the inactive FXT, the sub-word line SWL is no longer coupled to VCCP (through FXT) via transistor P1, but is coupled to a low potential via transistor P1. Therefore, SWL begins to discharge from VCCP to the intermediate sub-word line voltage through transistor P1. For example, SWL begins to discharge from VCCP until the potential of SWL is equal to the potential of the main word line MWL plus the threshold voltage V of transistor P1. tp Because FXF is still active low, transistor N2 is inactive, so the discharge rate of SWL is limited by P1.

[0082] Around T3, the enable signal may transition the enable signal En2 to an inactive (e.g., low) state. This may deactivate transistor N4 and activate transistor P3. Because transistor N3 is still activated by the enable signal En1, FXF and N_source are driven to the bias voltage V bias Therefore, V bias The voltage applied to the gate 715 of transistor N2 is increased to V bias SWL may be allowed to continue discharging from the middle sub-wordline potential toward Gnd. The discharge rate may be based at least in part on V bias The value of .

[0083] Around T4, the enable signal circuit 704 may transition En1 to an inactive (e.g., low) state. This may activate transistor P2 and deactivate transistor N3, driving FXF to an inactive (e.g., high) state. The inactive FXF signal may activate N2, which may allow SWL to quickly discharge to Gnd. Because transistor P3 is still active, N_source may remain at V bias .

[0084] As in Figure 6 and 8, the timing of the enable signal can allow for controlling the driving of the word driver signals FXT and FXF. FXF and FXT do not need to be driven to their active and / or inactive states at the same time. For example, after FXF is driven to the active state, the drive signal FXT can be driven to the active state. In another example, before FXF is driven to the inactive state and / or the intermediate potential, FXT can be driven to the inactive state. In addition, in combination with the word driver control circuit system (e.g., Figure 5 and 7 ), the enable signal may allow the drive signals FXT and / or FXF to be driven to a potential having a value between Gnd and VCCP (eg, between active and low potentials).

[0085] Activating and deactivating the drive signal at different times and / or driving the drive signal to an intermediate potential (e.g., V bias ) can allow for controlling the discharge of a word line (e.g., a sub-word line), such as reducing the rate at which the word line is discharged from a high potential to a low potential (e.g., VCCP to Gnd). In addition, the value of the intermediate potential can be used to control the discharge rate of the word line. In some applications, reducing the discharge rate of the word line can reduce the impact of a row hammering event.

[0086] Although it may be desirable to reduce the effects of row hammering events, in some embodiments, gradually (e.g., stepwise) controlling a drive signal (e.g., FXF) to control the discharge of a word line (e.g., SWL) may require additional circuitry (e.g., transistors, enable signal circuits, bias voltage generators). Therefore, in some applications, it may be desirable to share one or more of the drive signal control components (e.g., control circuits) among multiple word drivers (FXD).

[0087] Fig. 9 FIG. 9 is a block diagram 900 of a plurality of word drivers (FXD0, FXD2, FXD4, and FXD6) according to an embodiment of the present disclosure. In some embodiments, each word driver FXD0, FXD2, FXD4, and FXD6 may be provided by Figure 7 The word driver FXD 700 shown in FIG. Fig. 9 As shown in FIG. 5 , the sources of some signals can be shared by word drivers FXD0, FXD2, FXD4, and FXD6. For example, FXD0, FXD2, FXD4, and FXD6 can be driven from the same source (e.g., Figure 7 In some embodiments, in addition to the enable signal En2, the bias voltage V may be shared among the word drivers FXD0, FXD2, FXD4, and FXD6. bias and transistors P3 and N4. In some embodiments, the control circuit (eg, control component) indicated by block 902 may be equivalent to Figure 7 The components shown in block 790. Therefore, in some applications, Figure 7 and 9 The embodiment shown in FIG. 4 is used to implement the word driver to reduce the number of additional components required to implement the progressive control of the drive signal. Although four word drivers are shown to share enable signals and bias voltages, in other embodiments, more or fewer word drivers may share these components.

[0088] As in Fig. 9 As shown in FIG, each word driver FXD0, FXD2, FXD4 and FXD6 receives its own address signal ADDFX0, ADD FX2, ADD FX4, ADD FX6. Return to Figure 5 , through transistor P3 to access V bias The control is based on the enable signal En2 and the address signal ADD. Therefore, in some embodiments, according to Figure 5 The word drivers implemented in the embodiment shown in FIG. 1 may not be able to share the bias voltage V bias and / or coupled to a bias voltage V bias transistor. Therefore, in some applications, Figure 7 The word driver embodiment shown in FIG. 1 may be desirable because one or more drive signal control components can be shared. However, in some applications, it may be advantageous to drive the drive signal via a P-channel transistor, in which case, Figure 5 The word driver shown in may be desirable.

[0089] As reference Figures 5 to 9 As shown, in some embodiments, the word driver can receive a bias voltage. The value of the bias voltage can at least partially control the discharge rate of the word line (eg, sub-word line). In some embodiments, the bias voltage can be provided by a bias voltage generator.

[0090] Fig.10 is a circuit diagram of a bias voltage generator 1000 according to an embodiment of the present disclosure. The bias voltage generator 1000 can provide a bias voltage V bias In some embodiments, the bias voltage generator 1000 may be used to provide a bias voltage generated by a word driver (eg Figure 3 , 4 , 5, 7 and 9) receives the bias voltage.

[0091] The bias voltage generator 1000 may include a first operational amplifier (op-amp) 1004. The op-amp may receive a reference voltage VREF at a negative input. In some embodiments, VREF may be provided by a voltage generator circuit, such as Figure 11004 can output a voltage Vbias_REF, which can be provided to the positive input of the second operational amplifier 1002. The second operational amplifier 1002 can output a bias voltage V bias . Bias voltage V bias can be fed back to the negative input of the operational amplifier 1002. The bias generator 1000 can further include P-channel transistors P7 and P8, an N-channel transistor N7 and a variable resistor 1006, such as Fig.10 Indicated by the dotted box in .

[0092] Transistor P7 may have a node 1005 coupled to a node 1001 of voltage VPP and to a node 1013 of N7. The outputs of nodes 1005 and 1013 may be fed back to the positive input of operational amplifier 1004. Transistor P8 may also have a node 1007 coupled to voltage VPP. Gate 1003 of P7 and gate 1009 of P8 may be coupled together. Node 1011 of P8 may be coupled to gates 1003 and 1009 of transistors P7 and P8, respectively. Node 1011 of P8 may be further coupled to variable resistor 1006. Variable resistor 1006 may be coupled to ground Gnd. Gate 1015 of N5 may receive the output of operational amplifier 1004. Node 1017 of N7 may be coupled to Gnd. In some embodiments, transistor N7 may be an N-channel transistor (e.g., a gate of a sub-word driver SWD) coupled to a word driver line and a sub-word line (SWL) providing a drive signal FXF. Figure 5 and 7 A replica of the transistor N2 shown in FIG.

[0093] In operation, transistors P7 and P8 can be configured to provide a current mirror with a current I_ref across nodes 1001 and 1005 of P7 and nodes 1007 and 1011 of P8. When activated, transistor N7 can receive Vbias_REF and discharge the voltage VPP across transistor P7 to ground. Vbias_REF can cause the drain level of N7 to be equal to the level of the negative input node of operational amplifier 1004. In other words, I_ref can flow across N7, and when gate 1015 receives Vbias_REF, the drain level can be equal to the level of the negative input node of operational amplifier 1004. The resistance of variable resistor 1006 can be adjusted to adjust V bias In some embodiments, the bias voltage generator 1000 may be configured to provide a bias voltage between a low potential (e.g., Gnd, VKK) and a high potential (e.g., VCCP). In some embodiments, when the current driving capability of other components of the bias voltage generator is low, the second operational amplifier 1002 may be V biasProvides stability.

[0094] Fig.11 1 is a circuit diagram of a bias voltage generator according to an embodiment of the present disclosure. The bias voltage generator 1100 can provide a bias voltage V bias In some embodiments, the bias voltage generator 1100 may be used to provide a bias voltage generated by a word driver (eg Figure 3 , 4 , 5, 7 and 9) receives the bias voltage.

[0095] The bias voltage generator 1100 may include an operational amplifier (op amp) 1102, P-channel transistors P7 and P8, an N-channel transistor N7, and a variable resistor 1106, such as Fig.11 Indicated by the dotted box in .

[0096] Transistor P7 may have a node 1101 coupled to a voltage VPP and a node 1105 coupled to a node 1113 of N7. The outputs of nodes 1105 and 1013 may be provided to a gate 1115 of N7. Gate 1115 of N7 and nodes 1105 and 1013 may also be coupled to the positive input of operational amplifier 1102. Transistor P8 may also have a node 1107 coupled to a voltage VPP. Gate 1103 of P7 and gate 1109 of P8 may be coupled to each other. Node 1111 of P8 may be coupled to gates 1103 and 1109 of transistors P7 and P8, respectively. Node 1111 of P8 may be further coupled to a variable resistor 1106. Variable resistor 1106 may be coupled to ground Gnd. Node 1117 of N7 may also be coupled to Gnd. In some embodiments, transistor N7 may be an N-channel transistor (eg, a transistor of a sub-word driver SWD) coupled to a word driver line providing a drive signal FXF and a sub-word line (SWL). Figure 5 and 7 A replica of the transistor N2 shown in FIG.

[0097] In operation, transistors P7 and P8 can be configured to provide a current mirror with current I_ref across nodes 1101 and 1105 of P7 and nodes 1007 and 1011 of P8. Transistor N7 can receive current I_ref at gate 1115 and also drain current I_ref to ground across nodes 1113 and 1117, which generates voltage Vbias_REF. Vbias_REF can be received at the positive input by operational amplifier 1102, and operational amplifier 1102 can output bias voltage V bias . Bias voltage V bias can be fed back into the negative voltage of the operational amplifier 1102. In some embodiments, the operational amplifier 1102 can bias Provides stability, similar to Fig.10The operational amplifier 1002 in FIG. The resistance of the variable resistor 1106 can be adjusted to adjust V bias In some embodiments, the bias voltage generator 1100 may be configured to provide a bias voltage between a low potential (eg, Gnd) and a high potential (eg, VCCP).

[0098] Fig.10 and 11 The bias voltage generators 1000 and 1100 shown in FIG. 1 are provided for exemplary purposes only. In some embodiments, other bias voltage generators may be used to provide bias voltages to the word drivers.

[0099] As described herein, the word driver line FXL can be driven in a progressive manner. That is, the word driver line can be driven to one or more intermediate potentials having values ​​between the potentials associated with the active and inactive states. In some embodiments, the word driver line FXL can be driven in a progressive manner by providing various control signals to the word driver FXD. In some embodiments, the control signal may include one or more enable signals and an address signal. In some embodiments, the enable signal may be generated in response to an activation signal. In some embodiments, FXL may be driven to an intermediate potential between a high potential and a low potential as a "step" driven between active and low potentials. Driving FXL in a progressive manner may cause the sub-word line SWL to discharge in a stepwise manner and / or at a slower rate than when FXL is driven directly between active and low potentials. In some applications, controlling the discharge of SWL in this manner may reduce the effects of row hammering events.

[0100] From the foregoing it will be appreciated that although specific embodiments of the present disclosure have been described herein for purposes of illustration, various modifications may be made without departing from the spirit and scope of the present disclosure. Accordingly, the scope of the present disclosure should not be limited to any of the specific embodiments described herein.

Claims

1. A device for driving a sub-word line, comprising: a sub-word driver configured to drive the sub-word line; and a word driver configured to provide a first drive signal to the sub-word driver, wherein the word driver is further configured to drive the first drive signal to an intermediate potential when driving the first drive signal between an active state and an inactive state, wherein the intermediate potential has a value between a high potential and a low potential, wherein the word driver further provides a second drive signal to the sub-word driver, wherein the word driver drives the second drive signal to an active state at a different time than when the word driver drives the first drive signal to the active state, and Wherein after the first driving signal is driven to the active state, the second driving signal is driven to the active state.

2. The apparatus of claim 1, wherein the word driver drives the second drive signal to the inactive state at a different time than when the word driver drives the first drive signal to the inactive state.

3. The apparatus of claim 1, further comprising a bias voltage generator configured to provide a bias voltage to the word driver, wherein the intermediate potential is based at least in part on the bias voltage.

4. The apparatus of claim 1, wherein the word driver is configured to receive at least one enable signal and to drive the first drive signal to the intermediate potential in response to the at least one enable signal.

5. A device for driving a sub-word line, comprising: a sub-word driver configured to drive the sub-word line; and a word driver configured to provide a first drive signal to the sub-word driver, wherein the word driver is further configured to drive the first drive signal to an intermediate potential when driving the first drive signal between an active state and an inactive state, wherein the intermediate potential has a value between a high potential and a low potential, wherein the word driver further provides a second drive signal to the sub-word driver, wherein the word driver drives the second drive signal to the active state at a different time than when the word driver drives the first drive signal to the active state, wherein the word driver drives the second drive signal to the inactive state at a different time than when the word driver drives the first drive signal to the inactive state, and Wherein the second drive signal is driven to the inactive state before the first drive signal is driven to the inactive state.

6. The apparatus of claim 5, further comprising a bias voltage generator configured to provide a bias voltage to the word driver, wherein the intermediate potential is based at least in part on the bias voltage.

7. The apparatus of claim 5, wherein the word driver is configured to receive at least one enable signal and to drive the first drive signal to the intermediate potential in response to the at least one enable signal.

8. A device for driving a sub-word line, comprising: a sub-word driver configured to drive the sub-word line; and a word driver configured to provide a first drive signal to the sub-word driver, wherein the word driver is further configured to drive the first drive signal to an intermediate potential when driving the first drive signal between an active state and an inactive state, wherein the intermediate potential has a value between a high potential and a low potential, wherein the word driver is configured to receive at least one enable signal and drive the first drive signal to the intermediate potential in response to the at least one enable signal, wherein the at least one enable signal comprises a first enable signal and a second enable signal, wherein: When the first enable signal and the second enable signal are in an active state, the first drive signal is driven to the active state; When the first enable signal and the second enable signal are in an inactive state, the first drive signal is driven to the inactive state; and When the first enable signal is in the inactive state and the second enable signal is in the active state, the first drive signal is driven to the intermediate potential.

9. The apparatus of claim 8, wherein the at least one enable signal comprises a third enable signal, and the word driver further provides a second drive signal to the sub-word driver, wherein when the third enable signal is in an active state, the second drive signal is driven to an active state, and when the third enable signal is in an inactive state, the second drive signal is driven to an inactive state.

10. A device for driving a sub-word line, comprising: a control circuit configured to receive a first enable signal and output an intermediate voltage in response to the first enable signal; a plurality of word drivers coupled to the control circuit, individual ones of the plurality of word drivers being configured to: receiving an address signal; receiving a second enabling signal; and providing a first drive signal, wherein the first drive signal is provided in an active state when the address signal, the first enable signal, and the second enable signal are in an active state, and wherein the first drive signal is provided at the intermediate voltage when the address signal and the second enable signal are in an active state and the first enable signal is in an inactive state; and A plurality of sub-word drivers are configured to receive the first driving signal from respective ones of the plurality of word drivers, individual ones of the plurality of sub-word drivers being configured to drive corresponding sub-word lines.

11. The apparatus of claim 10, further comprising a bias voltage generator configured to provide the intermediate voltage to the control circuit, wherein the bias voltage generator includes a variable resistance, wherein a value of the intermediate voltage is based at least in part on a value of the variable resistance.

12. The apparatus of claim 10, wherein a discharge rate of the corresponding sub-word line is based at least in part on a value of the intermediate voltage.

13. The apparatus of claim 10, wherein a state of the first enable signal and a state of the second enable signal are based at least in part on an activation signal.

14. The apparatus of claim 10, wherein individual ones of the plurality of word drivers are further configured to: receiving a third enabling signal; A second drive signal is provided, wherein the second drive signal is provided in an active state when the third enable signal is in an active state, and wherein the second drive signal is provided in an inactive state when the third enable signal is in an inactive state.

15. The apparatus of claim 14, wherein when the first drive signal and the second drive signal are in an active state, the corresponding sub-word line is driven to a high potential, and when the second drive signal is in the inactive state and the first drive signal is at the intermediate voltage, the corresponding sub-word line is partially discharged.

16. The apparatus of claim 15, wherein when the second drive signal and the first drive signal are in an inactive state, the corresponding sub-word line is discharged to a low potential.

17. A device for driving a sub-word line, comprising: a sub-word driver configured to drive the sub-word line; and a word driver configured to provide a first driving signal and a second driving signal to the sub-word driver, wherein: In response to activation of the first drive signal and the second drive signal, the sub-word line is driven to a high potential; and In response to deactivating the first drive signal, the sub-word line is discharged to an intermediate sub-word line voltage, Wherein the discharge rate is based at least in part on a time difference between deactivating the first drive signal and driving the second drive signal to the intermediate sub-word line voltage.

18. A device for driving a sub-word line, comprising: a sub-word driver configured to drive the sub-word line; and a word driver configured to provide a first driving signal and a second driving signal to the sub-word driver, wherein: In response to activation of the first drive signal and the second drive signal, the sub-word line is driven to a high potential; and In response to deactivating the first drive signal, the sub-wordline is discharged to an intermediate sub-wordline voltage, wherein the intermediate sub-wordline voltage is based at least in part on a threshold voltage of a transistor of the sub-wordline driver.

19. A device for driving a sub-word line, comprising: a sub-word driver configured to drive the sub-word line; and a word driver configured to provide a first driving signal and a second driving signal to the sub-word driver, wherein: In response to activation of the first drive signal and the second drive signal, the sub-word line is driven to a high potential; and In response to deactivating the first drive signal, the sub-word line is discharged to an intermediate sub-word line voltage, wherein: The sub-word line is further discharged in response to deactivating the first drive signal and driving the second drive signal to an intermediate potential; and The sub-word line is fully discharged in response to deactivating the first driving signal and the second driving signal.

20. The apparatus of claim 19, further comprising a bias voltage generator configured to provide a bias voltage to the word driver, wherein a value of the intermediate potential is based at least in part on the bias voltage.

21. The apparatus of claim 20, wherein transistors of the bias voltage generator are replicas of transistors of the sub-word line driver.

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