Display device and method of driving the same

Abstract

Provided are an emission driver, a display device including the same, and a method of driving the display device. The emission driver includes a plurality of stages. A stage of the plurality of stages receives an activation signal, a first clock signal, a second clock signal, a protection signal, a first gate power voltage, and a second gate power voltage, and outputs an emission signal. The stage of the plurality of stages includes a pull-up switching element connected between a first gate power voltage terminal that receives the first gate power voltage and an emission signal output terminal that outputs the emission signal, a pull-down switching element connected between a second gate power voltage terminal that receives the second gate power voltage and the emission signal output terminal, and a protection switching element that applies the first gate power voltage to a control electrode of the pull-down switching element in response to the protection signal.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to an emission driver, a display apparatus including the same, and a method of driving the same. More particularly, embodiments of the present application relate to an emission driver including a stage including a flicker prevention switch element for preventing image flicker from occurring at an initial driving period and an abnormal shutdown case, a display apparatus including the same, and a method of driving the same. BACKGROUND

[0002] Generally, a display apparatus includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver includes a gate driver, a data driver, an emission driver, and a driving controller. The gate driver outputs gate signals to the plurality of gate lines, respectively. The data driver outputs data voltages to the plurality of data lines, respectively. The emission driver outputs emission signals to the plurality of emission lines, respectively. The driving controller controls the gate driver, the data driver, and the emission driver. SUMMARY

[0003] At an initial driving period of the display apparatus or an abnormal shutdown case of the display apparatus, an unintended emission signal can be applied to the display panel, so that the display panel can be flickered unintentionally.

[0004] Embodiments of the present application provide an emission driver capable of improving display quality of a display panel by preventing image flicker from occurring at an initial driving period and an abnormal shutdown case.

[0005] Embodiments of the present application also provide a display apparatus including the same.

[0006] Embodiments of the present application also provide a method of driving the same.

[0007] In embodiments of the emission driver according to the present application, the emission driver includes a plurality of stages. At least one stage of the plurality of stages receives a start signal, a first clock signal, a second clock signal, a protection signal, a first gate power voltage, and a second gate power voltage, and outputs an emission signal. The at least one stage of the plurality of stages includes a pull-up switch element connected between a first gate power voltage terminal receiving the first gate power voltage and an emission signal output terminal outputting the emission signal, a pull-down switch element connected between a second gate power voltage terminal receiving the second gate power voltage and the emission signal output terminal, and a protection switch element applying the first gate power voltage to a control electrode of the pull-down switch element in response to the protection signal.

[0008] In an embodiment, the at least one stage of the plurality of stages can further include: a first switching element to apply the start signal to the fourth node in response to a first clock signal; a second switching element to apply the first gate power supply voltage to the second node in response to a voltage of the first node; a third switching element to apply the second clock signal to the second node in response to a voltage of the third node; and a twelfth switching element to apply a voltage of the fourth node to the eighth node in response to the second gate power supply voltage.

[0009] In an embodiment, the at least one stage of the plurality of stages can further include: a fourth switching element to apply the first clock signal to the first node in response to a voltage of the fourth node; a fifth switching element to apply the second gate power supply voltage to the first node in response to the first clock signal; a sixth switching element to connect the fifth node to the seventh node in response to the second clock signal; a seventh switching element to apply the second clock signal to the fifth node in response to a voltage of the sixth node; an eighth switching element to apply the first gate power supply voltage to the seventh node in response to a voltage of the fourth node; and an eleventh switching element to connect the first node to the sixth node in response to the second gate power supply voltage.

[0010] In an embodiment, the at least one stage of the plurality of stages can further include a first capacitor including a first electrode connected to the first gate power supply voltage terminal and a second electrode connected to the seventh node.

[0011] In an embodiment, the at least one stage of the plurality of stages can further include a second capacitor including a first electrode connected to the fifth node and a second electrode connected to the sixth node.

[0012] In an embodiment, the at least one stage of the plurality of stages can further include a third capacitor including a first electrode connected to the second node and a second electrode connected to the third node.

[0013] In an embodiment, the protection switching element can be connected to the fourth node.

[0014] In an embodiment, the protection switching element can be connected to the eighth node.

[0015] In an embodiment, the protection signal can turn on the protection switching element in an initial driving period and turn off the protection switching element in a normal driving period after the initial driving period.

[0016] In an embodiment, in the initial driving period, the start signal has the first gate power supply voltage, the first clock signal has the second gate power supply voltage, the second clock signal has the second gate power supply voltage, and the protection signal has the second gate power supply voltage.

[0017] In an embodiment, a capacitance of a line to which the first gate power voltage is applied can be greater than a capacitance of a line to which the protection signal is applied.

[0018] In an embodiment of the display device according to the present application, the display device includes a display panel, a gate driver, a data driver, and an emission driver. The display panel displays an image. The gate driver provides a gate signal to the display panel. The data driver provides a data voltage to the display panel. The emission driver provides an emission signal to the display panel. The emission driver includes a plurality of stages. At least one stage of the plurality of stages receives an activation signal, a first clock signal, a second clock signal, a protection signal, a first gate power voltage, and a second gate power voltage, and outputs the emission signal. The at least one stage of the plurality of stages can include a pull-up switching element connected between a first gate power voltage terminal receiving the first gate power voltage and an emission signal output terminal outputting the emission signal, a pull-down switching element connected between a second gate power voltage terminal receiving the second gate power voltage and the emission signal output terminal, and a protection switching element applying the first gate power voltage to a control electrode of the pull-down switching element in response to the protection signal.

[0019] In an embodiment, the at least one stage of the plurality of stages can further include a first switching element applying the activation signal to a fourth node in response to the first clock signal, a second switching element applying the first gate power voltage to a second node in response to a voltage of a first node, a third switching element applying the second clock signal to the second node in response to a voltage of a third node, and a twelfth switching element applying a voltage of the fourth node to an eighth node in response to the second gate power voltage.

[0020] In an embodiment, the at least one stage of the plurality of stages can further include a fourth switching element applying the first clock signal to a first node in response to a voltage of the fourth node, a fifth switching element applying the second gate power voltage to the first node in response to the first clock signal, a sixth switching element connecting a fifth node to a seventh node in response to the second clock signal, a seventh switching element applying the second clock signal to the fifth node in response to a voltage of a sixth node, an eighth switching element applying the first gate power voltage to the seventh node in response to the voltage of the fourth node, and an eleventh switching element connecting the first node to the sixth node in response to the second gate power voltage.

[0021] In an embodiment, the at least one stage of the plurality of stages can further include a first capacitor including a first electrode connected to the first gate power voltage terminal and a second electrode connected to the seventh node, a second capacitor including a first electrode connected to the fifth node and a second electrode connected to the sixth node, and a third capacitor including a first electrode connected to the second node and a second electrode connected to the third node.

[0022] In an embodiment, the display panel can include a plurality of pixels. Each of the plurality of pixels can include an organic light emitting element. A pixel of the plurality of pixels can receive a data write gate signal, a data initialization gate signal, an organic light emitting element initialization gate signal, a data voltage, and an emission signal, and cause the organic light emitting element to emit light according to a level of the data voltage to display an image.

[0023] In an embodiment, at least one of the plurality of pixels can include: a first pixel switching element including a control electrode connected to a first pixel node, an input electrode connected to a second pixel node, and an output electrode connected to a third pixel node; a second pixel switching element including a control electrode to which the data write gate signal is applied, an input electrode to which the data voltage is applied, and an output electrode connected to the second pixel node; a third pixel switching element including a control electrode to which the data write gate signal is applied, an input electrode connected to the first pixel node, and an output electrode connected to the third pixel node; a fourth pixel switching element including a control electrode to which the data initialization gate signal is applied, an input electrode to which the initialization voltage is applied, and an output electrode connected to the first pixel node; a fifth pixel switching element including a control electrode to which the emission signal is applied, an input electrode to which the high power voltage is applied, and an output electrode connected to the second pixel node; a sixth pixel switching element including a control electrode to which the emission signal is applied, an input electrode connected to the third pixel node, and an output electrode connected to an anode electrode of the organic light emitting element; a seventh pixel switching element including a control electrode to which the organic light emitting element initialization gate signal is applied, an input electrode to which the initialization voltage is applied, and an output electrode connected to the anode electrode of the organic light emitting element; a storage capacitor including a first electrode to which the high power voltage is applied and a second electrode connected to the first pixel node; and the organic light emitting element including the anode electrode and a cathode electrode to which the low power voltage is applied.

[0024] In an embodiment of a method of driving a display apparatus, the method includes providing a gate signal to a display panel using a gate driver, providing a data voltage to the display panel using a data driver, and providing an emission signal to the display panel using an emission driver. The emission driver includes a plurality of stages. At least one stage of the plurality of stages receives an enable signal, a first clock signal, a second clock signal, a protection signal, a first gate power voltage, and a second gate power voltage, and outputs the emission signal. The at least one stage of the plurality of stages includes: a pull-up switching element connected between a first gate power voltage terminal receiving the first gate power voltage and an emission signal output terminal outputting the emission signal; a pull-down switching element connected between a second gate power voltage terminal receiving the second gate power voltage and the emission signal output terminal; and a protection switching element applying the first gate power voltage to a control electrode of the pull-down switching element in response to the protection signal.

[0025] In an embodiment, the protection signal can turn on the protection switching element in the initial driving period and turn off the protection switching element in the normal driving period after the initial driving period.

[0026] In an embodiment, a capacitance of a line to which the first gate power voltage is applied can be greater than a capacitance of a line to which the protection signal is applied. When the display device is abnormally turned off, the protection signal applied to the control electrode of the protection switching element can decrease faster than the first gate power voltage applied to the input electrode of the protection switching element, so that the protection switching element is turned on and the pull-down switching element is turned off.

[0027] According to the emission driver, the display device, and the method of driving the display device, the stage of the emission driver includes the anti-flicker switching element, so that image flicker can be prevented from occurring in the initial driving period and the abnormal turn-off case. Accordingly, the display quality of the display panel can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0028] The above and other features and advantages of the present application will become more apparent by describing in detail embodiments thereof with reference to the attached drawings in which:

[0029] Figure 1 is a block diagram illustrating an embodiment of a display device according to the present application;

[0030] Figure 2 is a circuit diagram illustrating a pixel of a display panel of Figure 1

[0031] Figure 3 is a timing chart illustrating input signals of a pixel of Figure 2

[0032] Figure 4 is a block diagram illustrating an emission driver of Figure 1

[0033] Figure 5 is a circuit diagram illustrating a stage of the emission driver of Figure 4

[0034] Figure 6 is a timing chart illustrating input signals, output signals, and control signals of the stage of Figure 5

[0035] Figure 7 is a conceptual diagram illustrating an abnormal turn-off operation of the emission driver of Figure 5 when the stage of Figure 1 does not include the thirteenth switching element;

[0036] Figure 8A is a conceptual diagram illustrating an embodiment of an abnormal turn-off operation of the emission driver of Figure 1 according to the present application;​​​​​

[0037] Figure 8B is a conceptual diagram illustrating an abnormal OFF operation of the emission driver of Embodiment 1 according to the present application; Figure 1

[0038] Figure 9 is a timing chart illustrating an initial drive operation of the emission driver of Embodiment 1 when the stage of Embodiment 1 does not include the thirteenth switching element; Figure 5 Figure 1

[0039] Figure 10 Figure 5 Figure 1

[0040] Figure 11 is a timing chart illustrating an initial drive operation of the emission driver of Embodiment 1; Figure 1

[0041] Figure 12 Figure 1

[0042] Figure 13 is a circuit diagram illustrating an embodiment of the stage of the emission driver of the display device according to the present application. DETAILED DESCRIPTION

[0043] Hereinafter, the present application will be explained in detail with reference to the accompanying drawings.

[0044] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements can be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0045] It will be understood that, although the terms "first", "second", "third", and the like can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element", "first component", "first region", "first layer" or "first portion" discussed below could be termed a second element, a second component, a second region, a second layer or a second portion without departing from the teachings of this document.

[0046] ​​​​​​​​​The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, including "at least one," unless the content clearly indicates otherwise. "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," as used herein, specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0047] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" can be used herein to describe one element's or feature's relationship to another element or feature as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. In embodiments where the device in one of the figures is turned over, so that it is oriented upside-down, relative terms such as "lower" and "bottom" can then be used to describe the reoriented or inverted orientation of the device. Accordingly, the exemplary term "lower" can encompass both an orientation of "lower" and "upper" depending on the particular orientation of the figure. Similarly, the exemplary term "below" or "under" can encompass both an orientation of "below" or "above" depending on the particular orientation of the figure.

[0048] "About" or "approximately" as used herein includes the stated value and the average of the specified value within an acceptable range of deviation determined by one of ordinary skill in the art to be within the scope of what is claimed. For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0050] Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. In embodiments, regions illustrated or described as flat can be have rough and / or nonlinear features. Moreover, the illustrated corners can be rounded. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

[0051] Figure 1 is a block diagram illustrating an embodiment of a display apparatus according to the present application.

[0052] Referring to Figure 1 , the display apparatus includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0053] The display panel 100 includes a display area on which an image is displayed and a peripheral area adjacent to the display area.

[0054] The display panel 100 includes a plurality of gate lines GWL, GIL, and GBL, a plurality of data lines DL, a plurality of emission lines EL, and a plurality of pixels electrically connected to the gate lines GWL, GIL, and GBL, the data lines DL, and the emission lines EL. The gate lines GWL, GIL, and GBL extend in a first direction D1, the data lines DL extend in a second direction D2 crossing the first direction D1, and the emission lines EL extend in the first direction D1.

[0055] The driving controller 200 receives input image data IMG and input control signals CONT from an external apparatus (not shown). In embodiments, for example, the input image data IMG can include red image data, green image data, and blue image data. The input image data IMG can include white image data. The input image data IMG can include magenta image data, cyan image data, and yellow image data. The input control signals CONT can include a main clock signal and a data enable signal. The input control signals CONT can further include a vertical synchronization signal and a horizontal synchronization signal.

[0056] The driving controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signals CONT.

[0057] The drive controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 can include a vertical start signal and a gate clock signal.

[0058] The drive controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 can include a horizontal start signal and a load signal.

[0059] The drive controller 200 generates a data signal DATA based on the input image data IMG. The drive controller 200 outputs the data signal DATA to the data driver 500.

[0060] The drive controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400.

[0061] The drive controller 200 generates a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT, and outputs the fourth control signal CONT4 to the emission driver 600.

[0062] The gate driver 300 generates gate signals for driving the gate lines GWL, GIL, and GBL in response to the first control signal CONT1 received from the drive controller 200. The gate driver 300 can output the gate signals to the gate lines GWL, GIL, and GBL in sequence. In an embodiment, for example, the gate driver 300 can be integrated on a peripheral area of the display panel 100. In an embodiment, for example, the gate driver 300 can be disposed (e.g., mounted) on a peripheral area of the display panel 100.

[0063] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA.

[0064] In an embodiment, the gamma reference voltage generator 400 can be disposed in the drive controller 200 or the data driver 500.

[0065] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into a data voltage having an analog type using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage to the data line DL.

[0066] The emission driver 600 generates an emission signal to drive the emission line EL in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 can output the emission signal to the emission line EL. In an embodiment, for example, the emission driver 600 can be integrated on the peripheral area of the display panel 100. In an embodiment, for example, the emission driver 600 can be disposed (e.g., mounted) on the peripheral area of the display panel 100. Although the gate driver 300 is disposed on the first side (e.g., left side) of the display panel 100 and the emission driver 600 is disposed on the second side (e.g., right side) of the display panel 100 opposite the first side of the display panel 100 in Figure 1

[0067] Figure 2 is a circuit diagram illustrating a pixel of the display panel 100 of Figure 1 Figure 3 is a timing chart illustrating input signals applied to a pixel of Figure 2

[0068] Referring to Figures 1 to 3 , the display panel 100 includes a plurality of pixels. Each pixel includes an organic light emitting element OLED. In an embodiment, for example, the organic light emitting element OLED can be an organic light emitting diode OLED.

[0069] The pixel receives the data write gate signal GW, the data initialization gate signal GI, the organic light emitting element initialization gate signal GB, the data voltage VDATA, and the emission signal EM, and the organic light emitting element OLED of the pixel emits light corresponding to a level of the data voltage VDATA to display an image.

[0070] At least one of the pixels can include a first to seventh pixel switching element T1 to T7, a storage capacitor CST, and an organic light emitting element OLED.

[0071] ​​​The first pixel switch element T1 includes a control electrode connected to the first pixel node N1, an input electrode connected to the second pixel node N2, and an output electrode connected to the third pixel node N3.

[0072] In an embodiment, for example, the first pixel switch element T1 can be a p-type thin film transistor (“TFT”). The control electrode of the first pixel switch element T1 can be a gate electrode, the input electrode of the first pixel switch element T1 can be a source electrode, and the output electrode of the first pixel switch element T1 can be a drain electrode.

[0073] The second pixel switch element T2 includes a control electrode to which a data write gate signal GW is applied, an input electrode to which a data voltage VDATA is applied, and an output electrode connected to the second pixel node N2.

[0074] In an embodiment, for example, the second pixel switch element T2 can be a p-type TFT. The control electrode of the second pixel switch element T2 can be a gate electrode, the input electrode of the second pixel switch element T2 can be a source electrode, and the output electrode of the second pixel switch element T2 can be a drain electrode.

[0075] The third pixel switch element T3 includes a control electrode to which a data write gate signal GW is applied, an input electrode connected to the first pixel node N1, and an output electrode connected to the third pixel node N3.

[0076] In an embodiment, for example, the third pixel switch element T3 can be a p-type TFT. The control electrode of the third pixel switch element T3 can be a gate electrode, the input electrode of the third pixel switch element T3 can be a source electrode, and the output electrode of the third pixel switch element T3 can be a drain electrode.

[0077] The fourth pixel switch element T4 includes a control electrode to which a data initialization gate signal GI is applied, an input electrode to which an initialization voltage VI is applied, and an output electrode connected to the first pixel node N1.

[0078] In an embodiment, for example, the fourth pixel switch element T4 can be a p-type TFT. The control electrode of the fourth pixel switch element T4 can be a gate electrode, the input electrode of the fourth pixel switch element T4 can be a source electrode, and the output electrode of the fourth pixel switch element T4 can be a drain electrode.

[0079] The fifth pixel switch element T5 includes a control electrode to which an emission signal EM is applied, an input electrode to which a high power supply voltage ELVDD is applied, and an output electrode connected to the second pixel node N2.

[0080] In an embodiment, for example, the fifth pixel switching element T5 can be a p-type TFT. The control electrode of the fifth pixel switching element T5 can be a gate electrode, the input electrode of the fifth pixel switching element T5 can be a source electrode, and the output electrode of the fifth pixel switching element T5 can be a drain electrode.

[0081] The sixth pixel switching element T6 includes a control electrode to which an emission signal EM is applied, an input electrode connected to the third pixel node N3, and an output electrode connected to the anode electrode of the organic light emitting element OLED.

[0082] In an embodiment, for example, the sixth pixel switching element T6 can be a p-type TFT. The control electrode of the sixth pixel switching element T6 can be a gate electrode, the input electrode of the sixth pixel switching element T6 can be a source electrode, and the output electrode of the sixth pixel switching element T6 can be a drain electrode.

[0083] The seventh pixel switching element T7 includes a control electrode to which an organic light emitting element initialization gate signal GB is applied, an input electrode to which an initialization voltage VI is applied, and an output electrode connected to the anode electrode of the organic light emitting element OLED.

[0084] In an embodiment, for example, the seventh pixel switching element T7 can be a p-type TFT. The control electrode of the seventh pixel switching element T7 can be a gate electrode, the input electrode of the seventh pixel switching element T7 can be a source electrode, and the output electrode of the seventh pixel switching element T7 can be a drain electrode.

[0085] The storage capacitor CST includes a first electrode to which a high power supply voltage ELVDD is applied and a second electrode connected to the first pixel node N1.

[0086] The organic light emitting element OLED includes an anode electrode and a cathode electrode. A low power supply voltage ELVSS can be applied to the cathode electrode.

[0087] In Figure 3 In the first duration DU1, the first pixel node N1 and the storage capacitor CST are initialized in response to a data initialization gate signal GI. In the second duration DU2, in response to a data write gate signal GW, the threshold voltage |VTH| of the first pixel switching element T1 is compensated, and a data voltage VDATA, which is compensated for the threshold voltage |VTH|, is written to the first pixel node N1. In the third duration DU3, the anode electrode of the organic light emitting element OLED is initialized in response to an organic light emitting element initialization gate signal GB. In the fourth duration DU4, the organic light emitting element OLED emits light in response to an emission signal EM, so that the display panel 100 displays an image.

[0088] During the first duration DU1, the data initialization gate signal GI may have an active level. In an embodiment, for example, the active level of the data initialization gate signal GI may be a low level. When the data initialization gate signal GI has an active level, the fourth pixel switching element T4 is turned on so that the initialization voltage (hereinafter, also referred to as "initialization signal") VI may be applied to the first pixel node N1. The data initialization gate signal GI[N] of the current stage may be the scan signal SCAN[N-1] of the previous stage.

[0089] During the second duration DU2, the data write gate signal GW may have an active level. In an embodiment, for example, the active level of the data write gate signal GW may be a low level. When the data write gate signal GW has an active level, the second pixel switch element T2 and the third pixel switch element T3 are turned on. In addition, the first pixel switch element T1 is turned on in response to the initialization signal VI. The data write gate signal GW[N] of the current stage may be the scan signal SCAN[N] of the current stage.

[0090] A voltage obtained by subtracting the threshold voltage |VTH| of the first pixel switching element T1 from the data voltage VDATA may be charged at the first pixel node N1 along a path generated by the first pixel switching element T1 , the second pixel switching element T2 , and the third pixel switching element T3 .

[0091] During the third duration DU3, the organic light emitting element initialization signal GB may have an active level. In an embodiment, for example, the active level of the organic light emitting element initialization gate signal GB may be a low level. When the organic light emitting element initialization gate signal GB has an active level, the seventh pixel switch element T7 is turned on, so that the initialization signal V1 may be applied to the anode electrode of the organic light emitting element OLED. The organic light emitting element initialization gate signal GB[N] of the current stage may be the scan signal SCAN[N+1] of the next stage.

[0092] Although the effective duration of the organic light emitting element initialization gate signal GB may be different from the effective duration of the data write gate signal GW in the illustrated embodiment, the effective duration of the organic light emitting element initialization gate signal GB may be the same as the effective duration of the data write signal GW. In an embodiment, for example, the organic light emitting element initialization gate signal GB of the current stage may be the scan signal SCAN[N] of the current stage. In this case, the control electrode of the seventh pixel switching element T7 may be connected to the control electrode of the second pixel switching element T2.

[0093] During the fourth duration DU4, the emission signal EM (e.g., EM[N]) can have an active level. The active level of the emission signal EM can be a low level. When the emission signal EM has the active level, the fifth pixel switching element T5 and the sixth pixel switching element T6 are turned on. In addition, the first pixel switching element T1 is turned on by the data voltage VDATA.

[0094] A drive current flows through the fifth pixel switching element T5, the first pixel switching element T1, and the sixth pixel switching element T6 to drive the organic light emitting element OLED. The intensity of the drive current can be determined by the level of the data voltage VDATA. The luminance of the organic light emitting element OLED is determined by the intensity of the drive current. The drive current ISD flowing through a path from the input electrode of the first pixel switching element T1 to the output electrode of the first pixel switching element T1 is determined as Equation 1 below.

[0095] [Equation 1]

[0096]

[0097] In Equation 1, μ is the mobility of the first pixel switching element T1. Cox is the capacitance per unit area of the first pixel switching element T1. W / L is the width-to-length ratio of the first pixel switching element T1. VSG is the voltage between the input electrode (i.e., the second pixel node N2) of the first pixel switching element T1 and the control electrode (i.e., the first pixel node (also referred to as a control pixel node) N1) of the first pixel switching element T1. |VTH| is the threshold voltage of the first pixel switching element T1.

[0098] The voltage VG of the first pixel node N1 after the threshold voltage |VTH| is compensated during the second duration DU2 can be expressed as Equation 2 below.

[0099] [Equation 2]

[0100] VG = VDATA - |VTH|

[0101] When the organic light emitting element OLED emits light during the fourth duration DU4, the drive voltage VOV and the drive current ISD can be expressed as Equations 3 and 4 below. In Equation 3, VS is the voltage of the second pixel node N2.

[0102] [Equation 3]

[0103] VOV = VS - VG - |VTH| = ELVDD - (VDATA - |VTH|) - |VTH| = ELVDD - VDATA

[0104] [Equation 4]

[0105]

[0106] The threshold voltage |VTH| is compensated for during the second duration DU2, so that when the organic light emitting element OLED emits light during the fourth duration DU4, the drive current ISD can be determined regardless of the threshold voltage |VTH| of the first pixel switching element T1.

[0107] Figure 4 is a block diagram of the emission driver 600. Figure 1 is a circuit diagram of a stage of the emission driver 600. Figure 5 is a circuit diagram of a stage of the emission driver 600. Figure 4 is a timing chart of input signals, output signals, and control signals of a stage of Figure 6 Figure 5 is a timing chart of input signals, output signals, and control signals of a stage of

[0108] Referring to Figures 1 to 5 , the emission driver 600 includes a plurality of stages ST1 to STM, where M is a natural number.

[0109] The stages ST1 to STM output an emission signal EM to a display area of the display panel 100. In an embodiment, for example, the number of the stages ST1 to STM can be the same as the number of the emission lines EL of the display area. In an embodiment, for example, the number of the stages ST1 to STM can be the same as the number of the pixel rows of the display area of the display panel 100.

[0110] At least one of the stages ST1 to STM can receive a start signal STR, a first clock signal CLK1, a second clock signal CLK2, a protection signal ESR, a first gate power voltage VGH, and a second gate power voltage VGL, and output the emission signal EM. The first gate power voltage VGH is a high gate power voltage. The second gate power voltage VGL is a low gate power voltage. The timing of the first clock signal CLK1 can be different from the timing of the second clock signal CLK2.

[0111] Each of the stages ST1 to STM outputs the emission signal EM, and the emission signal EM is input to an input terminal of a next stage. The start signal of a stage can be the emission signal EM of a previous stage. The first stage does not have a previous stage, so that the start signal STR can be input to the input terminal of the first stage ST1.

[0112] The emission signal EM[1] of the first stage ST1 is output to the display area through a first emission line. The emission signal EM[1] of the first stage ST1 is applied to the input terminal of the second stage ST2.

[0113] The emission signal EM[2] of the second stage ST2 is output to the display area through a second emission line. The emission signal EM[2] of the second stage ST2 is applied to the input terminal of the third stage ST3. ​

[0114] The emission signal EM[3] of the third stage ST3 is output to the display area through a third emission line. The emission signal EM[3] of the third stage ST3 is applied to the input terminal of the fourth stage ST4.

[0115] The emission signal EM[M] of the Mth stage STM is output to the display area through an Mth emission line. The emission signal EM[M-1] of the M-1th stage is applied to the input terminal of the Mth stage STM.

[0116] The first clock signal CLK1 and the second clock signal CLK2 can be alternately applied to the respective stages. In an embodiment, for example, the first clock signal CLK1 can be applied to the first clock terminal of the first stage ST1, and the second clock signal CLK2 can be applied to the second clock terminal of the first stage ST1. In contrast, the second clock signal CLK2 can be applied to the first clock terminal of the second stage ST2, and the first clock signal CLK1 can be applied to the second clock terminal of the second stage ST2. The first clock signal CLK1 can be applied to the first clock terminal of the third stage ST3, and the second clock signal CLK2 can be applied to the second clock terminal of the third stage ST3.

[0117] At least one of the stages ST1 to STM can include a ninth switching element M9 connected between a first gate power voltage terminal to which a first gate power voltage VGH is applied and an emission signal output terminal from which an emission signal EM is output, and a tenth switching element M10 connected between a second gate power voltage terminal to which a second gate power voltage VGL is applied and the emission signal output terminal.

[0118] The ninth switching element M9 can be a pull-up switching element that pulls up the emission signal EM to the first gate power voltage VGH. The tenth switching element M10 can be a pull-down switching element that pulls down the emission signal EM to the second gate power voltage VGL.

[0119] The stage can further include a thirteenth switching element M13 that applies the first gate power voltage VGH to a control electrode of the tenth switching element M10 in response to a protection signal ESR. The thirteenth switching element M13 is also referred to as a protection switching element.

[0120] The stage can include a pull-down portion for an operation of pulling down the emission signal EM to the second gate power voltage VGL. The pull-down portion can include the first switching element M1, the second switching element M2, the third switching element M3, the tenth switching element M10, and the twelfth switching element M12.

[0121] The first switching element M1 can output a start signal (STR or EM of a previous stage) to the fourth node X4 in response to a first clock signal CLK1. A control electrode of the first switching element M1 can be connected to a first clock terminal to which the first clock signal CLK1 is applied. An input electrode of the first switching element M1 can be connected to an input terminal IN to which an input signal (e.g., a start signal) is applied. An output electrode of the first switching element M1 can be connected to the fourth node X4.

[0122] The second switching element M2 can output the first gate supply voltage VGH to the second node X2 in response to a voltage of the first node X1. A control electrode of the second switching element M2 can be connected to the first node X1. An input electrode of the second switching element M2 can be connected to a first gate supply voltage terminal. An output electrode of the second switching element M2 can be connected to the second node X2.

[0123] The third switching element M3 can output a second clock signal CLK2 to the second node X2 in response to a voltage of the third node X3. A control electrode of the third switching element M3 can be connected to the third node X3. An input electrode of the third switching element M3 can be connected to a second clock terminal to which the second clock signal CLK2 is applied. An output electrode of the third switching element M3 can be connected to the second node X2.

[0124] The tenth switching element M10 can output a second gate supply voltage VGL to a transmission signal output terminal from which a transmission signal EM is output in response to a voltage of the eighth node X8. A control electrode of the tenth switching element M10 can be connected to the eighth node X8. An input electrode of the tenth switching element M10 can be connected to a second gate supply voltage terminal. An output electrode of the tenth switching element M10 can be connected to the transmission signal output terminal.

[0125] The twelfth switching element M12 can output a voltage of the fourth node X4 to the eighth node X8 in response to the second gate supply voltage VGL. A control electrode of the twelfth switching element M12 can be connected to the second gate supply voltage terminal. An input electrode of the twelfth switching element M12 can be connected to the fourth node X4. An output electrode of the twelfth switching element M12 can be connected to the eighth node X8.

[0126] The stage can include a pull-up portion for an operation of pulling up the transmission signal EM to the first gate supply voltage VGH. The pull-up portion can include a fourth switching element M4, a fifth switching element M5, a sixth switching element M6, a seventh switching element M7, an eighth switching element M8, a ninth switching element M9, and an eleventh switching element M11.

[0127] The fourth switching element M4 can output the first clock signal CLK1 to the first node X1 in response to a voltage of the fourth node X4. A control electrode of the fourth switching element M4 can be connected to the fourth node X4. An input electrode of the fourth switching element M4 can be connected to the first clock terminal. An output electrode of the fourth switching element M4 can be connected to the first node X1.

[0128] The fifth switching element M5 can output the second gate supply voltage VGL to the first node X1 in response to the first clock signal CLK1. A control electrode of the fifth switching element M5 can be connected to the first clock terminal. An input electrode of the fifth switching element M5 can be connected to the second gate supply voltage terminal. An output electrode of the fifth switching element M5 can be connected to the first node X1.

[0129] The sixth switching element M6 can connect the fifth node X5 to the seventh node X7 in response to the second clock signal CLK2. A control electrode of the sixth switching element M6 can be connected to the second clock terminal. An input electrode of the sixth switching element M6 can be connected to the fifth node X5. An output electrode of the sixth switching element M6 can be connected to the seventh node X7.

[0130] The seventh switching element M7 can output the second clock signal CLK2 to the fifth node X5 in response to a voltage of the sixth node X6. A control electrode of the seventh switching element M7 can be connected to the sixth node X6. An input electrode of the seventh switching element M7 can be connected to the second clock terminal. An output electrode of the seventh switching element M7 can be connected to the fifth node X5.

[0131] The eighth switching element M8 can output the first gate supply voltage VGH to the seventh node X7 in response to a voltage of the fourth node X4. A control electrode of the eighth switching element M8 can be connected to the fourth node X4. An input electrode of the eighth switching element M8 can be connected to the first gate supply voltage terminal. An output electrode of the eighth switching element M8 can be connected to the seventh node X7.

[0132] The ninth switching element M9 can output the first gate supply voltage VGH to the emission signal output terminal in response to a voltage of the seventh node X7. A control electrode of the ninth switching element M9 can be connected to the seventh node X7. An input electrode of the ninth switching element M9 can be connected to the first gate supply voltage terminal. An output electrode of the ninth switching element M9 can be connected to the emission signal output terminal.

[0133] The eleventh switching element M11 can connect the first node X1 to the sixth node X6 in response to the second gate supply voltage VGL. A control electrode of the eleventh switching element M11 can be connected to the second gate supply voltage terminal. An input electrode of the eleventh switching element M11 can be connected to the first node X1. An output electrode of the eleventh switching element M11 can be connected to the sixth node X6.

[0134] The stage can further include a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first capacitor C1 can include a first electrode connected to the first gate supply voltage terminal and a second electrode connected to the seventh node X7. The second capacitor C2 can include a first electrode connected to the fifth node X5 and a second electrode connected to the sixth node X6. The third capacitor C3 can include a first electrode connected to the second node X2 and a second electrode connected to the third node X3.

[0135] The first capacitor C1 can be a voltage stabilizing capacitor for stabilizing the voltage of the seventh node X7. The second capacitor C2 can be a boost capacitor for pulling down the voltage of the seventh node X7 to a low level. The third capacitor C3 can be a boost capacitor for pulling down the voltage of the eighth node X8 to a low level.

[0136] In the illustrated embodiment, the thirteenth switch element M13 can be connected to the fourth node X4.

[0137] The fourth node X4 can also be referred to as a Q node. In addition, the eighth node X8 is connected to the fourth node X4 in response to the second gate supply voltage VGL applied to the twelfth switch element M12, so that the eighth node X8 can also be referred to as a Q node. The seventh node X7 can also be referred to as a QB node.

[0138] In an embodiment, for example, the first switch element M1 to the thirteenth switch element M13 can be p-type TFTs. The control electrode of the first switch element M1 to the thirteenth switch element M13 can be a gate electrode, the input electrode of the first switch element M1 to the thirteenth switch element M13 can be a source electrode, and the output electrode of the first switch element M1 to the thirteenth switch element M13 can be a drain electrode.

[0139] When the first clock signal CLK1 has a low level VGL while the high level VGH is applied to the input terminal IN, the voltage of the fourth node X4 increases to the high level VGH applied to the input terminal IN. Here, for convenience, the term "low level VGL" can mean the level of the second gate supply voltage VGL, and the term "high level VGH" can mean the level of the first gate supply voltage VGH.

[0140] Then, when the second clock signal CLK2 has a low level VGL, the voltage of the seventh node X7 decreases to the low level VGL, and the emission signal EM increases to the high level VGH.

[0141] When the first clock signal CLK1 has the low level VGL and the signal of the input terminal IN decreases to the low level VGL, the voltage of the fourth node X4 decreases to the first low level (e.g., VGL), the voltage of the seventh node X7 increases to the high level VGH, and the emission signal EM decreases to the intermediate level VGL+2|VTH|. The intermediate level VGL+2|VTH| of the emission signal EM has a level slightly higher than the second gate power supply voltage VGL. The 2|VTH| component of the intermediate level VGL+2|VTH| of the emission signal EM can be the threshold voltage of the first switching element M1 and the threshold voltage of the tenth switching element M10.

[0142] Then, when the second clock signal CLK2 has the low level VGL, the voltage of the fourth node X4 decreases to the second low level 2VGL. Here, the emission signal EM decreases from the intermediate level VGL+2|VTH| to the low level VGL. When the intermediate level VGL+2|VTH| or the low level VGL of the emission signal EM is applied to the display panel 100, the display panel 100 can turn on. Although the intermediate level VGL+2|VTH| is not shown in FIG. 6 for convenience of explanation, the emission signal EM can temporarily have the intermediate level VGL+2|VTH| in the initial period of the fourth duration DU4. Figure 3

[0143] When the signal of the input terminal IN remains the low level VGL, the second clock signal CLK2 oscillates between the first low level VGL and the second low level 2VGL according to the waveform of the second clock signal CLK2.

[0144] Figure 7 is a conceptual diagram illustrating an abnormal off operation of the emission driver of Figure 5 when the stage of Figure 1 is a conceptual diagram illustrating an abnormal off operation of the emission driver of

[0145] Figure 7 is a conceptual diagram illustrating the stage of Figure 5 except that the stage of

[0146] Figure 7 A case in which the display apparatus is abnormal and suddenly off is assumed, and for example, the abnormal off case can be a momentary detachment of a battery.

[0147] Referring to Figure 7 , in the abnormal off case, the first gate power supply voltage VGH, the second gate power supply voltage VGL, the first clock signal CLK1, and the second clock signal CLK2 can gradually return to the ground level GND.

[0148] In an embodiment, for example, when the abnormal off case is the TA period (refer to FIG. 6), the first clock signal CLK1 and the second clock signal CLK2 can be set to the low level VGL.​Figure 6 ), the emission signal EM may have the low level VGL, the voltage of the fourth node X4 may have the second low level 2VGL, and the voltage of the seventh node X7 may have the high level VGH.

[0149] In this context, the tenth switching element M10 may be turned on by the voltage of the fourth node X4. In an abnormal shutdown state, the voltage of the seventh node X7 decreases to the ground level GND, so that the ninth switching element M9 and the tenth switching element M10 may be turned on at the same time.

[0150] When the ninth switching element M9 and the tenth switching element M10 are simultaneously turned on, the first gate power voltage VGH and the second gate power voltage VGL may be short-circuited so that all emission signals EM of the emission driver 600 may instantaneously have the ground level GND.

[0151] When all emission signals EM of the emission driver 600 instantaneously have the ground level GND, a low level is applied to Figure 2 The fifth pixel switching element T5 and Figure 2 The sixth pixel switching element T6 is turned on, so that the display panel 100 can flicker as a whole.

[0152] Figure 8A It shows that according to the present invention Figure 1 A conceptual diagram of an embodiment of an abnormal shutdown operation of an emission driver.

[0153] Figure 8A The thirteenth switching element M13 is shown. Figure 5 level. Figure 8A Assume that Figure 7 The assumed case where the display device becomes abnormal and suddenly shuts down.

[0154] refer to Figure 8A , the protection signal ESR applied to the thirteenth switching element M13 may turn on the thirteenth switching element M13 in the initial driving period, and may turn off the thirteenth switching element M13 in the normal driving period after the initial driving period.

[0155] Before the abnormal shutdown situation, the display device may be normally driven so that the protection signal ESR may have a high level and the thirteenth switching element M13 may have a turn-off state.

[0156] The capacitance of the line applying the first gate power supply voltage VGH may be greater than the capacitance of the line applying the protection signal ESR. The width of the line applying the first gate power supply voltage VGH may be greater than the width of the line applying the protection signal ESR. In addition, the load of the line applying the first gate power supply voltage VGH may be greater than the load of the line applying the protection signal ESR. The average level of the first gate power supply voltage VGH is substantially greater than the average level of the protection signal ESR.

[0157] For this reason, when the display device is abnormally shut down, the protection signal ESR applied to the control electrode of the thirteenth switching element M13 decreases faster than the first gate power supply voltage VGH applied to the input electrode of the thirteenth switching element M13, so that the thirteenth switching element M13 is turned on and the tenth switching element M10 is turned off.

[0158] In the illustrated embodiment, the tenth switching element M10 is turned off in the abnormal shutdown condition, so that Figure 7 Unlike the ninth switching element M9 and the tenth switching element M10, the ninth switching element M9 and the tenth switching element M10 are not turned on at the same time. Therefore, the first gate power supply voltage VGH and the second gate power supply voltage VGL are not short-circuited, so that flickering of the display panel 100 can be prevented.

[0159] Figure 8B It shows that according to the present invention Figure 1 A conceptual diagram of an embodiment of an abnormal shutdown operation of an emission driver.

[0160] exist Figure 8B In the embodiment of the present invention, each of the switching elements of the stages of the emission driver 600 may include a dual-gate electrode. The stages of the emission driver 600 may include dual-gate switching elements M1, M1-1, M2, M2-1, M3, M3-1, M4, M4-1, M5, M5-1, M6, M6-1, M7, M7-1, M8, M8-1, M9, M9-1, M10, M10-1, M11, M11-1, M12, M12-1, M13, and M13-1. The dual-gate switching elements may include switching elements forming a pair and connected in series with each other.

[0161] In addition to each of the switching elements of the stages of the emission driver 600 being a dual-gate switching element, Figure 8B The circuit diagram can be compared with Figure 8A The circuit diagrams are basically the same.

[0162] Figure 9 It shows that Figure 5 When the stage does not include the thirteenth switching element Figure 1 Timing diagram of the initial driving operation of the transmit driver. Figure 10 It shows that Figure 5 When the stage does not include the thirteenth switching element Figure 1a conceptual diagram of an initial driving operation of an emission driver.

[0163] Figure 9 and Figure 10 shows the stage except that the stage does not include the thirteenth switching element M13. Figure 5 the stage to explain the function of the thirteenth switching element M13.

[0164] Referring to Figure 9 and Figure 10 In the initial driving period INITIAL, the start signal STR can have the first gate power supply voltage VGH, the first clock signal CLK1 can have the second gate power supply voltage VGL, and the second clock signal CLK2 can have the second gate power supply voltage VGL.

[0165] In the initial driving period INITIAL, the start signal STR is applied to the first stage, and both the first clock signal CLK1 and the second clock signal CLK2 of the first stage can have a low level. Accordingly, the control electrode of the ninth switching element M9 can have a low level, and the control electrode of the tenth switching element M10 can have a high level. Then, the ninth switching element M9 is turned on and the tenth switching element M10 is turned off, so that the emission signal EM can output a high level. Figure 10 The high level of the emission signal EM output from the first stage is applied to the next stage as a carry signal, so that the stages of the emission driver 600 respectively output the emission signal EM in a cascading manner.

[0166] However, when the emission signal EM is applied to the next stage, a propagation delay can be generated by the wiring resistance RC and the load capacitance CL. In the last stage of the emission driver 600 in

[0167] the tenth switching element M10 is desired to be turned off when the ninth switching element M9 is turned on. However, in the last stage of the emission driver 600 in Figure 10 the tenth switching element M10 can be turned on when the ninth switching element M9 is turned on due to the propagation delay, so that the ninth switching element M9 and the tenth switching element M10 can be simultaneously turned on. Figure 10 When the ninth switching element M9 and the tenth switching element M10 are simultaneously turned on, the first gate power supply voltage VGH and the second gate power supply voltage VGL can be short-circuited, so that all of the emission signals EM of the emission driver 600 can momentarily have a ground level GND.

[0168] When all of the emission signals EM of the emission driver 600 momentarily have the ground level GND, a low level is applied to the fifth pixel switching element T5 of

[0169] and the sixth pixel switching element T6 of Figure 2 Figure 2 When all of the emission signals EM of the emission driver 600 momentarily have the ground level GND, a low level is applied to the fifth pixel switching element T5 of Figure 2the sixth pixel switching element T6, so that the display panel 100 can flicker as a whole.

[0170] Figure 11 is a timing chart illustrating an initial driving operation of the emission driver 600. Figure 1 Figure 12 is a conceptual diagram illustrating an initial driving operation of the emission driver 600. Figure 1

[0171] Figure 11 and Figure 12 illustrates a stage of the emission driver 600 including the thirteenth switching element M13. Figure 5 Figure 11 and Figure 12 indicates an operation of the emission driver 600 in the initial driving period INITIAL.

[0172] With reference to Figure 11 and Figure 12 , in the initial driving period INITIAL, the start signal STR can have the first gate power supply voltage VGH, the first clock signal CLK1 can have the second gate power supply voltage VGL, and the second clock signal CLK2 can have the second gate power supply voltage VGL.

[0173] In addition, the protection signal ESR can turn on the thirteenth switching element M13 in the initial driving period INITIAL, and can turn off the thirteenth switching element M13 in a normal driving period after the initial driving period INITIAL.

[0174] In the embodiment, for example, the protection signal ESR can have the second gate power supply voltage VGL in the initial driving period INITIAL.

[0175] In the initial driving period INITIAL, the thirteenth switching element M13 is turned on by the low level of the protection signal ESR, and the fourth node X4 is initialized to the first gate power supply voltage VGH. Thus, in the initial driving period INITIAL, the tenth switching element M10 is necessarily turned off.

[0176] In the illustrated embodiment, the tenth switching element M10 is turned off in the initial driving period INITIAL, so that, unlike Figure 10 , the ninth switching element M9 and the tenth switching element M10 are not turned on at the same time. Thus, the first gate power supply voltage VGH and the second gate power supply voltage VGL are not short-circuited, so that flicker of the display panel 100 can be prevented.

[0177] ​​​According to the illustrated embodiment, the stage of the emission driver 600 includes a flash prevention switching element (i.e., the thirteenth switching element M13), so that image flicker can be prevented from occurring in an initial driving period and an abnormal off case. Accordingly, the display quality of the display panel can be improved.

[0178] Figure 13 is a circuit diagram illustrating an embodiment of a stage of an emission driver according to the present application.

[0179] The emission driver, the display device, and the method of driving the display device in the illustrated embodiment are substantially the same as those described with reference to the previous embodiments except for the connection of the thirteenth switching element M13. Figures 1 to 12 The emission driver, the display device, and the method of driving the display device of the explained previous embodiments are substantially the same. Accordingly, the same reference numerals will be used to refer to the same or similar components as those described in the previous embodiments, and any repeated explanation regarding the above elements will be omitted. Figures 1 to 12

[0180] With reference to the previous embodiments, Figure 13 At least one of the stages can include a ninth switching element M9 connected between a first gate power voltage terminal to which a first gate power voltage VGH is applied and an emission signal output terminal outputting an emission signal EM, and a tenth switching element M10 connected between a second gate power voltage terminal to which a second gate power voltage VGL is applied and the emission signal output terminal.

[0181] The ninth switching element M9 can be a pull-up switching element that pulls up the emission signal EM to the first gate power voltage VGH. The tenth switching element M10 can be a pull-down switching element that pulls down the emission signal EM to the second gate power voltage VGL.

[0182] The stage can further include a thirteenth switching element M13 that applies the first gate power voltage VGH to a control electrode of the tenth switching element M10 in response to a protection signal ESR.

[0183] In the illustrated embodiment, the eighth node X8 can be connected to the thirteenth switching element M13.

[0184] In an embodiment, for example, similarly to Figure 8B , Figure 13 Each of the switching elements of the stage of the emission driver 600 can include a dual gate electrode.

[0185] According to the illustrated embodiment, the stage of the emission driver 600 includes a flash prevention switching element (i.e., the thirteenth switching element M13), so that image flicker can be prevented from occurring in an initial driving period and an abnormal off case. Accordingly, the display quality of the display panel can be improved. ​

[0186] According to the present application as explained above, the display quality of the display panel can be improved.

[0187] The foregoing is considered as illustrative only of the principles of the application. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the application to the exact construction and operation described. Accordingly, all such variations are intended to be included within the scope of the present application as defined in the claims. Thus, it should be understood that the above description is intended for illustrative purposes only and is not intended to limit the scope of the present application as defined by the following claims and the regions of equivalents thereof.

Claims

1. A transmit driver comprising a plurality of stages, in, A stage of the plurality of stages receives a start signal, a first clock signal, a second clock signal, a protection signal, a first gate power supply voltage, and a second gate power supply voltage, and outputs a transmission signal, and The stages in the plurality of stages include: a pull-up switching element connected between a first gate power supply voltage terminal receiving the first gate power supply voltage and a transmission signal output terminal outputting the transmission signal; a pull-down switching element connected between a second gate power supply voltage terminal receiving the second gate power supply voltage and the transmission signal output terminal; a protection switching element that applies the first gate power supply voltage to a control electrode of the pull-down switching element in response to the protection signal; and A twelfth switching element includes a control electrode electrically connected to the second gate power supply voltage terminal, a first electrode connected to the electrode of the protection switching element, and a second electrode connected to the control electrode of the pull-down switching element.

2. The transmit driver according to claim 1, wherein: The stage of the plurality of stages further comprises: a first switching element, applying the start signal to a fourth node in response to the first clock signal; a second switching element that applies the first gate power supply voltage to a second node in response to the voltage of the first node; and The third switching element applies the second clock signal to the second node in response to the voltage of the third node.

3. The transmit driver according to claim 2, wherein: The stage of the plurality of stages further comprises: a fourth switching element, configured to apply the first clock signal to the first node in response to a voltage of the fourth node; a fifth switching element, applying the second gate power supply voltage to the first node in response to the first clock signal; a sixth switching element, connected to the fifth node and the seventh node in response to the second clock signal; a seventh switching element, configured to apply the second clock signal to the fifth node in response to a voltage of the sixth node; an eighth switching element that applies the first gate power supply voltage to the seventh node in response to the voltage of the fourth node; and An eleventh switching element connects the first node to the sixth node in response to the second gate power supply voltage.

4. The transmit driver according to claim 3, wherein: The stage of the plurality of stages further includes a first capacitor including a first electrode connected to the first gate power supply voltage terminal and a second electrode connected to the seventh node.

5. The transmit driver according to claim 4, wherein: The stage of the plurality of stages further includes a second capacitor including a first electrode connected to the fifth node and a second electrode connected to the sixth node.

6. The transmit driver according to claim 5, wherein: The stage of the plurality of stages further includes a third capacitor including a first electrode connected to the second node and a second electrode connected to the third node.

7. The transmit driver according to any one of claims 2 to 6, wherein: The protection switching element is connected to the fourth node.

8. The transmit driver according to any one of claims 2 to 6, wherein: The protection switching element is connected to an eighth node.

9. The transmit driver according to any one of claims 1 to 6, wherein: The protection signal turns on the protection switching element in an initial driving period and turns off the protection switching element in a normal driving period following the initial driving period.

10. The transmit driver according to claim 9, wherein: In the initial driving period, The start signal has the first gate power supply voltage, the first clock signal having the second gate supply voltage, The second clock signal has the second gate supply voltage, and The protection signal has the second gate power supply voltage.

11. The transmit driver according to any one of claims 1 to 6, wherein: The capacitance of the line to which the first gate power supply voltage is applied is greater than the capacitance of the line to which the protection signal is applied.

12. A display device comprising: A display panel displays an image; a gate driver for providing a gate signal to the display panel; a data driver for providing a data voltage to the display panel; as well as an emission driver, providing an emission signal to the display panel, Wherein, the transmit driver includes multiple stages, wherein a stage in the plurality of stages receives a start signal, a first clock signal, a second clock signal, a protection signal, a first gate power supply voltage, and a second gate power supply voltage, and outputs the emission signal, and The stages in the plurality of stages include: a pull-up switching element connected between a first gate power supply voltage terminal receiving the first gate power supply voltage and a transmission signal output terminal outputting the transmission signal; a pull-down switching element connected between a second gate power supply voltage terminal receiving the second gate power supply voltage and the transmission signal output terminal; a protection switching element that applies the first gate power supply voltage to a control electrode of the pull-down switching element in response to the protection signal; and A twelfth switching element includes a control electrode electrically connected to the second gate power supply voltage terminal, a first electrode connected to the electrode of the protection switching element, and a second electrode connected to the control electrode of the pull-down switching element.

13. The display device according to claim 12, wherein: The stage of the plurality of stages further comprises: a first switching element, applying the start signal to a fourth node in response to the first clock signal; a second switching element that applies the first gate power supply voltage to a second node in response to the voltage of the first node; and The third switching element applies the second clock signal to the second node in response to the voltage of the third node.

14. The display device according to claim 13, wherein: The stage of the plurality of stages further comprises: a fourth switching element, configured to apply the first clock signal to the first node in response to a voltage of the fourth node; a fifth switching element, applying the second gate power supply voltage to the first node in response to the first clock signal; a sixth switching element, connected to the fifth node and the seventh node in response to the second clock signal; a seventh switching element, configured to apply the second clock signal to the fifth node in response to a voltage of the sixth node; an eighth switching element that applies the first gate power supply voltage to the seventh node in response to the voltage of the fourth node; and An eleventh switching element connects the first node to the sixth node in response to the second gate power supply voltage.

15. The display device according to claim 14, wherein The stage of the plurality of stages further comprises: a first capacitor including a first electrode connected to the first gate power supply voltage terminal and a second electrode connected to the seventh node; a second capacitor including a first electrode connected to the fifth node and a second electrode connected to the sixth node; and The third capacitor includes a first electrode connected to the second node and a second electrode connected to the third node.

16. The display device according to any one of claims 12 to 15, wherein: The display panel includes a plurality of pixels, each of the plurality of pixels includes an organic light emitting element, and The pixels among the plurality of pixels receive a data writing gate signal, a data initialization gate signal, an organic light emitting element initialization gate signal, the data voltage and the emission signal, and make the organic light emitting element emit light according to the level of the data voltage to display the image.

17. The display device according to claim 16, wherein: The pixels of the plurality of pixels include: a first pixel switching element comprising a control electrode connected to the first pixel node, an input electrode connected to the second pixel node, and an output electrode connected to the third pixel node; a second pixel switching element comprising a control electrode applied with the data write gate signal, an input electrode applied with the data voltage, and an output electrode connected to the second pixel node; a third pixel switching element comprising a control electrode to which the data write gate signal is applied, an input electrode connected to the first pixel node, and an output electrode connected to the third pixel node; a fourth pixel switching element comprising a control electrode applied with the data initialization gate signal, an input electrode applied with an initialization voltage, and an output electrode connected to the first pixel node; a fifth pixel switching element comprising a control electrode to which the emission signal is applied, an input electrode to which a high power supply voltage is applied, and an output electrode connected to the second pixel node; a sixth pixel switching element, comprising a control electrode to which the emission signal is applied, an input electrode connected to the third pixel node, and an output electrode connected to the anode electrode of the organic light emitting element; a seventh pixel switching element, comprising a control electrode applied with an initialization gate signal of the organic light emitting element, an input electrode applied with the initialization voltage, and an output electrode connected to the anode electrode of the organic light emitting element; a storage capacitor including a first electrode to which the high power supply voltage is applied and a second electrode connected to the first pixel node; and The organic light emitting element includes the anode electrode and a cathode electrode to which a low power supply voltage is applied.

18. A method for driving a display device, the method comprising: providing a gate signal to the display panel using a gate driver; supplying a data voltage to the display panel using a data driver; as well as providing an emission signal to the display panel using an emission driver, Wherein, the transmit driver includes multiple stages, wherein a stage in the plurality of stages receives a start signal, a first clock signal, a second clock signal, a protection signal, a first gate power supply voltage, and a second gate power supply voltage, and outputs the emission signal, and The stages in the plurality of stages include: a pull-up switching element connected between a first gate power supply voltage terminal receiving the first gate power supply voltage and a transmission signal output terminal outputting the transmission signal; a pull-down switching element connected between a second gate power supply voltage terminal receiving the second gate power supply voltage and the transmission signal output terminal; a protection switching element that applies the first gate power supply voltage to a control electrode of the pull-down switching element in response to the protection signal; and A twelfth switching element includes a control electrode electrically connected to the second gate power supply voltage terminal, a first electrode connected to the electrode of the protection switching element, and a second electrode connected to the control electrode of the pull-down switching element.

19. The method according to claim 18, wherein The protection signal turns on the protection switching element in an initial driving period and turns off the protection switching element in a normal driving period following the initial driving period.

20. The method according to claim 18 or 19, wherein The capacitance of the line to which the first gate power supply voltage is applied is greater than the capacitance of the line to which the protection signal is applied, and When the display device is abnormally shut down, the protection signal applied to the control electrode of the protection switch element decreases faster than the first gate power supply voltage applied to the input electrode of the protection switch element, so that the protection switch element is turned on and the pull-down switch element is turned off.

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