Data processing apparatus, data processing device and system for driving a display device

Abstract

The present disclosure relates to a data driving apparatus, a data processing apparatus, and a system for driving a display device, and more particularly, to a data driving apparatus, a data processing apparatus, and a system for smoothly performing low-speed communication through a communication line including an AC coupling capacitor.

Description

Technical Field

[0001] This disclosure relates to a technique for driving a display device. Background Technology

[0002] Existing technology

[0003] Display devices typically include a display panel for displaying images, and a timing controller, source drivers, and gate drivers for driving the display panel. The display panel includes multiple gate lines, multiple data lines, and multiple pixels. The source drivers output data signals to the data lines, and the gate drivers output gate signals to drive the gate lines. The timing controller controls the source drivers and gate drivers.

[0004] In this type of display device, an image is displayed by applying a gate signal with a gate on-voltage level to the gate line by a gate driver, and then providing a data signal corresponding to the image signal to the data line by a source driver.

[0005] The timing controller and the source driver are connected via signal lines. For the signal transmitted from the timing controller to be stably recovered in the source driver, the common-mode voltage level of the signal transmitted from the timing controller must match the common-mode voltage level of the signal processing circuitry within the source driver. However, due to the increased data transmission rate caused by the magnification of the display panel, and the increased communication speed resulting from the increased data transmission rate, the common-mode voltage level of the signal transmitted from the timing controller may differ from the common-mode voltage level of the signal processing circuitry within the source driver.

[0006] Here, if an AC coupling capacitor is connected to the communication line, the DC component in the signal transmitted from the timing controller can be minimized, thereby eliminating the difference between the levels of the common-mode voltage.

[0007] As described above, communication lines including AC coupling capacitors can allow the establishment of an environment for high-speed communication between the timing controller and the source driver.

[0008] On the other hand, timing controllers and source drivers can establish an environment for high-speed communication by performing low-speed communication before performing high-speed communication.

[0009] In low-speed communication with a timing controller, the source driver can use both positive (+) and negative (-) voltage levels to sense bits in the signal.

[0010] Traditionally, when generating high-speed communication signals and low-speed communication signals, such as Figure 8A and Figure 8B As shown, the timing controller uses common codes such as non-return-to-zero (NRZ) codes to encode high-speed and low-speed communication signals.

[0011] Because the AC coupling capacitor connected to the communication line is designed for high-speed communication, the source driver can smoothly handle high-speed communication signals encoded using common codes in high-speed communication.

[0012] However, in low-speed communication, the source driver may not be able to smoothly handle low-speed communication signals encoded using generic codes.

[0013] For example, in the case where a low-speed communication signal includes data bits corresponding to binary 0 bits that alternate with data bits corresponding to binary 1 bits, the low-speed communication signal encoded using a general code has the following characteristics: Figure 8A The alternation of negative (-) and positive (+) voltage levels shown allows the source driver to properly sense data bits of low-speed communication signals.

[0014] However, when a low-speed communication signal comprises at least two consecutive data bits corresponding to a binary number "0" or "1", the low-speed communication signal encoded using a generic code may include a portion whose voltage level remains unchanged, corresponding to at least two consecutive identical data bits. As the length of the portion of consecutive identical data bits increases, the probability that the source driver may fail to detect the data bits in that portion increases, and this may lead to abnormal detection of data bits in the low-speed communication signal. Summary of the Invention

[0015] In this context, one aspect of the present invention is to provide a technique for smoothly performing low-speed communication in a display device via a communication line including an AC coupling capacitor.

[0016] To this end, in one aspect, this disclosure provides a system comprising: a communication line including at least one alternating current (AC) coupling capacitor; a data processing device connected to one end of the communication line for transmitting a configuration data signal encoded using a DC balanced code to the communication line in low-speed communication and subsequently performing high-speed communication; and a data driving device connected to the other end of the communication line for receiving the configuration data signal from the communication line, decoding the configuration data signal into configuration data using the DC balanced code, establishing a high-speed communication environment based on the configuration data, and performing high-speed communication with the data processing device.

[0017] The DC balanced code may include Manchester code.

[0018] The configuration data signal may include multiple data entries, each data entry including header data, body data, and checksum data. The configuration data signal may also include a start bit placed before the multiple data entries and an end bit placed after the multiple data entries.

[0019] Before transmitting the configuration data signal to the data driving device via the communication line, the data processing device may transmit a preamble signal encoded using the Manchester code to the data driving device via the communication line. The preamble signal may be a signal that repeats the Manchester code corresponding to any binary number N times, where N is a natural number equal to or greater than 2.

[0020] The communication line may include a first line and a second line, wherein the first line includes a first AC coupling capacitor and the second line includes a second AC coupling capacitor.

[0021] The first line may further include a third AC coupling capacitor. In the first line, the first AC coupling capacitor may be configured to be adjacent to the data processing device, and the third AC coupling capacitor may be configured to be adjacent to the data driving device.

[0022] The second line may further include a fourth AC coupling capacitor. In the second line, the second AC coupling capacitor may be configured to be adjacent to the data processing device, and the fourth AC coupling capacitor may be configured to be adjacent to the data driving device.

[0023] The DC balance code may include 8B10B code.

[0024] The configuration data signal may include multiple data entries, each of which includes a start symbol, header data, body data, and checksum data. The configuration data signal may also include an end symbol placed after the multiple data entries.

[0025] The start symbol and the end symbol may each include a comma string.

[0026] The data processing device can transmit a preamble signal encoded using 8B10B code to the data driving device via the communication line before transmitting the configuration data signal to the data driving device via the communication line. The preamble signal can be a signal in which data bits corresponding to binary numbers "1" and "0" appear regularly, such that the number of data bits corresponding to binary numbers "1" and "0" appearing are balanced.

[0027] In another aspect, this disclosure provides a data driving device, comprising: a receiving circuit connected to a communication line including at least one AC coupling capacitor, for receiving a configuration data signal encoded using a DC balanced code via the communication line in low-speed communication; a decoder for receiving the configuration data signal from the receiving circuit, decoding the configuration data signal into configuration data using the DC balanced code, and outputting the configuration data; and a control circuit for activating the receiving circuit and the decoder to perform the low-speed communication via the communication line when power is applied, establishing a high-speed communication environment based on the configuration data output from the decoder, and performing high-speed communication via the communication line.

[0028] The configuration data may include the gain level of the equalizer used for the high-speed communication.

[0029] When performing the high-speed communication, the control circuit can disable the receiving circuit and the decoder.

[0030] In another aspect, this disclosure provides a data processing apparatus, comprising: a control circuit for generating configuration data for establishing a high-speed communication environment at a receiving side, and for generating a configuration data signal including the configuration data by encoding the configuration data into a configuration data signal using a DC balanced code; and a transmission circuit connected to a communication line including at least one AC coupling capacitor for transmitting the configuration data signal to the receiving side via the communication line in low-speed communication.

[0031] The control circuit can generate a preamble signal before transmitting the configuration data signal, in which the Manchester code corresponding to any binary number is repeated N times, where N is a natural number equal to or greater than 2, and the transmission circuit can transmit the preamble signal through the communication line in the low-speed communication.

[0032] As described above, according to this disclosure, DC balanced codes are used to encode low-speed protocol signals in the display device, and this can allow for minimization of communication errors caused by AC capacitors in the communication lines during low-speed communication of the display device. Attached Figure Description

[0033] The above and other aspects, features and advantages of this disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0034] Figure 1 This is a configuration diagram of a display device according to an embodiment;

[0035] Figure 2A and Figure 2BThis is a configuration diagram of the system according to an embodiment;

[0036] Figure 3 This is a diagram illustrating the signal sequence between a data processing device and a data driving device according to an embodiment;

[0037] Figure 4A and Figure 4B This is a diagram illustrating Manchester code;

[0038] Figure 5A and Figure 5B This is a timing diagram of the low-speed communication segment according to an embodiment;

[0039] Figure 6 This is a detailed configuration diagram of the data processing device and the data driving device according to an embodiment;

[0040] Figure 7 This is a flowchart illustrating the process by which a data-driven device according to an embodiment processes a receiving-side configuration data signal; and

[0041] Figure 8A and Figure 8B This is an illustration of a traditional technique. Detailed Implementation

[0042] Figure 1 This is a configuration diagram of a display device according to an embodiment.

[0043] Reference Figure 1 The display device 100 may include a display panel 110, a data driving device 120, a gate driving device 130, and a data processing device 140.

[0044] On the display panel 110, multiple data lines DL and multiple gate lines GL can be provided, and multiple pixels can also be provided. A pixel may include multiple subpixels SP. A subpixel may be a red (R) subpixel, a green (G) subpixel, a blue (B) subpixel, and a white (W) subpixel. A pixel may include RGB subpixel SP, RGBG subpixel SP, or RGBW subpixel SP. For ease of description, the following description will assume that the pixel includes RGB subpixels.

[0045] The data driving device 120, the gate driving device 130, and the data processing device 140 are used to generate signals for displaying images on the display panel 110.

[0046] The gate driving device 130 can provide a gate driving signal, such as an on-state voltage or an off-state voltage, via the gate line GL. When an on-state gate driving signal is provided to the sub-pixel SP, the sub-pixel SP is connected to the data line DL. When an off-state gate driving signal is provided to the sub-pixel SP, the sub-pixel SP is disconnected from the data line DL. The gate driving device 130 can be referred to as a gate driver.

[0047] The data driving device 120 can provide a data voltage Vp to the sub-pixel SP via the data line DL. The data voltage Vp provided via the data line DL can be provided to the sub-pixel SP according to the gate drive signal. The data driving device 120 can be referred to as a source driver.

[0048] The data driving device 120 may include at least one integrated circuit, which may be connected to the bonding pads of the display panel 110 by a tape-on-brush (TAB) method or a chip-on-glass (COG) method, formed directly on the display panel 110, or integrated on the display panel 110 as appropriate. Furthermore, the data driving device 120 may be formed using a chip-on-glass (COF) method.

[0049] The data processing device 140 can provide control signals to the gate driving device 130 and the data driving device 120. For example, the data processing device 140 can transmit a gate control signal GCS to initiate a scan to the gate driving device 130, output an image data signal to the data driving device 120, and transmit a data control signal DCS to control the data driving device 120 to supply the data voltage Vp to each sub-pixel SP. The data processing device 140 can be referred to as a timing controller.

[0050] According to an embodiment, when a drive voltage VCC is provided to the data processing device 140 and the data driving device 120, low-speed communication between the data processing device 140 and the data driving device 120 can be performed via the first communication line LN1. After low-speed communication, high-speed communication can be performed via the first communication line LN1.

[0051] This will be described in detail below.

[0052] Figure 2A and Figure 2B This is a configuration diagram of the system according to an embodiment, and Figure 3 This is a diagram illustrating the signal sequence between a data processing device and a data driving device according to an embodiment.

[0053] The first communication line (LN1) 200 may include at least one AC coupling capacitor 212, 222, such as Figure 2AAs shown. Specifically, the first communication line (LN1) 200 may include a first line 210 containing a first AC coupling capacitor 212 and a second line 220 containing a second AC coupling capacitor 222.

[0054] like Figure 2B As shown, the first line 210 may also include a third AC coupling capacitor 214, and the second line 220 may also include a fourth AC coupling capacitor 224.

[0055] In the case where the first line 210 also includes a third AC coupling capacitor 214, the first AC coupling capacitor 212 can be configured to be adjacent to the data processing device 140, and the third AC coupling capacitor 214 can be configured to be adjacent to the data driving device 120.

[0056] In the case where the second line 220 also includes a fourth AC coupling capacitor 224, the second AC coupling capacitor 222 can be configured to be adjacent to the data processing device 140, and the fourth AC coupling capacitor 224 can be configured to be adjacent to the data driving device 120.

[0057] Adding a third AC coupling capacitor 214 and a fourth AC coupling capacitor 224 to the first line 210 and the second line 220 respectively can allow for additional improvement in the receiving performance of the data driving device 120 in low-speed communication.

[0058] The data processing device 140 can be connected to one end of the first communication line (LN1) 200, and the data driving device 120 can be connected to the other end of the first communication line (LN1) 200. In other words, the data processing device 140 and the data driving device 120 can communicate with each other through the first communication line (LN1) 200.

[0059] When the driving voltage VCC is supplied to the data processing device 140 and the data driving device 120 while they are interconnected via the first communication line (LN1) 200, the data processing device 140 and the data driving device 120 can operate for a predetermined period of time (e.g., during...). Figure 3 During the command mode period, low-speed communication is performed via the first communication line (LN1) 200. After the predetermined time has elapsed (e.g., from...), low-speed communication is performed via the first communication line (LN1) 200. Figure 3 In the automatic training mode, the data processing device 140 and the data driving device 120 can perform high-speed communication. Here, the frequency of high-speed communication can be more than 10 times higher than the frequency of low-speed communication.

[0060] On the other hand, in high-speed communication, the data loss rate may vary greatly depending on the configuration of the data driving device 120 as the receiving side, or communication may not be performed smoothly.

[0061] According to an embodiment, before performing high-speed communication between the data processing device 140 and the data driving device 120, the receiving-side configuration data for smoothing high-speed communication can be transmitted to the data driving device 120 using a low-speed protocol signal PS2, which corresponds to low-speed communication. This is because, in low-speed communication, the data loss rate does not vary significantly depending on the configuration of the data driving device 120; therefore, the receiving-side configuration data can be transmitted to the data driving device 120 relatively correctly.

[0062] According to an embodiment, before transmitting the high-speed protocol signal PS1 corresponding to high-speed communication, the data processing device 140 may transmit a low-speed protocol signal PS2 including receiving-side configuration data.

[0063] Here, the data processing device 140 can encode the low-speed protocol signal PS2 using a DC balanced code.

[0064] The reason is that when the low-speed protocol signal PS2 is encoded using DC balanced code, the data can be modulated so that binary numbers "0" and "1" appear at similar frequencies in long segments of the low-speed protocol signal PS2. This modulation results in a state where there are no segments with constant data or such segments with constant data are short, and this allows for a reduction in transmission errors caused by at least one AC coupling capacitor 212, 222 included in the first communication line (LN1) 200.

[0065] According to an embodiment, the DC balanced code may include Manchester code or 8B10B code.

[0066] When using Manchester code, the voltage level can be changed at the middle position of each data bit, such as... Figure 4A and Figure 4B As shown. For example, even as Figure 4A The data bits shown are repeated, corresponding to the binary number "0", or as follows: Figure 4B The data bits corresponding to the binary number "1" shown can also have their voltage levels changed at the middle position of each data bit. Therefore, the data driving device 120 can sense the repeated changes in voltage level, and this allows the data driving device 120 to correctly sense the repeated data bits.

[0067] When using 8B10B code, the number of repetitions of data bits corresponding to binary "1" or binary "0" can be minimized (e.g., a maximum of 4). Therefore, the reduction in the sensing rate of the data driving device 120 for repetitive data bits can be minimized.

[0068] On the other hand, such as Figure 3 As shown, the time segment during which the data processing device 140 transmits the low-speed protocol signal PS2 (e.g., Figure 3 The command mode section (CFG) can include a preamble section, a CFG data section, and a CFG completion section.

[0069] In the preamble section, the low-speed protocol signal PS2 may include a preamble signal that serves as a low-speed communication clock signal. Here, the data processing device 140 may encode the preamble signal using a DC balanced code.

[0070] When the DC balanced code is Manchester code, the preamble signal can be a signal in which the Manchester code corresponding to the binary number "1" or binary number "0" can be repeated N times (N is a natural number equal to or greater than 2). For example, when the Manchester code corresponding to the binary number "0" is repeated N times, such as... Figure 5A As shown, the preamble signal can have a general clock pattern, and the data driving device 120 can use the preamble signal to train a clock for low-speed communication.

[0071] When the DC balanced code is 8B10B code, the preamble signal can be a signal in which data bits corresponding to binary "1" and binary "0" appear regularly such that the number of occurrences of data bits corresponding to binary "1" and binary "0" is balanced. For example, the preamble signal can be a signal in which data bits corresponding to binary "1" and data bits corresponding to binary "0" can repeat and alternate with each other.

[0072] When the data bits corresponding to binary "1" and binary "0" can appear regularly such that the number of data bits corresponding to binary "1" and binary "0" is balanced, the preamble signal can have the following characteristics: Figure 5B The general clock pattern shown is used, and the data driving device 120 can use a preamble signal to train a clock for low-speed communication.

[0073] On the other hand, the low-speed protocol signal (PS2) may include receiver-side configuration data in the CFG data segment. The data driving device 120 may use a clock for low-speed communication in the CFG data segment to receive the low-speed protocol signal PS2. Hereinafter, the low-speed protocol signal PS2 transmitted or received in the CFG data segment will be referred to as the receiver-side configuration data signal.

[0074] When using Manchester code to encode the receiver configuration data signal CFG DATA (CFG data), such as Figure 5A As shown, the received-side configuration data signal CFG DATA may include multiple configuration data CFG DATA "1" to CFG DATA "N", and may also include a start bit CFGS placed before the multiple configuration data CFG DATA "1" to CFG DATA "N" and an end bit CFGE placed after the multiple configuration data CFG DATA "1" to CFG DATA "N". Each configuration data includes header data, body data, and checksum data. Here, the start bit CFGS and the end bit CFGE may each contain different data bits. For example, if the start bit CFGS is a data bit corresponding to the binary number "0", then the end bit CFGE may be a data bit corresponding to the binary number "1".

[0075] When using 8B10B code to encode the receiver configuration data signal CFG DATA, such as Figure 5B As shown, the receiving-side configuration data signal CFG DATA may include multiple configuration data CFG DATA "1" to CFG DATA "N", and may also include an end symbol arranged after the multiple configuration data CFG DATA "1" to CFG DATA "N". Each configuration data includes a start symbol, header data, body data, and checksum data. Here, the start symbol in each of the multiple configuration data CFG DATA "1" to CFG DATA "N" and the end symbol arranged after the multiple configuration data CFG DATA "1" to CFG DATA "N" may each include a comma bit string, each comma bit string being a special bit string used to distinguish between signals. For example, the start symbol may include a comma bit string such as "001111", and the end symbol may include a comma bit string such as "110000".

[0076] After receiving the receiving-side configuration data signal, the data driver device 120 can decode the receiving-side configuration data signal into receiving-side configuration data using a DC balanced code. Then, the data driver device 120 can establish a high-speed communication environment and perform high-speed communication with the data processing device 140 based on the receiving-side configuration data.

[0077] The receiver-side configuration data, including multiple configuration data CFG DATA "1" to CFG DATA "N", may include configuration data for the data driving device 120 used for high-speed communication, such as equalizer gain level, scrambling information, and line polarity information. The data driving device 120 can use the receiver-side configuration data to establish circuitry for high-speed communication. Here, the scrambling information may include information related to whether the data is scrambled when the data processing device 140 transmits data to the data driving device 120, and the line polarity information may include information indicating the polarity of the first line of a pixel.

[0078] In the CFG completion segment, the second protocol PS2 may include a message indicating the end of low-speed communication. The data driving device 120 can terminate communication according to the second protocol PS2 by checking this message. Here, the message indicating the end of low-speed communication may be formed by a signal maintained at a high or low level for a predetermined time.

[0079] After passing through the CFG completion section, the data processing device 140 and the data driving device 120 can perform high-speed communication via the first communication line (LN1) 200.

[0080] on the other hand, Figure 1 The auxiliary communication signal ALP shown can initially be maintained at a low level and then changed to a high level when the training of the low-speed data communication clock is completed. When a drive voltage VCC is provided, the data driving device 120 can maintain the auxiliary communication signal ALP at a low level, and then change it to a high level when the training of the low-speed communication clock is completed in the preamble segment. After the level of the auxiliary communication signal ALP changes to a high level, the data processing device 140 can transmit the receiver configuration data signal, which is the low-speed protocol signal PS2. Here, the auxiliary communication signal ALP can be referred to as the lock signal LOCK, and it is transmitted to the data processing device 140 via the second communication line LN2 shown in FIG. 2.

[0081] If any abnormality or unpredictable communication error occurs in the internal state after the auxiliary communication signal ALP has been changed to a high level, the data driver device 120 may change the level of the auxiliary communication signal ALP to a low level. For example, if the data driver device 120 fails to receive the receiving side configuration data signal or if the clock breaks in the CFG data segment or CFG completion segment, the data driver device 120 may change the level of the auxiliary communication signal ALP to a low level.

[0082] When the low-speed protocol signal PS2 remains at a high or low level for a predetermined time in the CFG completion segment, the data driver device 120 can initialize the clock training for low-speed communication and change the level of the auxiliary communication signal ALP from high to low.

[0083] The detailed configuration of the data processing device 140 and the data driving device 120 will be described below.

[0084] Figure 6 This is a detailed configuration diagram of the data processing device and the data driving device according to an embodiment.

[0085] The data drive device 120 may include a low-speed communication circuit 610, a high-speed communication circuit 620, a receiving control circuit 630, and a locking control circuit 640.

[0086] The low-speed communication circuit 610 can communicate at low speed with the data processing device 140 through the first communication line (LN1) 200.

[0087] The low-speed communication circuit 610 may include a receiving circuit 612 and a decoder 614.

[0088] The receiving circuit 612 can be connected to a first communication line (LN1) 200, which includes at least one AC coupling capacitor 212, 222.

[0089] The receiving circuit 612 can receive the receiving-side configuration data signal encoded using DC balanced code via the first communication line (LN1) 200. The receiving-side configuration data signal can be transmitted from the transmission circuit 730 of the data processing device 140.

[0090] The receiving circuit 612 may include a buffer for temporarily storing the receiving side configuration data signal when the receiving circuit 612 receives the receiving side configuration data signal.

[0091] The receiving circuit 612 can transmit the receiving-side configuration data signal temporarily stored in the buffer to the decoder 614.

[0092] On the other hand, the receiving circuit 612 can receive a preamble signal, which serves as a low-speed communication clock signal, before receiving the configuration data signal from the receiving side. The preamble signal can also be encoded using DC balanced code.

[0093] When the DC balanced code is Manchester code, the preamble signal can be a signal in which the Manchester code corresponding to the binary number "1" or binary number "0" is repeated N times.

[0094] When the DC balanced code is 8B10B code, the preamble signal can be a signal in which data bits corresponding to binary number "1" and data bits corresponding to binary number "0" can appear regularly so that the number of data bits corresponding to binary number "1" and data bits corresponding to binary number "0" are balanced with each other.

[0095] Decoder 614 can receive the preamble signal from receiver circuit 612 and train a clock for low-speed communication. Here, decoder 614 can receive an internal clock from an internal clock generation circuit (not shown) included in data drive device 120, and can synchronize the internal clock with the preamble signal through clock training.

[0096] Subsequently, the decoder 614 can receive the receiving side configuration data signal from the receiving circuit 612, decode the receiving side configuration data signal using DC balanced code to output the receiving side configuration data, and transmit the receiving side configuration data to the receiving control circuit 630.

[0097] Here, since the DC balanced code can be Manchester code or 8B10B code, the decoder 614 can include a Manchester decoder or an 8B10B decoder.

[0098] The receiver circuit 612 and the decoder 614 can be activated or deactivated by the receiver control circuit 630, which will be described below.

[0099] In other words, when power is applied to the data drive device 120, the receiver circuit 612 and the decoder 614 can be activated by the control of the receiver control circuit 630.

[0100] When the decoder 614 decodes the end bit or end symbol of the configuration data signal on the receiving side, or when the receiving circuit 612 receives the low-speed protocol signal PS2 in the CFG completion section, the receiving circuit 612 and the decoder 614 can be deactivated by the control of the receiving control circuit 630.

[0101] The high-speed communication circuit 620 can communicate at high speed with the data processing equipment through the first communication line (LN1) 200.

[0102] The high-speed communication circuit 620 may include an equalizer 622, a clock recovery circuit 624, and a parallelization circuit 626.

[0103] Equalizer 622 can improve the receiving performance of data drive device 120 by compensating for the loss of high-speed protocol signal PS1 due to the characteristics of the first communication line (LN1) 200.

[0104] The clock recovery circuit 624 can train the clock used for high-speed communication to recover the clock from the high-speed protocol signal PS1.

[0105] The parallelization circuit 626 can use the clock recovered by the clock recovery circuit 624 to convert the serial data included in the high-speed protocol signal PS1 into parallel data. The parallel data may be image data corresponding to the image displayed on the display panel 110.

[0106] The receiving control circuit 630 can control the operation of the low-speed communication circuit 610 and the high-speed communication circuit 620.

[0107] In other words, when power is applied to the data drive device 120, the receive control circuit 630 can transmit the enable information LS_E to the low-speed communication circuit 610 to activate the receive circuit 612 and the decoder 614.

[0108] This allows low-speed communication to be performed via the first communication line (LN1) 200.

[0109] Additionally, the receive control circuit 630 can establish a high-speed communication environment based on the receive-side configuration data output from the decoder 614. The receive control circuit 630 can also establish the equalizer 622 based on the gain level of the equalizer 622 included in the receive-side configuration data.

[0110] Subsequently, the receiving control circuit 630 can transmit the enable information HS_E to the high-speed communication circuit 620 to activate the equalizer 622, the clock recovery circuit 624, and the parallelization circuit 626.

[0111] This allows high-speed communication to be performed via the first communication line (LN1) 200.

[0112] According to an embodiment, when the enable information HS_E is transmitted to the high-speed communication circuit 620, the receiving control circuit 630 can transmit the disable information to the low-speed communication circuit 610 to disable the low-speed communication circuit 610, namely the receiving circuit 612 and the decoder 614.

[0113] The locking control circuit 640 can generate a low-level auxiliary communication signal ALP, and transmit the auxiliary communication signal to the locking monitoring circuit 740 of the data processing device 140 via the second communication line LN2 before the clock training in the decoder 614 or the clock recovery circuit 624 is completed.

[0114] After clock training is completed in decoder 614 or clock recovery circuit 624, lock control circuit 640 can generate a high-level auxiliary communication signal ALP and transmit the auxiliary communication signal to lock monitoring circuit 740.

[0115] The data processing device 140 may include a transmission control circuit 710, a serialization circuit 720, a transmission circuit 730, and a lock monitoring circuit 740.

[0116] When power is applied to the data processing device 140, the transmission control circuit 710 can activate the serialization circuit 720, the transmission circuit 730, and the lock monitoring circuit 740.

[0117] The transmission control circuit 710 can generate receiver-side configuration data for establishing a high-speed communication environment for the data-driven device 120 as the receiver. Here, the receiver-side configuration data may include multiple configuration data entries (…). Figure 5A and Figure 5B The CFG DATA "1" to CFG DATA "N" are in the range, and the transmission control circuit 710 can generate the receiver configuration data in serial or parallel form.

[0118] The transmission control circuit 710 can generate a receiver-side configuration data signal, which is a low-speed protocol signal PS2 that includes receiver-side configuration data. Here, the transmission control circuit 710 can encode the receiver-side configuration data signal using a DC balanced code, which can be Manchester code or 8B10B code.

[0119] When the receiver configuration data is generated in parallel, the transmission control circuit 710 transmits the receiver configuration data signal encoded with DC balanced code to the serialization circuit 720.

[0120] When the receiving-side configuration data is generated in serial form, the transmission control circuit 710 can transmit the receiving-side configuration data signal to the transmission circuit 730 instead of transmitting the receiving-side configuration data signal to the serialization circuit 720.

[0121] After configuring the data signal on the receiving side, the transmission control circuit 710 can receive image data from an external device or generate a high-speed protocol signal PS1 including image data. Subsequently, the transmission control circuit 710 can transmit the high-speed protocol signal PS1 to the serialization circuit 720.

[0122] Here, the transmission control circuit 710 can use 8B10B code or non-return-to-zero (NRZ) code to encode the high-speed protocol signal PS1.

[0123] According to an embodiment, the transmission control circuit 710 can generate a preamble signal encoded using DC balanced code before generating the receiving-side configuration data signal, and transmit the preamble signal to the serialization circuit 720 or the transmission circuit 730. In other words, the transmission control circuit 710 can generate the preamble signal in parallel and transmit it to the serialization circuit 720, or generate the preamble signal in serial form and transmit it to the transmission circuit 730.

[0124] Here, the preamble signal can be a signal in which the Manchester code corresponding to the binary number "1" or binary number "0" is repeated N times (N is a natural number equal to or greater than 2), or a signal in which the data bits corresponding to the binary number "1" and binary number "0" appear regularly so that the number of data bits corresponding to the binary number "1" and binary number "0" appear in a balanced manner.

[0125] The serialization circuit 720 can receive at least one of the parallel-form receiver configuration data signal and the high-speed protocol signal PS1 from the transmission control circuit 710, and convert it into a serial form.

[0126] Subsequently, the serialization circuit 720 can transmit the receiver configuration data signal converted into serial form or the high-speed protocol signal PS1 converted into serial form to the transmission circuit 730.

[0127] According to an embodiment, the serialization circuit 720 can receive a preamble signal in parallel form from the transmission control circuit 710, and convert the preamble signal into a serial form before receiving the receiving-side configuration data signal. The serialization circuit 720 can then transmit the preamble signal converted into a serial form to the transmission circuit 730.

[0128] The transmission circuit 730 can be connected to a first communication line (LN1) 200, which includes at least one AC coupling capacitor 212, 222.

[0129] After receiving a serial-formatted receiver configuration data signal from the transmission control circuit 710 or the serialization circuit 720, in low-speed communication, the transmission circuit 730 can transmit the receiver configuration data signal to the data drive device 120 via the first communication line (LN1) 200. Here, the transmission circuit 730 can transmit the receiver configuration data signal in analog form.

[0130] According to an embodiment, the transmission circuit 730 can receive a preamble signal from the transmission control circuit 710 or the serialization circuit 720 before transmitting the configuration data signal on the receiving side, transmit the preamble signal to the data driving device 120 via the first communication line (LN1) 200, and then transmit the configuration data signal on the receiving side. Here, the transmission circuit 730 can transmit the preamble signal in analog form during low-speed communication.

[0131] After completing the transmission of the receiving-side configuration data signal, the transmission circuit 730 can receive the high-speed protocol signal PS1 from the serialization circuit 720 and transmit the high-speed protocol signal PS1 to the data driving device 120 via the first communication line (LN1) 200. Here, the transmission circuit 730 can transmit the high-speed protocol signal PS1 in analog form during high-speed communication.

[0132] The lock monitoring circuit 740 can receive auxiliary communication signal ALP from the lock control circuit 640 of the data drive device 120.

[0133] When the auxiliary communication signal ALP received by the lock-on monitoring circuit 740 changes from low level to high level in low-speed communication, the transmission control circuit 710 can generate receiver configuration data.

[0134] When the auxiliary communication signal ALP received by the lock monitoring circuit 740 changes from low level to high level during high-speed communication, the transmission control circuit 710 can transmit the image data to the serialization circuit 720.

[0135] As described above, according to the embodiment, since the display device 100 uses DC balanced code to encode the low-speed protocol signal PS2, communication errors in the low-speed communication of the display device 100 caused by the AC coupling capacitor of the communication line can be minimized.

[0136] The process by which the data-driven device 120 processes the receiving-side configuration data signal will be described below.

[0137] Figure 7 This is a flowchart illustrating the process by which a data-driven device according to an embodiment processes a receiving-side configuration data signal.

[0138] Reference Figure 7 When the driving voltage VCC is provided to the data processing device 140 and the data driving device 120, the data driving device 120 can receive the receiving side configuration data signal encoded with DC balanced code by communicating at low speed with the data processing device 140 connected to the data driving device 120 through the first communication line (LN1) 200 (S710).

[0139] Subsequently, the data driver device 120 can decode the receiver configuration data signal into receiver configuration data using a DC balanced code (S720). The receiver configuration data decoded in the data driver device 120 can be in serial form.

[0140] The data drive device 120 can establish a high-speed communication environment based on the configuration data of the receiving side, and communicate at high speed with the data processing device 140 through the first communication line (LN1) 200 (S730, S740).

[0141] According to an embodiment, the data driving device 120 can receive a preamble signal transmitted from the data processing device 140 via the first communication line (LN1) 200 before performing step S720, and use the preamble signal to train a clock for low-speed communication.

[0142] Cross-references to related applications

[0143] This application claims priority to Korean Patent Application No. 10-2020-0062423, filed on May 25, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A communication system, comprising: A communication line, which includes at least one AC coupling capacitor; A data processing device, connected to one end of the communication line, is used to transmit configuration data signals encoded using DC balanced code to the communication line in low-speed communication and subsequently perform high-speed communication. as well as A data-driven device, connected to the other end of the communication line, is used to receive the configuration data signal from the communication line, decode the configuration data signal into configuration data using the DC balanced code, establish a high-speed communication environment based on the configuration data, and perform high-speed communication with the data processing device. The configuration data signal includes configuration data used to establish the high-speed communication environment on the receiving side. The DC balanced code includes Manchester code, and Before transmitting the configuration data signal to the data driving device via the communication line, the data processing device transmits a preamble signal encoded with the Manchester code to the data driving device via the communication line. The preamble signal is a signal that repeats the Manchester code corresponding to any binary number N times, where N is a natural number equal to or greater than 2.

2. The communication system according to claim 1, wherein, The configuration data signal includes multiple data entries, each of which includes header data, body data, and checksum data. The configuration data signal also includes a start bit placed before the multiple data entries and an end bit placed after the multiple data entries.

3. The communication system according to claim 1, wherein, The communication line includes a first line and a second line, the first line including a first AC coupling capacitor and the second line including a second AC coupling capacitor.

4. The communication system according to claim 3, wherein, The first line also includes a third AC coupling capacitor, and in the first line, the first AC coupling capacitor is configured to be adjacent to the data processing device, and the third AC coupling capacitor is configured to be adjacent to the data driving device.

5. The communication system according to claim 3, wherein, The second line also includes a fourth AC coupling capacitor, and in the second line, the second AC coupling capacitor is configured to be adjacent to the data processing device, and the fourth AC coupling capacitor is configured to be adjacent to the data driving device.

6. A communication system, comprising: A communication line, which includes at least one AC coupling capacitor; A data processing device, connected to one end of the communication line, is used to transmit configuration data signals encoded using DC balanced code to the communication line in low-speed communication and subsequently perform high-speed communication. as well as A data-driven device, connected to the other end of the communication line, is used to receive the configuration data signal from the communication line, decode the configuration data signal into configuration data using the DC balanced code, establish a high-speed communication environment based on the configuration data, and perform high-speed communication with the data processing device. The configuration data signal includes configuration data used to establish the high-speed communication environment on the receiving side. The DC balanced code includes 8B10B code, and Before transmitting the configuration data signal to the data driving device via the communication line, the data processing device transmits a preamble signal encoded using 8B10B code to the data driving device via the communication line. The preamble signal can be a signal in which data bits corresponding to binary "1" and binary "0" appear regularly, such that the number of data bits corresponding to binary "1" and binary "0" appearing are balanced.

7. The communication system according to claim 6, wherein, The configuration data signal includes multiple data lines, each of which includes a start symbol, header data, body data, and checksum data. The configuration data signal also includes an end symbol placed after the multiple data lines.

8. The communication system according to claim 7, wherein, The start symbol and the end symbol each include a comma string.

9. A data-driven device, comprising: A receiving circuit connected to a communication line including at least one AC coupling capacitor, for receiving configuration data signals encoded using DC balanced code via the communication line in low-speed communication. A decoder is configured to receive the configuration data signal from the receiving circuit, decode the configuration data signal into configuration data using the DC balanced code, and output the configuration data. as well as A control circuit is configured to activate the receiving circuit and the decoder when power is applied to perform low-speed communication via the communication line, establish a high-speed communication environment based on the configuration data output from the decoder, and perform high-speed communication via the communication line. The configuration data signal includes configuration data for establishing the high-speed communication environment on the receiving side, and The receiving circuit receives a preamble signal before receiving the configuration data signal. In the preamble signal, the data bits corresponding to the binary number "1" and the data bits corresponding to the binary number "0" can appear regularly, so that the number of data bits corresponding to the binary number "1" and the number of data bits corresponding to the binary number "0" are balanced.

10. The data-driven device according to claim 9, wherein, The configuration data includes the gain level of the equalizer used for the high-speed communication.

11. The data-driven device according to claim 9, wherein, When the high-speed communication is performed, the control circuit disables the receiving circuit and the decoder.

12. The data-driven device according to claim 9, wherein, The preamble signal is encoded in Manchester code.

13. A data processing device, comprising: A control circuit is used to generate configuration data for establishing a high-speed communication environment on the receiving side, and to generate the configuration data signal including the configuration data by encoding the configuration data into a configuration data signal using a DC balanced code. as well as A transmission circuit, connected to a communication line including at least one AC coupling capacitor, is used to transmit the configuration data signal to the receiving side via the communication line in low-speed communication. The configuration data signal includes configuration data for establishing the high-speed communication environment on the receiving side, and The control circuit generates a preamble signal before transmitting the configuration data signal. In the preamble signal, the Manchester code corresponding to any binary number is repeated N times, where N is a natural number equal to or greater than 2. The transmission circuit transmits the preamble signal through the communication line during the low-speed communication.

14. The data processing apparatus according to claim 13, wherein, The DC balanced code is either Manchester code or 8B10B code.

15. The data processing apparatus according to claim 13, wherein, The communication line includes multiple AC coupling capacitors connected in series.

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