Wafer film pasting process optimization method

By optimizing the wafer bonding process parameters and adopting the DOE matrix design method, the problem of wafer grinding and cracking caused by poor wafer bonding was solved, and safe processing and high-yield wafer production were achieved.

CN113725069BActive Publication Date: 2026-05-05HUATIAN TECH XIAN
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
HUATIAN TECH XIAN
Filing Date
2021-08-27
Publication Date
2026-05-05

AI Technical Summary

Technical Problem

In existing technologies, poor wafer lamination processes can lead to wafer breakage during grinding, affecting product packaging and yield.

Method used

The wafer bonding process parameters, including adhesive type, blade type, cutting speed, cutting angle, and cutting blade temperature, were optimized using the DOE matrix design method. Combined with the experimental process of DOE matrix design, the process parameters that maximize safe life were determined.

Benefits of technology

Ensure that the cutting blades receive an early warning before reaching the end of their lifespan, safely process products, avoid defective products, and meet process quality standards.

✦ Generated by Eureka AI based on patent content.

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Abstract

This invention discloses a method for optimizing wafer lamination process. This method designs experiments based on the parameters involved in the wafer lamination process using the Design of Elements (DOE) matrix design method. By conducting experiments in the specified order, the process parameters that maximize the wafer lifespan are obtained as the optimized process parameters. The process parameters obtained by this method can ensure that the cutting blade can provide early warning before the end of its lifespan. The safety margin ensures that products already installed on the equipment can be safely processed and meet the process quality standards without defective products.
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Description

Technical Field

[0001] This invention belongs to the field of packaging technology, specifically relating to an optimization method for wafer bonding process. Background Technology

[0002] Wafer grinding is an essential process in IC packaging. Wafer grinding uses a grinding machine to reduce the thickness of the wafer. Before thinning or cutting, a film needs to be applied to the side of the wafer with the circuit structure to protect it. However, if there are problems in the film application process, the wafer may crack during the subsequent thinning or cutting process, affecting the product packaging and product yield. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide an optimized method for wafer lamination process to solve the problem of wafer grinding and cracking caused by poor lamination quality in the prior art.

[0004] To achieve the above objectives, the present invention employs the following technical solution:

[0005] A method for optimizing wafer bonding process includes the following steps:

[0006] Step 1: Determine the optimized process parameters for the wafer lamination process. The process parameters include adhesive type, blade type, cutting speed, cutting angle, and cutting blade temperature.

[0007] Step 2: Design the film application test process using the DOE matrix design method;

[0008] Step 3: Conduct a film application test according to the parameters designed in the DOE matrix;

[0009] When applying the film with any set of parameters, after each application of the film onto the circuit surface of the wafer, the blade repeatedly cuts the wafer to obtain the safe lifespan of the wafer cut with the set of parameters; the safe lifespan is the time when the blade cuts the wafer without defects and the blade lifespan is maximized when the blade cuts with the set of parameters.

[0010] Step 4: Repeat step 3 to test all groups of process parameters, and select the group with the longest safe life as the optimized process parameters.

[0011] A further improvement of the present invention is that:

[0012] Preferably, in step 1, the adhesive type is selected based on the adhesive parameters, which include structure, thickness, thickness accuracy, bonding strength, and the total thickness change of the wafer during the grinding process.

[0013] Preferably, in step 1, the cutting speed includes 100mm / s, 150mm / s, 200mm / s, 250mm / s, and 300mm / s.

[0014] Preferably, in step 1, the cutting angle includes 85°, 90°, and 95°.

[0015] Preferably, in step 1, the temperature of the cutting blade includes 120°C, 150°C, 170°C, and 200°C.

[0016] Preferably, in step 3, the defect is excess film at the edge of the wafer or film wrinkles on the wafer surface.

[0017] Preferably, in step 4, the service life of the blade is determined based on the DOE test results.

[0018] Preferably, after step 4, the optimized process parameters are verified through the film application process and the thinning process.

[0019] Preferably, the verification items for the film application process include the appearance of the film and the lifespan of the film application blade.

[0020] Preferably, the verification items for the thinning process include the grinding current value, the thickness after thinning, the total thickness after thinning, and the roughness.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] This invention discloses a method for optimizing wafer lamination processes. This method designs experiments based on the parameters involved in the wafer lamination process using the Design of Experiments (DOE) matrix design method. By conducting experiments in this sequence, the process parameters that maximize the wafer lifespan are obtained as the optimized process parameters. The process parameters obtained through this method ensure that the cutting blades can provide early warnings before reaching their lifespan milestones. The safety margin ensures that products already installed on the equipment can be safely processed and meet process quality standards, with no defective products. Attached Figure Description

[0023] Figure 1 This is a diagram illustrating the film application process of the present invention;

[0024] Figure 2 This is a schematic diagram of defects in the wafer edge with excess film according to the present invention;

[0025] Figure 3 This is a schematic diagram of the defects of film wrinkles on the wafer surface according to the present invention;

[0026] Wherein, 1-wafer; 2-film; 3-film wrinkle Detailed Implementation

[0027] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. The terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, unless otherwise explicitly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection or a detachable connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two elements. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0028] This invention discloses an optimization method for wafer bonding process, see [link to relevant documentation]. Figure 1 The adhesive film 2 is adhered to the circuit surface of wafer 1 to protect the circuit surface from contamination, scratches, or damage during subsequent polishing processes. The method includes the following steps:

[0029] Step 1: Determine the optimized process parameters for the wafer 1 film application process. The process parameters include adhesive type 2, blade type, cutting speed, cutting angle, and cutting blade temperature.

[0030] Different adhesive 2 models correspond to different adhesive parameters, but each type of adhesive 2 takes into account the following parameters: structure, thickness, thickness accuracy, adhesive strength, and the total thickness change of the wafer during the grinding process when using the adhesive.

[0031] The available models for Adhesive 2 are SB-145, CP9003-205, E-8180, and HT-260, each with different parameters as described above.

[0032] Specifically, the blade model is matched with the cutting equipment; in this invention, XB10S is selected.

[0033] Specifically, the test parameters for the cutting speed include 100mm / s, 150mm / s, 200mm / s, 250mm / s, and 300mm / s.

[0034] Specifically, the cutting angle includes 85°, 90° and 95°.

[0035] Specifically, the cutting blade temperature includes 120°C, 150°C, 170°C, and 200°C.

[0036] Step 2: Design the film application test process using the DOE matrix design method; design the DOE matrix by taking into account all data of all process parameters involved.

[0037] Step 3: Conduct film application tests according to multiple sets of parameters designed by the DOE matrix. During the verification of each set of parameters, after applying the film 2 to the wafer, the blade repeatedly cuts wafer 1. For example, when using the first set of parameters for verification, first verify whether the blade is damaged after 200 cuts, and whether there are defects on the surface of the cut wafer 1. If not, cutting can continue. When it is found that defects appear on the surface of the cut wafer 1 after 300 cuts, it is considered that 300 cuts are too many under this set of parameters, and the number of cuts needs to be reduced. After multiple tests, determine the safe value of the service life. Under this safe service life, the cut wafer 1 is defect-free, which can ensure the maximum number of blade uses and that the cut wafer 1 is defect-free. Repeat the above process to obtain the safe value of the service life of each set of parameters.

[0038] Defects include such as Figure 2 The excess membrane at the edge, or the membrane surface has wrinkles 3.

[0039] Step 4: Based on the experimental results of the DOE matrix, when using a certain set of parameters, the number of wafers repeatedly cut by the blade is the highest. The set of parameters is the optimized process parameters.

[0040] Step 5: Collect data and key control points from small-batch trial production, and standardize them into a thinning standard operating procedure guide.

[0041] After obtaining the above process parameters, the optimized parameters are verified using Table 1 below.

[0042] Table 1 Project Validation and Sampling Quantity

[0043] Station Validate Project standard Sampling amount screen protector Film appearance Reference quality standards 100% screen protector Film application blade lifespan Define warning values ​​and mandatory values. 100% thinning Grinding current value Comparable to existing SI materials 5 pieces / piece thinning thickness Reference quality standards 25 per set thinning TTV Reference quality standards 25 per set thinning roughness Reference quality standards 5 per set

[0044] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for optimizing wafer lamination process, characterized in that, Includes the following steps: Step 1, determine the optimized process parameters for the wafer (1) film application process, including the adhesive (2) type, blade type, cutting speed, cutting angle and cutting blade temperature; The selection of adhesive (2) model is based on the adhesive parameters, which include structure, thickness, thickness accuracy, bonding strength and total thickness change of the wafer during the grinding process; Step 2: Design the film application test process using the DOE matrix design method; Step 3: Conduct a film application test according to the parameters designed in the DOE matrix; When applying the film with any set of parameters, after each application of the film, the adhesive (2) is applied to the circuit surface of the wafer (1), the blade repeatedly cuts the wafer (1) to obtain any set of safe lifespan for cutting the wafer; the safe lifespan is when the blade cuts the wafer (1) with the parameters of the set of parameters, the wafer (1) is cut without defects and the blade lifespan is maximized. The defect is that there is excess film at the edge of the wafer or film wrinkles on the surface of the wafer (3). Step 4: Repeat step 3 to test all groups of process parameters, and select the group with the longest safe life as the optimized process parameters.

2. The wafer lamination process optimization method according to claim 1, characterized in that, In step 1, the cutting speed includes 100mm / s, 150mm / s, 200mm / s, 250mm / s and 300mm / s.

3. The wafer lamination process optimization method according to claim 1, characterized in that, In step 1, the cutting angle includes 85°, 90° and 95°.

4. The wafer lamination process optimization method according to claim 1, characterized in that, In step 1, the temperature of the cutting blade includes 120°C, 150°C, 170°C, and 200°C.

5. The wafer lamination process optimization method according to claim 1, characterized in that, In step 4, the service life of the blade is determined based on the DOE test results.

6. The wafer lamination process optimization method according to any one of claims 1-5, characterized in that, After step 4, the optimized process parameters are verified through the film application process and the thinning process.

7. The wafer lamination process optimization method according to claim 6, characterized in that, The verification items for the film application process include the appearance of the film and the lifespan of the film application blade.

8. The wafer lamination process optimization method according to claim 6, characterized in that, The verification items for the thinning process include the grinding current value, the thickness after thinning, the total thickness after thinning, and the roughness.

Citation Information

Patent Citations

  • Gallium nitride wafer production process parameter design method

    CN112287543A