Panel control circuit and display device including the same

Abstract

The present application discloses a panel control circuit and a display device including the panel control circuit. The panel control circuit is used to control a display panel including a first data line and a second data line, and the panel control circuit includes: a timing controller configured to generate input data including first input data and second input data; a first driving circuit configured to output a first video signal corresponding to the first input data to the first data line; and a second driving circuit configured to output a second video signal corresponding to the second input data to the second data line, wherein the timing controller is configured to disconnect the second driving circuit based on a first deviation, a second deviation, or a third deviation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0077991 filed on June 25, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety for all purposes by reference. Technical Field

[0003] The following description relates to a panel control circuit and a display device including such a panel control circuit. Background Art

[0004] The display panel may include sub-pixels capable of emitting light. Examples of such a display panel may be a liquid crystal display (LCD) panel, a plasma display panel (PDP), and an organic light emitting display (OLED) panel.

[0005] At the same time, as the resolution of such a display panel increases, the number of sub-pixels included in the display panel may increase, and therefore, the power consumption of a driver driving the display panel may increase accordingly. Moreover, relative to the same frame rate, the time available for driving one gate line of the display panel may also be reduced accordingly. Summary of the invention

[0006] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0007] In one general aspect, a panel control circuit for controlling a display panel including a first data line and a second data line includes: a timing controller configured to generate input data including first input data and second input data; a first drive circuit configured to output a first video signal corresponding to the first input data to the first data line; and a second drive circuit configured to output a second video signal corresponding to the second input data to the second data line, wherein the timing controller is configured to disconnect the second drive circuit based on a first deviation between the first input data of a current row and the second input data of the current row, a second deviation between the first input data of the current row and the second input data of a previous row, or a third deviation between the first input data of the current row and the first input data of the previous row.

[0008] The timing controller may be configured to generate control data for turning off the second driving circuit based on the first deviation and the second deviation or the third deviation.

[0009] The timing controller may include: an input data generating circuit configured to generate input data; an input data buffer configured to store input data of a previous row generated by the input data generating circuit; and a control data generating circuit configured to generate control data by using the input data of a current row sent from the input data generating circuit and the input data of a previous row read from the input data buffer.

[0010] The control data generation circuit may include at least one logic circuit configured to calculate the first deviation, the second deviation, and the third deviation.

[0011] In response to the first deviation being equal to or less than the first reference deviation and in response to the second deviation being equal to or less than the second reference deviation or the third deviation being equal to or less than the third reference deviation, the timing controller may be configured to generate control data for turning off the second driving circuit.

[0012] The first reference deviation may be smaller than the second reference deviation and the third reference deviation.

[0013] The timing controller may be configured to generate the control data as 1-bit data.

[0014] The timing controller may be configured to fill the control data onto the second input data, and configured to output the second input data filled with the control data to the second driving circuit.

[0015] The first driving circuit may include: a first latch configured to store first input data; a first conversion circuit configured to convert the first input data output from the first latch into an analog value; and a first output buffer configured to output a first video signal using the analog value output by the first conversion circuit.

[0016] The second driving circuit may include: a second latch configured to store second input data; a second conversion circuit configured to convert the second input data output from the second latch into an analog value; and a second output buffer configured to output a second video signal using the analog value output by the second conversion circuit, wherein the second latch may be configured to receive control data and configured to output the control data to the second conversion circuit, and wherein the second conversion circuit may be configured to generate a control signal for disconnecting the second output buffer based on the control data.

[0017] The panel control circuit may further include a switch configured to transmit an output of the first output buffer to an output terminal of the second output buffer, wherein the switch is turned on in response to the control signal.

[0018] The panel control circuit may further include a switch, and when the second driving circuit is disconnected, the switch electrically connects the first driving circuit with the second driving circuit.

[0019] In one general aspect, a panel control circuit for controlling a display panel including data lines includes: a driving circuit configured to output multiple input data to the data lines; a timing controller configured to output the multiple input data; and an output switching circuit configured to switch a portion of the multiple input data and configured to output to the data lines, wherein the timing controller is configured to: disconnect the driving circuit that outputs the fifth input data based on a first deviation between the first input data of a current row and the fifth input data of the current row, a second deviation between the first input data of the current row and the seventh input data of the previous row, or a third deviation between the first input data of the current row and the third input data of the previous row.

[0020] The timing controller may be configured to generate control data for turning off the driving circuit outputting the fifth input data based on the first deviation and the second deviation or the third deviation.

[0021] The timing controller may be configured to generate control data for turning off the driving circuit outputting the fifth input data in response to the first deviation being equal to or less than the first reference deviation and in response to the second deviation being equal to or less than the second reference deviation or the third deviation being equal to or less than the third reference deviation.

[0022] The timing controller may be configured to fill the control data onto the fifth input data, and may be configured to output the filling data through the driving circuit outputting the fifth input data.

[0023] In one general aspect, a panel control circuit for controlling a display panel including data lines includes: a driving circuit configured to output multiple input data to the data lines; a timing controller configured to output the multiple input data; and an output switching circuit configured to switch a portion of the multiple input data and output to the multiple data lines, wherein the timing controller disconnects the driving circuit that outputs the seventh input data based on a first deviation between the third input data of a current row and the seventh input data of the current row, a second deviation between the third input data of the current row and the fifth input data of a previous row, or a third deviation between the third data of the current row and the first input data of the previous row.

[0024] The timing controller may be configured to generate control data for turning off the driving circuit outputting the seventh input data based on the first deviation and the second deviation or the third deviation.

[0025] The timing controller may be configured to generate control data for turning off the driving circuit outputting the seventh input data in response to the first deviation being equal to or less than the first reference deviation and in response to the second deviation being equal to or less than the second reference deviation or the third deviation being equal to or less than the third reference deviation.

[0026] The timing controller may be configured to fill the control data onto the seventh input data, and configured to output the filling data through the driving circuit outputting the seventh input data.

[0027] In one general aspect, a panel control circuit for controlling a display panel including a first data line and a second data line includes: a timing controller configured to generate input data including first input data and second input data; a first drive circuit configured to output a first video signal corresponding to the first input data to the first data line; and a second drive circuit configured to output a second video signal corresponding to the second input data to the second data line, wherein the timing controller is configured to disconnect the second drive circuit based on a deviation between the input data of a current row and another input data.

[0028] The timing controller can be configured to disconnect the second driving circuit based on a first deviation between the first input data of the current row and the second input data of the current row, a second deviation between the first input data of the current row and the second input data of the previous row, or a third deviation between the first input data of the current row and the first input data of the previous row.

[0029] The timing controller may be configured to generate control data for turning off the second driving circuit based on the first deviation and the second deviation or the third deviation.

[0030] The panel control circuit may further include a switch, and when the second driving circuit is disconnected, the switch electrically connects the first driving circuit with the second driving circuit.

[0031] In another general aspect, a display device includes a panel control circuit according to the above-mentioned aspects.

[0032] Other features and aspects will be apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A display device according to one or more embodiments is shown.

[0034] Figure 2 Sub-pixels according to one or more embodiments are shown.

[0035] Figure 3 A source driver circuit according to one or more embodiments is shown.

[0036] Figure 4 A timing controller according to one or more embodiments is shown.

[0037] Figure 5 is a diagram for describing an operation of a control data generation circuit according to one or more embodiments.

[0038] Figure 6 is a diagram for describing an operation of a control data generation circuit according to one or more embodiments.

[0039] Figure 7 is a diagram for describing an operation of a control data generation circuit according to one or more embodiments.

[0040] Figure 8 is a flow chart illustrating the operation of a panel control circuit according to one or more embodiments.

[0041] Fig. 9 A source driver circuit according to one or more embodiments is shown.

[0042] Figures 10 to 12 Is used to describe Fig. 9 2. The operation of the control data generation circuit shown in FIG.

[0043] Throughout the drawings and detailed description, the same reference numerals refer to the same elements. The drawings may not be drawn to scale, and the relative sizes, proportions, and depictions of elements in the drawings may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0044] The following detailed description is provided to help the reader obtain a comprehensive understanding of the methods, devices and / or systems described herein. However, after understanding the disclosure of the present application, various changes, modifications and equivalents of the methods, devices and / or systems described herein will become apparent. For example, the order of operations described herein is only an example and is not limited to the order set forth herein, but can be changed except for operations that must appear in a specific order, which becomes apparent after understanding the disclosure of the present application. In addition, in order to increase clarity and brevity, the description of features known in the art may be omitted.

[0045] The features described herein may be implemented in different forms and should not be construed as being limited to the examples described herein. Moreover, the examples described herein are provided only to illustrate some of the many possible ways to implement the methods, devices and / or systems described herein, which will become apparent after understanding the disclosure of the present application.

[0046] Throughout the specification, when an element such as a layer, a region, or a substrate is described as being "on," "connected to," or "coupled to" another element, it may be directly "on," "connected to," or "coupled to" another element, or one or more other elements may be present in between. In contrast, when an element is described as being "directly on," "directly connected to," or "directly coupled to" another element, no other elements may be interposed therebetween.

[0047] As used herein, the term "and / or" includes any one and any combination of any two or more of the associated listed items.

[0048] Although terms such as "first", "second", and "third" may be used herein to describe various members, components, regions, layers, or portions, these members, components, regions, layers, or portions are not limited by these terms. Moreover, these terms are only used to distinguish one member, component, region, layer, or portion from another member, component, region, layer, or portion. Therefore, without departing from the teachings of this example, what is referred to as the first member, first component, first region, first layer, or first portion in the examples described herein may also be referred to as the second member, second component, second region, second layer, or second portion.

[0049] To describe the relationship of one element to another element as shown in the figure, spatially related terms such as "above", "above", "below", and "below" may be used herein. In addition to the directions depicted in the figures, such spatially related terms are also intended to include different orientations of the device in use or operation. For example, if the device in the figure is turned over, the element described as being "above" or "above" another element will be "below" or "below" the other element. Therefore, depending on the spatial orientation of the device, the term "above" includes both the directions of "above" and "below". The device can also be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially related terms used in this article are understood accordingly.

[0050] The terms used in this article are only for describing various examples and are not used to limit the present disclosure. The terms without quantifier modification and "the" are also intended to include plural forms unless the context clearly indicates otherwise. The terms "comprise", "include" and "have" specify the presence of the features, numbers, operations, components, elements and / or their combinations, but do not exclude the presence or addition of one or more other features, numbers, operations, components, elements and / or their combinations.

[0051] Variations in the shapes shown in the drawings may occur due to manufacturing techniques and / or tolerances. Therefore, the examples described herein are not limited to the specific shapes shown in the drawings but include variations in shapes generated during manufacturing.

[0052] The features of the examples described herein can be combined in various ways, which will become apparent after understanding the disclosure of the present application. In addition, although the examples described herein have multiple configurations, other configurations are possible, which will become apparent after understanding the disclosure of the present application.

[0053] In this document, it should be noted that the use of the term "may" with respect to examples or embodiments (e.g., with respect to an example or embodiment may include or implement) indicates that there is at least one example or embodiment that includes or implements such a feature, but all examples and embodiments are not limited thereto.

[0054] An object of the present disclosure is to provide a panel control circuit capable of reducing power consumption of a driver driving a display panel and a display device including the panel control circuit.

[0055] The panel control circuit according to the embodiment can disconnect a part of the driving circuits in the driving circuits based on the deviation between the input data of the current row and the deviation between the input data of the current row and the input data of the previous current row. Therefore, not only the same color representation can be achieved, but also the power consumption of the panel control circuit can be reduced.

[0056] Figure 1 A display device according to one or more embodiments is shown. Figure 1 , the display device 1000 can display an image or a video. For example, as a non-limiting example, the display device 1000 can be called a TV, a smart phone, a tablet PC, a mobile phone, a video phone, an e-book reader, a computer, a camera, a wearable device, etc., and the display device 1000 is not limited to these listed examples.

[0057] The display device 1000 may include a display panel 100, a timing controller 200, a source driving circuit 300, and a gate driving circuit 400. According to one or more embodiments, the gate driving circuit 400 may be integrally formed with the display panel 100. The timing controller 200 and the source driving circuit 300 may be referred to as a panel control circuit. However, the embodiments are not necessarily limited to these listed embodiments.

[0058] The display panel 100 may be configured to output a video. For example, as a non-limiting example, the display panel 100 may be implemented as a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, an active matrix OLED (AMOLED) display, an electrochromic display (ECD), a digital mirror device (DMD), a driven mirror device (AMD), a grating light valve (GLV), a plasma display panel (PDP), an electroluminescent display (ELD), a vacuum fluorescent display (VFD), but the display panel 100 is not limited to these listed examples.

[0059] The display panel 100 may include a plurality of sub-pixels PX that emit light. The plurality of sub-pixels PX may be arranged in rows and columns. For example, the plurality of sub-pixels PX may be arranged in the form of a dot matrix structure consisting of n rows and m columns, where n and m are natural numbers. For the display panel 100, the rows in which the sub-pixels PX are arranged are referred to as sub-pixel rows SPR, and the columns in which the sub-pixels PX are arranged are referred to as sub-pixel columns SPC. For example, in Figure 1 , the first SPC, the second SPC, . . . , the mth SPC may be arranged from left to right, thereby providing an array of columns of sub-pixels PX.

[0060] The sub-pixels PX may each be a basic unit that can emit light. Each sub-pixel PX may include a driving element. According to one or more embodiments, the light emitted from each sub-pixel PX may be one of red, green, and blue, and may not be limited to these listed embodiments. For example, white light may be output from the sub-pixel PX.

[0061] According to one or more embodiments, the sub-pixel PX may include a light-emitting device configured to emit light and a pixel circuit driving the light-emitting device. The pixel circuit may include a plurality of switching elements, and the plurality of switching elements may control the flow of the video signal and the driving voltage applied to the light-emitting device. For example, as a non-limiting example, the light-emitting device may be a light-emitting diode (LED), an organic LED (OLED), a quantum dot LED (QLED), or a micro LED. However, the embodiments are not limited to the above types of light-emitting devices.

[0062] The subpixels PX of the display panel 100 may be driven in units of gate lines, which are referred to as "rows" hereinafter. That is, the subpixels PX may be driven in units of subpixel rows. For example, the subpixels arranged in one gate line may be driven during a first period, and the subpixels arranged in another gate line may be driven during a second period adjacent to the first period. In such an example, the unit time period during which the subpixels PX are driven may be referred to as 1 horizontal (1H) period or row.

[0063] The timing controller 200 may receive the video data RGB from the external device, and may thus generate the input data IN by appropriately processing or converting the video data RGB. Then, the timing controller 200 may transmit the input data IN to the source driving circuit 300.

[0064] The timing controller 200 may receive an external control signal OCS from an external device. As non-limiting examples, the external control signal OCS may include a horizontal synchronization signal HS, a vertical synchronization signal VS, and / or a clock signal DCLK, but the external control signal OCS is not limited to these listed examples.

[0065] The timing controller 200 may control the operation of the source driving circuit 300 and the gate driving circuit 400 based on the external control signal OCS. According to one or more embodiments, the timing controller 200 may receive the external control signal OCS and may accordingly generate a source control signal SCS for controlling the source driving circuit 300 and may generate a gate control signal GCS for controlling the gate driving circuit 400.

[0066] The source driving circuit 300 may generate video signals VS1 to VSm corresponding to a video displayed on the display panel 100 based on the input data IN and the source control signal SCS. In addition, the source driving circuit 300 may output the generated video signals VS1 to VSm to the display panel 100. According to one or more embodiments, the source driving circuit 300 may generate the video signals VS1 to VSm having voltage values ​​corresponding to the input data IN.

[0067] The source driving circuit 300 may sequentially output video signals VS1 to VSm to be output for each sub-pixel row. According to one or more embodiments, the source driving circuit 300 may provide the video signals VS1 to VSm to the sub-pixels PX driven during the 1H period. Therefore, the video signals VS1 to VSm output from the source driving circuit 300 may be transmitted to each sub-pixel PX through the data lines DL1 to DLm of the display panel 100.

[0068] The gate driving circuit 400 may sequentially output a plurality of gate signals GS1 to GSn in response to receiving the gate control signal GCS. According to one or more embodiments, the gate driving circuit 400 may generate the gate signals GS1 to GSn by using the gate control signal GCS.

[0069] The gate signals GS1 to GSn are used to respectively turn on the sub-pixels PX connected to the gate lines GL1 to GLn, and may be applied to the gate terminal of the transistor included in each sub-pixel PX. According to one or more embodiments, as a non-limiting example, each of the gate signals GS1 to GSn may include at least one of a scan signal, a light emitting signal, and an initialization signal.

[0070] According to one or more embodiments, at least two of the timing controller 200, the source driving circuit 300, and the gate driving circuit 400 may be implemented using one integrated circuit. In addition, according to one or more embodiments, at least two of the timing controller 200, the source driving circuit 300, and the gate driving circuit 400 may be implemented to be mounted on the display panel 100.

[0071] Figure 2 Sub-pixels according to one or more embodiments are shown. Figure 2 A sub-pixel PX connected between a data line DL and a gate line GL is shown.

[0072] Reference Figure 1 and Figure 2 According to one or more non-limiting examples, the sub-pixel PX may include a switching transistor ST, a pixel circuit PC connected to the switching transistor, and a light emitting device LD connected to the pixel circuit.

[0073] For example, the subpixel PX may be connected to the data line DL and the gate line GL, and may operate according to receiving the video signal VS, the gate signal GS, and the driving voltages ELVDD and ELVSS.

[0074] The video signal VS can be applied through the data line DL, and the gate signal GS can be applied through the gate line GL, but the transmission of the video signal VS and the gate signal GS is not limited to these listed example methods. For example, the gate signal GS can be transmitted through another conductive line instead of the gate line GL.

[0075] A first electrode (e.g., source electrode) of the switching transistor ST may be electrically connected to the data line DL, and a second electrode (e.g., drain electrode) may be electrically connected to the pixel circuit PC. A gate electrode of the switching transistor ST may be electrically connected to the gate line GL. When a gate signal at a gate-on level is applied to the gate line GL, the switching transistor ST may be turned on and may transmit a video signal applied to the data line DL to the pixel circuit PC.

[0076] The pixel circuit PC may control the light emitting device LD based on the gate signal GS and the driving voltage ELVDD. According to one or more embodiments, the pixel circuit PC may control the amount of driving current flowing through the light emitting device LD in response to the received gate signal GS.

[0077] The pixel circuit PC may include a driving transistor DT connected between the light emitting device LD and the driving voltage ELVDD, and may further include a storage capacitor CST connected to one end of the driving transistor.

[0078] Such a storage capacitor CST may charge a voltage between the first node N1 and the second node N2 .

[0079] The driving transistor DT may control the amount of driving current flowing through the light emitting device LD in response to a voltage applied to the gate electrode. For example, the driving transistor DT may control the amount of driving current flowing through the light emitting device LD based on a gate signal GS applied to the pixel circuit PC.

[0080] The light emitting device LD may emit light corresponding to the driving current. For example, as a non-limiting example, the light emitting device LD may emit light corresponding to any one of red, green, blue, and white. As a non-limiting example, the light emitting device LD may be an organic light emitting diode (OLED) or a very small inorganic light emitting diode having a size ranging from micrometer level to nanometer level, but the light emitting device LD is not limited to these listed examples. Subsequently, in the present disclosure, one or more embodiments in which the light emitting device LD includes an organic light emitting diode will be described, but the following discussion relates to examples using inorganic light emitting diodes or other examples of the light emitting device LD.

[0081] In addition, the structure of the sub-pixel PX of the current one or more embodiments should not be interpreted as being limited to the reference Figure 2 According to one or more embodiments, the subpixel PX may further include at least one device for compensating for a threshold voltage of the driving transistor DT or for initializing a voltage of a gate electrode of the driving transistor DT and / or a voltage of an anode electrode of the light emitting device LD.

[0082] Figure 3 A source driver circuit according to one or more embodiments is shown. Figures 1 to 3 , the source driving circuit 300 may include a plurality of driving circuits 310 - 1 to 310 - m.

[0083] The plurality of driving circuits 310-1 to 310-m may respectively receive input data IN1 to INm transmitted from the timing controller 200, and may output video signals VS1 to VSm corresponding to the input data IN1 to INm to the display panel 100. According to one or more embodiments, the plurality of driving circuits 310-1 to 310-m may respectively output the video signals VS1 to VSm to corresponding sub-pixel columns or data lines. For example, the first driving circuit 310-1 may output the first video signal VS1 to the first sub-pixel column connected to the first data line DL1.

[0084] According to one or more embodiments, the video signals VS1 to VSm may be outputted through the channels CH1 to CHm connected to the drive circuits 310-1 to 310-m, respectively, and the channels CH1 to CHm may be connected to the data lines DL1 to DLm, respectively. Meanwhile, although in the present disclosure, as a non-limiting embodiment, the number of channels CH1 to CHm is described as being the same as the number of data lines DL1 to DLm, the embodiments are not limited to the enumerated embodiments. For example, the number of channels CH1 to CHm may be different from the number of data lines DL1 to DLm. Meanwhile, the number of channels CH1 to CHm may be the same as the number of drive circuits 310-1 to 310-m.

[0085] The driving circuits 310-1 to 310-m may include latches 311-1 to 311-m, level shifters 313-1 to 313-m, decoders 315-1 to 315-m, and output buffers 317-1 to 317-m, respectively. For example, according to a non-limiting example, the first driving circuit 310-1 may include a first latch 311-1, a first level shifter 313-1, a first decoder 315-1, and a first output buffer 317-1.

[0086] According to one or more embodiments, the level shifters 313 - 1 to 313 - m and the decoders 315 - 1 to 315 - m are collectively referred to as a conversion circuit.

[0087] The latches 311-1 to 311-m may store input data IN1 to INm transmitted from the timing controller 200. According to one or more embodiments, the latches 311-1 to 311-m may receive and store a plurality of bits corresponding to the input data IN1 to INm.

[0088] The latches 311 - 1 to 311 - m may output the stored input data IN1 to INm. According to one or more embodiments, the latches 311 - 1 to 311 - m may output the stored input data IN1 to INm to the level shifters 313 - 1 to 313 - m.

[0089] The level shifters 313 - 1 to 313 - m and the decoders 315 - 1 to 315 - m may convert input data IN1 to INm in a digital format into analog values, and then may output the analog values ​​corresponding to the input data IN1 to INm to the buffers 317 - 1 to 317 - m.

[0090] The level shifters 313-1 to 313-m can change or dock the level of the input data IN1 to INm received from the latches 311-1 to 311-m, for example, as a voltage referenced by a logic value. According to one or more embodiments, the level shifters 313-1 to 313-m can collectively raise or lower the level of the received input data. For example, as a non-limiting example, the level shifters 313-1 to 313-m can change the level of the received input data from a logic level "1" of a reference voltage of 3.3V to a logic level "1" of a reference voltage of 5V. However, the embodiments are not limited to such a specific value of the reference voltage, and other suitable reference voltages can be used in other embodiments.

[0091] The decoders 315-1 to 315-m may output gray voltages corresponding to input data (e.g., input data from a latch or input data converted by a level shifter) to output buffers 317-1 to 317-m. According to one or more embodiments, the decoders 315-1 to 315-m may generate gray voltages corresponding to the input data by using a plurality of reference gray voltages stored in advance, and may output the generated gray voltages to the buffers 317-1 to 317-m as a result.

[0092] According to one or more embodiments, as a non-limiting example, the plurality of reference gray voltages may depend on the color represented by the sub-pixel, such as red, green, blue, and white, etc. For example, the reference gray voltage for red input data output to a red sub-pixel may be different from the reference gray voltage for green input data output to a green sub-pixel. Depending on the particular pixel to which the input data is output, the decoders 315-1 to 315-m may use the appropriate reference gray voltage.

[0093] The output buffers 317-1 to 317-m may generate video signals VS1 to VSm by using the gray voltages output from the decoders 315-1 to 315-m, and may output the video signals VS1 to VSm to the display panel 100. According to one or more embodiments, the output buffers 317-1 to 317-m may convert the gray voltages output from the decoders 315-1 to 315-m, and may then output the converted voltages as the video signals VS1 to VSm.

[0094] According to one or more embodiments, the first group of driving circuits 310-1 to 310-m may be connected to each other. According to the relationship between the input data input to the first group of driving circuits 310-1 to 310-m connected to each other, a portion of the first group of driving circuits may be appropriately disconnected. Here, alternatively, the video signal alternately output from the disconnected driving circuit may be output from other driving circuits in the first group. Therefore, the power consumption for driving the driving circuits 310-1 to 310-m may be reduced. Figure 3 , Figure 3 It is shown that the first driving circuit 310-1 and the second driving circuit 310-2 in the driving circuits 310-1 to 310-m can be connected to each other. The second driving circuit 310-2 can be disconnected based on the control of the timing controller 200, and the output value of the first driving circuit 310-1, that is, the video signal, can be output instead of the output value of the second driving circuit 310-2. Therefore, the power consumption of the source driving circuit 300 can be reduced.

[0095] According to one or more embodiments, the first drive circuit 310-1 and the second drive circuit 310-2 of the plurality of drive circuits 310-1 to 310-m may be connected to each other through a switch SW. When the second drive circuit 310-2 is disconnected, the switch SW may be turned on. Then, when the switch SW is turned on, the first video signal VS1 output by the first drive circuit 310-1 may be sent to the output terminal of the second drive circuit 310-2 through the switch SW. Therefore, alternatively, the video signal that should be output from the second drive circuit 310-2 may be output from the first drive circuit 310-1 connected to the second drive circuit 310-2.

[0096] According to one or more embodiments, the video signals generated by the first driving circuit 310-1 and the second driving circuit 310-2 may be output to sub-pixels that emit light of the same color. For example, the video signals generated by the first driving circuit 310-1 and the second driving circuit 310-2 may be sent to sub-pixels that all output red light, but the embodiments are not limited to this specific example.

[0097] According to one or more embodiments, the second driving circuit 310-2 may be turned off in response to receiving the control data CDATA output from the timing controller 200. For example, the second driving circuit 310-2 may receive the control data CDATA from the timing controller 200 and may generate the control signal CS based on the received control data CDATA. The second driving circuit 310-2 may then be turned off in response to receiving the control signal CS.

[0098] The second latch 311-2 may receive the control data CDATA from the timing controller 200. For example, the second latch 311-2 may receive the second input data IN2 and the control data CDATA as a single data unit. For example, as a non-limiting example, the control data CDATA may be 1-bit data, but the control data CDATA is not limited to this specific example.

[0099] The second level shifter 313-2 may generate a control signal CS by changing the level of the control data CDATA. The control signal CS may be applied to the second output buffer 317-2, and the second output buffer 317-2 may be disconnected in response to receiving the control signal CS. Therefore, since the second output buffer 317-2 is disconnected, the second output buffer 317-2 may not output the second video signal VS2.

[0100] The switch SW connecting the first drive circuit 310-1 and the second drive circuit 310-2 may be turned on in response to the disconnection of the second drive circuit 310-2. According to one or more embodiments, the switch SW may be turned on in response to the control signal CS generated from the second drive circuit 310-2. Therefore, when the switch SW is turned on, the video signal output from the first output buffer 317-1 may be output through the second channel CH2 connected to the second drive circuit 310-2 through the switch SW. That is, even in the case where the second drive circuit 310-2 may be disconnected, the video signal generated by the first drive circuit 310-1 can still be output through the second channel CH2 connected to the second drive circuit 310-2. Therefore, the effect of reducing the power consumption of the source driver circuit 300 can be produced.

[0101] at the same time, Figure 3 It is shown that based on receiving the control data CDATA, the second driving circuit 310-2 among the plurality of driving circuits 310-1 to 310-m is disconnected. However, according to one or more embodiments, at least one of the other driving circuits may be disconnected by the control data CDATA. Here, the disconnected driving circuit may be connected to the undisconnected driving circuit through a switch.

[0102] Figure 4 A timing controller according to one or more embodiments is shown. As a non-limiting example, the timing controller 200 may include an input data generation circuit 210 , an input data buffer 220 , and a control data generation circuit 230 .

[0103] The input data generating circuit 210 may generate input data IN by using video data RGB received from the outside of the timing controller 200. The generated input data IN may be output to the source driving circuit 300. According to one or more embodiments, the input data generating circuit 210 may generate input data IN corresponding to the video signal VS to be output to each row of the display panel 100. For example, the input data generating circuit 210 may generate and output input data IN of a row to which the current video signal VS is output (hereinafter referred to as a "current row"). CUR .

[0104] The input data buffer 220 may store the input data IN generated by the input data generating circuit 210. According to one or more embodiments, the input data buffer 220 may store the input data IN of a row (hereinafter referred to as a previous row) that has been output before the current row. PRV .

[0105] According to one or more embodiments, the input data buffer 220 may store input data IN corresponding to one row, and may update the stored data each time a row is output. For example, the input data IN of the previous row may be updated. PRV The stored input data IN of the previous row may then be erased. PRV , and can input the current row of data IN CUR Stored in the input data buffer 220.

[0106] For example, as a non-limiting example, the input data buffer 220 may include at least one of a non-volatile memory and a volatile memory.

[0107] The control data generation circuit 230 may generate control data CDATA for turning off or on a portion of the plurality of driving circuits 310-1 to 310-m. According to one or more embodiments, the control data generation circuit 230 may generate control data CDATA for turning off or on a portion of the plurality of driving circuits 310-1 to 310-m based on the input data IN of the previous row. PRV and the input data IN of the current row CUR To generate control data CDATA.

[0108] The control data generation circuit 230 can be based on the input data IN of the current row. CUR The comparison result between the video data included in and the input data IN of the previous line PRV The input data IN of the current row CURFor example, for the operation of the control data generation circuit 230, the control data generation circuit 230 may include at least one logic gate capable of performing a logic comparison operation, such as an OR gate, an AND gate, an XOR gate, a NOR gate, a NAND gate, etc., or a combination of such logic gates.

[0109] For example, Figure 4 As shown, the control data generation circuit 230 may be based on the input data IN of the current row of the first driving circuit 310-1 and the second driving circuit 310-2 of the plurality of driving circuits 310-1 to 310-m. CUR and the previous row of input data IN PRV Then, the control data generating circuit 230 may output the generated control data CDATA to the second driving circuit 310 - 2 .

[0110] According to one or more embodiments, the control data generation circuit 230 may receive the input data IN of the current row from the input data generation circuit 210. CUR , the input data IN of the previous row stored in the input data buffer 220 can be read PRV and can be done by using the current row's input data IN CUR and the previous row of input data IN PRV To generate control data CDATA.

[0111] Figure 5 is a diagram for describing the operation of a control data generation circuit according to one or more embodiments. Figures 1 to 5 , the input data IN of the previous row PRV It can be the input data of the kth line, and the input data IN of the current line CUR It may be input data of the k+1th line, where k is a natural number having a value of 1 or greater and less than m.

[0112] Input data IN PRV and IN CUR According to one or more embodiments, the input data IN PRV and IN CUR The first input data IN1 of the current row may be divided into units of, for example, 8 bits, which may be input to each driving circuit, and each unit IN1 to INm of the divided input data may be input to the plurality of driving circuits 310-1 to 310-m. CUR and the first input data IN1 of the previous row PRVcan be input into the first driving circuit 310-1, and the second input data IN2 of the current row CUR and the second input data IN2 of the previous row PRV can be input into the second driving circuit 320 - 2 .

[0113] The control data generation circuit 230 may be based on the input data IN of the previous row. PRV and the input data IN of the current row CUR According to one or more embodiments, the control data generating circuit 230 may generate the control data CDATA for disconnecting the driving circuit to be controlled based on the following deviations: a deviation between input data of a current row input to a driving circuit to be controlled (e.g., the second driving circuit 310-2) among the plurality of driving circuits 310-1 to 310-m and input data of a current row input to another driving circuit; a deviation between input data of a previous row input to the driving circuit to be controlled and input data of a current row input to another driving circuit; or a deviation between input data of a current row input to another driving circuit and input data of a previous row input to another driving circuit.

[0114] According to one or more embodiments, when the drive circuit to be controlled is as follows Figure 3 When the second driving circuit 310-2 is shown, the control data generating circuit 230 may generate a second input data IN2 of the current row input to the second driving circuit 310-2 based on the second input data IN2 of the current row input to the second driving circuit 310-2. CUR The first input data IN1 of the current row input to the first driving circuit 310-1 connected to the second driving circuit 310-2 CUR The first deviation DV1 between the first input data IN1 of the current row CUR The second input data IN2 of the previous row PRV The control data generation circuit 230 can also generate the control data CDATA based on the first input data IN1 of the previous row. PRV The first input data IN1 of the current row CUR For example, the control data generating circuit 230 may generate the control data CDATA based on the first deviation DV1, the second deviation DV2, and / or the third deviation DV3.

[0115] According to one or more embodiments, when the first input data IN1 of the current row CUR The second input data IN2 of the current row CUR When the first deviation DV1 between the first input data IN1 and the second input data IN2 is equal to or less than the first reference deviation, CURThe second input data IN2 of the previous row PRV When the second deviation DV2 between the current row and the first input data IN1 is equal to or smaller than the second reference deviation, or when the first input data IN1 of the current row CUR The first input data IN1 of the previous row PRV When the third deviation DV3 between the reference values ​​is equal to or less than the third reference deviation, the control data generating circuit 230 may generate the control data CDATA.

[0116] According to one or more embodiments, the first reference deviation may be 0, and the second reference deviation and the third reference deviation may both be 0 or greater.

[0117] That is, when the input data IN2 of the current row input to the second driving circuit 310-2 CUR The input data IN1 of the current row input to the first driving circuit 310-1 connected to the second driving circuit 310-2 CUR When the deviation between the two is small, and when the input data IN1 of the current row input to the first driving circuit 310-1 is CUR The input data IN2 of the previous row input to the second driving circuit 310-2 PRV If the deviation between the first and second driving circuits is small, the timing controller 200 may disconnect the second driving circuit 310-2 and may output the output of the first driving circuit 310-1 instead as the output of the second driving circuit, and the first input data IN1 of the current row may be used as the output of the second driving circuit. CUR The first input data IN1 of the previous row PRV Therefore, the power consumption of the display device 1000 can be reduced.

[0118] Also, as an example, Figure 5 It is shown that the control data generation circuit 230 can use the deviation between the input data of the first drive circuit 310-1 and the second drive circuit 310-2. However, the embodiment is not limited to this specific operation example. For example, the control data generation circuit 230 can use the deviation between the input data of the second drive circuit 310-2 and the i-th drive circuit 310-i, where 3≤i≤m.

[0119] Figure 6 is a diagram for describing the operation of a control data generation circuit according to one or more embodiments. Figures 1 to 6 , the control data generation circuit 230 can be based on the input data IN of the current row CUR and the previous row of input data IN PRV To generate control data CDATA.

[0120] like Figure 6 As shown, the second input data IN2 of the current rowCUR The first input data IN1 of the current row CUR can have the same value "11101010", and the first input data IN1 of the current row CUR The second input data IN2 of the previous row PRV In this example, since the first deviation DV1 and the second deviation DV2 are both 0, the control data generation circuit 230 can generate the control data CDATA to have a value of "1", which is different from the first input data IN1 of the current row. CUR The first input data IN1 of the previous row PRV As further described above, the control data CDATA may be used to turn off the second driving circuit 310 - 2 .

[0121] The control data generation circuit 230 may output the control data CDATA to the second driving circuit 310-2. According to an embodiment, the control data generation circuit 230 may output the control data CDATA for turning off the second driving circuit 310-2 together with the second input data IN2 of the current row. CUR For example, the control data generation circuit 230 may fill the control data CDATA into the second input data IN2 of the current row. CUR Therefore, the second driving circuit 310 - 2 may be turned off based on the control data CDATA.

[0122] Figure 7 is a diagram for describing the operation of a control data generation circuit according to one or more embodiments. Figures 1 to 7 , the control data generation circuit 230 can be based on the input data IN of the current row CUR and the previous row of input data IN PRV To generate control data CDATA.

[0123] like Figure 7 As shown, the second input data IN2 of the current row CUR and the first input data IN1 of the current row CUR can have the same value as "11101010". However, in this example, the first input data IN1 of the current row CUR The second input data IN2 of the previous row PRV The second deviation DV2 between may be 16. Similarly, in this example, the first input data IN1 of the current row CUR The first input data IN1 of the previous row PRVThe third deviation DV3 between them is also 16. Therefore, in such an example, when both the second reference deviation and the third reference deviation are less than 16, the second deviation DV2 exceeds the second reference deviation, and the third deviation DV3 also exceeds the third reference deviation. As a result, the control data generation circuit 230 may not generate the control data CDATA.

[0124] In other words, according to one or more embodiments, when the deviation between the input data of the current row and the input data of the previous row (i.e., the second deviation DV2 and the third deviation DV3) exceeds the reference deviation (i.e., the second reference deviation and the third reference deviation), the control data CDATA may not be generated, and thus the driving circuit may not be disconnected.

[0125] Figure 8 is a flow chart illustrating the operation of a panel control circuit according to one or more embodiments. Figures 1 to 8 In operation S110, the panel control circuit may receive video data RGB from an external device. According to an embodiment, the video data RGB may be in a digital format. However, the embodiment is not limited thereto.

[0126] In operation S120, the panel control circuit may generate first input data IN1 and second input data IN2 based on the video data RGB. For example, the first input data IN1 may be transmitted to the first driving circuit 310-1, and the second input data IN2 may be transmitted to the second driving circuit 310-2. According to one or more embodiments, the timing controller 200 may generate input data IN1 to INm by processing the video data RGB, and may transmit the input data IN1 to INm to the driving circuits 310-1 to 310-m.

[0127] In operation S130, the panel control circuit may calculate the first input data IN1 of the current row. CUR The second input data IN2 of the current row CUR According to one or more embodiments, the timing controller 200 may include at least one logic circuit, and may calculate the first input data IN1 of the current row by using the at least one logic circuit. CUR The second input data IN2 of the current row CUR The first deviation DV1 between them.

[0128] In operation S140, the panel control circuit may calculate the first input data IN1 of the current row. CUR The second input data IN2 of the previous row PRV The second deviation DV2 between the two and the first input data IN1 of the current row can be calculated CUR The first input data IN1 of the previous rowPRV According to one or more embodiments, the timing controller 200 may include at least one logic circuit, and may perform the above operation by using the included at least one logic circuit.

[0129] In operation S150, the panel control circuit may disconnect a portion of the driving circuits 310-1 to 310-m based on the first deviation DV1, the second deviation DV2, or the third deviation DV3. According to an embodiment, when the first deviation DV1 is equal to or less than the first reference deviation and when the second deviation DV2 is equal to or less than the second reference deviation or when the third deviation DV3 is equal to or less than the third reference deviation, the timing controller 200 may generate the control data CDATA. The timing controller 200 may send the control data CDATA to the second driving circuit 310-2. Then, the second driving circuit 310-2 may be disconnected in response to receiving the control data CDATA. Accordingly, when the second driving circuit 310-2 is disconnected, the switch SW connecting the first driving circuit 310-1 and the second driving circuit 310-2 may be turned on in response to the control signal CS generated by the control data CDATA.

[0130] Fig. 9 A source driver circuit according to one or more embodiments is shown.

[0131] Reference Figures 1 to 9 , the source driving circuit 300 can receive input data IN CUR and IN PRV and can be based on the input data IN CUR and IN PRV To generate and output video signal VS CUR and VS PRV .

[0132] For ease of description, according to a non-limiting example, Fig. 9 Input data IN CUR and IN PRV Input data for R pixels (red pixels), B pixels (blue pixels), and G pixels (green pixels) may be included. Fig. 9 The superscript of the input data shown indicates whether the input data is input data of the current row with a superscript of n+1 or input data of the previous row with a superscript of n. Fig. 9 The subscripts of the input data shown identify the input driver circuit. For example, the input data IN(R n 1) may indicate that it is input data of the R pixels input to the first driving circuit 310 - 1 in the previous row n.

[0133] Similarly, by way of non-limiting example, Fig. 9 Video signal VSCUR and VS PRV Video signals for R pixels, B pixels, and G pixels may be included. Fig. 9 The superscript of the video signal shown in may indicate whether the video signal is the video signal of the current row with superscript n+1 or the previous row with superscript n. Fig. 9 The subscripts of the video signals shown identify the input drive circuits. n+1 3) may mean that this is a video signal for a B pixel output through the first output pad OP1 after the data input through the third driving circuit 310 - 3 is switched by the output switching circuit 320 in the current row n+1.

[0134] As mentioned above, refer to Figure 3 , the plurality of driving circuits 310 - 1 to 310 - 8 may output a video signal VS based on the input data IN.

[0135] The output switch circuit 320 may receive the video signals VS1 to VS8 from the plurality of driving circuits 310-1 to 310-8 and may output the video signals VS1 to VS8 to the display panel 100. According to an embodiment, the output switch circuit 320 may be connected to the plurality of driving circuits 310-1 to 310-8 and to output pads OP1 to OP8 respectively corresponding to the plurality of driving circuits 310-1 to 310-8.

[0136] According to an embodiment, the output switch circuit 320 may selectively output the first video signal VS1 output from the first drive circuit 310-1 from the plurality of drive circuits 310-1 to 310-8 through the first output pad OP1 or the third output pad OP3. The output switch circuit 320 may selectively output the third video signal VS3 output from the third drive circuit 310-3 through the third output pad OP3 or the first output pad OP1.

[0137] As described above, the output switch circuit 320 can selectively output the fifth video signal VS5 output from the fifth drive circuit 310-5 from the plurality of drive circuits 310-1 to 310-8 through the fifth output pad OP5 or the seventh output pad OP7. The output switch circuit 320 can selectively output the seventh video signal VS7 output from the seventh drive circuit 310-7 through the seventh output pad OP7 or the fifth output pad OP5.

[0138] According to an embodiment, as a non-limiting example, the output switch circuit 320 may include a plurality of switches or multiplexers that may selectively connect the driving circuits 310-1 to 310-8 and the output pad OP, respectively. However, the output switch circuit 320 may not be limited to such a specific example.

[0139] Each of the plurality of driving circuits 310 - 1 to 310 - 8 may receive input data IN transmitted from the timing controller 200 . PRV and IN CUR and can be combined with the input data IN PRV and IN CUR The corresponding video signal VS PRV and VS CUR Output to the display panel 100 .

[0140] According to one or more embodiments, the driving circuits 310-1 to 310-8 may include a group of driving circuits, which include driving circuits connected to each other. Depending on the relationship between the units of the input data input to the group of driving circuits, a part of the driving circuits connected to each other included in the group of driving circuits may be disconnected. For example, a video signal output from a disconnected part of the driving circuit may be replaced with a video signal output from other driving circuits included in the group of driving circuits. Therefore, the power consumption for driving a group of driving circuits may be reduced.

[0141] exist Fig. 9 In the example of the source driver circuit of , the first driver circuit 310-1 and the fifth driver circuit 310-5 can be connected to each other as a first group. The second driver circuit 310-2 and the fourth driver circuit 310-4 can be connected to each other as a second group. The third driver circuit 310-3 and the seventh driver circuit 310-7 can be connected to each other as a third group. The sixth driver circuit 310-6 and the eighth driver circuit 310-8 can be connected to each other as a fourth group. According to an embodiment, the driver circuits in each group can be connected to each other through switches SW1 to SW4.

[0142] According to an embodiment, a driving circuit included in each group of driving circuits may process any one of the R pixels and the B pixels, or may alternatively process the G pixels.

[0143] The input data IN (R n+1 1) and IN(R n+1 5) and the input data IN (B) of the previous row input to the third group of driving circuits (310-3 and 310-7) n 7) and IN(B n3) to disconnect the fifth driving circuit 310-5 of the first group of driving circuits (310-1 and 310-5). When the fifth driving circuit 310-5 is disconnected, the second switch SW2 connecting the fifth driving circuit 310-5 and the first driving circuit 310-1 can be turned on, so that the video signal VS1 output from the first driving circuit 310-1 can be output through the fifth channel CH5 connected to the fifth driving circuit 310-5.

[0144] According to an embodiment, the timing controller 200 may generate a timing signal based on the input data IN (R ) of the current row input to the first group of driving circuits ( 310 - 1 and 310 - 5 ). n+1 1) and IN(R n+1 5) and the input data IN (B) of the previous row input to the third group of driving circuits (310-3 and 310-7) n 7) and IN(B n 3) to generate the second control data CDATA2. For example, the second control data CDATA2 may be 1-bit data or include 1-bit data. The generated second control data CDATA2 may be sent to the fifth drive circuit 310-5. The second control data CDATA2 may be input to the fifth latch 311-5 and may be sent to the fifth level shifter 313-5. The fifth level shifter 313-5 may output the second control signal CS2 by using the second control data CDATA2. The fifth output buffer 317-5 may be disconnected in response to the second control signal CS2, and thus the fifth video signal VS5 may not be output. In addition, the second switch SW2 may be turned on in response to the second control signal CS2, and then the first drive circuit 310-1 and the fifth drive circuit 310-5 may be connected to each other. Therefore, the first video signal VS1 generated by the first drive circuit 310-1 may be output as the fifth video signal VS5 instead.

[0145] Similarly, depending on the input data IN(G n+1 2) IN(G n+1 4) IN(G n 2) and IN(G n 4), the fourth driving circuit 310-4 of the second group of driving circuits (310-2 and 310-4) can be disconnected. When the fourth driving circuit 310-4 is disconnected, the first switch SW1 connecting the fourth driving circuit 310-4 and the second driving circuit 310-2 can be turned on, so that the video signal VS2 output from the second driving circuit 310-2 can be output through the fourth channel CH4 connected to the fourth driving circuit 310-4.

[0146] According to an embodiment, the timing controller 200 may generate a timing signal based on the input data IN (G ) input to the second group of driving circuits ( 310 - 2 and 310 - 4 ). n+1 2) IN(G n+1 4) IN(G n 2) and IN(G n 4). Depending on the first control data CDATA1, the fourth driving circuit 310-4 may be turned off.

[0147] Similarly, the input data IN (B) of the current row input to the third group of driving circuits (310-3 and 310-7) may be used to generate the current row of the driving circuits. n+1 3) and IN(B n+1 7) and the input data IN (R) of the previous row input to the first group (310-1 and 310-5). n 1) and IN(R n 5) to disconnect the seventh driving circuit 310-7 of the third group of driving circuits (310-3 and 310-7). When the seventh driving circuit 310-7 is disconnected, the third switch SW3 connecting the seventh driving circuit 310-7 and the third driving circuit 310-3 can be turned on, so that the video signal VS3 output from the third driving circuit 310-3 can be output through the seventh channel CH7 connected to the seventh driving circuit 310-7.

[0148] According to an embodiment, the timing controller 200 may generate a timing signal based on the input data IN (B) of the current row input to the third group of driving circuits (310-3 and 310-7). n+1 3) and IN(B n+1 7) and the input data IN (R) of the previous row input to the first group of driving circuits (310-1 and 310-5) n 1) and IN(R n 5). Depending on the third control data CDATA3, the seventh driving circuit 310-7 may be turned off.

[0149] Similarly, depending on the input data IN (G n+1 6) IN(G n+1 8) IN(G n 6) and IN(G n8), the eighth driving circuit 310-8 of the fourth group of driving circuits (310-6 and 310-8) can be disconnected. When the eighth driving circuit 310-8 is disconnected, the fourth switch SW4 connecting the eighth driving circuit 310-8 and the sixth driving circuit 310-6 can be turned on, so that the video signal VS6 output from the sixth driving circuit 310-6 can be output through the eighth channel CH8 connected to the eighth driving circuit 310-8.

[0150] According to an embodiment, the timing controller 200 may generate a timing signal based on the input data IN (G ) input to the fourth group of driving circuits ( 310 - 6 and 310 - 8 ). n+1 6) IN(G n+1 8) IN(G n 6) and IN(G n 8) to generate the fourth control data CDATA4. Depending on the fourth control data CDATA4, the eighth driving circuit 310-8 may be turned off.

[0151] Therefore, depending on the relationship between input data input into a group of drive circuits, a part of the drive circuits connected to each other included in the group of drive circuits can be disconnected. Here, the video signal output from the disconnected part of the drive circuit can be replaced with the video signal output from the other drive circuits included in the group of drive circuits. Therefore, the power consumption for driving the group of drive circuits can be reduced.

[0152] Figures 10 to 12 It is used to show Fig. 9 The operation of the control data generation circuit is shown in FIG. Figure 4 As described above, the control data generation circuit 230 can be based on the input data IN of the previous row. PRV and the input data IN of the current row CUR To generate control data CDATA.

[0153] Figures 10 to 12 shows the input data IN of the previous row in the control data generation circuit 230 PRV The input data IN of the current row CUR The comparison logic between .

[0154] Then, Figures 10 to 12 The logical operation described in the above may be a bitwise logical operation. According to one or more embodiments, the number of bits of the bitwise logical operation may be equal to or less than the number of bits of the input data. For example, when the input data is 8-bit data, the number of bits of the bitwise logical product may be 8-bit data. In this example, even if the bitwise logical product differs from the 8-bit input data by three bits, it can be determined that the above two input data are the same.

[0155] Reference Fig.10, the control data generation circuit 230 can calculate the input data IN (B n 3) and input data IN(R n+1 1) is a result value L1 of the logical product (AND operation). According to the embodiment, when the input data IN (B n 3) and input data IN(R n+1 1) are the same, the control data generation circuit 230 may calculate the result value L1 as bit 1.

[0156] The control data generation circuit 230 can calculate the input data IN (B n 7) and input data IN(R n+1 1) is the result value L2 of the logical product.

[0157] The control data generation circuit 230 may calculate a result value L3 which is a logical sum of the result value L1 and the result value L2 .

[0158] The control data generation circuit 230 can calculate the input data IN (R n+1 1) and input data IN(R n+1 5) is the result value L4 of the logical product.

[0159] The control data generation circuit 230 may generate a result value of the logical product of the result value L3 and the result value L4 as the control data CDATA. According to an embodiment, the control data generation circuit 230 may generate a result value of the logical product of the result value L3 and the result value L4 as the second control data CDATA2.

[0160] Reference Fig.11 , the control data generation circuit 230 can calculate the input data IN (B n+1 3) and input data IN(B n+1 7) is the result value L1 of the logical product (AND operation).

[0161] The control data generation circuit 230 can calculate the result value L1, the input data IN (B n+1 3) and input data IN(R n 1) is the result value L2 of the logical product.

[0162] The control data generation circuit 230 can calculate the result value L1, the input data IN (B n+1 3) and input data IN(R n 5) is the result value L3 of the logical product.

[0163] The control data generation circuit 230 may calculate a logical sum (or operation) of the result value L2 and the result value L3 as the control data CDATA. According to an embodiment, the control data generation circuit 230 may generate a logical sum of the result value L2 and the result value L3 as the third control data CDATA3.

[0164] Reference Fig.12 , the control data generation circuit 230 can calculate the input data IN(G n+1 2) and input data IN(G n+1 4) is the result value L1 of the logical product.

[0165] The control data generation circuit 230 can calculate the result value L1, the input data IN (G n+1 2) and input data IN(G n 2) is the result value L2 of the logical product.

[0166] The control data generation circuit 230 can calculate the result value L1, the input data IN (G n+1 2) and input data IN(G n 4) is the result value L3 of the logical product.

[0167] The control data generation circuit 230 may calculate a logical sum of the result value L2 and the result value L3 as the control data CDATA. According to an embodiment, the control data generation circuit 230 may generate a logical sum of the result value L2 and the result value L3 as the first control data CDATA1.

[0168] The method of generating the fourth control data CDATA4 may be substantially the same as the method of generating the first control data CDATA1 except for the fact that the data to be input is different. Therefore, for the sake of brevity, the description of the method of generating the fourth control data CDATA4 is omitted.

[0169] Although the present disclosure includes specific examples, it will be apparent after understanding the disclosure of the present application that various changes in form and detail may be made to these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are considered in a descriptive sense only, and not for limiting purposes. The description of the features or aspects in each example is considered to be applicable to similar features or aspects in other examples. If the described techniques are performed in a different order, and / or if the components in the described systems, structures, devices, or circuits are combined in different ways and / or replaced or supplemented by other components or their equivalents, suitable results may be obtained. Therefore, the scope of the present disclosure is defined by the claims and their equivalents, not by specific embodiments, and all changes within the scope of the claims and their equivalents are considered to be included in the present disclosure.

Claims

1. A panel control circuit for controlling a display panel including a first data line and a second data line, the panel control circuit comprising: a timing controller configured to generate input data including first input data and second input data; a first driving circuit configured to output a first video signal corresponding to the first input data to the first data line; as well as a second driving circuit configured to output a second video signal corresponding to the second input data to the second data line, The timing controller is configured to: based on a comparison result between a first deviation between the first input data of a current row and the second input data of the current row and a first reference deviation, and The second driving circuit is disconnected based on a comparison result between a second deviation and a second reference deviation between the first input data of the current row and the second input data of the previous row, or a comparison result between a third deviation and a third reference deviation between the first input data of the current row and the first input data of the previous row.

2. The panel control circuit according to claim 1, wherein: The timing controller is configured to generate control data for turning off the second driving circuit based on the first deviation and the second deviation or the third deviation.

3. The panel control circuit according to claim 2, wherein: The timing controller comprises: An input data generating circuit configured to generate the input data; an input data buffer configured to store the input data of the previous row generated by the input data generating circuit; and A control data generating circuit is configured to generate the control data by using the input data of the current row transmitted from the input data generating circuit and the input data of the previous row read from the input data buffer.

4. The panel control circuit according to claim 3, wherein: The control data generation circuit includes at least one logic circuit configured to calculate the first deviation, the second deviation, and the third deviation.

5. The panel control circuit according to claim 2, wherein: In response to the first deviation being equal to or less than the first reference deviation and in response to the second deviation being equal to or less than the second reference deviation or the third deviation being equal to or less than the third reference deviation, the timing controller is configured to generate control data for turning off the second driving circuit.

6. The panel control circuit according to claim 5, wherein: The first reference deviation is smaller than the second reference deviation and the third reference deviation.

7. The panel control circuit according to claim 2, wherein: The timing controller is configured to generate the control data as 1-bit data.

8. The panel control circuit according to claim 7, wherein: The timing controller is configured to fill the control data onto the second input data, and the timing controller is configured to output the second input data filled with the control data to the second driving circuit.

9. The panel control circuit according to claim 2, wherein: The first driving circuit comprises: a first latch configured to store the first input data, a first conversion circuit configured to convert the first input data output from the first latch into an analog value, and A first output buffer is configured to output the first video signal using the analog value output by the first conversion circuit.

10. The panel control circuit according to claim 9, wherein: The second driving circuit comprises: a second latch configured to store the second input data; a second conversion circuit configured to convert the second input data output from the second latch into an analog value; and a second output buffer configured to output the second video signal using the analog value output by the second conversion circuit, wherein the second latch is configured to receive the control data and is configured to output the control data to the second conversion circuit, and The second conversion circuit is configured to generate a control signal for disconnecting the second output buffer based on the control data.

11. The panel control circuit according to claim 10, further comprising: A switch is configured to transmit the output of the first output buffer to an output terminal of the second output buffer, wherein the switch is turned on in response to the control signal. 12 . The panel control circuit according to claim 1 , further comprising a switch, wherein when the second driving circuit is disconnected, the switch electrically connects the first driving circuit with the second driving circuit.

13. A panel control circuit for controlling a display panel including a data line, the panel control circuit comprising: A driving circuit configured to output a plurality of input data to the data lines; a timing controller configured to output the plurality of input data; as well as an output switch circuit configured to switch a part of the plurality of input data and configured to output to the data line, The timing controller is configured to: based on a comparison result between a first deviation between the first input data of the current row and the fifth input data of the current row and a first reference deviation, and The driving circuit that outputs the fifth input data is disconnected based on the comparison result between the second deviation and the second reference deviation between the first input data of the current row and the seventh input data of the previous row, or the comparison result between the third deviation and the third reference deviation between the first input data of the current row and the third input data of the previous row.

14. The panel control circuit according to claim 13, wherein: The timing controller is configured to generate control data for turning off a driving circuit that outputs the fifth input data based on the first deviation and the second deviation or the third deviation.

15. The panel control circuit according to claim 14, wherein: The timing controller is configured to generate control data for disconnecting a driving circuit that outputs the fifth input data in response to the first deviation being equal to or less than the first reference deviation and in response to the second deviation being equal to or less than the second reference deviation or the third deviation being equal to or less than the third reference deviation.

16. The panel control circuit according to claim 14, wherein: The timing controller is configured to fill the control data onto the fifth input data, and the timing controller is configured to output the filled data through a driving circuit that outputs the fifth input data.

17. A panel control circuit for controlling a display panel including a data line, the panel control circuit comprising: A driving circuit configured to output a plurality of input data to the data lines; a timing controller configured to output the plurality of input data; as well as an output switch circuit configured to switch a part of the plurality of input data and output to a plurality of data lines, wherein the timing controller is based on a comparison result between a first deviation between the third input data of the current row and the seventh input data of the current row and a first reference deviation, and The driving circuit that outputs the seventh input data is disconnected based on a comparison result between a second deviation and a second reference deviation between the third input data of the current row and the fifth input data of the previous row, or a comparison result between a third deviation and a third reference deviation between the third data of the current row and the first input data of the previous row.

18. The panel control circuit according to claim 17, wherein: The timing controller is configured to generate control data for turning off a driving circuit that outputs the seventh input data based on the first deviation and the second deviation or the third deviation.

19. The panel control circuit according to claim 18, wherein: The timing controller is configured to generate control data for disconnecting a driving circuit that outputs the seventh input data in response to the first deviation being equal to or less than the first reference deviation and in response to the second deviation being equal to or less than the second reference deviation or the third deviation being equal to or less than the third reference deviation.

20. The panel control circuit according to claim 18, wherein: The timing controller is configured to fill the control data onto the seventh input data, and is configured to output the filled data through a driving circuit that outputs the seventh input data.

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