Pixels and display devices

Abstract

This invention discloses a pixel and a display device. The pixel includes: a light-emitting element; a driving transistor that controls the amount of driving current flowing to the light-emitting element according to a gate-source voltage; a first compensation transistor and a second compensation transistor that operate in response to a first scan signal and are connected in series between the gate and drain of the driving transistor; a first gate initialization transistor and a second gate initialization transistor that operate in response to a second scan signal and are connected in series between a voltage line and the gate of the driving transistor; and a node-connecting transistor that connects a first floating node and a second floating node to each other in response to the second scan signal. The first floating node is between the first compensation transistor and the second compensation transistor, and the second floating node is between the first gate initialization transistor and the second gate initialization transistor.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0078812, filed on June 26, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to pixels and display devices. Background Technology

[0004] Organic light-emitting display devices may include light-emitting elements (e.g., organic light-emitting diodes) having brightness that varies with current. Pixels of an organic light-emitting display device may include light-emitting elements, driving transistors, and switching transistors. The driving transistor controls the amount of current supplied to the light-emitting element based on the voltage between its gate and source. The switching transistor transmits a data voltage for controlling the brightness of the light-emitting element to the driving transistor.

[0005] To maintain a constant brightness of the light-emitting element during a frame, the voltage between the gate and source of the driving transistor must remain constant. For this purpose, the pixel may further include a storage capacitor electrically connected to the gate of the driving transistor.

[0006] To display more vivid images, the resolution of organic light-emitting display devices has been gradually increased, while the pixel size has been gradually decreased. To reduce the pixel size, the capacitance of the storage capacitors has also been reduced. Therefore, even a small amount of leakage current can change the gate voltage of the driving transistor, resulting in variations in the brightness of the light-emitting element.

[0007] Furthermore, to reduce power consumption in organic light-emitting display devices or electronic devices electrically connected to them, techniques have been used to drive them at low frame rates as needed. The frame period can be further increased, and thus users can better perceive changes in the brightness of the light-emitting elements.

[0008] It should be understood that this background section is intended to provide, in part, useful background for understanding the technology. However, this background section may also include ideas, concepts, or knowledge that were known or understood by a person skilled in the art prior to the corresponding valid application date, but do not constitute the subject matter disclosed herein. Summary of the Invention

[0009] One or more embodiments may provide a pixel capable of reducing the cutoff current of a switching transistor electrically connected to a storage capacitor, and a display device including the pixel.

[0010] The technical objectives achieved by this disclosure are not limited to those described above, and other technical objectives not mentioned herein can be clearly understood by those skilled in the art based on the description of this disclosure.

[0011] According to one or more embodiments, a pixel may include: a light-emitting element; a driving transistor that controls the amount of driving current flowing to the light-emitting element according to a gate-source voltage; a storage capacitor electrically connected to the gate of the driving transistor; a scanning transistor that transmits a data voltage to the source of the driving transistor in response to a first scan signal; a first compensation transistor and a second compensation transistor that operate in response to the first scan signal, the first compensation transistor and the second compensation transistor being connected in series between the gate and drain of the driving transistor; a first gate initialization transistor and a second gate initialization transistor that operate in response to a second scan signal, the first gate initialization transistor and the second gate initialization transistor being connected in series between a voltage line and the gate of the driving transistor, the voltage line transmitting an initialization voltage; and a node-connecting transistor that connects a first floating node and a second floating node to each other in response to the second scan signal, the first floating node being between the first compensation transistor and the second compensation transistor, and the second floating node being between the first gate initialization transistor and the second gate initialization transistor.

[0012] The node connection transistor can be turned off in response to the rising edge of the second scan signal, the first compensation transistor and the second compensation transistor can be turned off in response to the rising edge of the first scan signal, and the potential of the first floating node can be coupled to the rising edge of the second scan signal at the time when the node connection transistor is turned off, thereby increasing the potential of the first floating node.

[0013] The first gate initialization transistor and the second gate initialization transistor can be turned off in response to the rising edge of the second scan signal, and the potential of the second floating node can be coupled to the rising edge of the second scan signal at the time when the first gate initialization transistor and the second gate initialization transistor are turned off, thereby increasing the potential of the second floating node.

[0014] The increase in potential of the first floating node caused by coupling with the rising edge of the first scan signal at the time points when the first compensation transistor and the second compensation transistor are turned off can be less than the increase in potential of the second floating node caused by coupling with the rising edge of the second scan signal at the time points when the first gate initialization transistor and the second gate initialization transistor are turned off.

[0015] When both the node-connecting transistor and the first compensation transistor are turned off, the cutoff current flowing from the first floating node through the node-connecting transistor to the second floating node can be greater than the cutoff current flowing from the first floating node through the first compensation transistor to the gate of the driving transistor.

[0016] Within a frame period, after the first gate initialization transistor, the second gate initialization transistor, and the node connection transistor are turned on in response to a second scan signal with a pulse voltage having an on level, the scan transistor, the first compensation transistor, and the second compensation transistor may be turned on in response to a first scan signal with a pulse voltage having an on level.

[0017] The pixel may further include an anode initialization transistor that can apply an initialization voltage to the anode of the light-emitting element in response to a third scan signal.

[0018] The third scan signal can be synchronized with the first scan signal.

[0019] The pixel may further include: a first emitter control transistor that connects a power line to the source of a driving transistor in response to an emitter control signal, the power line transmitting a driving voltage; and a second emitter control transistor that connects the drain of the driving transistor to the anode of a light-emitting element in response to an emitter control signal.

[0020] Storage capacitors can be electrically connected between the power line and the gate of the driving transistor.

[0021] The pixel may further include a third compensation transistor that connects the gate of the driving transistor to the first compensation transistor in response to the first scan signal.

[0022] The pixel may further include a third compensation transistor that connects the second compensation transistor to the drain of the driving transistor in response to the first scan signal.

[0023] According to one or more embodiments, a pixel may be electrically connected to a first scan line to a third scan line that transmits a first scan signal to a third scan signal, an transmit control line that transmits a transmit control signal, a data line that transmits a data voltage, a power line that transmits a drive voltage, and a voltage line that transmits an initialization voltage. A pixel may include: a light-emitting element including an anode and a cathode; a storage capacitor including a first electrode and a second electrode, the first electrode being electrically connected to the power line; and a first transistor including a gate electrically connected to the second electrode of the storage capacitor, a source electrically connected to the power line, and a drain. A pixel may also include: a second transistor including a gate electrically connected to the first scan line, a source electrically connected to the data line, and a drain electrically connected to the source of the first transistor; and a third transistor including a first compensation transistor and a second compensation transistor, the first compensation transistor including a gate electrically connected to the first scan line, a source electrically connected to the first floating node, and a drain electrically connected to the gate of the first transistor, and the second compensation transistor including a gate electrically connected to the first scan line, a source electrically connected to the drain of the first transistor, and a drain electrically connected to the first floating node. A pixel may include a fourth transistor, which includes a first anode initialization transistor and a second anode initialization transistor. The first anode initialization transistor includes a gate electrically connected to a second scan line, a source electrically connected to the gate of the first transistor, and a drain electrically connected to a second floating node. The second anode initialization transistor includes a gate electrically connected to the second scan line, a source electrically connected to the second floating node, and a drain electrically connected to a voltage line. A pixel may also include: a fifth transistor including a gate electrically connected to an emission control line, a source electrically connected to a power line, and a drain electrically connected to the source of the first transistor; a sixth transistor including a gate electrically connected to an emission control line, a source electrically connected to the drain of the first transistor, and a drain electrically connected to the anode of the light-emitting element; a seventh transistor including a gate electrically connected to a third scan line, a source electrically connected to the anode of the light-emitting element, and a drain electrically connected to a voltage line; and an eighth transistor including a gate electrically connected to the second scan line, a source electrically connected to the first floating node, and a drain electrically connected to the second floating node.

[0024] The eighth transistor can be turned off in response to the rising edge of the second scan signal, the first compensation transistor and the second compensation transistor can be turned off in response to the rising edge of the first scan signal, and the potential of the first floating node can be coupled to the rising edge of the second scan signal at the time when the eighth transistor is turned off, thereby increasing the potential of the first floating node, and can also be coupled to the rising edge of the first scan signal at the time when the first compensation transistor and the second compensation transistor are turned off, thereby increasing the potential of the first floating node.

[0025] The first gate initialization transistor and the second gate initialization transistor can be turned off in response to the rising edge of the second scan signal, and the potential of the second floating node can be coupled to the rising edge of the second scan signal at the time when the first gate initialization transistor and the second gate initialization transistor are turned off, thereby increasing the potential of the second floating node.

[0026] The increase in potential of the first floating node caused by coupling with the rising edge of the first scan signal at the time points when the first compensation transistor and the second compensation transistor are turned off can be less than the increase in potential of the second floating node caused by coupling with the rising edge of the second scan signal at the time points when the first gate initialization transistor and the second gate initialization transistor are turned off.

[0027] When both the eighth transistor and the first compensation transistor are turned off, the cutoff current flowing from the first floating node through the eighth transistor to the second floating node can be greater than the cutoff current flowing from the first floating node through the first compensation transistor to the gate of the first transistor.

[0028] According to one or more embodiments, a display device may include: a substrate extending in a first direction and a second direction; a first scan line and a second scan line that respectively transmit a first scan signal and a second scan signal, the first scan line and the second scan line extending in the first direction; a data line that transmits a data voltage and extends in the second direction; a power line that transmits a driving voltage; a voltage line that transmits an initialization voltage and extends in the first direction; and pixels disposed on the substrate in the first direction and the second direction. Each pixel may include: a light-emitting element; a driving transistor that controls the amount of driving current flowing from the power line to the light-emitting element according to the gate-source voltage; a storage capacitor electrically connected to the gate of the driving transistor; a scan transistor that transmits a data voltage to the source of the driving transistor in response to a first scan signal; a first compensation transistor and a second compensation transistor that operate in response to the first scan signal, the first compensation transistor and the second compensation transistor being connected in series between the gate and drain of the driving transistor; a first gate initialization transistor and a second gate initialization transistor that operate in response to a second scan signal, the first gate initialization transistor and the second gate initialization transistor being connected in series between the gate of the driving transistor and the voltage line; and a node connection transistor that connects a first floating node to a second floating node in response to the second scan signal, the first floating node being between the first compensation transistor and the second compensation transistor, and the second floating node being between the first gate initialization transistor and the second gate initialization transistor.

[0029] The potential of the first floating node can be coupled to the rising edge of the second scan signal at the time point when the node connection transistor is turned off, causing the potential of the first floating node to increase by a first level. It can also be coupled to the rising edge of the first scan signal at the time point when the first compensation transistor and the second compensation transistor are turned off, causing the potential of the first floating node to increase by a second level. The potential of the second floating node can be coupled to the rising edge of the second scan signal at the time point when the first gate initialization transistor and the second gate initialization transistor are turned off, causing the potential of the second floating node to increase by a third level greater than the second level.

[0030] When both the node-connecting transistor and the first compensation transistor are turned off, the cutoff current flowing from the first floating node through the node-connecting transistor to the second floating node can be greater than the cutoff current flowing from the first floating node through the first compensation transistor to the gate of the driving transistor.

[0031] Other aspects, features, and advantages besides those described above will become apparent from the following detailed description, claims, and drawings used to carry out this disclosure. Attached Figure Description

[0032] The above and other aspects, features and advantages of specific embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0033] Figure 1 This is a schematic block diagram of an organic light-emitting display device according to an embodiment;

[0034] Figure 2 This is a schematic diagram of the pixel circuit according to an embodiment;

[0035] Figure 3 It is used for operation Figure 2 A schematic timing diagram of the control signals for the pixel circuit shown;

[0036] Figure 4 yes Figure 2 A schematic diagram of the voltage waveforms at each node of the pixel circuit shown.

[0037] Figure 5 This is a schematic diagram of a pixel circuit according to another embodiment; and

[0038] Figure 6 This is a schematic diagram of a pixel circuit according to another embodiment. Detailed Implementation

[0039] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, these embodiments are described below only with reference to the accompanying drawings to explain aspects of the description.

[0040] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. The terms “and” and “or” may be used in a combined or separate sense and may be understood as equivalent to “and / or”. Throughout the disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0041] Because this disclosure allows for various modifications and several embodiments, specific embodiments will be shown in the accompanying drawings and described in detail in the specific description. The effects and features of this disclosure, as well as methods of implementing them, will be illustrated with reference to the embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments and can be embodied in various forms.

[0042] To clearly describe the embodiments, irrelevant parts of the description have been omitted, and in the description with reference to the accompanying drawings, the same or corresponding elements are indicated by the same reference numerals, and their redundant descriptions have been omitted.

[0043] While the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. In the following embodiments, the singular forms “a” and “the (described)” are intended to also include the plural forms, unless the context clearly indicates otherwise. It will be understood that when an element is referred to as “connected” to another element, the element may be “directly connected” to the other element or “indirectly connected” to the other element, with an intermediate element between them. Furthermore, it will be understood that when a unit is referred to as “comprising,” “having,” or “including,” etc., relative to another element, it may not exclude the other element but may further include it, unless there is an explicit indication to the contrary.

[0044] Figure 1 This is a schematic block diagram of an organic light-emitting display device 100 according to an embodiment.

[0045] refer to Figure 1 The organic light-emitting display device 100 may include a display section 110, a gate driver 120, a data driver 130, a timing controller 140, and a voltage generator 150.

[0046] Display portion 110 may include pixels PX (such as pixels PXij located in the i-th row and j-th column). For ease of understanding, Figure 1 The diagram only shows one pixel PXij, but m×n pixels PX can be set up as a matrix, for example. Here, i can be a natural number greater than or equal to 1 and less than or equal to m, and j can be a natural number greater than or equal to 1 and less than or equal to n.

[0047] Pixel PX can be electrically connected to the first scan lines SL1_1 to SL1_m, the second scan lines SL2_1 to SL2_m+1, the transmit control lines EML_1 to EML_m, and the data lines DL_1 to DL_n. Pixel PX can also be electrically connected to power lines (e.g., PL_j) and voltage lines (e.g., VL1_i). For example, as... Figure 1 As shown, pixel PXij can be electrically connected to the first scan line SL1_i, the second scan line SL2_i, the transmit control line EML_i, the data line DL_j, the power line PL_j, the voltage line VL1_i, and the second scan line SL2_i+1. The second scan line SL2_i+1 can be referred to as the third scan line relative to pixel PXij.

[0048] The first scan lines SL1_1 to SL1_m, the second scan lines SL2_1 to SL2_m+1, the emission control lines EML_1 to EML_m, and the voltage lines may extend in a first direction (e.g., the row direction) and be electrically connected to the pixels PX located in the same row. The data lines DL_1 to DL_n and the power lines may extend in a second direction (e.g., the column direction) and be electrically connected to the pixels PX located in the same column. Although not shown, the organic light-emitting display device 100 may further include a substrate extending in both the first and second directions, and the pixels PX may be disposed on the substrate in both directions.

[0049] The first scan lines SL1_1 to SL1_m can respectively transmit the first scan signals GW_1 to GW_m output from the gate driver 120 to the pixel PX in the same row. The second scan lines SL2_1 to SL2_m can respectively transmit the second scan signals GI_1 to GI_m output from the gate driver 120 to the pixel PX in the same row. Furthermore, the second scan lines SL2_2 to SL2_m+1 can respectively transmit the third scan signals GB_1 to GB_m output from the gate driver 120 to the pixel PX in the same row. Both the second scan signal GI_m and the third scan signal GB_m-1 can be transmitted through the second scan line SL2_m, and can actually be the same signal.

[0050] Transmit control lines EML_1 to EML_m can transmit transmit control signals EM_1 to EM_m output from gate driver 120 to pixels PX in the same row, respectively. Data lines DL_1 to DL_n can transmit data voltages D1 to Dn output from data driver 130 to pixels PX in the same column, respectively. Pixel PXij can receive first to third scan signals GW_i, GI_i, and GB_i, data voltage Dj, and transmit control signal EM_i (see, for example, [reference needed]). Figure 2 ).

[0051] The power line can transmit the first drive voltage ELVDD output from the voltage generator 150 to the pixel PX in the same column. The voltage line can transmit the initialization voltage VINT output from the voltage generator 150 to the pixel PX in the same row.

[0052] Pixel PXij may include a light-emitting element and a driving thin-film transistor (TFT) that controls the amount of driving current flowing to the light-emitting element based on the data voltage Dj. The data voltage Dj may be output from the data driver 130 and may be received by pixel PXij via the data line DL_j. The light-emitting element may be, for example, an organic light-emitting diode. Since the light-emitting element can emit light with a brightness corresponding to the amount of driving current received from the driving TFT, pixel PXij can represent a grayscale corresponding to the data voltage Dj.

[0053] Pixel PX may correspond to a portion of a unit pixel capable of displaying full color, for example, a subpixel. Pixel PXij may further include at least one switching TFT and at least one capacitor. (See reference...) Figure 2 and Figure 3 A more detailed description of pixel PXij.

[0054] Voltage generator 150 can generate the voltage required to drive pixel PXij. For example, voltage generator 150 can generate a first driving voltage ELVDD, a second driving voltage ELVSS, and an initialization voltage VINT. The level of the first driving voltage ELVDD can be higher than the level of the second driving voltage ELVSS. The level of the initialization voltage VINT can be higher than the level of the second driving voltage ELVSS. The level difference between the initialization voltage VINT and the second driving voltage ELVSS can be less than the threshold voltage required for the light-emitting element of pixel PX to emit light.

[0055] like Figure 1As shown, voltage generator 150 can generate a first gate voltage VGH and a second gate voltage VGL for controlling the switching transistor of pixel PXij, and provide the generated first gate voltage VGH and second gate voltage VGL to gate driver 120. When the first gate voltage VGH is applied to the gate of the switching transistor, the switching transistor can be turned off, and when the second gate voltage VGL is applied to the gate of the switching transistor, the switching transistor can be turned on. The first gate voltage VGH can be referred to as the gate turn-off voltage, and the second gate voltage VGL can be referred to as the gate turn-on voltage. The switching transistor of pixel PXij can be a p-type metal-oxide-semiconductor field-effect transistor (MOSFET), and the level of the first gate voltage VGH can be higher than the level of the second gate voltage VGL. Although in Figure 1 It is not shown in the figure, but voltage generator 150 can generate a gamma reference voltage and provide it to data driver 130.

[0056] The timing controller 140 can control the display section 110 by controlling the operating timing of the gate driver 120 and the data driver 130. For each frame cycle, the pixels PX of the display section 110 can receive new data voltages D1 to Dn and emit light with brightness corresponding to the data voltages D1 to Dn, thereby displaying an image corresponding to the image source data RGB of a frame.

[0057] According to an embodiment, a frame cycle may include a gate initialization period, a data writing and anode initialization period, and a light emission period. During the gate initialization period, an initialization voltage VINT may be applied to pixel PX synchronously with a second scan signal GI. During the data writing and anode initialization periods, data voltages D1 to Dn may be provided to pixel PX synchronously with a first scan signal GW, and the initialization voltage VINT may be applied to pixel PX synchronously with a third scan signal GB. During the light emission period, pixel PX of the display portion 110 may emit light.

[0058] The timing controller 140 can receive image source data RGB and control signal CONT from an external source. Based on the characteristics of the display unit 110 and pixels PX, the timing controller 140 can convert the image source data RGB into image data DATA. The timing controller 140 can then provide the image data DATA to the data driver 130.

[0059] The control signal CONT may include at least one of a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal. The timing controller 140 can use the control signal CONT to control the operating timing of the gate driver 120 and the data driver 130.

[0060] The timing controller 140 can control a horizontal scan period 1H (see...) Figure 3 The frame period is determined by counting the data enable signals. The vertical and horizontal sync signals supplied from external sources can be omitted. The image source data RGB can include luminance information for pixels PX. Luminance can have a specific number (e.g., 1024 = 2). 10 ), 256 (=2 8 ) or 64 (=2 6 ( ) grayscale values.

[0061] The timing controller 140 can generate control signals, including a gate timing control signal GDC for controlling the operating timing of the gate driver 120 and a data timing control signal DDC for controlling the operating timing of the data driver 130.

[0062] The gate timing control signal GDC may include a gate start pulse, a gate shift clock, and a gate output enable signal. The gate start pulse can be supplied to the gate driver 120, which generates a first scan signal GW at the beginning of the scan period. The gate shift clock can be a clock signal commonly input to the gate driver 120, and can also be a clock signal used to shift the gate start pulse. The gate output enable signal controls the output of the gate driver 120.

[0063] The data timing control signal (DDC) may include a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls the start point of data sampling in the data driver 130 and can be provided to the data driver 130 at the beginning of the scan period. The source sampling clock can be a clock signal that controls the sampling operation of data in the data driver 130 based on the rising or falling edge. The source output enable signal controls the output of the data driver 130. Depending on the data transmission method, the source start pulse supplied to the data driver 130 may be omitted.

[0064] The gate driver 120 can respond to the gate timing control signal GDC supplied from the timing controller 140 by using the first gate voltage VGH and the second gate voltage VGL provided from the voltage generator 150 to sequentially generate the first scan signals GW_1 to GW_m, the second scan signals GI_1 to GI_m and the third scan signals GB_1 to GB_m.

[0065] Data driver 130 can sample and latch image data DATA supplied from timing controller 140 in response to data timing control signal DDC supplied from timing controller 140, and convert the image data DATA into data in a parallel data system. In the case of converting to data in a parallel data system, data driver 130 can convert the image data DATA into a gamma reference voltage, and can also convert the gamma reference voltage into an analog data voltage. Data driver 130 provides data voltages D1 to Dn to pixel PX via data lines DL_1 to DL_n. Pixel PX can receive data voltages D1 to Dn in response to first scan signals GW_1 to GW_m.

[0066] Figure 2 This is a schematic diagram of a pixel circuit according to an embodiment.

[0067] refer to Figure 2 Pixel PXij can be electrically connected to the first to third scan lines GWL_i, GIL_i, and GBL_i for transmitting the first to third scan signals GW_i, GI_i, and GB_i respectively, the data line DL_j for transmitting the data voltage Dj, and the transmit control line EML_i for transmitting the transmit control signal EM_i. Pixel PXij can be electrically connected to the power line PL_j for transmitting the first drive voltage ELVDD and the voltage line VL_i for transmitting the initialization voltage VINT. Pixel PXij can be electrically connected to a common electrode to which a second drive voltage ELVSS can be applied. Pixel PXij can correspond to... Figure 1 The pixel PXij.

[0068] The first scan line GWL_i can correspond to Figure 1 The first scan line SL1_i and the second scan line GIL_i can correspond to Figure 1 The second scan line SL2_i, and the third scan line GBL_i can correspond to Figure 1 The second scan line SL2_i+1.

[0069] Pixel PXij may include a light-emitting element (OLED), first TFTs T1 to eighth TFTs T8, and a storage capacitor Cst. The light-emitting element OLED may be an organic light-emitting diode having an anode and a cathode. The cathode may be a common electrode that can be applied with a second driving voltage ELVSS. The storage capacitor Cst may include a first electrode and a second electrode.

[0070] The first TFT T1 can be a driving transistor in which the amount of source-drain current can be determined according to the gate-source voltage, and the second TFT T2 to the eighth TFT T8 can be switching transistors that can be turned on / off according to the gate-source voltage (e.g., essentially the gate voltage). Each of the second TFT T2 to the eighth TFT T8 can be provided as a switching transistor or as a plurality of switching transistors that can be simultaneously controlled by the same gate signal and electrically connected in series with each other.

[0071] The first TFT T1 can be called the driving TFT, the second TFT T2 can be called the scanning TFT, the third TFT T3 can be called the compensation TFT, the fourth TFT T4 can be called the gate initialization TFT, the fifth TFT T5 can be called the first emission control TFT, the sixth TFT T6 can be called the second emission control TFT, the seventh TFT T7 can be called the anode initialization TFT, and the eighth TFT T8 can be called the node connection TFT.

[0072] The driving TFT T1 can control the amount of driving current Id flowing from the power line PL_j to the light-emitting element OLED based on the gate-source voltage. The driving TFT T1 may include a gate electrically connected to the second electrode of the storage capacitor Cst, a source electrically connected to the power line PL_j via a first emission control TFT T5, and a drain electrically connected to the anode of the light-emitting element OLED via a second emission control TFT T6.

[0073] The driving TFT T1 can output a driving current Id to the light-emitting element OLED. The amount of the driving current Id can be determined based on the gate-source voltage of the driving TFT T1. The gate-source voltage of the driving TFT T1 can correspond to the difference between the gate voltage and the source voltage. For example, the amount of the driving current Id can be determined based on the difference between the gate-source voltage of the driving TFT T1 and the threshold voltage of the driving TFT T1. The light-emitting element OLED can receive the driving current Id from the driving TFT T1 and emit light with brightness according to the amount of driving current Id.

[0074] The scanning TFT T2 can receive the data voltage Dj in response to the first scan signal GW_i. The scanning TFT T2 can also transmit the data voltage Dj to the source of the driving TFT T1 in response to the first scan signal GW_i. The scanning TFT T2 may include a gate electrically connected to the first scan line GWL_i, a source electrically connected to the data line DL_j, and a drain electrically connected to the source of the driving TFT T1.

[0075] The storage capacitor Cst can be electrically connected to the gate of the driving TFT T1. The storage capacitor Cst can be electrically connected between the power line PL_j and the gate of the driving TFT T1. The storage capacitor Cst can include a first electrode electrically connected to the power line PL_j and a second electrode electrically connected to the gate of the driving TFT T1. The storage capacitor Cst can store the difference between the first driving voltage ELVDD applied to the power line PL_j and the gate voltage of the driving TFT T1, and can maintain the gate voltage of the driving TFT T1.

[0076] The storage capacitor Cst can store (e.g., essentially store) the gate-source voltage of the driving TFT T1 during the light-emitting period. However, even if the level of the first driving voltage ELVDD remains constant, the gate potential of the driving TFT T1 may change due to leakage current. For example, when leakage current flows into the gate of the driving TFT T1, the gate voltage of the driving TFT T1 can gradually increase during the light-emitting period. Therefore, the gate-source voltage of the driving TFT T1 can decrease, and the amount of the driving current Id can also decrease. The brightness of the OLED light-emitting element can be gradually reduced from the desired brightness.

[0077] The compensation TFT T3 can be electrically connected between the gate and drain of the driving TFT T1, and can be electrically connected to each other in response to the first scan signal GW_i. The compensation TFT T3 may include a first compensation TFT T3a and a second compensation TFT T3b, which can be simultaneously controlled by the first scan signal GW_i and are connected in series between the gate and drain of the driving TFT T1.

[0078] The first compensation TFT T3a may include a gate electrically connected to the first scan line GWL_i, a source electrically connected to the first floating node FN1, and a drain electrically connected to the gate of the driving TFT T1. The second compensation TFT T3b may include a gate electrically connected to the first scan line GWL_i, a source electrically connected to the drain of the driving TFT T1, and a drain electrically connected to the first floating node FN1.

[0079] When the first compensation TFT T3a and the second compensation TFT T3b are turned on in response to the first scan signal GW_i, the drain and gate of the driving TFT T1 can be electrically connected to each other, and therefore the driving TFT T1 can be diode-connected. The source of the driving TFT T1 receives the data voltage Dj in response to the first scan signal GW_i, and the data voltage Dj can be transmitted to the gate of the driving TFT T1 through the diode-connected driving TFT T1. When the gate voltage of the driving TFT T1 becomes equal to the voltage obtained by subtracting the threshold voltage of the driving TFT T1 from the data voltage Dj, the driving TFT T1 can be turned off, and the voltage obtained by subtracting the threshold voltage of the driving TFT T1 from the data voltage Dj can be stored in the storage capacitor Cst.

[0080] When the first compensation TFT T3a and the second compensation TFT T3b are turned off in response to the first scan signal GW_i, the first floating node FN1 can be floating (e.g., substantially floating). The potential of the first floating node FN1 can fluctuate due to signals around it (e.g., the first scan signal GW_i and the second scan signal GI_i). Specifically, the potential of the first floating node FN1 can be coupled to and increase at the rising edge of the first scan signal GW_i. Therefore, the source-drain voltage of the first compensation TFT T3a can increase, and the cutoff current (e.g., leakage current) of the first compensation TFT T3a can increase.

[0081] With the first compensation TFT T3a and the second compensation TFT T3b turned off, the drain and gate of the driving TFT T1 can be insulated. However, a small current can actually flow from the drain of the driving TFT T1 to the gate, which can be referred to as the cutoff current. In the case of the storage capacitor Cst, since the cutoff current may cause a change in the gate voltage of the driving TFT T1, this cutoff current can be referred to as the leakage current. In the following description, the current flowing through the turned-off first compensation TFT T3a can be referred to as the first leakage current.

[0082] The gate initialization TFT T4 can apply an initialization voltage VINT to the gate of the driving TFT T1 in response to the second scan signal GI_i. The gate initialization TFT T4 may include a first gate initialization TFT T4a and a second gate initialization TFT T4b, which can be simultaneously controlled by the second scan signal GI_i and are connected in series with each other between the gate of the driving TFT T1 and the voltage line VL_i.

[0083] The first gate initialization TFT T4a may include a gate electrically connected to the second scan line GIL_i, a source electrically connected to the gate of the driving TFT T1, and a drain electrically connected to the second floating node FN2. The second gate initialization TFT T4b may include a gate electrically connected to the second scan line GIL_i, a source electrically connected to the second floating node FN2, and a drain electrically connected to the voltage line VL_i that transmits the initialization voltage VINT.

[0084] With the first gate initialization TFT T4a and the second gate initialization TFT T4b turned off, the gate of the driving TFT T1 and the voltage line VL_i can be isolated. However, a small current can actually flow from the gate of the driving TFT T1 to the voltage line VL_i, which can be referred to as the cutoff current. In the following description, the current flowing through the turned-off first gate initialization TFT T4a can be referred to as the second leakage current.

[0085] The anode initialization TFT T7 can apply an initialization voltage VINT to the anode of the light-emitting element OLED in response to the third scan signal GB_i. The anode initialization TFT T7 may include a gate electrically connected to the third scan line GBL_i, a source electrically connected to the anode of the light-emitting element OLED, and a drain electrically connected to the voltage line VL_i.

[0086] The first emission control TFT T5 can connect the power line PL_j to the source of the driving TFT T1 in response to the emission control signal EM_i. The first emission control TFT T5 may include a gate electrically connected to the emission control line EML_i, a source electrically connected to the power line PL_j, and a drain electrically connected to the source of the driving TFT T1.

[0087] The second emission control TFT T6 can connect the drain of the driving TFT T1 to the anode of the light-emitting element OLED in response to the emission control signal EM_i. The second emission control TFT T6 may include a gate electrically connected to the emission control line EML_i, a source electrically connected to the drain of the driving TFT T1, and a drain electrically connected to the anode of the light-emitting element OLED.

[0088] The node-connected TFT T8 can connect the first floating node FN1 and the second floating node FN2 to each other in response to the second scan signal GI_i. The node-connected TFT T8 may include a gate electrically connected to the second scan line GIL_i, a source electrically connected to the first floating node FN1, and a drain electrically connected to the second floating node FN2.

[0089] The node connection TFT T8, electrically connected between the first floating node FN1 and the second floating node FN2, can reduce the increase in the potential of the first floating node FN1 caused by coupling with the rising edge of the first scan signal GW_i. Furthermore, the node connection TFT T8 can provide a path for the cutoff current from the first floating node FN1 to the second floating node FN2, thereby reducing the potential of the first floating node FN1 more quickly and reducing the cutoff current of the first compensation TFT T3a.

[0090] In the following description, the current flowing through the cut-off node connected to TFT T8 can be referred to as the third leakage current.

[0091] Figure 3 It is used for operation Figure 2 The diagram shows a schematic timing sequence of the control signals for the pixel circuit.

[0092] refer to Figure 3 as well as Figure 2 During the period when the transmit control signal EM_i is high, the first transmit control TFTT5 and the second transmit control TFTT6 can be turned off. The period when the transmit control signal EM_i is high can be referred to as the non-transmit period.

[0093] During non-emission periods, the driving TFT T1 can stop outputting the driving current Id, and the light-emitting element OLED can stop emitting light.

[0094] The second scan signal GI_i can initially be low. The period during which the second scan signal GI_i has a low-level pulse voltage can be referred to as the gate initialization period.

[0095] During the gate initialization period, the gate initialization TFT T4 can be turned on, and the initialization voltage VINT can be applied to the gate of the driving TFT T1 (e.g., the second electrode of the storage capacitor Cst). The difference between the first driving voltage ELVDD and the initialization voltage VINT (ELVDD-VINT) can be stored in the storage capacitor Cst. Furthermore, the node-connecting TFT T8 can be turned on, the first floating node FN1 and the second floating node FN2 can be electrically connected to each other, and the initialization voltage VINT can be applied to both the first floating node FN1 and the second floating node FN2.

[0096] After the second scan signal GI_i goes high again, the first scan signal GW_i can go low. The period during which the first scan signal GW_i has a low pulse voltage can be called the data writing period.

[0097] During the data writing period, scan TFT T2 and compensation TFT T3 can be turned on, and the data voltage Dj can be received at the source of drive TFT T1. Drive TFT T1 can be connected to and forward biased by a diode via compensation TFT T3. The voltage at the second electrode of storage capacitor Cst can be increased at the initialization voltage VINT. When the gate voltage of drive TFT T1 becomes equal to the voltage obtained by subtracting the threshold voltage Vth of drive TFT T1 from the data voltage Dj (Dj-|Vth|), drive TFT T1 can be turned off, and the increase of the gate voltage of drive TFT T1 can stop. Therefore, the gate voltage of drive TFT T1 becomes Dj-|Vth|, and the difference between the first drive voltage ELVDD and the gate voltage (Dj-|Vth|) (ELVDD-Dj+|Vth|) can be stored in storage capacitor Cst.

[0098] Furthermore, after the second scan signal GI_i transitions to a high level, the third scan signal GB_i can be low. The period during which the third scan signal GB_i has a low-level pulse voltage can be referred to as the anode initialization period.

[0099] During the anode initialization period, the anode initialization TFT T7 can be turned on, and the initialization voltage VINT can be applied to the anode of the OLED. By applying the initialization voltage VINT to the anode of the OLED to completely prevent it from emitting light, the phenomenon of the OLED weakly emitting light in response to the black grayscale in the next frame can be eliminated.

[0100] Subsequently, the first scan signal GW_i and the third scan signal GB_i can transition to a high level, while the transmit control signal EM_i can be at a low level. The period during which the transmit control signal EM_i is at a low level can be referred to as the emission period.

[0101] During the light-emitting period, the first emission control TFT T5 and the second emission control TFT T6 can be turned on. The driving TFT T1 outputs a driving current Id with an amount corresponding to the voltage (ELVDD-Dj) obtained by subtracting the threshold voltage (|Vth|) of the driving TFT T1 from the voltage stored in the storage capacitor Cst (e.g., the source-gate voltage (ELVDD-Dj+|Vth|) of the driving TFT T1), and the light-emitting element OLED can emit light with a brightness corresponding to the amount of driving current Id.

[0102] The second scan signal GI_i can be synchronized with the first scan signal GW_i-1 of the previous row (e.g., substantially synchronized). The third scan signal GB_i can be synchronized with the first scan signal GW_i (e.g., substantially synchronized). According to another example, the third scan signal GB_i can be synchronized with the first scan signal GW_i+1 of the next row (e.g., substantially synchronized). The difference between the timing of the second scan signal GI_i with a falling edge and the timing of the first scan signal GW_i with a falling edge can be a horizontal scan period 1H.

[0103] Figure 4 yes Figure 2 The diagram shows the voltage waveforms of each node in the pixel circuit.

[0104] refer to Figure 4 as well as Figure 2 This shows the way through Figure 2 The data signal Data transmitted via the data line DL in the middle. Figure 2 The first scan signal GW transmitted by the first scan line GWL and through Figure 2 The second scan signal GI is transmitted through the second scan line GIL.

[0105] Furthermore, the voltage waveforms of the first floating node FN1 (T3_SD), the second floating node FN2 (T4_SD), and the gate T1_G driving TFT T1 are shown. The voltage level of the data signal Data can be represented as the data voltage Vdata, and the absolute value of the threshold voltage driving TFT T1 can be simply represented as Vth.

[0106] First, the second floating node FN2 will be described. The initialization voltage VINT can be applied to the second floating node FN2 during the period when the second scan signal GI is low.

[0107] The first gate initialization TFT T4a and the second gate initialization TFT T4b can be turned off in response to the rising edge of the second scan signal GI, and the second floating node FN2 can be floating. The potential of the second floating node FN2 can be coupled to the rising edge of the second scan signal GI and increase the first level ΔVn1. The first level ΔVn1 can be changed due to the parasitic capacitance between the second floating node FN2 and the first scan line GWL, and the parasitic capacitance between the second floating node FN2 and other conductors. Subsequently, the potential of the second floating node FN2, which has increased the first level ΔVn1, can be changed according to the cutoff current of the first gate initialization TFT T4a and the second gate initialization TFT T4b. For example, as... Figure 4 As shown, the potential of the second floating node FN2 can be gradually reduced.

[0108] As described above, the initialization voltage VINT can also be applied to the gate T1_G of the driving TFT T1 during the period when the second scan signal GI is low. Furthermore, the initialization voltage VINT can also be applied to the first floating node FN1 via the node-connected TFT T8. However, as a comparative example, if the node-connected TFT T8 is not present, the initialization voltage VINT may not be applied to the first floating node FN1.

[0109] Subsequently, during the period when the first scan signal GW is at a low level, the potential of the gate T1_G of the driving TFT T1 can be increased from the initialization voltage VINT to a voltage Vdata-Vth obtained by subtracting the threshold voltage Vth from the data voltage Vdata. Since the first compensation TFT T3a and the second compensation TFT T3b can be turned on, the potential of the first floating node FN1 also increases to a voltage Vdata-Vth obtained by subtracting the threshold voltage Vth from the data voltage Vdata.

[0110] Subsequently, when the first scan signal GW has a rising edge, the first compensation TFT T3a and the second compensation TFT T3b can be turned off, and the first floating node FN1 can be floated.

[0111] The potential of the first floating node FN1 can be coupled to the rising edge of the first scan signal GW and increase the second level ΔVnw. The second level ΔVnw can be less than the first level ΔVn1. The first floating node FN1 can be capacitively coupled to the first scan line GWL and the second scan line GIL. Therefore, when the first scan signal GW has a low level, the potential of the first floating node FN1 can also be coupled to the second scan signal GI, which has a constant level, and thus the increase in the potential of the first floating node FN1 can become relatively small.

[0112] However, since the first floating node FN1 can be capacitively coupled to both the first scan line GWL and the second scan line GIL, the potential of the first floating node FN1 can also be coupled to the rising edge of the second scan signal GI, and at that moment, the third level ΔVni can be increased. However, for the same reason as the second level ΔVnw, the third level ΔVni can be less than the first level ΔVn1. However, subsequently, when the first scan signal GW has a low level, the voltage of the first floating node FN1 becomes equal to the initialization voltage VINT. Furthermore, the potential of the first floating node FN1 can be coupled to the falling edge of the first scan signal GW and decrease. Therefore, when the potential of the first floating node FN1 can be coupled to the rising edge of the second scan signal GI and the third level ΔVni increases, the operation of the pixel can be unaffected.

[0113] As a comparative example, in the absence of node connection TFT T8, the first floating node FN1 can be capacitively coupled (e.g., substantially capacitively coupled) to the first scan line GWL. The potential of the first floating node FN1 can be coupled to the rising edge of the first scan signal GW and increase the fourth level ΔVn'. The fourth level ΔVn' can be approximately similar to the first level ΔVn1 and can be greater than the second level ΔVnw, such as... Figure 4 As shown in the image.

[0114] Subsequently, the potential of the first floating node FN1, which has already increased the second level ΔVnw, can be changed based on the cutoff current of the first compensation TFT T3a, the second compensation TFT T3b, and the node-connected TFT T8. For example, as... Figure 4 As shown, the potential of the first floating node FN1 can be gradually reduced.

[0115] Since both the second scan signal GI and the first scan signal GW are at a high level, the first compensation TFT T3a and the second compensation TFT T3b, the first gate initialization TFT T4a and the second gate initialization TFT T4b, and the node connection TFT T8 can all be turned off, but a weak cutoff current may flow through them. Therefore, the voltage of the gate T1_G driving TFT T1 can be gradually increased by ΔVg.

[0116] As a comparative example, when node-connected TFT T8 is absent, since the voltage of the first floating node FN1 at the fourth level ΔVn' has been increased, the first leakage current flowing from the first floating node FN1 through the cut-off first compensation TFT T3a to the gate T1_G of the driving TFT T1 may be quite large. On the other hand, since the voltage of the second floating node FN2 at the first level ΔVn1 has been increased, the second leakage current flowing from the gate T1_G of the driving TFT T1 through the cut-off first gate initialization TFT T4a to the second floating node FN2 can be relatively small. In the comparative example, the first leakage current flowing through the cut-off first compensation TFT T3a can be greater than the second leakage current flowing through the cut-off first gate initialization TFT T4a, and the voltage of the gate T1_G of the driving TFT T1 can gradually increase ΔVg'.

[0117] According to an embodiment, the node-connected TFT T8 can provide a path for the third leakage current. The charge accumulated in the first floating node FN1 can flow out through the cutoff current of the first compensation TFT T3a or through the cutoff current of the node-connected TFT T8. Typically, the cutoff currents of the first gate initialization TFT T4a and the second gate initialization TFT T4b can flow from the gate T1_G of the driving TFT T1 to the voltage line VL_i during the light-emitting period, and therefore the voltage of the second floating node FN2 can be lower than the voltage of the gate T1_G of the driving TFT T1. Therefore, the source-drain voltage of the cutoff node-connected TFT T8 can be greater than the source-drain voltage of the cutoff first compensation TFT T3a, and therefore the cutoff current of the node-connected TFT T8 can be greater than the cutoff current of the first compensation TFT T3a. For example, since at least half of the charge accumulated in the first floating node FN1 can move through the node-connected TFT T8 to the second floating node FN2 and to the voltage line VL_i, the amount of charge moving to the gate T1_G of the driving TFT T1 through the first compensation TFT T3a can be significantly reduced compared to the comparative example. Therefore, as Figure 4 As shown, the voltage of the gate T1_G of the driving TFT T1 can be gradually increased, but at a rate lower than that in the comparative example. Therefore, the change in the amount of driving current output from the driving TFT T1 can also be reduced.

[0118] Furthermore, compared to the comparative example, the increase in potential of the first floating node FN1 due to coupling with the rising edge of the first scan signal GW can also be reduced, and therefore the amount of the first leakage current through the cut-off first compensation TFT T3a can also be reduced compared to the comparative example. Thus, the change in the amount of driving current output from the driving TFT T1 can be reduced, and the brightness change of the light-emitting element OLED can also be reduced.

[0119] Figure 5 This is a schematic diagram of a pixel circuit according to another embodiment.

[0120] refer to Figure 5 Pixel PXij can be with Figure 2 The pixel PXij is basically the same, except that the compensation TFT T3 can further include a third compensation TFT T3c.

[0121] The third compensation TFT T3c may be included in the compensation TFT T3 together with the first compensation TFT T3a and the second compensation TFT T3b. The third compensation TFT T3c may be disposed between the gate of the driving TFT T1 and the first compensation TFT T3a, and may connect the gate of the driving TFT T1 and the drain of the first compensation TFT T3a to each other in response to the first scan signal GW_i. The third compensation TFT T3c may include a gate electrically connected to the first scan line GWL_i, a source electrically connected to the drain of the first compensation TFT T3a, and a drain electrically connected to the gate of the driving TFT T1.

[0122] Figure 6 This is a schematic diagram of a pixel circuit according to another embodiment.

[0123] refer to Figure 6 Pixel PXij can be with Figure 2 The pixel PXij is basically the same, except that the compensation TFT T3 further includes a third compensation TFT T3c.

[0124] The third compensation TFT T3c may be included in the compensation TFT T3 together with the first compensation TFT T3a and the second compensation TFT T3b. The third compensation TFT T3c may be disposed between the second compensation TFT T3b and the drain of the driving TFT T1, and may connect the source of the second compensation TFT T3b and the drain of the driving TFT T1 to each other in response to the first scan signal GW_i. The third compensation TFT T3c may include a gate electrically connected to the first scan line GWL_i, a source electrically connected to the drain of the driving TFT T1, and a drain electrically connected to the source of the second compensation TFT T3b.

[0125] According to one or more embodiments, the cutoff current of the switching transistor electrically connected to the storage capacitor of the pixel can be reduced. Furthermore, by reducing the leakage current flowing to the gate of the driving transistor, the gate voltage of the driving transistor can be kept constant. Therefore, the display device according to one or more embodiments can display more vivid images.

[0126] Although this disclosure has been described with respect to limited embodiments in the specification, various embodiments are possible within the scope of this disclosure. Furthermore, although not shown, equivalent means may be incorporated into this disclosure as is. Therefore, the true scope of protection of this disclosure should be defined by the foregoing claims (including their equivalents).

[0127] It should be understood that the embodiments described herein should be considered for descriptive purposes only and not for limiting purposes. The description of features or aspects in each embodiment should typically be considered as applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various modifications in form and detail may be made thereto without departing from the spirit and scope as defined by the appended claims (including their equivalents).

Claims

1. A pixel, comprising: Light-emitting elements; The driving transistor controls the amount of driving current flowing to the light-emitting element based on the gate-source voltage; A storage capacitor is electrically connected to the gate of the driving transistor; A scanning transistor, in response to a first scanning signal, transmits a data voltage to the source of the driving transistor; The first compensation transistor and the second compensation transistor operate in response to the first scan signal, and the first compensation transistor and the second compensation transistor are connected in series between the gate and the drain of the driving transistor. A first gate initialization transistor and a second gate initialization transistor operate in response to a second scan signal. The first gate initialization transistor and the second gate initialization transistor are connected in series and electrically connected between a voltage line and the gate of the driving transistor. The voltage line transmits an initialization voltage. as well as A node-connecting transistor connects a first floating node and a second floating node to each other in response to a second scan signal. The first floating node is located between the first compensation transistor and the second compensation transistor, and the second floating node is located between the first gate initialization transistor and the second gate initialization transistor.

2. The pixel according to claim 1, wherein, The node-connecting transistor is turned off in response to the rising edge of the second scan signal. The first compensation transistor and the second compensation transistor are turned off in response to the rising edge of the first scan signal, and The potential of the first floating node is coupled to the rising edge of the second scan signal at the time point when the node connection transistor is turned off, causing the potential of the first floating node to increase, and is coupled to the rising edge of the first scan signal at the time points when the first compensation transistor and the second compensation transistor are turned off, causing the potential of the first floating node to increase.

3. The pixel according to claim 2, wherein, The first gate initialization transistor and the second gate initialization transistor are turned off in response to the rising edge of the second scan signal, and The potential of the second floating node is coupled to the rising edge of the second scan signal at the time point when the first gate initialization transistor and the second gate initialization transistor are turned off, causing the potential of the second floating node to increase.

4. The pixel according to claim 3, wherein, The increase in potential of the first floating node caused by coupling with the rising edge of the first scan signal at the time point when the first compensation transistor and the second compensation transistor are turned off is less than the increase in potential of the second floating node caused by coupling with the rising edge of the second scan signal at the time point when the first gate initialization transistor and the second gate initialization transistor are turned off.

5. The pixel according to claim 1, wherein, When both the node-connecting transistor and the first compensation transistor are turned off, the cutoff current flowing from the first floating node through the node-connecting transistor to the second floating node is greater than the cutoff current flowing from the first floating node through the first compensation transistor to the gate of the driving transistor.

6. The pixel according to claim 1, wherein, Within a frame period, after the first gate initialization transistor, the second gate initialization transistor, and the node connection transistor are turned on in response to the second scan signal with a pulse voltage having an on-level, the scan transistor, the first compensation transistor, and the second compensation transistor are turned on in response to the first scan signal with a pulse voltage having an on-level.

7. The pixel according to claim 1, further comprising: An anode initialization transistor that applies the initialization voltage to the anode of the light-emitting element in response to a third scan signal.

8. The pixel according to claim 7, wherein, The third scan signal is synchronized with the first scan signal.

9. The pixel according to claim 7, further comprising: A first emitter control transistor that connects a power line to the source of the drive transistor in response to an emitter control signal, the power line transmitting a drive voltage; as well as A second emission control transistor that connects the drain of the driving transistor to the anode of the light-emitting element in response to the emission control signal.

10. The pixel according to claim 9, wherein, The storage capacitor is electrically connected between the power line and the gate of the driving transistor.

11. The pixel of claim 1, further comprising: In response to the first scan signal, the gate of the driving transistor is connected to the third compensation transistor of the first compensation transistor.

12. The pixel of claim 1, further comprising: A third compensation transistor that connects the second compensation transistor to the drain of the driving transistor in response to the first scan signal.

13. A pixel electrically connected to a first scan line to a third scan line that transmits a first scan signal to a third scan signal, a transmit control line that transmits a transmit control signal, a data line that transmits a data voltage, a power line that transmits a drive voltage, and a voltage line that transmits an initialization voltage, the pixel comprising: Light-emitting elements, including anodes and cathodes; A storage capacitor including a first electrode and a second electrode, wherein the first electrode is electrically connected to the power line; The first transistor includes a gate electrically connected to the second electrode of the storage capacitor, a source electrically connected to the power line, and a drain. The second transistor includes a gate electrically connected to the first scan line, a source electrically connected to the data line, and a drain electrically connected to the source of the first transistor. The third transistor includes a first compensation transistor and a second compensation transistor. The first compensation transistor includes a gate electrically connected to the first scan line, a source electrically connected to the first floating node, and a drain electrically connected to the gate of the first transistor. The second compensation transistor includes a gate electrically connected to the first scan line, a source electrically connected to the drain of the first transistor, and a drain electrically connected to the first floating node. The fourth transistor includes a first gate initialization transistor and a second gate initialization transistor. The first gate initialization transistor includes a gate electrically connected to the second scan line, a source electrically connected to the gate of the first transistor, and a drain electrically connected to the second floating node. The second gate initialization transistor includes a gate electrically connected to the second scan line, a source electrically connected to the second floating node, and a drain electrically connected to the voltage line. The fifth transistor includes a gate electrically connected to the emitter control line, a source electrically connected to the power line, and a drain electrically connected to the source of the first transistor; The sixth transistor includes a gate electrically connected to the emission control line, a source electrically connected to the drain of the first transistor, and a drain electrically connected to the anode of the light-emitting element; The seventh transistor includes a gate electrically connected to the third scan line, a source electrically connected to the anode of the light-emitting element, and a drain electrically connected to the voltage line; as well as The eighth transistor includes a gate electrically connected to the second scan line, a source electrically connected to the first floating node, and a drain electrically connected to the second floating node.

14. The pixel according to claim 13, wherein, The eighth transistor is turned off in response to the rising edge of the second scan signal. The first compensation transistor and the second compensation transistor are turned off in response to the rising edge of the first scan signal, and The potential of the first floating node is coupled to the rising edge of the second scan signal at the time point when the eighth transistor is turned off, causing the potential of the first floating node to increase, and is coupled to the rising edge of the first scan signal at the time points when the first compensation transistor and the second compensation transistor are turned off, causing the potential of the first floating node to increase.

15. The pixel according to claim 14, wherein, The first gate initialization transistor and the second gate initialization transistor are turned off in response to the rising edge of the second scan signal, and The potential of the second floating node is coupled to the rising edge of the second scan signal at the time point when the first gate initialization transistor and the second gate initialization transistor are turned off, causing the potential of the second floating node to increase.

16. The pixel according to claim 15, wherein, The increase in potential of the first floating node caused by coupling with the rising edge of the first scan signal at the time point when the first compensation transistor and the second compensation transistor are turned off is less than the increase in potential of the second floating node caused by coupling with the rising edge of the second scan signal at the time point when the first gate initialization transistor and the second gate initialization transistor are turned off.

17. The pixel according to claim 13, wherein, When both the eighth transistor and the first compensation transistor are turned off, the cutoff current flowing from the first floating node through the eighth transistor to the second floating node is greater than the cutoff current flowing from the first floating node through the first compensation transistor to the gate of the first transistor.

18. A display device, comprising: A substrate extending in a first direction and a second direction; A first scan line and a second scan line that respectively transmit a first scan signal and a second scan signal, the first scan line and the second scan line extending in the first direction; A data line for transmitting data voltage, the data line extending in the second direction; Electric power lines that transmit driving voltage; A voltage line for transmitting initialization voltage, the voltage line extending in the first direction; as well as Pixels disposed on the substrate in the first direction and the second direction. Each of the pixels includes: Light-emitting elements; The driving transistor controls the amount of driving current flowing from the power line to the light-emitting element based on the gate-source voltage; A storage capacitor electrically connected to the gate of the driving transistor; A scan transistor that transmits the data voltage to the source of the driving transistor in response to the first scan signal; A first compensation transistor and a second compensation transistor that operate in response to the first scan signal, the first compensation transistor and the second compensation transistor being connected in series between the gate and drain of the driving transistor; A first gate initialization transistor and a second gate initialization transistor, which operate in response to the second scan signal, are connected in series and electrically connected between the gate of the driving transistor and the voltage line; and A node connection transistor that connects a first floating node to a second floating node in response to a second scan signal, the first floating node being between a first compensation transistor and a second compensation transistor, and the second floating node being between a first gate initialization transistor and a second gate initialization transistor.

19. The display device according to claim 18, wherein, The potential of the first floating node is coupled to the rising edge of the second scan signal at the time point when the node connection transistor is turned off, causing the potential of the first floating node to increase by a first level, and coupled to the rising edge of the first scan signal at the time points when the first compensation transistor and the second compensation transistor are turned off, causing the potential of the first floating node to increase by a second level. The potential of the second floating node is coupled to the rising edge of the second scan signal at the time point when the first gate initialization transistor and the second gate initialization transistor are turned off, such that the potential of the second floating node increases to a level greater than the third level of the second level.

20. The display device according to claim 18, wherein, When both the node-connecting transistor and the first compensation transistor are turned off, the cutoff current flowing from the first floating node through the node-connecting transistor to the second floating node is greater than the cutoff current flowing from the first floating node through the first compensation transistor to the gate of the driving transistor.

Images