Display device

Abstract

A display device includes a display panel including a first surface and a second surface, wherein a display area displaying an image is arranged on the first surface; a driving panel arranged on the display panel and including a first surface and a second surface; and a filling portion filled between the display panel and the driving panel. In a cross-sectional view, the display panel and the driving panel are stacked in a vertical direction, and a signal line of the display panel can be electrically connected to a signal line of the driving panel, respectively, through a contact hole passing through the display panel and the driving panel.

Description

[0001] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2020-0080501, filed on June 30, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] One or more embodiments relate to display devices. Background Technology

[0003] Typically, display devices can be used in mobile devices such as smartphones, laptops, digital cameras, portable video cameras, portable information terminals, laptops or tablet computers, or in electronic devices such as desktop computers, televisions, outdoor billboards, display devices for exhibitions, dashboards for vehicles, or head-up displays (“HUDs”).

[0004] In addition to the display area used to display images, the display device also includes a peripheral area called the dead zone, which does not directly participate in the generation of light. Signal lines or drivers can be arranged in the dead zone and can be electrically connected to components in the display area. Summary of the Invention

[0005] There is a need to reduce the area occupied by dead zones in order to obtain a display device capable of displaying full-screen images.

[0006] One or more embodiments provide a display device in which dead zones are minimized.

[0007] Additional aspects will be set forth in part in the description which follows and will be apparent in part from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0008] The display device according to aspects of this disclosure includes: a display panel including a first surface and a second surface opposite to the first surface, wherein a display area for displaying an image is disposed on the first surface; a driving panel disposed on the display panel and including the first and second surfaces, wherein the first surface of the driving panel faces the second surface of the display panel, and the second surface of the driving panel is opposite to the first surface of the driving panel; and a filling portion filling the space between the display panel and the driving panel. In a cross-sectional view, the display panel and the driving panel may be stacked vertically, and signal lines of the display panel may be electrically connected to signal lines of the driving panel respectively through contact holes passing through the display panel and the driving panel.

[0009] According to an embodiment, the contact hole may include a plurality of first contact holes and a plurality of second contact holes, wherein the plurality of first contact holes may be defined in a display panel and the plurality of second contact holes may be defined in a drive panel.

[0010] According to an embodiment, a plurality of first signal lines electrically connected to the display area can be arranged on a first surface of the display panel, a plurality of second signal lines electrically connected to the plurality of first signal lines and a driver electrically connected to the plurality of second signal lines can be arranged on a first surface of the driving panel, and an integrated circuit (“IC”) electrically connected to the driver can be arranged on a second surface of the driving panel.

[0011] According to an embodiment, a plurality of first connection portions may be arranged on a second surface of a display panel, and each of the plurality of first connection portions may be electrically connected to each of a plurality of first signal lines through each of a plurality of first contact holes. A plurality of second connection portions may be arranged on a first surface of a drive panel, and each of the plurality of second connection portions may be electrically connected to each of the plurality of first connection portions and electrically connected to each of a plurality of second signal lines.

[0012] According to an embodiment, the bump may be located between the first connecting portion and the second connecting portion.

[0013] According to an embodiment, a plurality of third signal lines can be electrically connected to a driver and arranged on a first surface of a driver panel, a plurality of fourth signal lines can be electrically connected to an IC and arranged on a second surface of a driver panel, and each of the plurality of third signal lines can be electrically connected to each of the plurality of fourth signal lines via each of a plurality of second contact holes.

[0014] According to an embodiment, a driver arranged on a drive panel can apply signals to display elements arranged in a display area.

[0015] According to an embodiment, the filling portion can be filled in the gap between the second surface of the display panel and the first surface of the driving panel.

[0016] According to an embodiment, in a plan view, the display panel may overlap with the driving panel, and the size of the driving panel is smaller than the size of the display panel.

[0017] According to an embodiment, the driving panel may include a first driving panel and a second driving panel. The first driving panel may be arranged above the display panel in a plan view, and the second driving panel may be arranged below the display panel in a plan view. Attached Figure Description

[0018] The above and other aspects, features and advantages of certain embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 This is a schematic plan view of a display device according to an embodiment;

[0020] Figure 2 yes Figure 1 The equivalent circuit diagram of the pixels in the diagram;

[0021] Figure 3 It is along Figure 1 A cross-sectional view of the display device taken by line III-III';

[0022] Figure 4A This is a plan view of the first surface of the display panel according to an embodiment;

[0023] Figure 4B yes Figure 4A A plan view of the second surface of the display panel;

[0024] Figure 5A This is a plan view of the first surface of the drive panel according to an embodiment;

[0025] Figure 5B yes Figure 5A A plan view of the second surface of the drive panel;

[0026] Figure 6 This is a plan view showing the display panel and drive panel arranged according to an embodiment;

[0027] Figure 7 It is along Figure 6 A cross-sectional view of the display panel and the drive panel taken by line VII-VII';

[0028] Figures 8A to 8E It is a diagram that sequentially illustrates the operation of manufacturing a display device according to an embodiment; and

[0029] Figure 9 and Figure 10 Each is a diagram of an electronic device including a display device according to an embodiment. Detailed Implementation

[0030] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, in which the same reference numerals consistently refer to the same elements. In this respect, present embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, embodiments are described below with reference to the accompanying drawings only to illustrate aspects of this description. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “the,” and “the” are intended to include the plural forms containing “at least one,” unless the context clearly indicates otherwise. “At least one” is not to be construed as limiting “a.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. It will be further understood that, when used in this specification, the terms “comprising” or “including” and / or variations thereof specify the presence of the described features, areas, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components and / or groups thereof.

[0031] Because this disclosure allows for various modifications and numerous embodiments, specific embodiments will be shown in the accompanying drawings and described in detail in the written description. The effects and features of this disclosure, as well as methods of implementing this disclosure, will be apparent from the embodiments and drawings described below in detail. However, this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein.

[0032] It will be understood that when a layer, region, or component is referred to as "formed on" another layer, region, or component, it can be formed directly or indirectly on that other layer, region, or component; for example, intermediate layers, regions, or components may exist. For ease of illustration, the dimensions of components in the figures may be exaggerated. In other words, since the dimensions and thicknesses of components in the figures are arbitrarily shown for ease of illustration, the following embodiments are not limited thereto.

[0033] The x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted more broadly. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0034] Although terms such as "first" and "second" can be used to describe various components, these components are not necessarily limited to these terms. The terms are only used to distinguish one component from another.

[0035] In the following embodiments, unless the meaning is obviously different in the context, the singular expression includes the plural expression.

[0036] In the following embodiments, it should be understood that terms such as “comprising” and “having” are intended to indicate the presence of features or elements disclosed in this disclosure and are not intended to exclude the possibility that one or more other features or elements may be present or added.

[0037] When an embodiment can be implemented differently, a particular process can be performed in a different order than that described. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0038] In the following description, embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings. The same reference numerals denote the same elements in the drawings, and therefore their descriptions will be omitted.

[0039] It will be understood that when a layer, region, or component is referred to as being connected to another layer, region, or component, it can be directly or indirectly connected to that other layer, region, or component. That is, for example, intermediate layers, regions, or components may exist. It will also be understood that when a layer, region, or component is referred to as being electrically connected to another layer, region, or component, it can be directly or indirectly electrically connected to that other layer, region, or component. That is, for example, intermediate layers, regions, or components may exist.

[0040] Figure 1 This is a schematic plan view of the display device 100 according to an embodiment.

[0041] See Figure 1 The display device 100 can be a device for displaying images. Although an organic light-emitting display device is described as an example of the display device 100, the display device disclosed herein is not limited thereto. As another embodiment, the display device 100 can be a display device such as an inorganic light-emitting display device or a quantum dot light-emitting display device. The emitting layer of the display element included in the display device 100 may include organic materials, inorganic materials, quantum dots, organic materials and quantum dots, or inorganic materials and quantum dots.

[0042] The display device 100 includes a display area DA on a substrate 101 and a peripheral area PA extending around the display area DA. The display device 100 can provide certain images by using light emitted from a plurality of pixels arranged in the display area DA.

[0043] The display area DA includes multiple pixels P connected to a data line DL extending in the Y direction and a scan line SL extending in the X direction, which intersects the Y direction. Each of the multiple pixels P can be connected to a drive voltage line PL extending in the Y direction.

[0044] Each of the plurality of pixels P may include a display element such as an organic light-emitting diode (“OLED”). Each of the plurality of pixels P may emit red, green, blue, or white light. As another embodiment, all the OLEDs included in the plurality of pixels P may emit light of the same color, and the color of each of the plurality of pixels P may be implemented by a color filter or color conversion layer, etc., arranged on top of the OLED in a cross-sectional view.

[0045] Figure 2 yes Figure 1 The equivalent circuit diagram of pixel P in the diagram.

[0046] See Figure 2 Each pixel P includes a pixel circuit PC connected to the scan line SL and the data line DL, and an organic light-emitting diode (OLED) connected to the pixel circuit PC.

[0047] The pixel circuit PC includes a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. The switching thin-film transistor T2 is connected to the scan line SL and the data line DL, and is configured to transmit the data signal Dm input through the data line DL to the driving thin-film transistor T1 according to the scan signal Sn input through the scan line SL.

[0048] The storage capacitor Cst is connected to the switching thin-film transistor T2 and the drive voltage line PL, and stores a voltage corresponding to the difference between the voltage received from the switching thin-film transistor T2 and the first power supply voltage ELVDD (or drive voltage) supplied to the drive voltage line PL.

[0049] The driving thin-film transistor T1 can be connected to the driving voltage line PL and the storage capacitor Cst, and the driving current flowing from the driving voltage line PL to the organic light-emitting diode (OLED) can be controlled according to the voltage value stored in the storage capacitor Cst. The OLED can then emit light with a certain brightness based on the driving current.

[0050] Figure 2 The pixel circuit PC shown includes two thin-film transistors and one storage capacitor, but the number of thin-film transistors and storage capacitors and the circuit design according to the present invention are not limited thereto, and the number of thin-film transistors and storage capacitors and the circuit design can be varied.

[0051] Figure 3 It is along Figure 1 The cross-sectional view of the display device 100 taken by line III-III'.

[0052] See Figure 3The display elements can be arranged on the substrate 301. The display elements may include thin-film transistors (TFTs) and organic light-emitting diodes (OLEDs).

[0053] Substrate 301 may comprise glass or polymer resin. The polymer resin may comprise polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate, etc. Substrate 301 may comprise a single layer or multiple layers, and in the case of a multilayer structure, may further comprise an inorganic layer (not shown). Substrate 301 may be flexible, rollable, or bendable.

[0054] A buffer layer 302 may be disposed on a substrate 301. The buffer layer 302 may reduce or prevent the penetration of foreign matter, moisture, or outside air, and may provide a flat surface on the substrate 301. The buffer layer 302 may comprise inorganic materials, organic materials, or organic-inorganic composites, such as oxides or nitrides. The buffer layer 302 may comprise a single layer or multiple layers of inorganic and organic materials.

[0055] The thin-film transistor (TFT) can be disposed on the buffer layer 302. The TFT may include a semiconductor layer 334, a gate electrode 336 overlapping the semiconductor layer 334 in a planar view, and a source electrode 337 and a drain electrode 338 electrically connected to the semiconductor layer 334. The TFT can be connected to and drive an organic light-emitting diode (OLED).

[0056] Semiconductor layer 334 may be disposed on buffer layer 302 and may include a channel region 331 overlapping with gate electrode 336 in a planar view, as well as a source region 332 and a drain region 333. Source region 332 and drain region 333 are disposed on opposite sides of channel region 331 and include impurities with a higher concentration than those in channel region 331. Impurities may include N-type or P-type impurities. Source region 332 and drain region 333 may be electrically connected to source electrode 337 and drain electrode 338, respectively.

[0057] Semiconductor layer 334 may comprise an oxide semiconductor or a silicon semiconductor. When semiconductor layer 334 comprises an oxide semiconductor, it may comprise an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). For example, semiconductor layer 334 may comprise indium tin zinc oxide (“ITZO”; InSnZnO) or indium gallium zinc oxide (“IGZO”; InGaZnO), etc. When semiconductor layer 334 comprises a silicon semiconductor, it may comprise amorphous silicon (a-Si) or low-temperature polycrystalline silicon (“LTPS”) in which a-Si is crystallized.

[0058] The first gate insulating layer 303 may be disposed on the semiconductor layer 334. The first gate insulating layer 303 may comprise materials including silicon oxide (SiO2) and silicon nitride (SiN). x The first gate insulating layer 303 may comprise at least one inorganic insulating material selected from the group consisting of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO).

[0059] The gate electrode 336 may be disposed on the first gate insulating layer 303. The gate electrode 336 may comprise at least one metal selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may comprise a single layer or multiple layers. The gate electrode 336 may be connected to a gate line.

[0060] The second gate insulating layer 305 can be disposed on the gate electrode 336. The second gate insulating layer 305 may include materials such as silicon oxide (SiO2) and silicon nitride (SiN). x The second gate insulating layer 305 may comprise at least one inorganic insulating material selected from the group consisting of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO).

[0061] The storage capacitor Cst can be disposed on the second gate insulating layer 305. The storage capacitor Cst may include a lower electrode 344 and an upper electrode 346 that overlaps with the lower electrode 344 in a plan view. The lower electrode 344 of the storage capacitor Cst can be connected to the gate electrode 336 of the thin-film transistor TFT and can be disposed integrally. As another embodiment, the storage capacitor Cst may not overlap with the thin-film transistor TFT in a plan view, and the lower electrode 344 of the storage capacitor Cst may be a separate component separate from the gate electrode 336 of the thin-film transistor TFT.

[0062] The upper electrode 346 of the storage capacitor Cst may include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W and / or Cu, and may include a single layer or multiple layers.

[0063] An interlayer insulating layer 307 can be disposed on the upper electrode 346 of the storage capacitor Cst. The interlayer insulating layer 307 may comprise materials including silicon oxide (SiO2) and silicon nitride (SiN). x The interlayer insulation layer 307 may comprise at least one inorganic insulating material selected from the group consisting of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO).

[0064] The data line DL, the lower drive voltage line PL1, the source electrode 337, and the drain electrode 338 can be disposed on the interlayer insulating layer 307. The data line DL, the lower drive voltage line PL1, the source electrode 337, and the drain electrode 338 can include conductive materials comprising Mo, Al, Cu, or Ti, and can comprise a single layer or multiple layers. The data line DL, the lower drive voltage line PL1, the source electrode 337, and the drain electrode 338 can comprise multiple layers of Ti / Al / Ti. As an embodiment, the data line DL, the lower drive voltage line PL1, the source electrode 337, and the drain electrode 338 can comprise the same material.

[0065] The data cable DL can be electrically connected to the data drive circuit. Data signals from the data drive circuit can be provided to pixel P via the data cable DL. Although not in... Figure 3 As shown, however, the scan lines electrically connected to the scan driving circuit can be arranged above the first gate insulating layer 303 or the second gate insulating layer 305, and the emission control lines electrically connected to the emission driving circuit can be arranged above the first gate insulating layer 303 or the second gate insulating layer 305. The scan signal of the scan driving circuit can be provided to the pixel P via the scan lines, and the emission control signal of the emission driving circuit can be provided to the pixel P via the emission control lines.

[0066] The first planarization layer 311 may be disposed on the data line DL, the lower drive voltage line PL1, the source electrode 337, and the drain electrode 338. The first planarization layer 311 may comprise a single layer or multiple layers of a film containing organic or inorganic materials. As an example, the first planarization layer 311 may comprise benzocyclobutene (“BCB”), polyimide (“PI”), hexamethyldisiloxane (“HMDSO”), a general commercial polymer such as polymethyl methacrylate (“PMMA”) or polystyrene (“PS”), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoropolymer, a p-xylene polymer, a vinyl alcohol polymer, or a mixture thereof.

[0067] The first planarization layer 311 may include silicon oxide (SiO2) and silicon nitride (SiN). x Materials such as silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO) can be used. After forming the first planarization layer 311, chemical and mechanical polishing operations can be performed on the first planarization layer 311 to provide a flat top surface.

[0068] The upper driving voltage line PL2 and the contact metal layer CM can be disposed on the first planarization layer 311. The upper driving voltage line PL2 and the contact metal layer CM can include Al, Cu, or Ti, and can include multiple layers or a single layer. The upper driving voltage line PL2 and the contact metal layer CM can include multiple layers of Ti / Al / Ti. As an embodiment, the upper driving voltage line PL2 and the contact metal layer CM can include the same material.

[0069] The upper drive voltage line PL2 can be electrically connected to the lower drive voltage line PL1 through a contact hole passing through the first planarization layer 311 to prevent voltage drop of the drive voltage supplied through the drive voltage line. Here, in the cross-sectional view, the upper drive voltage line PL2 is located above the lower drive voltage line PL1.

[0070] The contact metal layer CM can be electrically connected to the thin-film transistor TFT through a contact hole passing through the first planarization layer 311, and the pixel electrode 310 can be electrically connected to the contact metal layer CM through a contact hole passing through the second planarization layer 313.

[0071] The second planarization layer 313 may be disposed on the upper driving voltage line PL2 and the contact metal layer CM. The second planarization layer 313 may comprise a single layer or multiple layers of a film containing organic or inorganic materials. As an example, the second planarization layer 313 may comprise BCB, PI, HMDSO, general commercial polymers such as PMMA or PS, polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoropolymers, p-xylene polymers, vinyl alcohol polymers, or mixtures thereof.

[0072] The second planarization layer 313 may include silicon oxide (SiO2) or silicon nitride (SiN). x Materials such as silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO) can be used. After forming the second planarization layer 313, chemical and mechanical polishing operations can be performed on the second planarization layer 313 to provide a flat top surface.

[0073] An organic light-emitting diode (OLED) comprising a pixel electrode 310, an intermediate layer 320, and a counter electrode 330 can be disposed on a second planarization layer 313. The pixel electrode 310 can be electrically connected to a contact metal layer CM through contact holes passing through the second planarization layer 313, and the contact metal layer CM can be electrically connected to the drain electrode 338 of a thin-film transistor (TFT) through contact holes passing through the first planarization layer 311. Therefore, the organic light-emitting diode (OLED) can be electrically connected to the thin-film transistor (TFT).

[0074] Pixel electrode 310 may be disposed on second planarization layer 313. Pixel electrode 310 may include a (semi-)transparent electrode or a reflective electrode. Pixel electrode 310 may include a reflective film and a transparent or semi-transparent electrode layer formed above the reflective film, the reflective film including Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, Cu, or compounds thereof. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (“IGO”), and zinc aluminum oxide (“AZO”). Pixel electrode 310 may include ITO / Ag / ITO.

[0075] A pixel defining film 380 may be disposed on a second planarization layer 313, and the pixel defining film 380 may have an opening that exposes at least a portion of the pixel electrode 310. The area exposed by the opening of the pixel defining film 380 may be defined as an emission region EA. The periphery of the emission region EA may be a non-emission region NEA, and the non-emission region NEA may surround the emission region EA. Specifically, the display region DA may include multiple emission regions EA and non-emission regions NEA surrounding the multiple emission regions EA. The pixel defining film 380 may prevent arcing or the like at the edge of the pixel electrode 310 by increasing the distance between the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310. The pixel defining film 380 may include an organic insulating material, such as polyimide, polyamide, acrylic resin, BCB, HMDSO, or phenolic resin, and may be formed by spin coating or the like.

[0076] The intermediate layer 320 may be disposed on the pixel electrode 310, which is at least partially exposed by the pixel defining film 380. The intermediate layer 320 may include an emission layer 320b, and a first functional layer 320a and a second functional layer 320c may be selectively disposed on and below the emission layer 320b.

[0077] The first functional layer 320a may include a hole injection layer (“HIL”) and / or a hole transport layer (“HTL”), and the second functional layer 320c may include an electron transport layer (“ETL”) and / or an electron injection layer (“EIL”).

[0078] The emitter layer 320b may include low molecular weight organic materials or polymeric organic materials.

[0079] When the emitter layer 320b comprises a low molecular weight organic material, the intermediate layer 320 may include a structure in which HIL, HTL, emitter layer, ETL or EIL are stacked in a single or composite structure.

[0080] Low molecular weight organic materials can include a variety of organic materials, such as copper phthalocyanine (CuPc), N,N'-bis(naphthyl-1-yl)-N,N'-biphenyl-benzidine, or tri-8-hydroxyquinoline aluminum (Alq3). These layers can be formed by vacuum deposition.

[0081] When the emitter layer 320b comprises a polymeric organic material, the intermediate layer 320 may comprise a structure including an HTL and an emitter layer. In this case, the HTL may comprise poly(3,4-ethylenedioxythiophene) (“PEDOT”), and the emitter layer may comprise a polymeric material, such as poly(p-phenylenevinylene) (“PPV”) or polyfluorene. The emitter layer may be formed by screen printing, inkjet printing, or laser-induced thermal imaging (“LITI”) methods.

[0082] Counter electrode 330 can be disposed on intermediate layer 320. Counter electrode 330 can cover intermediate layer 320. As an embodiment, counter electrode 330 can be disposed above display area DA and can cover display area DA. Counter electrode 330 can be formed as a single unit on the entire panel by using an open mask to cover multiple pixels P disposed in display area DA.

[0083] The counter electrode 330 may include a conductive material with a low work function. For example, the counter electrode 330 may include a (semi-)transparent layer, which may include Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or alloys thereof. The counter electrode 330 may further include a layer such as ITO, IZO, ZnO, or In2O3 above the (semi-)transparent layer comprising the above-mentioned materials.

[0084] An organic light-emitting diode (OLED) can be covered by a thin-film encapsulation layer 340. The thin-film encapsulation layer 340 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. As an embodiment, the thin-film encapsulation layer 340 may include a first inorganic encapsulation layer 350, a second inorganic encapsulation layer 370, and an organic encapsulation layer 360 disposed between the first inorganic encapsulation layer 350 and the second inorganic encapsulation layer 370.

[0085] Each of the first inorganic encapsulation layer 350 and the second inorganic encapsulation layer 370 may include one or more inorganic insulating materials. The inorganic insulating materials may include alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride. The organic encapsulation layer 360 may include polymeric materials. Polymeric materials may include acrylic resins, epoxy resins, polyimide, or polyethylene, etc. For example, the organic encapsulation layer 360 may include acrylic resins, PMMA, or polyacrylic acid, etc.

[0086] The display device 100 includes a display panel 400 (in which...) Figure 4A and Figure 4B (shown in) and drive panel 500 (in Figure 5A and Figure 5B (As shown in the diagram). The driving panel 500 can be arranged above the display panel 400 in a plan view (i.e., in the Z direction). The display panel 400 and the driving panel 500 can be separated from each other in the vertical direction (i.e., the Z direction). External circuitry such as data drivers, scan drivers, and control drivers can be arranged on the driving panel 500, wherein the external circuitry is connected to signal lines such as data lines DL, scan lines SL, or transmit control lines, and the signal lines are electrically connected to display elements arranged in the display area DA.

[0087] According to an embodiment, Figure 4AThis is a plan view of the first surface 410 of the display panel 400, and Figure 4B yes Figure 4A A plan view of the second surface 420 of the display panel 400.

[0088] See Figure 4A A display area DA for displaying an image can be arranged on a first surface 410 of the display panel 400, and a peripheral area PA can be arranged around the display area DA. The peripheral area PA can surround the display area DA. The display panel 400 includes... Figure 3 The structure shown is a combination of substrate 301 and thin film encapsulation layer 340. Figure 3 The display elements can be arranged in the display area DA.

[0089] Multiple first signal lines 430 can be arranged in the upper and lower parts of the peripheral region PA outside the display area DA. Specifically, in the X direction of the display panel 400, multiple first upper signal lines 431 can be arranged in the upper peripheral region 411, and multiple first lower signal lines 432 can be arranged in the lower peripheral region 412. The multiple first upper signal lines 431 and the multiple first lower signal lines 432 can transmit electrical signals to the display element arranged in the display area DA. The multiple first upper signal lines 431 and the multiple first lower signal lines 432 can alternately transmit signals to the display area DA. As another embodiment, one of the multiple first upper signal lines 431 and the multiple first lower signal lines 432 can be arranged in one of the upper peripheral region 411 and the lower peripheral region 412.

[0090] See Figure 4B The second surface 420 of the display panel 400 may be a surface opposite to the first surface 410 of the display panel 400 in the thickness direction (i.e., the Z direction). Here, in the cross-sectional view (see...) Figure 7 The first surface 410 may be the lower surface of the display panel 400, and the second surface 420 may be the upper surface of the display panel 400. A plurality of first connection portions 440 electrically connected to a plurality of first signal lines 430 may be arranged on the second surface 420 of the display panel 400. Specifically, in the X direction of the display panel 400, a plurality of first upper connection portions 441 may be arranged in the upper peripheral region 421, and a plurality of first lower connection portions 442 may be arranged in the lower peripheral region 422. The plurality of first upper connection portions 441 may be arranged at positions corresponding to the plurality of first upper signal lines 431, and the plurality of first lower connection portions 442 may be arranged at positions corresponding to the plurality of first lower signal lines 432.

[0091] Each of the plurality of first upper signal lines 431 can pass through a first contact hole in the display panel 400 in the thickness direction (i.e., the Z direction). Figure 7 The first signal line 430 is electrically connected to each of the plurality of first upper connection portions 441 via the first contact hole 490. Each of the plurality of first lower signal lines 432 can be electrically connected to each of the plurality of first lower connection portions 442 via the first contact hole 490. Conductive material can be filled in the first contact hole 490 to electrically connect the first signal line 430 to the first connection portion 440.

[0092] According to an embodiment, Figure 5A This is a plan view of the first surface of the drive panel 500, and Figure 5B yes Figure 5A A plan view of the second surface of the drive panel 500.

[0093] See Figure 5A The driving panel 500 may include a first driving panel 500a and a second driving panel 500b. The first driving panel 500a and the second driving panel 500b may be panels having substantially the same structure. The first driving panel 500a may be arranged on the upper part of the display panel 400, and the second driving panel 500b may be arranged on the lower part of the display panel 400. Figures 4A to 5B The parts or elements shown, designated as "above" or "below," describe their relative positions in the plan view (i.e., "above" means it is located in the +Y direction from the center, and "below" means it is located in the -Y direction from the center), and Figure 3 and Figure 7 The components or elements shown, designated as "upper" or "lower," describe their relative positions in the cross-sectional view (i.e., "upper" means it is located in the +Z direction from the center, and "lower" means it is located in the -Z direction from the center). As another embodiment, one of a first drive panel 500a and a second drive panel 500b may be provided.

[0094] The first surface 510a of the first driving panel 500a may face the second surface 420 of the display panel 400. Multiple second upper signal lines 531 may be arranged on the first surface 510a of the first driving panel 500a and electrically connected to the multiple first upper signal lines 431 (see [link to documentation]). Figure 7 Multiple second upper signal lines 531 can be electrically connected to the upper driver 501. The multiple second upper signal lines 531 can have a fan-out shape.

[0095] A plurality of second upper connection portions 541 may be arranged on a first surface 510a of a first drive panel 500a. Each of the plurality of second upper connection portions 541 may be electrically connected to each of a plurality of second upper signal lines 531. The plurality of second upper connection portions 541 may be arranged at positions corresponding to the plurality of first upper connection portions 441. Each of the plurality of first upper connection portions 441 may be connected via a bump ( Figure 7 710) is electrically connected to each of the plurality of second upper connection portions 541. A plurality of third upper signal lines 551 may be arranged on the first surface 510a of the first drive panel 500a and electrically connected to the upper driver 501.

[0096] Multiple second lower signal lines 532 can be arranged on the first surface 510b of the second drive panel 500b and electrically connected to multiple first lower signal lines 432. Multiple second lower signal lines 532 can be electrically connected to the lower driver 502. Multiple second lower signal lines 532 can have a fan-out shape.

[0097] A plurality of second lower connection portions 542 may be arranged on a first surface 510b of a second drive panel 500b. Each of the plurality of second lower connection portions 542 may be connected to each of a plurality of second lower signal lines 532. The plurality of second lower connection portions 542 may be arranged at positions corresponding to a plurality of first lower connection portions 442. Each of the plurality of first lower connection portions 442 may be electrically connected to each of the plurality of second lower connection portions 542 via a bump 710. Each of a plurality of third lower signal lines 552 may be arranged on the first surface 510b of the second drive panel 500b and electrically connected to a lower driver 502.

[0098] See Figure 5B The second surface 520a of the first drive panel 500a may be the surface opposite to the first surface 510a of the first drive panel 500a in the thickness direction. Here, in the cross-sectional view (see...) Figure 7 The first surface 510a can be the lower surface of the first driving panel 500a, and the second surface 520a can be the upper surface of the first driving panel 500a.

[0099] Multiple fourth upper signal lines 571 can be arranged on the second surface 520a of the first drive panel 500a and electrically connected to multiple third upper signal lines 551. Each of the multiple third upper signal lines 551 can pass through a second contact hole in the thickness direction of the first drive panel 500a. Figure 7590) is electrically connected to each of the plurality of fourth upper signal lines 571. The plurality of fourth upper signal lines 571 may be electrically connected to an upper integrated circuit (IC) 561. The upper IC 561 may be electrically connected to a plurality of external upper signal lines 581, and the plurality of external upper signal lines 581 are electrically connected to terminals on an external circuit board.

[0100] Multiple fourth lower signal lines 572 can be arranged on the second surface 520b of the second drive panel 500b and electrically connected to multiple third lower signal lines 552. Each of the multiple third lower signal lines 552 can be electrically connected to each of the multiple fourth lower signal lines 572 through a second contact hole 590 passing through the second drive panel 500b in the thickness direction. The multiple fourth lower signal lines 572 can be electrically connected to a lower IC 562. The lower IC 562 can be electrically connected to multiple external lower signal lines 582, and the multiple external lower signal lines 582 are electrically connected to terminals on an external circuit board.

[0101] Thus, the upper driver 501 can be arranged on the first surface 510a of the first driving panel 500a, and the lower driver 502 can be arranged on the first surface 510b of the second driving panel 500b. More specifically, the upper driver 501 and the lower driver 502 may not be arranged on the display panel 400, but rather on the first driving panel 500a and the second driving panel 500b, which are separate from the display panel 400. Electrical signals can be transmitted to the display element arranged in the display area DA via multiple signal lines respectively arranged on the two surfaces of the display panel 400 and the two surfaces of the driving panel 500.

[0102] In an embodiment, for example, the upper driver 501 and / or the lower driver 502 may be a data driving circuit and may be electrically connected to the data line DL. The data signal of the data driving circuit can be provided to the pixel P through the data line DL.

[0103] As an example, the upper driver 501 and / or the lower driver 502 may be a scan drive circuit and may be electrically connected to the scan line SL. The scan signal of the scan drive circuit can be provided to the pixel P through the scan line SL.

[0104] As an example, the upper driver 501 and / or the lower driver 502 may be a transmission drive circuit and may be electrically connected to the transmission control line. The transmission control signal of the transmission drive circuit can be provided to pixel P through the transmission control line.

[0105] As an example, the upper driver 501 and / or the lower driver 502 may be a switching circuit. The switching circuit may demultiplex (i.e., de-multiplex) the data signal output from the data driving circuit and supply the demultiplexed data signal to the data line DL.

[0106] Figure 6 This is a plan view showing the display panel 400 and the drive panel 500 arranged according to an embodiment.

[0107] See Figure 6 The driver panel 500 can be arranged on the display panel 400. The display panel 400 and the driver panel 500 can be arranged separately and overlap each other in the plan view.

[0108] In the plan view, the size (i.e., area) of each of the first driving panel 500a and the second driving panel 500b can be smaller than the size (i.e., area) of the display panel 400. Thus, the first driving panel 500a can be arranged above the display panel 400 in the X direction. The second driving panel 500b can be arranged below the display panel 400 in the X direction.

[0109] In an embodiment, for example, the width Wp of the display panel 400 in the Y direction may be greater than the width Wd1 of the first driving panel 500a or the width Wd2 of the second driving panel 500b. Additionally, in the Y direction, the width Wp of the display panel 400 may be greater than the sum of the widths Wd1 of the first driving panel 500a and Wd2 of the second driving panel 500b. On the other hand, the length Lp of the display panel 400 in the X direction may be the same as the length Ld1 of the first driving panel 500a or the length Ld2 of the second driving panel 500b. The dimensions of either the driving panel 500 or the display panel 400 are not limited to any specific value, provided that the size (i.e., area) of the driving panel 500 is smaller than the size (i.e., area) of the display panel 400 in the plan view and is arranged within the area in which the display panel 400 is arranged.

[0110] Figure 7 It is along Figure 6 The cross-sectional view of the display panel 400 and the drive panel 500 taken by line VII-VII'.

[0111] Here, although in Figure 7 The diagram shows a structure in which the display panel 400 and the first driving panel 500a are coupled, but the structure in which the display panel 400 and the second driving panel 500b are coupled can be substantially the same. Therefore, its description will be omitted.

[0112] See Figure 7 As mentioned above, the display panel 400 and the drive panel ( Figure 5AThe 500s in the display panel 400 can be stacked in the vertical direction (i.e., the Z direction). A display area DA for displaying an image and a first upper signal line 431 electrically connected to the display area DA can be arranged on a first surface 410 of the display panel 400. A first upper connection portion 441 can be arranged on a second surface 420 of the display panel 400 and electrically connected to the first upper signal line 431. The first upper signal line 431 can be electrically connected to the first upper connection portion 441 by passing through a first contact hole 490 of the display panel 400 in the thickness direction (Z direction).

[0113] The second upper signal line 531 and the upper driver 501 electrically connected to the second upper signal line 531 can be arranged on the first surface 510a of the first drive panel 500a. The second upper signal line 531 can be electrically connected to the first upper signal line 431. Specifically, the second upper connection portion 541 can be arranged on the first surface 510a of the first drive panel 500a at a position corresponding to the first upper connection portion 441. The bump 710 can be arranged between the first upper connection portion 441 and the second upper connection portion 541, and electrically connects the first upper connection portion 441 to the second upper connection portion 541.

[0114] An upper driver 501 disposed on a first surface 510a of the first driving panel 500a can be electrically connected to an upper IC 561 disposed on a second surface 520a of the first driving panel 500a. Specifically, a third upper signal line 551 electrically connected to the upper driver 501 can be disposed on the first surface 510a of the first driving panel 500a. Multiple fourth upper signal lines 571 electrically connected to the upper IC 561 can be disposed on the second surface 520a of the first driving panel 500a. The third upper signal line 551 can be electrically connected to the multiple fourth upper signal lines 571 by passing through a second contact hole 590 of the first driving panel 500a in the thickness direction (i.e., the Z direction).

[0115] The filling unit 720 can be disposed between the display panel 400 and the first driving panel 500a stacked in the vertical direction (Z direction). Specifically, a distance d in the Z direction can exist between the second surface 420 of the display panel 400 and the first surface 510a of the first driving panel 500a. The upper driver 501 and the connection portion between the first upper connecting portion 441 and the second upper connecting portion 541 can be disposed within the distance d. The filling unit 720 can be disposed within the distance d. The filling unit 720 can protect the upper driver 501 and the connection portion between the first upper connecting portion 441 and the second upper connecting portion 541. In addition, the filling unit 720 can fix the display panel 400 and the first driving panel 500a to each other.

[0116] The filling unit 720 may include a resin. As an example, the filling unit 720 may include an organic material, such as methyl silicone, phenyl silicone, or polyimide. As another example, the filling unit 720 may include a polyurethane resin, epoxy resin, acrylic resin as an organic sealant, or silicone as an inorganic sealant.

[0117] The electrical signal transmission of the display device 100 having the above structure can be as follows.

[0118] As an electrical path in the first drive panel 500a, electrical signals can be transmitted in the following order: upper IC 561, fourth upper signal line 571, second contact hole 590, third upper signal line 551, upper driver 501, second upper signal line 531, and second upper connection portion 541.

[0119] As an electrical path between the first driving panel 500a and the display panel 400, electrical signals can be transmitted in the order of the second upper connecting portion 541, the protrusion 710, and the first upper connecting portion 441.

[0120] As an electrical path in the display panel 400, electrical signals can be transmitted in the order of the first upper connection portion 441, the first contact hole 490, the first upper signal line 431, and the display area DA.

[0121] Figures 8A to 8E The operation of the manufacturing display device 100 according to the embodiment is shown sequentially.

[0122] See Figure 8A A mother substrate 800 is provided. The mother substrate 800 is sized to simultaneously manufacture multiple display panels 400 and multiple driving panels 500. Each of the multiple display panels 400 and each of the multiple driving panels 500 may include a substrate having the same material. The mother substrate 800 may include glass or polymer resin. The glass substrate may include alkali-free glass. The polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate, etc.

[0123] Display elements and components such as signal lines arranged on the first surface 410 of each of the plurality of display panels 400 are patterned on the first surface 810 of the mother substrate 800. Simultaneously, display elements and components such as signal lines arranged on the first surface 510a of each of the plurality of first driving panels 500a and the first surface 510b of each of the plurality of second driving panels 500b are patterned on the first surface 810 of the mother substrate 800.

[0124] See Figure 8BWhen the first patterning operation on the first surface 810 of the mother substrate 800 is completed, the mother substrate 800 is inverted. Display elements and components such as signal lines arranged on the second surface 420 of each of the plurality of display panels 400 are patterned on the second surface 820 of the mother substrate 800. Simultaneously, display elements and components such as signal lines arranged on the second surface 520a of each of the plurality of first driving panels 500a and the second surface 520b of each of the plurality of second driving panels 500b are patterned on the second surface 820 of the mother substrate 800.

[0125] See Figure 8C The mother substrate 800 is cut. Multiple display panels 400, multiple first driving panels 500a and multiple second driving panels 500b are separated into individual display panels 400, individual first driving panels 500a and individual second driving panels 500b using a cutting device such as a cutting wheel or a laser device.

[0126] See Figure 8D A single first driving panel 500a is disposed on a single display panel 400, and the first driving panel 500a is electrically connected to the display panel 400. At this time, the second surface 420 of the display panel 400 and the first surface 510a of the first driving panel 500a are arranged to face each other. The first upper connecting portion 441 and the second upper connecting portion 541 are electrically connected by a protrusion 710.

[0127] Although not in Figure 8D As shown, however, a single second driving panel 500b is arranged on a single display panel 400, and the second driving panel 500b is electrically connected to the display panel 400. The second surface 420 of the display panel 400 and the first surface 510b of the second driving panel 500b are arranged to face each other, and the first lower connecting portion 442 and the second lower connecting portion 542 are electrically connected by a bump 710.

[0128] See Figure 8E The filling unit 720 can be arranged between a single display panel 400 and a single first driving panel 500a. A distance d can exist between the second surface 420 of the display panel 400 and the first surface 510a of the first driving panel 500a, and the resin-containing filling unit 720 can be filled in the distance d (i.e., the gap). Although not in Figure 8E As shown, however, the distance d can also exist between the second surface 420 of a single display panel 400 and the first surface 510b of a single second drive panel 500b, and the filling unit 720 can be filled in the gap.

[0129] Through the operations described above, the combination of a single first driving panel 500a and a single second driving panel 500b to the display panel 400 is completed.

[0130] Figure 9 and Figure 10 Figures are respectively of electronic devices including display device 900 and display device 1000 according to embodiments.

[0131] See Figure 9 and Figure 10 Display devices 900 and 1000 can be included in electronic devices such as televisions or monitors, or electronic devices such as laptop computers. Alternatively, display devices 900 and 1000 can be used in various electronic devices such as smart photo frames or large billboards.

[0132] Display devices 900 and 1000 are not limited to electronic devices with horizontally elongated rectangular screens. In another embodiment, for example, display devices 900 and 1000 can be used in electronic devices with vertically elongated rectangular screens.

[0133] The display device and method of manufacturing the display device according to the present disclosure can separate the display panel and the driving panel, and transmit electrical signals from a driver arranged on the driving panel to the display panel, thereby minimizing the dead zone around the panel.

[0134] In addition to the above description, the effects of this disclosure can be derived from the following description with reference to the accompanying drawings.

[0135] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A display device, comprising: A display panel including a first surface and a second surface opposite to the first surface, wherein a display area for displaying an image is arranged on the first surface; A driving panel disposed on the display panel and including a first surface and a second surface, wherein the first surface of the driving panel faces the second surface of the display panel, and the second surface of the driving panel is opposite to the first surface of the driving panel; as well as Fill the space between the display panel and the drive panel. In the cross-sectional view, the display panel and the driving panel are stacked vertically. The display panel has a first contact hole extending from the first surface of the display panel to the second surface of the display panel in the thickness direction of the display panel. The drive panel has a second contact hole extending from the first surface of the drive panel to the second surface of the drive panel in the thickness direction. Signal lines arranged on the first surface of the display panel are electrically connected to signal lines arranged on the second surface of the driving panel through the first contact hole of the display panel and the second contact hole of the driving panel, respectively.

2. The display device according to claim 1, wherein, The first contact hole is provided in a plurality of portions to include a plurality of first contact holes, and the second contact hole is provided in a plurality of portions to include a plurality of second contact holes. The plurality of first contact holes are defined in the display panel, and The plurality of second contact holes are defined in the drive panel.

3. The display device according to claim 2, wherein, Multiple first signal lines electrically connected to the display area are arranged on the first surface of the display panel. Multiple second signal lines electrically connected to the multiple first signal lines and a driver electrically connected to the multiple second signal lines are arranged on the first surface of the drive panel, and An integrated circuit (IC) electrically connected to the driver is disposed on the second surface of the driver panel.

4. The display device according to claim 3, wherein, A plurality of first connection portions are arranged on the second surface of the display panel, and each of the plurality of first connection portions is electrically connected to each of the plurality of first signal lines through each of the plurality of first contact holes. A plurality of second connection portions are arranged on the first surface of the drive panel, and each of the plurality of second connection portions is electrically connected to each of the plurality of first connection portions and electrically connected to each of the plurality of second signal lines.

5. The display device according to claim 4, wherein, The bump is located between the first connecting portion and the second connecting portion.

6. The display device according to claim 3, wherein, Multiple third signal lines are electrically connected to the driver and arranged on the first surface of the driver panel. Multiple fourth signal lines are electrically connected to the IC and arranged on the second surface of the drive panel, and Each of the plurality of third signal lines is electrically connected to each of the plurality of fourth signal lines via each of the plurality of second contact holes.

7. The display device according to claim 3, wherein, The driver arranged on the drive panel is configured to apply signals to display elements arranged in the display area.

8. The display device according to any one of claims 1 to 7, wherein, The filling portion is filled in the gap between the second surface of the display panel and the first surface of the driving panel.

9. The display device according to any one of claims 1 to 7, wherein, In the plan view, the display panel overlaps with the driving panel, and The size of the driving panel is smaller than the size of the display panel.

10. The display device according to claim 9, wherein, The drive panel includes a first drive panel and a second drive panel. The first driving panel is arranged above the display panel in the plan view, and The second driving panel is arranged at the bottom of the display panel in the plan view.

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