Active matrix substrate and method for manufacturing the same

Abstract

An active matrix substrate is provided which has a plurality of oxide semiconductor TFTs having a top gate structure and different characteristics. An active matrix substrate includes a first TFT and a second TFT each having an oxide semiconductor layer and a gate electrode disposed on a portion of the oxide semiconductor layer with a gate insulating layer interposed therebetween. In the first TFT, a first region of the oxide semiconductor layer, which is covered with the gate electrode with the gate insulating layer interposed therebetween, has a stacked structure including a lower oxide semiconductor film and an upper oxide semiconductor film throughout the region, and the upper oxide semiconductor film has a higher mobility than the lower oxide semiconductor film. In the second TFT, at least a portion of the first region of the oxide semiconductor layer includes one of the lower oxide semiconductor film and the upper oxide semiconductor film and does not include the other of the lower oxide semiconductor film and the upper oxide semiconductor film.

Description

Technical Field

[0001] This invention relates to active matrix substrates and their manufacturing methods. Background Technology

[0002] Active matrix substrates used in liquid crystal display devices, organic electroluminescent (EL) display devices, etc., have: a display area having multiple pixels; and an area outside the display area (non-display area or bezel area). In the display area, each pixel has a switching element such as a thin film transistor (hereinafter referred to as "TFT"). As such switching elements, TFTs with an amorphous silicon film as the active layer (hereinafter referred to as "amorphous silicon TFT") and TFTs with a polycrystalline silicon film as the active layer (hereinafter referred to as "polycrystalline silicon TFT") have been widely used in the past.

[0003] As the active layer material for TFTs, oxide semiconductors have been proposed to replace amorphous silicon and polycrystalline silicon. This type of TFT is called an "oxide semiconductor TFT." Oxide semiconductors have higher mobility than amorphous silicon. Therefore, oxide semiconductor TFTs can operate at higher speeds than amorphous silicon TFTs.

[0004] TFTs are broadly classified into bottom-gate and top-gate structures. Currently, oxide semiconductor TFTs mostly employ bottom-gate structures, but the use of top-gate structures has also been proposed (e.g., Patent Document 1). In top-gate structures, the gate insulating layer can be thinned, thus achieving higher current supply performance.

[0005] In the non-display areas of an active matrix substrate, peripheral circuits such as driving circuits are sometimes formed monolithically. By forming the driving circuits monolithically, costs are reduced by miniaturizing the non-display area and simplifying the installation process. For example, in the non-display area, gate driver circuits are sometimes formed monolithically, while source driver circuits are mounted in a COG (Chip on Glass) manner.

[0006] In devices with high requirements for narrow bezels, such as smartphones, sometimes not only are gate drivers formed on a single chip, but also source-shared driving (SSD) circuits and other multiplexing circuits are formed on a single chip. An SSD circuit distributes video data from a single video signal line from each terminal of the source driver to multiple source wirings. By incorporating an SSD circuit, the area for configuring terminals and wiring in the non-display area (terminal / wiring formation area) can be narrowed. Furthermore, the number of outputs from the source driver is reduced, allowing for a smaller circuit size and thus lowering the cost of the driver IC.

[0007] Peripheral circuits such as driving circuits and SSD circuits include TFTs. In this specification, the TFTs configured as switching elements in each pixel of the display area are called "pixel TFTs," and the TFTs constituting the peripheral circuits are called "circuit TFTs." In addition, the TFTs constituting the driving circuits in the circuit TFTs are called "driving circuit TFTs," and the TFTs constituting the SSD circuits are called "SSD circuit TFTs."

[0008] In active matrix substrates where oxide semiconductor TFTs are used as pixel TFTs, from a manufacturing process point of view, it is preferable that the circuit TFTs also use the same oxide semiconductor film as the pixel TFTs and are formed using the same process. Therefore, the circuit TFTs and pixel TFTs typically have the same structure. The characteristics of these TFTs are also largely the same.

[0009] Existing technical documents

[0010] Patent documents

[0011] Patent Document 1: Japanese Patent Application Publication No. 2015-109315 Summary of the Invention

[0012] The problem the invention aims to solve

[0013] However, pixel TFTs and circuit TFTs require different characteristics. Furthermore, even within circuit TFTs, the required characteristics differ between TFTs used in driving circuits and TFTs used in SSD circuits. In recent years, the types of peripheral circuits monolithically formed on active matrix substrates have increased, leading to a further diversification of the performance requirements for circuit TFTs.

[0014] Furthermore, in organic EL display devices, a pixel circuit is provided within each pixel, comprising at least two types of pixel TFTs (referred to as "driving TFTs" and "selection TFTs") and capacitor elements. The selection TFT has the function of selecting a pixel by varying the voltage applied to the driving TFT. The driving TFT has the function of supplying the current required for light emission. Since the selection TFT and the driving TFT perform different functions, their required characteristics may also differ.

[0015] Thus, in an active matrix substrate with multiple TFTs for different purposes, in order for each TFT to have the characteristics required for its application, it is necessary to fabricate multiple oxide semiconductor TFTs with different characteristics separately.

[0016] The embodiments of the present invention were made in view of the above circumstances, and the object is to provide an active matrix substrate having a plurality of oxide semiconductor TFTs having top gate structures and different characteristics.

[0017] Solution for solving the problem

[0018] This specification discloses the active matrix substrate and the method for manufacturing the active matrix substrate as described in the following items.

[0019] [Project 1] An active matrix substrate, having a display area comprising multiple pixel areas and a non-display area disposed around the display area, comprising:

[0020] Substrate; and

[0021] Multiple oxide semiconductor TFTs are supported on the substrate and disposed in the display area or the non-display area. Each of the multiple oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a portion of the oxide semiconductor layer through a gate insulating layer.

[0022] The aforementioned oxide semiconductor layer includes a first region covered by the aforementioned gate electrode, separated from the aforementioned gate insulating layer.

[0023] The aforementioned plurality of oxide semiconductor TFTs include a first TFT and a second TFT.

[0024] In the first TFT described above, the first region of the oxide semiconductor layer has a stacked structure throughout its entirety, comprising a lower oxide semiconductor film and an upper oxide semiconductor film disposed on the lower oxide semiconductor film, wherein the mobility of the upper oxide semiconductor film is higher than that of the lower oxide semiconductor film.

[0025] In the second TFT, at least a portion of the first region of the oxide semiconductor layer comprises one of the lower oxide semiconductor film and the upper oxide semiconductor film, but does not comprise the other oxide semiconductor film.

[0026] [Project 2] According to the active matrix substrate described in Project 1, wherein,

[0027] At least a portion of the first region in the second TFT includes the lower oxide semiconductor film but does not include the upper oxide semiconductor film.

[0028] [Project 3] According to the active matrix substrate described in Project 1, wherein,

[0029] At least a portion of the first region in the second TFT includes the upper oxide semiconductor film but does not include the lower oxide semiconductor film.

[0030] [Project 4] An active matrix substrate has a display area comprising multiple pixel areas and a non-display area disposed around the display area, wherein the active matrix substrate comprises:

[0031] Substrate; and

[0032] A plurality of oxide semiconductor TFTs, supported on the substrate, are disposed in the display area or the non-display area. Each of the plurality of oxide semiconductor TFTs has: an oxide semiconductor layer; a gate electrode disposed on a portion of the oxide semiconductor layer with respect to a gate insulating layer; and a source electrode and a drain electrode.

[0033] The aforementioned oxide semiconductor layer includes a first region covered by the gate electrode through the aforementioned gate insulating layer, and a first contact region and a second contact region located on both sides of the first region. The first contact region is electrically connected to the aforementioned source electrode, and the second contact region is electrically connected to the aforementioned drain electrode.

[0034] The aforementioned plurality of oxide semiconductor TFTs include a first TFT and a second TFT.

[0035] In the first TFT described above, the first region of the oxide semiconductor layer has a stacked structure throughout its entirety, comprising a lower oxide semiconductor film and an upper oxide semiconductor film disposed on the lower oxide semiconductor film, wherein the mobility of the upper oxide semiconductor film and the lower oxide semiconductor film are different from each other.

[0036] In the second TFT, the first contact region and the second contact region of the oxide semiconductor layer have the stacked structure, but at least a portion of the first region includes one of the lower oxide semiconductor film and the upper oxide semiconductor film, and does not include the other oxide semiconductor film.

[0037] [Project 5] According to the active matrix substrate described in Project 4, wherein,

[0038] At least a portion of the first region in the second TFT includes the lower oxide semiconductor film but does not include the upper oxide semiconductor film.

[0039] [Project 6] According to the active matrix substrate described in Project 4, wherein,

[0040] At least a portion of the first region in the second TFT includes the upper oxide semiconductor film but does not include the lower oxide semiconductor film.

[0041] [Item 7] The active matrix substrate according to any one of Items 4 to 6, wherein,

[0042] In the second TFT, a portion of the first region of the oxide semiconductor layer has the aforementioned stacked structure, and another portion contains one of the aforementioned oxide semiconductor films but does not contain the other of the aforementioned oxide semiconductor films.

[0043] [Item 8] The active matrix substrate according to any one of Items 4 to 6, wherein,

[0044] In the second TFT, the entire extent of the first region of the oxide semiconductor layer includes one of the oxide semiconductor films but does not include the other oxide semiconductor film.

[0045] [Item 9] The active matrix substrate according to any one of Items 4 to 8, wherein,

[0046] The mobility of the upper oxide semiconductor film is higher than that of the lower oxide semiconductor film.

[0047] [Item 10] An active matrix substrate according to any one of Items 4 to 8, wherein,

[0048] The mobility of the upper oxide semiconductor film is lower than that of the lower oxide semiconductor film.

[0049] [Item 11] An active matrix substrate according to any one of Items 4 to 10, wherein,

[0050] Each of the aforementioned plurality of oxide semiconductor TFTs further comprises an insulating layer covering the aforementioned oxide semiconductor layer and the aforementioned gate electrode.

[0051] The source electrode is in contact with the first contact region within the first opening formed in the insulating layer, and the drain electrode is in contact with the second contact region within the second opening formed in the insulating layer.

[0052] [Item 12] An active matrix substrate according to any one of Items 1 to 11, wherein,

[0053] In the first TFT described above, the gate insulating layer is in contact with the upper surface of the upper oxide semiconductor film.

[0054] In the second TFT described above, the gate insulating layer is in contact with the upper surface of the oxide semiconductor film described above.

[0055] [Item 13] An active matrix substrate according to any one of Items 4 to 6, wherein,

[0056] The aforementioned plurality of oxide semiconductor TFTs also include a third TFT.

[0057] In the second TFT described above, the entire range of the first region includes one of the lower oxide semiconductor film and the upper oxide semiconductor film, but does not include the other oxide semiconductor film.

[0058] In the third TFT, the first contact region and the second contact region of the oxide semiconductor layer, as well as a portion of the first region, have the aforementioned stacked structure. Another portion of the first region contains one of the oxide semiconductor films and does not contain the other oxide semiconductor film.

[0059] [Item 14] An active matrix substrate according to any one of Items 1 to 12, wherein,

[0060] The aforementioned plurality of oxide semiconductor TFTs also include a third TFT.

[0061] In the third TFT, at least a portion of the first region in the oxide semiconductor layer includes the other oxide semiconductor film, and does not include the other oxide semiconductor film.

[0062] [Item 15] An active matrix substrate according to any one of Items 1 to 14, wherein,

[0063] The first TFT is disposed in each of the plurality of pixel regions.

[0064] The second TFT mentioned above is included in the peripheral circuitry disposed in the non-display area.

[0065] [Item 16] An active matrix substrate according to any one of Items 1 to 14, wherein,

[0066] Each of the aforementioned pixel regions has a pixel circuit that includes at least a driving TFT, a selection TFT, and a capacitor element.

[0067] One of the aforementioned first TFT and the aforementioned second TFT is the aforementioned driving TFT, and the other TFT is the aforementioned selection TFT.

[0068] [Item 17] A method for manufacturing an active matrix substrate is a method for manufacturing an active matrix substrate having a display area comprising multiple pixels and a non-display area disposed around the display area. The active matrix substrate includes multiple oxide semiconductor TFTs disposed in the display area or the non-display area. The multiple oxide semiconductor TFTs include a first TFT formed in a first TFT forming area and a second TFT formed in a second TFT forming area. The method for manufacturing the active matrix substrate includes:

[0069] In process (A), a lower oxide semiconductor film is formed on the substrate in each TFT forming region of the first TFT forming region and the second TFT forming region;

[0070] In step (B), the lower oxide semiconductor film is patterned to remove at least a portion of the portion of the lower oxide semiconductor film located in the second TFT formation region.

[0071] Step (C): After step (B), an upper oxide semiconductor film is formed in each TFT forming region of the first TFT forming region and the second TFT forming region in such a way as to cover the lower oxide semiconductor film.

[0072] In process (D), the lower oxide semiconductor film and the upper oxide semiconductor film are patterned to form a first oxide semiconductor layer in the first TFT forming region, comprising a stacked structure including the lower oxide semiconductor film and the upper oxide semiconductor film; and in the second TFT forming region, a second oxide semiconductor layer comprising a first portion is formed, wherein the first portion comprises the upper oxide semiconductor film and does not comprise the lower oxide semiconductor film; and

[0073] In step (E), a gate insulating layer and a gate electrode are formed, wherein, in the first TFT forming region, the gate electrode is disposed on a portion of the first oxide semiconductor layer through the gate insulating layer, and in the second TFT forming region, the gate electrode is disposed on at least a portion of the first portion of the second oxide semiconductor layer through the gate insulating layer.

[0074] [Item 18] A method for manufacturing an active matrix substrate is a method for manufacturing an active matrix substrate having a display area comprising multiple pixels and a non-display area disposed around the display area. The active matrix substrate includes multiple oxide semiconductor TFTs disposed in the display area or the non-display area. The multiple oxide semiconductor TFTs include a first TFT formed in a first TFT forming area and a second TFT formed in a second TFT forming area. The method for manufacturing the active matrix substrate includes:

[0075] In step (a), in each of the first TFT forming regions and the second TFT forming regions, a laminated film comprising a lower oxide semiconductor film and an upper oxide semiconductor film disposed on the lower oxide semiconductor film is formed on the substrate.

[0076] In step (b), the above-mentioned stacked film is patterned, thereby forming a first oxide semiconductor layer having a stacked structure including the lower oxide semiconductor film and the upper oxide semiconductor film in the first TFT forming region, and forming a stacked body having a stacked structure including the lower oxide semiconductor film and the upper oxide semiconductor film in the second TFT forming region.

[0077] Step (c) involves removing at least a portion of the upper oxide semiconductor film in the stack in the second TFT formation region, thereby forming a second oxide semiconductor layer comprising the first portion in the second TFT formation region, wherein the first portion comprises the lower oxide semiconductor film and does not comprise the upper oxide semiconductor film; and

[0078] In step (d), a gate insulating layer and a gate electrode are formed, wherein, in the first TFT forming region, the gate electrode is disposed on a portion of the first oxide semiconductor layer through the gate insulating layer, and in the second TFT forming region, the gate electrode is disposed on at least a portion of the first portion of the second oxide semiconductor layer through the gate insulating layer.

[0079] [Item 19] A method for manufacturing an active matrix substrate according to Item 17 or 18, wherein,

[0080] The second oxide semiconductor layer further includes a stacked portion having the above-described stacked structure.

[0081] In the second TFT forming region, the gate electrode is configured to cover at least a portion of the first portion of the second oxide semiconductor layer and a portion of the stacked portion, separated by the gate insulating layer.

[0082] [Item 20] A method for manufacturing an active matrix substrate according to Item 17 or 18, wherein,

[0083] The second oxide semiconductor layer further includes a stacked portion having the above-described stacked structure.

[0084] In the second TFT forming region, the gate electrode is configured to cover the first portion of the second oxide semiconductor layer through the gate insulating layer, but not to cover the stacked portion.

[0085] [Item 21] The active matrix substrate according to Item 13 or 14, wherein,

[0086] The aforementioned active matrix substrate also includes driving circuitry and SSD circuitry configured in the aforementioned non-display area.

[0087] The first TFT is disposed in each of the plurality of pixel regions.

[0088] At least one of the second TFT and the third TFT is included in the driving circuit, and the other TFT is included in the SSD circuit.

[0089] [Item 22] An active matrix substrate according to any one of Items 1 to 16, wherein,

[0090] Both the upper oxide semiconductor film and the lower oxide semiconductor film contain In and / or Sn.

[0091] The total ratio of the number of In and Sn atoms relative to all metal elements in the oxide semiconductor film with lower mobility in the upper oxide semiconductor film and the lower oxide semiconductor film is less than the total ratio of the number of In and Sn atoms relative to all metal elements in the oxide semiconductor film with higher mobility.

[0092] [Item 23] An active matrix substrate according to any one of Items 1 to 16, wherein,

[0093] The oxide semiconductor film with higher mobility in the upper oxide semiconductor film and the lower oxide semiconductor film contains Sn, while the oxide semiconductor film with lower mobility does not contain Sn, or contains Sn at a lower concentration than the oxide semiconductor film with higher mobility.

[0094] [Item 24] An active matrix substrate according to any one of Items 1 to 16, wherein,

[0095] Both the upper oxide semiconductor film and the lower oxide semiconductor film mentioned above contain In-Ga-Zn-O semiconductors.

[0096] In the aforementioned upper oxide semiconductor film and the aforementioned lower oxide semiconductor film, the ratio of In atoms to all metal elements in the oxide semiconductor film with higher mobility is higher than the ratio of In atoms to all metal elements in the oxide semiconductor film with lower mobility.

[0097] [Item 25] The active matrix substrate according to Item 24, wherein,

[0098] The In-Ga-Zn-O semiconductor in the upper oxide semiconductor film and / or the lower oxide semiconductor film contains a crystalline portion.

[0099] [Item 26] An active matrix substrate according to any one of items 1 to 16 and 22 to 25, wherein,

[0100] When viewed from the normal direction of the substrate, in the oxide semiconductor layer of the first TFT, the upper oxide semiconductor film is located inside the upper surface of the lower oxide semiconductor film.

[0101] [Item 27] ​​An active matrix substrate according to any one of items 1 to 16 and 22 to 25, wherein,

[0102] In the oxide semiconductor layer of the first TFT, the upper oxide semiconductor film covers the upper surface and side surface of the lower oxide semiconductor film.

[0103] [Item 28] The manufacturing method of the active matrix substrate according to Item 18, wherein,

[0104] The lower oxide semiconductor film contains Sn, while the upper oxide semiconductor film does not contain Sn, or contains Sn at a lower concentration than the lower oxide semiconductor film.

[0105] Step (c) includes the following step: selectively etching the upper oxide semiconductor film in the above-mentioned stack by using wet etching with PAN-based etchant.

[0106] Invention Effects

[0107] According to one embodiment of the present invention, an active matrix substrate having multiple oxide semiconductor TFTs with top gate structures and different characteristics can be provided. Furthermore, according to another embodiment of the present invention, a method for manufacturing an active matrix substrate capable of separately fabricating multiple oxide semiconductor TFTs with different characteristics using the same oxide semiconductor film can be provided. Attached Figure Description

[0108] Figure 1 This is a schematic diagram showing an example of the planar structure of the active matrix substrate 1000 of the first embodiment.

[0109] Figure 2 This is a cross-sectional view illustrating the first TFT 100 and the second TFT 200 formed on the active matrix substrate 1000.

[0110] Figure 3 This is a diagram illustrating the Vg-Id characteristics of TFT100 and TFT200.

[0111] Figure 4A This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0112] Figure 4B This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0113] Figure 4C This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0114] Figure 4D This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0115] Figure 4E This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0116] Figure 4F This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0117] Figure 4G This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0118] Figure 4H This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0119] Figure 4I This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0120] Figure 4J This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0121] Figure 4K This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0122] Figure 4L This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0123] Figure 4M This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1000.

[0124] Figure 5 A schematic cross-sectional view of the first TFT 100 and the second TFT 300 in another active matrix substrate 1001 of the first embodiment.

[0125] Figure 6 This is a diagram illustrating the Vg-Id characteristics of TFT100 and TFT300.

[0126] Figure 7A This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1001.

[0127] Figure 7B This is a cross-sectional view showing the manufacturing method of the active matrix substrate 1001.

[0128] Figure 7CThis is a cross-sectional view showing the manufacturing method of the active matrix substrate 1001.

[0129] Figure 8A This is a schematic cross-sectional view showing the first TFT 100 and the second TFT 400 of the active matrix substrate 2000 in the second embodiment.

[0130] Figure 8B This is a schematic top view of the TFT400.

[0131] Figure 9A This is a cross-sectional view showing the manufacturing method of the active matrix substrate 2000.

[0132] Figure 9B This is a cross-sectional view showing the manufacturing method of the active matrix substrate 2000.

[0133] Figure 9C This is a cross-sectional view showing the manufacturing method of the active matrix substrate 2000.

[0134] Figure 9D This is a cross-sectional view showing the manufacturing method of the active matrix substrate 2000.

[0135] Figure 9E This is a cross-sectional view showing the manufacturing method of the active matrix substrate 2000.

[0136] Figure 10A This is a schematic cross-sectional view showing the first TFT 100 and the second TFT 500 of another active matrix substrate 2001 in the second embodiment.

[0137] Figure 10B This is a schematic top view showing the TFT500.

[0138] Figure 11 This is a cross-sectional view illustrating another active matrix substrate 2002.

[0139] Figure 12A This is a schematic cross-sectional view showing the first TFT 100 and the second TFT 600 of the active matrix substrate 3000 in the third embodiment.

[0140] Figure 12B This is a schematic top view of the TFT600.

[0141] Figure 13A This is a cross-sectional view showing the manufacturing method of the active matrix substrate 3000.

[0142] Figure 13B This is a cross-sectional view showing the manufacturing method of the active matrix substrate 3000.

[0143] Figure 13CThis is a cross-sectional view showing the manufacturing method of the active matrix substrate 3000.

[0144] Figure 13D This is a cross-sectional view showing the manufacturing method of the active matrix substrate 3000.

[0145] Figure 14A This is a schematic cross-sectional view showing the first TFT 100 and the second TFT 700 of another active matrix substrate 3001 in the third embodiment.

[0146] Figure 14B This is a schematic top view showing the TFT700.

[0147] Figure 15 This is a cross-sectional view illustrating another active matrix substrate 3002.

[0148] Figure 16 This is a schematic cross-sectional view illustrating the active matrix substrate 4000 of the fourth embodiment.

[0149] Figure 17 This is a diagram illustrating the Id-Vg characteristics of TFTs 100, 700, and 200 when the lower oxide semiconductor film has a lower mobility than the upper oxide semiconductor film.

[0150] Figure 18 This is a schematic cross-sectional view illustrating another active matrix substrate 4001 of the fourth embodiment.

[0151] Figure 19 This is a schematic cross-sectional view illustrating yet another active matrix substrate 4002.

[0152] Figure 20A This is a cross-sectional view used to illustrate another example of the first TFT100 in the first embodiment.

[0153] Figure 20B This is a cross-sectional view used to illustrate another example of the first TFT100 in the first embodiment.

[0154] Figure 21A This is a cross-sectional view showing another manufacturing method of the active matrix substrate 2000.

[0155] Figure 21B This is a cross-sectional view showing another manufacturing method of the active matrix substrate 2000.

[0156] Figure 22A This is a cross-sectional view showing another manufacturing method of the active matrix substrate 3000.

[0157] Figure 22B This is a cross-sectional view showing another manufacturing method of the active matrix substrate 3000.

[0158] Figure 22C This is a cross-sectional view showing another manufacturing method of the active matrix substrate 3000.

[0159] Figure 23 This is a cross-sectional view showing another example of an active matrix substrate 1000.

[0160] Figure 24 This is a diagram illustrating the shift register circuit in a gate drive circuit.

[0161] Figure 25 This is a diagram illustrating a unit shift register circuit SR.

[0162] Figure 26 This is a diagram illustrating an SSD circuit.

[0163] Figure 27 This is a diagram illustrating a pixel circuit.

[0164] Explanation of reference numerals in the attached figures

[0165] 1 substrate

[0166] 2A, 2B, 2C, 2D, 2E, 2F, 2G Lower conductive layer

[0167] 4A, 4B, 4C, 4D, 4E, 4F, 4G Oxide semiconductor layers

[0168] 4Ac, 4Bc, 4Cc, 4Dc, 4Ec, 4Fc, 4Gc Region 1

[0169] 4As, 4Bs, 4Cs, 4Ds, 4Es, 4Fs, 4Gs First contact area

[0170] 4Ad, 4Bd, 4Cd, 4Dd, 4Ed, 4Fd, 4Gd Second contact area

[0171] 4L, 4Ld, 4Ls - Layer 1

[0172] 4U, 4Us, 4Ud - Layer 2

[0173] 5A, 5B, 5C, 5D, 5E, 5F, 5G gate insulating layers

[0174] 7A, 7B, 7C, 7D, 7E, 7F, 7G gate electrodes

[0175] 8A, 8B, 8C, 8D, 8E, 8F, 8G Source Electrodes

[0176] 9A, 9B, 9C, 9D, 9E, 9F, 9G Drain electrodes

[0177] 10 interlayer insulation layers

[0178] 11 Inorganic insulating layer

[0179] 12 Organic Insulation Layer

[0180] 12A, 12B, 12C, 12D, 12E, 12F, 12G Lower conductive layer

[0181] 17 Dielectric layer

[0182] 41 Lower oxide semiconductor film

[0183] 42 Upper oxide semiconductor film

[0184] p1 Lower layer

[0185] p2 Upper layer

[0186] pa layer

[0187] CE common electrode

[0188] PE pixel electrode

[0189] DR display area

[0190] FR Non-display area

[0191] GL gate bus

[0192] SL source bus

[0193] 1000, 1001, 2000, 2001, 2002, 3000, 3001, 3002, 4000, 4001, 4002 Active matrix substrates. Detailed Implementation

[0194] As mentioned above, the characteristics required for a TFT disposed on an active matrix substrate differ depending on its application. Hereinafter, taking an active matrix substrate used in a liquid crystal display device as an example, an example of preferred TFT characteristics will be described.

[0195] Oxide semiconductor TFTs exhibit excellent cutoff characteristics when the gate bias voltage is zero V. Therefore, no charge is released from the TFT when the gate is cut off, making discharge through the TFT difficult. However, the presence of residual charge (uneven charging) can cause liquid crystal operation and display defects. To suppress this, when using an TFT as a pixel TFT, the threshold voltage of the TFT is sometimes reduced, increasing the cutoff leakage current.

[0196] In contrast, when using oxide semiconductor TFTs in driving circuits such as gate drivers, it is preferable to shift their threshold voltage in the positive direction compared to the threshold voltage of the pixel TFT to reduce cutoff leakage current. A large cutoff leakage current can lead to increased power consumption, malfunctions in the driving circuit, and accidental operation. TFTs used in driving circuits can, for example, have enhancement characteristics with a positive threshold voltage.

[0197] On the other hand, the TFTs used in SSD circuits require a relatively large on-state current, demanding high current driving force. Therefore, it is preferable to reduce the threshold voltage to further increase the on-state current. TFTs for SSD circuits can, for example, have depletion characteristics with a negative threshold voltage.

[0198] Furthermore, in the active matrix substrate used in organic EL display devices, a pixel circuit comprising at least a driving TFT and a selection TFT is provided within each pixel. Preferably, the driving TFT has enhancement characteristics. Additionally, for proper multi-grayscale display, the Vg (gate voltage) - Id (drain current) characteristic of the driving TFT is preferably relatively flat (i.e., not steep). Therefore, a large subthreshold coefficient (S-value) is required for the driving TFT. To increase the threshold voltage in the positive direction and increase the S-value, for example, an oxide semiconductor with low mobility can be used. On the other hand, a high mobility (i.e., large on-current) is preferred for the selection TFT. The threshold voltage of the selection TFT can be negative (depletion characteristic). Furthermore, the S-value in the selection TFT can be small. Instead, a small S-value and high switching speed are required.

[0199] Furthermore, the applications and required characteristics of TFTs are not limited to the examples mentioned above and are diverse.

[0200] However, it is difficult to form multiple TFTs with different characteristics using the same oxide semiconductor film. For example, while TFTs for SSD circuits and pixel TFTs preferably use oxide semiconductors with high mobility, the threshold voltage of the TFT tends to shift negatively with the increase of the mobility of oxide semiconductors, and there is a tendency to develop depletion characteristics. Therefore, sometimes high-mobility oxide semiconductors are not suitable for TFTs used in driving circuits. On the other hand, in order to obtain enhanced characteristics, TFTs for driving circuits preferably use oxide semiconductors with relatively low mobility. However, in TFTs with enhanced characteristics, it is difficult to further increase the conduction current, so they may not be suitable for other peripheral circuits such as SSD circuits.

[0201] Furthermore, in TFTs with a top-gate structure (hereinafter referred to as "top-gate TFTs"), the oxide semiconductor layer is usually electrically connected to the source / drain electrodes within an opening (contact hole) in the interlayer insulating layer covering the oxide semiconductor layer. However, depending on the structure of the oxide semiconductor layer, a portion of the oxide semiconductor layer may sometimes be removed during the formation of the contact hole. As a result, the contact resistance increases, and the desired conduction characteristics may not be obtained.

[0202] Based on the above insights, the inventors of this invention have discovered a method for separately fabricating multiple top-gate TFTs that utilize the same oxide semiconductor film but have different characteristics. Furthermore, the inventors of this invention have discovered a method for separately fabricating multiple top-gate TFTs that can suppress the increase in contact resistance between the oxide semiconductor layer and the source / drain electrodes and have different characteristics.

[0203] (First Embodiment)

[0204] Hereinafter, the active matrix substrate of the first embodiment will be described with reference to the accompanying drawings, taking the active matrix substrate used in a liquid crystal display device as an example.

[0205] <Basic Structure of Active Matrix Substrate 1000>

[0206] Figure 1 This is a schematic diagram showing an example of the planar structure of the active matrix substrate 1000 of this embodiment.

[0207] The active matrix substrate 1000 has a display area DR and an area outside the display area DR (non-display area or bezel area) FR. The display area DR includes pixel areas PIX arranged in a matrix. Pixel areas PIX (sometimes simply referred to as "pixels") are areas corresponding to pixels of the display device. The non-display area FR is an area located around the display area DR that does not contribute to the display.

[0208] In the non-display area FR, for example, gate drivers and multiplexing circuits that function as SSD circuits are integrally (monolithically) disposed. Source drivers are, for example, mounted on the active matrix substrate 1000.

[0209] In the display area DR, multiple gate buses GL extending in the row direction (x-direction) and multiple source buses SL extending in the column direction (y-direction) are formed. Each pixel area PIX is defined, for example, by the gate buses GL and the source buses SL. The gate buses GL are connected to the terminals of the gate drivers, respectively. The source buses SL are connected to the terminals of the source drivers, respectively.

[0210] Each pixel region (PIX) has a thin-film transistor (TFT) Tp and a pixel electrode (PE). The TFT Tp is also called a "pixel TFT". The gate electrode of the TFT Tp is electrically connected to the corresponding gate bus GL, and the source electrode is electrically connected to the corresponding source bus SL. The drain electrode is electrically connected to the pixel electrode (PE). When the active matrix substrate 1000 is applied to a display device with a lateral electric field mode such as FFS (Fringe Field Switching) mode, although not shown, an electrode (shared electrode) shared by multiple pixels is provided in the active matrix substrate 1000.

[0211] Multiple circuit TFTs constituting peripheral circuits are formed in the non-display area of ​​the active matrix substrate 1000. The circuit TFTs include TFTs for driving circuits constituting gate drivers, TFTs for SSD circuits constituting SSD circuits, etc.

[0212] <TFT Structure in Active Matrix Substrate 1000>

[0213] Next, the structure of the multiple top-gate TFTs included in the active matrix substrate 1000 will be described.

[0214] The characteristics of a top-gate TFT with an oxide semiconductor layer as the active layer can be varied, for example, depending on the structure of the region in the oxide semiconductor layer covered by the gate electrode through the gate insulating layer. In this specification, the region in the oxide semiconductor layer covered by the gate electrode through the gate insulating layer is referred to as the "first region". The first region includes the region where the channel is formed. Furthermore, the structure of the first region in the oxide semiconductor layer is sometimes referred to as the "active layer structure".

[0215] In this embodiment, the active matrix substrate 1000 includes a plurality of oxide semiconductor TFTs having a top gate structure. The plurality of oxide semiconductor TFTs include at least one first TFT and one second TFT having mutually different active layer structures.

[0216] In the first TFT, a first region of the oxide semiconductor layer has a stacked structure comprising a lower oxide semiconductor film and an upper oxide semiconductor film disposed on the lower oxide semiconductor film. On the other hand, in the second TFT, at least a portion of the first region of the oxide semiconductor layer comprises one of the lower oxide semiconductor film and the upper oxide semiconductor film, but not the other. The lower oxide semiconductor film and the upper oxide semiconductor film have different mobilities.

[0217] In this specification, the portion of the oxide semiconductor layer having a stacked structure including a lower oxide semiconductor film and an upper oxide semiconductor film is referred to as "stacked portion p1". Furthermore, the portion of the oxide semiconductor layer including the lower oxide semiconductor film but not the upper oxide semiconductor film is referred to as "lower layer p1", and the portion including the upper oxide semiconductor film but not the lower oxide semiconductor film is referred to as "upper layer p2". Sometimes, "lower layer p1" and "upper layer p2" are collectively referred to as "part 1". Lower layer p1 may have a single-layer structure including only the lower oxide semiconductor film, or it may also include other semiconductor films. Similarly, upper layer p2 may include only the upper oxide semiconductor film, or it may also include other semiconductor films.

[0218] The first TFT and the second TFT have different active layer structures, and therefore can have different characteristics. For example, the threshold voltage of the first TFT can be lower or higher than the threshold voltage of the second TFT.

[0219] The applications of the first TFT and the second TFT are not limited. For example, the first TFT can be a pixel TFT configured in each pixel area, and the second TFT can be a circuit TFT constituting peripheral circuits such as driving circuits or SDD circuits. Alternatively, the first TFT can be a circuit TFT, and the second TFT can be a pixel TFT. Furthermore, the first TFT and the second TFT can be circuit TFTs used by different peripheral circuits.

[0220] The structure of each TFT will now be described in more detail with reference to the accompanying drawings.

[0221] Figure 2 This is a cross-sectional view illustrating the first TFT 100 and the second TFT 200 formed on the active matrix substrate 1000. Here, an example is given where TFT 100 is a pixel TFT and TFT 200 is a circuit TFT (e.g., a TFT for a driving circuit). The active matrix substrate 1000 can have multiple TFTs 100 and multiple TFTs 200, but only a single TFT 100 and a single TFT 200 are illustrated here for explanation.

[0222] TFT100 and 200 are top-gate TFTs supported on substrate 1 and having an active layer containing an oxide semiconductor film.

[0223] TFT100 includes: an oxide semiconductor layer 4A disposed on a substrate 1; a gate insulating layer 5A covering the oxide semiconductor layer 4A; a gate electrode 7A disposed on the gate insulating layer 5A; and a source electrode 8A and a drain electrode 9A. The gate electrode 7A is disposed such that it covers a portion of the oxide semiconductor layer 4A through the gate insulating layer 5A.

[0224] The oxide semiconductor layer 4A includes: a first region 4Ac covered by a gate electrode 7A through a gate insulating layer 5A; and a region not covered by the gate electrode 7A when viewed from the normal direction of the substrate 1 (hereinafter referred to as the "second region").

[0225] The entire extent of the first region 4Ac in the oxide semiconductor layer 4A is a stack portion pa having a stacked structure comprising a lower oxide semiconductor film 41 and an upper oxide semiconductor film 42 disposed on the lower oxide semiconductor film 41. The lower oxide semiconductor film 41 and the upper oxide semiconductor film 42 have different mobilities. In this embodiment, the upper oxide semiconductor film 42 has a higher mobility than the lower oxide semiconductor film 41.

[0226] The second region of the oxide semiconductor layer 4A can be a low-resistivity region with a lower resistivity than the first region 4Ac. This low-resistivity region can be formed, for example, by using the gate electrode 7A as a mask to perform a low-resistivity treatment on the oxide semiconductor layer 4A.

[0227] When viewed from the normal direction of substrate 1, the second region (low-resistance region) includes a first contact region 4As and a second contact region 4Ad disposed on both sides of the first region 4Ac, respectively. The first contact region 4As is electrically connected to the source electrode 8A, and the second contact region 4Ad is electrically connected to the drain electrode 9A. The first contact region 4As and the second contact region 4Ad may also be a stacked portion pa. In the illustrated example, the entire extent of the oxide semiconductor layer 4A includes a lower oxide semiconductor film 41 and an upper oxide semiconductor film 42. Furthermore, in this embodiment, as long as the first region 4Ac of the oxide semiconductor layer 4A is a stacked portion pa throughout its entire extent, the second region may also have a portion that does not include the lower oxide semiconductor film 41 or the upper oxide semiconductor film 42.

[0228] The gate insulating layer 5A may also cover the first region 4Ac but not the first contact region 4As and the second contact region 4Ad. In the illustrated example, the gate insulating layer 5A is formed only in the region that overlaps with the gate electrode 7A when viewed from the normal direction of the substrate 1. The edge of the gate insulating layer 5A is aligned with the edge of the gate electrode 7A.

[0229] The gate electrode 7A is disposed on the gate insulating layer 5A in such a way that it overlaps with the first region 4Ac when viewed from the normal direction of the substrate 1 and does not overlap with the first contact region 4As and the second contact region 4Ad.

[0230] The oxide semiconductor layer 4A, the gate insulating layer 5A, and the gate electrode 7A are covered by the interlayer insulating layer 10. The interlayer insulating layer 10 may also be in contact with a portion of the upper surface of the oxide semiconductor layers 4A and 4B.

[0231] The source electrode 8A and drain electrode 9A are disposed, for example, on the interlayer insulating layer 10. In this example, the interlayer insulating layer 10 has: a first opening 10As that exposes a first contact region 4As of the oxide semiconductor layer 4A; and a second opening 10Ad that exposes a portion of the second contact region 4Ad. The source electrode 8A is disposed on the interlayer insulating layer 10 and within the first opening 10As, and is connected to the first contact region 4As within the first opening 10As. The drain electrode 9A is disposed on the interlayer insulating layer 10 and within the second opening 10Ad, and is connected to the second contact region 4Ad within the second opening 10Ad.

[0232] The TFT 100 may also have a lower conductive layer 2A on the substrate 1 side of the oxide semiconductor layer 4A, which functions as a light-shielding layer. The lower conductive layer 2A is covered by a lower insulating layer 3. The oxide semiconductor layer 4A of the TFT 100 is disposed on the lower insulating layer 3. The lower conductive layer 2A may be configured to overlap with at least a first region 4Ac in the oxide semiconductor layer 4A when viewed from the normal direction of the substrate 1. As a result, the characteristic degradation of the oxide semiconductor layer 4A caused by light (backlight light) from the substrate 1 side can be suppressed. Furthermore, the lower conductive layer 2A may be in an electrically floating state or fixed at a GND potential (0V). Alternatively, the lower conductive layer 2A may function as a lower gate electrode by electrically connecting the lower conductive layer 2A to the gate electrode 7A via a connection portion not shown.

[0233] Using TFT100 as Figure 1 In the case of the thin-film transistor Tp (pixel TFT) shown, the gate electrode 7A is electrically connected to the corresponding gate bus GL. The gate electrode 7A can be integrally formed with the corresponding gate bus GL using the same conductive film. The source electrode 8A is electrically connected to the corresponding source bus SL. The source electrode 8A can be integrally formed with the corresponding source bus SL using the same conductive film. The drain electrode 9A is electrically connected to the corresponding pixel electrode PE.

[0234] On the other hand, TFT200, like TFT100, has: an oxide semiconductor layer 4B; a gate electrode 7B disposed on a portion of the oxide semiconductor layer 4B with respect to a gate insulating layer 5B; and a source electrode 8B and a drain electrode 9B. TFT200 may also have a lower conductive layer 2B on the substrate 1 side of the oxide semiconductor layer 4B.

[0235] The oxide semiconductor layer 4B, like the oxide semiconductor layer 4A, includes a first region 4Bc that overlaps with the gate electrode 7A when viewed from the normal direction of the substrate 1, and a second region that does not overlap with the gate electrode 7A. The second region may be a low-resistivity region with a lower resistivity than the first region 4Ac.

[0236] Furthermore, when viewed from the normal direction of the substrate 1, the oxide semiconductor layer 4B includes a first contact region 4Bs and a second contact region 4Bd respectively disposed on both sides of the first region 4Bc. The first contact region 4Bs and the second contact region 4Bd are disposed in the second region (low resistance region). The first contact region 4Bs is electrically connected to the source electrode 8B, and the second contact region 4Bd is electrically connected to the drain electrode 9B.

[0237] In TFT 200, the first region 4Bc of the oxide semiconductor layer 4B has a lower layer p1 that includes a lower oxide semiconductor film 41 but does not include an upper oxide semiconductor film 42. As shown, the entire extent of the oxide semiconductor layer 4B may include the lower oxide semiconductor film 41 but not the upper oxide semiconductor film 42. This is only required if at least a portion of the first region 4Bc in the oxide semiconductor layer 4B is the lower layer p1. For example, the second region of the oxide semiconductor layer 4B may also include the lower oxide semiconductor film 41.

[0238] Except for the structure of the oxide semiconductor layer 4B, TFT200 can have the same structure as TFT100. However, the planar shape, size, channel length, and channel width of each layer of TFT100 and TFT200 can also be different from each other.

[0239] The lower oxide semiconductor film 41 of the oxide semiconductor layers 4A and 4B of TFT100 and TFT200 is formed of the same oxide semiconductor film. Alternatively, the gate insulating layers 5A and 5B of each TFT can be formed of the same insulating film, the gate electrodes 7A and 7B can be formed of the same conductive film (conductive film for gate), and the source electrodes 8A and 8B and the drain electrodes 9A and 9B can be formed of the same conductive film (conductive film for source). Therefore, TFT100 and TFT200 can be manufactured using a common process.

[0240] The structures of TFT100 and TFT200 are not limited to Figure 2 The structure shown is as follows. For example, the source electrode and / or drain electrode may be located on the substrate side closer to the oxide semiconductor layer. Alternatively, the source electrode 8A of the TFT 100 may be formed using the same conductive film as the lower conductive layer 2A, and the oxide semiconductor layer 4A may be connected to the source electrode 8A within the opening formed in the lower insulating layer 3.

[0241] <Effect>

[0242] According to this embodiment, TFT100 and TFT200 with different characteristics can be fabricated separately using a common oxide semiconductor film (here, the lower oxide semiconductor film 41).

[0243] Figure 3 This is a graph illustrating the Vg-Id characteristics of TFT100 and TFT200. The horizontal axis of the graph represents the gate electrode potential (gate-drain voltage) Vdg, which is based on the drain electrode potential, and the vertical axis represents the drain current Id.

[0244] according to Figure 3 It is known that TFT200 has a higher threshold voltage than TFT100. This can be attributed to the fact that the first region 4Bc (channel region) of the oxide semiconductor layer 4B of TFT200 contains a lower oxide semiconductor film 41 with low mobility and does not contain an upper oxide semiconductor film 42 with high mobility. Therefore, compared with the oxide semiconductor layer 4A containing the upper oxide semiconductor film 42, the overall mobility of the first region is lower, and the threshold voltage is shifted in the positive direction.

[0245] When the TFT200 is used, for example, in a driving circuit, circuit malfunctions can be suppressed, thus preventing a decrease in yield. The TFT200 preferably has an enhancement characteristic with a positive threshold voltage. This allows for more effective suppression of circuit malfunctions.

[0246] Compared to TFT200, TFT100 has a lower threshold voltage and increased cutoff leakage current. When TFT100 is used, for example, in pixel TFTs, it can reduce display unevenness caused by residual charge. TFT100 can have enhancement characteristics with a positive threshold voltage or depletion characteristics with a negative threshold voltage.

[0247] Alternatively, TFT100 can be used as a TFT for SSD circuits, and TFT200 can be used as a TFT for drive circuits.

[0248] Alternatively, TFT100 and TFT200 can be mixed in the driving circuit. For example, TFT100 can also be used as the output transistor in the gate driving circuit (see reference). Figure 25 (As will be discussed later), the TFT200 will be used as other transistors.

[0249] In an active matrix substrate used as the backplane of an organic EL display device, pixel circuits (see reference) can also be provided in each pixel area. Figure 27(As will be described later) TFT100 and TFT200 are mixed together. For example, TFT100 with a large conduction current can be used as the selection TFT in the pixel circuit, and TFT200 with enhanced characteristics can be used as the driving TFT.

[0250] <Lower oxide semiconductor film 41 and upper oxide semiconductor film 42>

[0251] The lower oxide semiconductor film 41 and the upper oxide semiconductor film 42 only need to have different mobilities; their composition, thickness, crystal structure, and formation method are not particularly limited. In this specification, the lower oxide semiconductor film with the higher mobility is referred to as the "high-mobility oxide semiconductor film," and the upper oxide semiconductor film with the lower mobility is referred to as the "low-mobility oxide semiconductor film." The high-mobility oxide semiconductor film and / or the low-mobility oxide semiconductor film can be a single layer or a stacked film comprising multiple oxide semiconductor films. When the oxide semiconductor film is a stacked film, the "mobility" of each oxide semiconductor film refers to the overall mobility of the stacked film.

[0252] Low-mobility oxide semiconductor films and high-mobility oxide semiconductor films can have different compositions or composition ratios. By making the metal elements or their ratios contained in the oxide semiconductors of the low-mobility oxide semiconductor film and the high-mobility oxide semiconductor film different, when forming the oxide semiconductor layer 4B of TFT200, the difference in etching rate of these oxide semiconductor films can sometimes make it easier to etch only the upper oxide semiconductor film 42.

[0253] As an example, a high-mobility oxide semiconductor film and a low-mobility oxide semiconductor film may contain In and / or Sn, respectively. The total atomic ratio of In and Sn to all metal elements in the low-mobility oxide semiconductor film is less than the total atomic ratio of In and Sn to all metal elements in the high-mobility oxide semiconductor film.

[0254] For example, both the high-mobility oxide semiconductor film and the low-mobility oxide semiconductor film can be In-Ga-Zn-O based oxide semiconductor layers, with the proportion of In atoms in the low-mobility oxide semiconductor film being smaller than that in the high-mobility oxide semiconductor film. Alternatively, the proportion of Ga atoms in the low-mobility oxide semiconductor film can be greater than that in the high-mobility oxide semiconductor film. In this case, for example, the etching rate relative to the oxalic acid-based etchant is greater in the high-mobility oxide semiconductor film than in the low-mobility oxide semiconductor film. Therefore, when a high-mobility oxide semiconductor film is formed as the upper oxide semiconductor film 42, the difference in etching rate can be used to etch only the upper oxide semiconductor film 42.

[0255] Alternatively, the high-mobility oxide semiconductor film may contain Sn, while the low-mobility oxide semiconductor film may not contain Sn. Alternatively, the low-mobility oxide semiconductor film may contain Sn at a lower concentration than the high-mobility oxide semiconductor film. That is, the atomic ratio of Sn to all metal elements in the low-mobility oxide semiconductor film can be less than that in the high-mobility oxide semiconductor film. In this case, a PAN-based etching solution containing phosphoric acid, nitric acid, and acetic acid can be used to selectively etch only the low-mobility oxide semiconductor film. Therefore, it is particularly advantageous to use the low-mobility oxide semiconductor film as the upper oxide semiconductor film 42, as described in the embodiments below. For example, the atomic ratio of Sn to all metal elements in the low-mobility oxide semiconductor film may be 10 at% or less, while the atomic ratio of Sn to all metal elements in the high-mobility oxide semiconductor film may be 11 at% or more. This allows for more reliable and selective etching of the low-mobility oxide semiconductor.

[0256] For example, In-Ga-Zn-O semiconductor films (In:Ga:Zn = 1:1:1, etc.) can be used as low-mobility oxide semiconductor films. For example, In-Ga-Zn-O semiconductor films (In:Ga:Zn = 5:1:4, etc.), In-Sn-Zn-O semiconductor films, In-Al-Sn-Zn-O semiconductor films, In-W-Zn-O semiconductor films, In-Sn-O semiconductor films, In-Zn-O semiconductor films, In-Ga-Sn-O semiconductor films, In-Sn-Ti-Zn-O semiconductor films, etc., can be used as high-mobility oxide semiconductor films.

[0257] Furthermore, low-mobility oxide semiconductor films and high-mobility oxide semiconductor films can also have different crystal structures. For example, one of these oxide semiconductor films can be an amorphous oxide semiconductor film, while the other is a crystalline oxide semiconductor film containing crystalline components.

[0258] Furthermore, even with the same ratio of metal elements, the mobility of the oxide semiconductor film can be varied by different film formation methods or conditions. For example, the atmosphere within the cavity (e.g., the flow ratio of oxygen to Ar supplied to the cavity) can be different when forming an oxide semiconductor film by sputtering. Specifically, when forming a low-mobility oxide semiconductor film, the oxygen-to-Ar flow ratio can be set to be large (e.g., 80%), while when forming a high-mobility oxide semiconductor film, the oxygen-to-Ar flow ratio can be set to be smaller (e.g., 20%) than when forming a low-mobility oxide semiconductor film.

[0259] The thicknesses of the low-mobility oxide semiconductor film and the high-mobility oxide semiconductor film can be approximately the same or different. The high-mobility oxide semiconductor film can be thinner than the low-mobility oxide semiconductor film. By thinning the high-mobility oxide semiconductor film, the threshold voltage of the TFT using the high-mobility oxide semiconductor film can be set to near 0V. This results in a TFT that not only has enhanced characteristics but also high on-state current. The thickness of the high-mobility oxide semiconductor film can, for example, be 5 nm or more but less than 20 nm. The thickness of the low-mobility oxide semiconductor film can, for example, be 20 nm or more but less than 100 nm.

[0260] Furthermore, from a manufacturing process perspective, the lower oxide semiconductor film 41 can be thicker than the upper oxide semiconductor film 42. This provides the advantage of not only suppressing damage to the lower oxide semiconductor film 41 but also allowing patterning only the upper oxide semiconductor film 42. Additionally, when dry etching is used to pattern only the upper oxide semiconductor film 42, even if the surface portion of the lower oxide semiconductor film 41 is etched (over-etched), the lower oxide semiconductor film 41 can still have a predetermined thickness. The thickness of the lower oxide semiconductor film 41 is preferably, for example, 20 nm or more.

[0261] <Manufacturing Method of Active Matrix Substrate 1000>

[0262] The TFT100 and TFT200 in the active matrix substrate 1000 can be manufactured, for example, by the following method.

[0263] Figures 4A to 4M These are cross-sectional views illustrating the manufacturing method of the active matrix substrate 1000. These views show the TFT forming region R1 for forming TFT 100 and the TFT forming region R2 for forming TFT 200. Here, we will describe an example where TFT 100 is used as a pixel TFT and TFT 200 is used as a circuit TFT in an active matrix substrate for an FFS mode liquid crystal display device. Therefore, TFT forming region R1 is part of each pixel region, and TFT forming region R2 is part of the non-display region.

[0264] STEP 1: Formation of the lower conductive layer Figure 4A )

[0265] On substrate 1, a lower conductive film (thickness: for example, 50 nm to 500 nm) is formed by sputtering. Next, the lower conductive film is patterned using a known photolithography process. Thus, as... Figure 4A As shown, a lower conductive layer 2A and a lower conductive layer 2B of the TFT are formed in the TFT forming region R1 and the TFT forming region R2, respectively.

[0266] As substrate 1, transparent and insulating substrates such as glass substrates, silicon substrates, and heat-resistant plastic substrates (resin substrates) can be used.

[0267] The material of the lower conductive film is not particularly limited, and films containing metals such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), and copper (Cu), or their alloys, or metal nitrides, can be used. Alternatively, a laminated film formed by stacking multiple films can also be used.

[0268] Here, a single-layer film containing a metal film (including an alloy film) of Cu or Al is used as the lower conductive film. Alternatively, a multilayer film with a metal film containing Cu or Al as the uppermost layer can also be used.

[0269] STEP 2: Formation of the lower insulating layer 3 Figure 4B )

[0270] Next, as Figure 4B As shown, a lower insulating layer 3 (thickness: for example, 200nm or more and 600nm or less) is formed in such a way as to cover the lower conductive layers 2A and 2B.

[0271] The lower insulating layer 3 is formed, for example, by a CVD method. As the lower insulating layer 3, silicon oxide (SiOx) layers, silicon nitride (SiNx) layers, silicon oxynitride (SiOxNy; x>y) layers, and silicon oxynitride (SiNxOy; x>y) layers can be appropriately used. The lower insulating layer 3 can be a single layer or have a stacked structure. For example, to prevent impurities from diffusing from the substrate 1, a silicon nitride (SiNx) layer or a silicon oxynitride layer can be formed on the substrate side (lower layer), and to ensure insulation, a silicon oxide (SiO2) layer or a silicon oxynitride layer can be formed on top of it (upper layer).

[0272] STEP 3: Formation of the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42 ( Figure 4C )

[0273] Next, a lower oxide semiconductor film 41 (thickness: for example, 15 nm to 200 nm) and an upper oxide semiconductor film 42 (thickness: for example, 15 nm to 200 nm) are sequentially formed on the lower insulating layer 3, and the resulting stacked film is patterned. Thus, as... Figure 4C As shown, an oxide semiconductor layer 4A, which becomes the active layer of TFT 100, is formed in TFT formation region R1. A laminate 4B' comprising a lower oxide semiconductor film 41 and an upper oxide semiconductor film 42 is formed in TFT formation region R2.

[0274] The lower oxide semiconductor film 41 and the upper oxide semiconductor film 42 can be formed, for example, by sputtering. Here, an In-Ga-Zn-O semiconductor film with a thickness of 40 nm (e.g., In:Ga:Zn = 1:1:1) is formed as the lower oxide semiconductor film 41, and an In-Ga-Zn-O semiconductor film with a thickness of 10 nm (e.g., In:Ga:Zn = 5:1:4) is formed as the upper oxide semiconductor film 42. Furthermore, the composition ratio of each oxide semiconductor film is not limited to the above, but it is preferable that the atomic ratio of In in the upper oxide semiconductor film 42 is greater than the atomic ratio of In in the lower oxide semiconductor film 41 (or, the atomic ratio of Ga in the upper oxide semiconductor film 42 is less than the atomic ratio of Ga in the lower oxide semiconductor film 41). The patterning of the stacked films can be performed, for example, by wet etching using an oxalic acid-based etchant. Thus, the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42 can be etched simultaneously. In this case, in the oxide semiconductor layer 4A, the side surface of the lower oxide semiconductor film 41 is aligned with the side surface of the upper oxide semiconductor film 42.

[0275] Alternatively, an oxide semiconductor film without Sn, such as an In-Ga-Zn-O semiconductor film with a thickness of 40 nm, can be formed as the lower oxide semiconductor film 41, and an oxide semiconductor film containing Sn, such as an In-Sn-Zn-O semiconductor film (e.g., In2O3-SnO2-ZnO) with a thickness of 10 nm, can be formed as the upper oxide semiconductor film 42. Even in this case, it is possible to simultaneously etch the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42 using an oxalic acid-based etchant.

[0276] Annealing can also be performed on the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42 before or after patterning.

[0277] STEP 4: Etching of the upper oxide semiconductor film 42 ( Figure 4D )

[0278] Next, as Figure 4D As shown, the upper oxide semiconductor film 42 is etched, and in the TFT formation region R2, only the upper oxide semiconductor film 42 is removed, leaving the lower oxide semiconductor film 41. Thus, an oxide semiconductor layer 4B, which becomes the active layer of the TFT 200, is formed in the TFT formation region R2. The oxide semiconductor layer 4B includes the lower oxide semiconductor film 41 but not the upper oxide semiconductor film 42.

[0279] The etching of the upper oxide semiconductor film 42 is performed under conditions where the upper oxide semiconductor film 42 is selectively removed while the lower oxide semiconductor film 41 remains. When both the upper and lower oxide semiconductor films 42 and 41 are In-Ga-Zn-O based semiconductor films, the upper oxide semiconductor film 42 can be wet-etched using a PAN-based or oxalic acid-based etchant. The upper oxide semiconductor film 42 has a higher In ratio (or a lower Ga ratio) than the lower oxide semiconductor film 41, and therefore a higher etching rate. Thus, by utilizing the difference in etching rates, the upper oxide semiconductor film 42 can be selectively etched.

[0280] When the upper oxide semiconductor film 42 is an In-Sn-Zn-O semiconductor film or the like containing Sn, and the lower oxide semiconductor film 41 is an In-Ga-Zn-O semiconductor film or the like not containing Sn, by using an oxalic acid-based etching solution and controlling etching conditions such as etching time, not only can the lower oxide semiconductor film 41 be left behind, but the upper oxide semiconductor film 42 can also be removed.

[0281] The etching process in this step is not limited to wet etching; it can also be performed by dry etching. In this case, the surface portion of the lower oxide semiconductor film 41 may sometimes be etched (over-etched).

[0282] STEP 5: Formation of gate insulating film 50 ( Figure 4E )

[0283] Next, as Figure 4E As shown, a gate insulating film 50 is formed in such a way as to cover oxide semiconductor layers 4A and 4B.

[0284] An insulating film identical to the lower insulating layer 3 (exemplified as the lower insulating layer 3) can be used as the gate insulating film 50. Here, a silicon oxide (SiO2) film is formed as the gate insulating film 50. When an oxide film such as silicon oxide is used as the gate insulating film 50, the oxide defects generated in the channel region of the oxide semiconductor layers 4A and 4B can be reduced by the oxide film, thereby suppressing the low resistance of the channel region.

[0285] STEP 6: Formation of gate electrodes 7A and 7B ( Figure 4F )

[0286] Next, a gate conductive film (thickness: for example, 50 nm to 500 nm) is formed on the gate insulating film 50. Then, the gate conductive film is patterned using a known photolithography process. As a result, gate electrodes 7A and 7B are formed in the TFT formation region R1 and TFT formation region R2, respectively. Although not shown, a gate bus is also formed using the gate conductive film. The portions of the oxide semiconductor layers 4A and 4B that overlap with the gate electrodes 7A and 7B when viewed from the normal direction of the substrate 1 become the first regions 4Ac and 4Bc, respectively, containing the channel region.

[0287] For example, metals such as molybdenum (Mo), tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), and tantalum (Ta), or their alloys, can be used as the conductive film for the gate. The conductive film for the gate can also have a stacked structure comprising multiple layers formed of different conductive materials. Here, a Cu / Ti stacked film with a Ti film as the lower layer and a Cu film as the upper layer is used as the conductive film for the gate, or a Cu / Mo stacked film with a Mo film as the lower layer and a Cu film as the upper layer is used as the conductive film for the gate.

[0288] STEP 7: Formation of gate insulating layers 5A and 5B ( Figure 4G )

[0289] Next, the gate insulating film 50 is patterned using the resist mask used for patterning the conductive film for the gate, or by using the gate electrodes 7A and 7B as a mask, to form gate insulating layers 5A and 5B. According to this method, when viewed from the normal direction of the substrate 1, the sides of the gate electrodes 7A and 7B are aligned with the sides of the gate insulating layers 5A and 5B, respectively. However, depending on the etching conditions of each film, misalignment may occur. For example, if the gate electrodes 7A and 7B are over-etched, the sides of the gate electrodes 7A and 7B may be significantly offset from the sides of the resist mask. Subsequently, when dry etching of the gate insulating film 50 is performed using the resist mask, when viewed from the normal direction of the substrate 1, the sides of the gate electrodes 7A and 7B may sometimes be located inside the sides of the gate insulating layers 5A and 5B.

[0290] Alternatively, after patterning the gate insulating film 50, the gate conductive film can be formed and patterned.

[0291] After forming the gate electrodes 7A and 7B, the oxide semiconductor layers 4A and 4B can also undergo a low-resistivity treatment. For example, plasma treatment can be performed as a low-resistivity treatment. As a result, when viewed from the normal direction of the main surface of the substrate 1, the regions (exposed regions) in the oxide semiconductor layers 4A and 4B that do not overlap with the gate electrodes 7A and 7B and the gate insulating layers 5A and 5B become low-resistivity regions with lower resistivity than the regions (including channel regions) that overlap with the gate electrodes 7A and 7B and the gate insulating layers 5A and 5B. The low-resistivity regions can be conductive regions (e.g., sheet resistance: 200 Ω / □ or less). In this embodiment, an oxide semiconductor layer 4A and 4B is obtained that includes a first region 4Ac and 4Bc that overlaps with the gate electrodes 7A and 7B when viewed from the normal direction of the substrate 1, and a low-resistivity region located on both sides of the first region with a resistivity lower than that of the first region 4Ac and 4Bc. Furthermore, the method of low-resistivity treatment is not limited to plasma treatment.

[0292] STEP 8: Formation of interlayer insulation layer 10 ( Figure 4H )

[0293] Next, an interlayer insulating layer 10 is formed, covering oxide semiconductor layers 4A and 4B, gate insulating layers 5A and 5B, and gate electrodes 7A and 7B. Then, the interlayer insulating layer 10 is patterned using a known photolithography process. Thus, as... Figure 4H As shown, in the TFT forming region R1, a first opening 10As and a second opening 10Ad are formed in the interlayer insulating layer 10 to expose the first contact regions 4As and 4Ad, which are part of the low resistance region of the oxide semiconductor layer 4A. In the TFT forming region R2, a first opening 10Bs and a second opening 10Bd are formed in the interlayer insulating layer 10 to expose the contact regions 4Bs and 4Bd, which are part of the low resistance region of the oxide semiconductor layer 4B.

[0294] Inorganic insulating layers such as silicon oxide films, silicon nitride films, silicon oxynitride films, and silicon oxynitride films can be formed as single layers or stacked layers as interlayer insulating layers 10. The thickness of the inorganic insulating layer can be 100 nm or more and 500 nm or less. When an insulating film such as a silicon nitride film that reduces the oxide semiconductor is used to form the interlayer insulating layer 10, the resistivity of the regions in the oxide semiconductor layers 4A and 4B that are in contact with the interlayer insulating layer 10 (in this case, low-resistance regions) can be maintained at a low level, which is therefore preferred. Here, for example, a SiNx layer (thickness: 300 nm) is formed by CVD as the interlayer insulating layer 10.

[0295] When an insulating layer capable of reducing oxide semiconductors (e.g., a hydrogen-donating layer such as a silicon nitride layer) is used as the interlayer insulating layer 10, even without the aforementioned low-resistance treatment, the portions of oxide semiconductor layers 4A and 4B that are in contact with the interlayer insulating layer 10 can be made to have lower resistance than the portions that are not in contact with the interlayer insulating layer 10.

[0296] • STEP 9: Formation of source electrodes 8A and 8B and drain electrodes 9A and 9B ( Figure 4I )

[0297] Next, a source conductive film (thickness: for example, 50 nm to 500 nm) is formed on the interlayer insulating layer 10, and the source conductive film is patterned. Thus, as shown... Figure 4I As shown, source electrodes 8A and 8B and drain electrodes 9A and 9B are formed. Although not shown, a source bus is also formed by the conductive film at the source.

[0298] Source electrodes 8A and 8B are respectively disposed on the interlayer insulating layer 10 and within the openings 10As and 10Bs, and are connected to the first contact regions 4As and 4Bs of the oxide semiconductor layers 4A and 4B within the openings 10As and 10Bs. Drain electrodes 9A and 9B are respectively disposed on the interlayer insulating layer 10 and within the openings 10Ad and 10Bd, and are connected to the second contact regions 4Ad and 4Bd of the oxide semiconductor layers 4A and 4B within the openings 10Ad and 10Bd.

[0299] As the conductive film for the source electrode, elements selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), or tungsten (W), or alloys composed of these elements, can be used. For example, a three-layer structure of titanium film-aluminum film-titanium film, a three-layer structure of molybdenum film-aluminum film-molybdenum film, etc., can be used. Furthermore, the conductive film for the source electrode is not limited to a three-layer structure, but can also have a single-layer or two-layer structure, or a stacked structure of four or more layers. Here, a stacked film with a Ti film (thickness: 15-70 nm) as the lower layer and a Cu film (thickness: 50-400 nm) as the upper layer is used. When a stacked film with an ohmic conductive film such as a Ti film as the lowermost layer is used, the contact resistance with the oxide semiconductor layers 4A and 4B can be reduced more effectively.

[0300] • STEP 10: Formation of inorganic insulating layer 11 and organic insulating layer 12 ( Figure 4J )

[0301] Next, as Figure 4JAs shown, an inorganic insulating layer 11 (thickness: for example, 100 nm or more and 500 nm or less) and an organic insulating layer 12 (thickness: for example, 1 to 4 μm, preferably 2 to 3 μm) are sequentially formed to cover the interlayer insulating layer 10, the source electrodes 8A and 8B, and the drain electrodes 9A and 9B.

[0302] The same inorganic insulating film as the interlayer insulating layer 10 can be used as the inorganic insulating layer 11. Here, for example, a SiNx layer (thickness: 300 nm) is formed by CVD as the inorganic insulating layer 11. The organic insulating layer 12 can be, for example, an organic insulating film containing a photosensitive resin material (e.g., an acrylic resin film).

[0303] Next, the organic insulating layer 12 is patterned. As a result, in each pixel region, an opening 12p is formed in the organic insulating layer 12, exposing a portion of the inorganic insulating layer 11. The opening 12p is configured to overlap with the drain electrode 9B of the TFT 200, which becomes a pixel TFT, when viewed from the normal direction of the substrate 1. During this patterning, the entire portion of the organic insulating layer 12 located in the non-display area may also be removed.

[0304] STEP 11: Formation of the common electrode CE ( Figure 4K )

[0305] Next, as Figure 4K As shown, a first transparent conductive film (thickness: 20–300 nm) is formed on the organic insulating layer 12 and patterned. This forms a common electrode CE in the display area. Metal oxides such as indium zinc oxide, indium tin oxide (ITO), and ZnO can be used as the first transparent conductive film.

[0306] STEP 12: Formation of dielectric layer 17 Figure 4L )

[0307] Next, as Figure 4L As shown, a dielectric layer 17 (thickness: 50-500 nm) is formed to cover the common electrode CE.

[0308] The material of the dielectric layer 17 can be the same as the material exemplified as the inorganic insulating layer 11. Here, for example, a SiN film is formed by CVD as the dielectric layer 17.

[0309] STEP 13: Formation of the pixel electrode PE ( Figure 4M )

[0310] Next, the dielectric layer 17 and the inorganic insulating layer 11 are patterned to form a pixel contact hole CH that exposes the drain electrode 9B of the TFT 200. In this example, the pixel contact hole CH includes an opening in the dielectric layer 17, an opening in the organic insulating layer 12, and an opening in the inorganic insulating layer 11.

[0311] Next, a second transparent conductive film (thickness: 20–300 nm, not shown) is formed on the dielectric layer 17 and within the pixel contact hole CH. The second transparent conductive film can be formed using the same material as the first transparent conductive film. Then, the second transparent conductive film is patterned. Thus, as… Figure 4M As shown, pixel electrodes PE are formed in each pixel region. The pixel electrodes PE are connected to the drain electrode 9B of the TFT 200, which becomes a pixel TFT, within the pixel contact hole CH. In this way, the active matrix substrate 1000 is manufactured.

[0312] The pixel electrode PE and the common electrode CE can be arranged opposite each other with the dielectric layer 17 in between. Here, although an example is shown in which the common electrode CE is arranged on the substrate 1 side of the pixel electrode PE, the common electrode CE can also be arranged on the pixel electrode PE with the dielectric layer 17 in between.

[0313] The manufacturing method of the active matrix substrate 1000 in this embodiment is not limited to the method described above. Figure 4C In the patterning process of the laminated film shown, the upper oxide semiconductor film 42 and the lower oxide semiconductor film 41 may not be etched simultaneously. For example, after the laminated film is formed, only the upper oxide semiconductor film 42 may be etched first, and then the lower oxide semiconductor film 41 may be etched separately.

[0314] Alternatively, it can be used as a substitute Figure 4C and Figure 4D The process shown involves forming oxide semiconductor layers 4A and 4B as follows: First, a lower oxide semiconductor film 41 is formed and patterned to form the lower layer (first layer) of oxide semiconductor layer 4A and oxide semiconductor layer 4B. Next, an upper oxide semiconductor film 42 is formed to cover the patterned lower oxide semiconductor film 41. Afterward, only the upper oxide semiconductor film 42 is patterned to form the upper layer (second layer) of oxide semiconductor layer 4A.

[0315] When the upper oxide semiconductor film 42 and the lower oxide semiconductor film 41 are etched separately, the side surface of the lower oxide semiconductor film 41 may not be aligned with the side surface of the upper oxide semiconductor film 42 in the oxide semiconductor layer 4A. For example, it may be as follows: Figure 20AAs illustrated, the width of the upper oxide semiconductor film 42 is smaller than the width of the lower oxide semiconductor film 41, and when viewed from the normal direction of the substrate 1, the upper oxide semiconductor film 42 is located inside the upper surface of the lower oxide semiconductor film 41. By making the size of the high-mobility oxide semiconductor film smaller than the size of the low-mobility oxide semiconductor film, depletion of the TFT 100 is less likely to occur. Alternatively, it can be as follows: Figure 20B As illustrated, the width of the upper oxide semiconductor film 42 is greater than the width of the lower oxide semiconductor film 41, and the upper oxide semiconductor film 42 covers the upper surface and side surfaces of the lower oxide semiconductor film 41. Thus, the upper oxide semiconductor film 42, as a high-mobility oxide semiconductor film, is exposed on the upper surface and side surfaces of the oxide semiconductor layer 4A. Therefore, through the low-resistivity treatment, the resistivity of the low-resistivity region of the oxide semiconductor layer 4A can be reduced.

[0316] Although the manufacturing method of the active matrix substrate used in a liquid crystal display device has been described above, the active matrix substrate used in an organic EL display device can be manufactured by the same method.

[0317] like Figure 23 As illustrated, in the active matrix substrate used in an organic EL display device, TFTs 100 and 200 can be formed in each pixel region, for example. TFTs 100 and 200 can be used as driving TFTs and selection TFTs for pixel circuits, respectively. A planarization layer 19 is formed on TFTs 100 and 200, and a pixel electrode PE is disposed on the planarization layer 19. The pixel electrode PE is electrically connected to the drain electrode of TFT 200, which serves as the selection TFT. Furthermore, in the case of an organic EL display device using a color filter method, a color filter layer (not shown) can also be disposed between the planarization layer 19 and the inorganic insulating layer 11. Between adjacent pixel regions, a bank (not shown) formed of insulating material is provided on the planarization layer 19 and the pixel electrode PE. In addition, although not shown, an organic EL layer is disposed on the pixel electrode PE, and an upper electrode is disposed on the organic EL layer. For example, the pixel electrode PE functions as an anode, and the upper electrode functions as a cathode. Furthermore, in the case of top-emitting organic EL display devices, it is also possible not to form a light-shielding layer (lower conductive layers 2A, 2B) on each TFT.

[0318] <Variation Example 1>

[0319] Figure 5 This is a schematic cross-sectional view of the first TFT 100 and the second TFT 300 in another active matrix substrate 1001 in this embodiment.

[0320] In the active matrix substrate 1001 of Modified Example 1, the second TFT 300 includes an upper layer p2, which is consistent with... Figure 2 The active matrix substrate 1000 shown is different. Hereinafter, only the differences from the active matrix substrate 1000 will be described, and descriptions of the same configuration will be omitted.

[0321] Like TFTs 100 and 200, TFT 300 has: an oxide semiconductor layer 4C; a gate electrode 7C disposed on a portion of the oxide semiconductor layer 4C with a gate insulating layer 5C in between; and a source electrode 8C and a drain electrode 9C. TFT 300 may also have a lower conductive layer 2C on the substrate 1 side of the oxide semiconductor layer 4C.

[0322] The oxide semiconductor layer 4C has an upper portion p2 that includes an upper oxide semiconductor film 42 but does not include a lower oxide semiconductor film 41. As shown, the entire extent of the oxide semiconductor layer 4C may include the upper oxide semiconductor film 42 but not the lower oxide semiconductor film 41. Furthermore, in this modified example, as long as the first region 4Cc of the oxide semiconductor layer 4C is the lower portion p2 over its entire extent, other regions may include the lower oxide semiconductor film 41.

[0323] Figure 6 This is a graph illustrating the Vg-Id characteristics of TFT100 and TFT300. The horizontal axis of the graph represents the gate-drain voltage Vdg, and the vertical axis represents the drain current Id.

[0324] according to Figure 6 It is known that TFT300 has a lower threshold voltage than TFT100. This can be attributed to the fact that the first region 4Cc of the oxide semiconductor layer 4C of TFT300 contains an upper oxide semiconductor film 42 with high mobility but does not contain a lower oxide semiconductor film 41 with low mobility. Therefore, compared with the oxide semiconductor layer 4A containing the lower oxide semiconductor film 41, the overall mobility of the first region is higher, and the threshold voltage is shifted in the negative direction.

[0325] TFT100 can be used as a pixel TFT, and TFT300 can be used as a TFT for SSD circuits. Using TFT300 in, for example, SSD circuits can increase the on-state current, which is advantageous. TFT300 can also have a depletion characteristic with a negative threshold voltage. This further increases the on-state current of TFT300. Alternatively, TFT100 can be used as a TFT for driving circuits, and TFT300 can be used as a TFT for SSD circuits.

[0326] Alternatively, TFT100 and TFT300 can be mixed in the driving circuit. For example, TFT300 can be used as the output transistor in the gate driving circuit, and TFT100 can be used as other transistors.

[0327] In an active matrix substrate used as the backplane of an organic EL display device, TFT100 and TFT300 can be mixed in the pixel circuits provided in each pixel area. For example, TFT300 with a large conduction current can be used as a selection TFT in the pixel circuit, and TFT100 with a threshold voltage offset in the positive direction compared to TFT300 can be used as a driving TFT.

[0328] In addition, although Figure 6 In the example shown, TFT100 has depletion characteristics, but when TFT100 is used as a TFT for driving circuits or a TFT for driving pixel circuits, TFT100 preferably has enhancement characteristics.

[0329] <Manufacturing Method of Active Matrix Substrate 1001>

[0330] Next, an example of a manufacturing method for the active matrix substrate 1001 will be described with reference to the accompanying drawings. Hereinafter, the materials, thicknesses, and forming processes of each layer will be described in relation to the active matrix substrate 1000 (see attached drawings). Figures 4A to 4M If the same conditions are met, the description is omitted. These figures show the TFT forming region R1 that forms TFT100 and the TFT forming region R3 that forms TFT300.

[0331] Figures 7A to 7C These are schematic cross-sectional views illustrating the manufacturing method of the active matrix substrate 1001.

[0332] like Figure 7A As shown, a lower conductive layer 2A, a lower conductive layer 2C, and a lower insulating layer 3 are formed on substrate 1. Next, as... Figure 7B As shown, after forming a lower oxide semiconductor film 41 on the lower insulating layer 3, the lower oxide semiconductor film 41 is patterned. This removes the portion of the lower oxide semiconductor film 41 located in the TFT formation region R3. The portion of the lower oxide semiconductor film 41 located in the TFT formation region R1 may remain without removal.

[0333] The etching of the lower oxide semiconductor film (e.g., In-Ga-Zn-O semiconductor film) 41 can be performed, for example, by wet etching using PAN-based or oxalic acid-based etchants.

[0334] Next, as Figure 7CAs shown, an upper oxide semiconductor film (e.g., an In-Ga-Zn-O based semiconductor film) 42 is formed to cover the lower insulating layer 3 and the patterned lower oxide semiconductor film 41, and the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42 are patterned. For example, a PAN-based etchant or an oxalic acid-based etchant can be used to pattern both the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42. When a Sn-containing film (e.g., an In-Sn-Zn-O based semiconductor film) is used as the upper oxide semiconductor film 42, an oxalic acid-based etchant can be used to pattern both the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42.

[0335] Therefore, an oxide semiconductor layer 4A having a stacked structure including a lower oxide semiconductor film 41 and an upper oxide semiconductor film 42 is formed in the TFT formation region R1. An oxide semiconductor layer 4C including the upper oxide semiconductor film 42 but not the lower oxide semiconductor film 41 is formed in the TFT formation region R3.

[0336] Subsequently, similarly to the active matrix substrate 1000, a gate insulating layer, a gate electrode, an interlayer insulating layer, a source electrode, and a drain electrode are formed to obtain the active matrix substrate 1001.

[0337] In this modified example, the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42 may not be etched simultaneously. For example, in Figure 7C In the patterning process of the stacked film shown, the upper oxide semiconductor film 42 and the lower oxide semiconductor film 41 can also be etched separately.

[0338] Alternatively, it can be replaced Figure 7B and Figure 7C The process shown is as follows to form oxide semiconductor layers 4A and 4C. First, a lower oxide semiconductor film 41 is formed and patterned to form the first layer of oxide semiconductor layer 4A. Next, an upper oxide semiconductor film 42 is formed to cover the patterned lower oxide semiconductor film 41. Then, only the upper oxide semiconductor film 42 is etched to form the second layer of oxide semiconductor layer 4A and oxide semiconductor layer 4C.

[0339] When the upper oxide semiconductor film 42 and the lower oxide semiconductor film 41 are etched separately, as shown in the reference... Figure 20A and Figure 20B As explained, in the oxide semiconductor layer 4A, the side surface of the lower oxide semiconductor film 41 may not be aligned with the side surface of the upper oxide semiconductor film 42.

[0340] (Second Implementation)

[0341] Hereinafter, the active matrix substrate of the second embodiment will be described with reference to the accompanying drawings. In the following description, the differences from the first embodiment will be mainly explained, and the configurations that are the same as those in the first embodiment will be omitted.

[0342] Figure 8A This is a schematic cross-sectional view showing the first TFT 100 and the second TFT 400 in the active matrix substrate 2000 of this embodiment. Figure 8B This is a schematic top view of the TFT400. Figure 8A The cross-section of the TFT400 shown is Figure 8B The cross section of line VIIIa-VIIIa'.

[0343] In the active matrix substrate 2000, the second TFT 400 has an active layer structure different from that in the aforementioned embodiment, which is consistent with... Figure 2 The active matrix substrate 1000 shown is different. Furthermore, the first TFT 100 has the same characteristics as... Figure 2 The TFT100 shown has the same active layer structure.

[0344] Like TFT100, TFT400 has: an oxide semiconductor layer 4D; a gate electrode 7D disposed on a portion of the oxide semiconductor layer 4D with respect to a gate insulating layer 5D; and a source electrode 8D and a drain electrode 9D. TFT400 may also have a lower conductive layer 2D on the substrate 1 side of the oxide semiconductor layer 4D.

[0345] In TFT400, the oxide semiconductor layer 4D has: a lower layer p1 that includes a lower oxide semiconductor film 41 and does not include an upper oxide semiconductor film 42; and a stacked layer pa that includes the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42.

[0346] In the illustrated example, a portion of the first region 4Dc of the oxide semiconductor layer 4D is the lower layer p1, and the other portion is the stacked portion pa. Both the first contact region 4Ds and the second contact region 4Dd in the oxide semiconductor layer 4D are stacked portions pa. Alternatively, the entire extent of the second region in the oxide semiconductor layer 4D can be the stacked portion pa.

[0347] In the illustrated example, in the oxide semiconductor layer 4D, a second layer 4Us and 4Ud, including an upper oxide semiconductor film 42, are disposed on top of a first layer 4L, including a lower oxide semiconductor film 41, with spaced intervals between them. The portion of the first layer 4L located between the second layers 4Us and 4Ud is referred to as the "lower layer p1". The gate insulating layer 5D is, for example, in contact with the upper surface and side surface of the second layers 4Us and 4Ud, and the exposed portion of the upper surface of the first layer 4L. The width of the channel of the gate electrode 7D in the length direction is greater than the width of the interval between the second layers 4Us and 4Ud (i.e., the width of the lower layer p1). When viewed from the normal direction of the substrate 1, the gate electrode 7D is configured to cover the lower layer p1 and the end of the second layers 4Us and 4Ud on the lower layer p1 side. Other structures are the same as those of the TFTs 200 and 300 in the aforementioned embodiments.

[0348] The same oxide semiconductor film as in the aforementioned embodiment can be used as the upper oxide semiconductor film 42 and the lower oxide semiconductor film 41. However, in this embodiment, the mobility of the upper oxide semiconductor film 42 may be higher or lower than that of the lower oxide semiconductor film 41.

[0349] <Effect>

[0350] When the upper oxide semiconductor film 42 is a high-mobility oxide semiconductor film and the lower oxide semiconductor film 41 is a low-mobility oxide semiconductor film, the Vg-Id characteristics of TFT100 and TFT400 respectively have the same characteristics as... Figure 3 The illustrated TFTs 100 and 200 exhibit the same tendency. That is, the threshold voltage of TFT 400 is shifted in the positive direction compared to TFT 100. This is conceivable because a portion of the first region 4Dc of the oxide semiconductor layer 4D of TFT 400 contains a low-mobility oxide semiconductor film and does not contain a high-mobility oxide semiconductor film. Therefore, compared to an oxide semiconductor layer 4A whose entire first region 4Ac contains a high-mobility oxide semiconductor film, the overall mobility of the first region is lower. With this characteristic, TFT 100 can be used, for example, as a pixel TFT, and TFT 400 can be used, for example, as a TFT for a driving circuit. TFT 100 can have either depletion characteristics or enhancement characteristics. TFT 400 preferably has enhancement characteristics.

[0351] On the other hand, when the upper oxide semiconductor film 42 is a low-mobility oxide semiconductor film and the lower oxide semiconductor film 41 is a high-mobility oxide semiconductor film, the Vg-Id characteristics of TFT100 and TFT400 respectively have the same characteristics as... Figure 6The illustrated TFT100 and TFT300 exhibit the same tendency. That is, the threshold voltage of TFT400 is shifted in the negative direction compared to TFT100. In this case, TFT100 can be used, for example, as a pixel TFT, and TFT400 can be used, for example, as a TFT for SSD circuits.

[0352] The ratio W1 of the width of the lower layer p1 in the channel length direction to the width of the first region 4Dc in the channel length direction (the width of the gate electrode 7D) is not particularly limited, and can be, for example, more than 1 / 3 and less than 9 / 10. Alternatively, the width of the lower layer p1 in the channel length direction can be more than 3μm and less than 30μm. By adjusting the ratio W1 or the width of the lower layer p1, the threshold voltage of the TFT400 can be controlled.

[0353] As mentioned earlier, in existing top-gate TFTs, if the oxide semiconductor layer is thin during the etching process that forms the opening in the interlayer insulating layer to expose the oxide semiconductor layer, the portion of the oxide semiconductor layer located within the opening in the interlayer insulating layer may be removed in the thickness direction. As a result, the contact resistance between the oxide semiconductor layer and the source / drain electrodes increases, potentially preventing the desired conduction characteristics from being achieved. Furthermore, it is also possible that the oxide semiconductor layer is not electrically connected to the source / drain electrodes, thus failing to function as a TFT.

[0354] In contrast, according to this embodiment, the contact regions 4As, 4Ad, 4Ds, and 4Dd of the oxide semiconductor layers 4A and 4D have a stacked structure and sufficient thickness. Therefore, during the etching process of the interlayer insulating layer 10, even if the surface portions of the first contact region 4Ds and the second contact region 4Dd of the oxide semiconductor layer 4D are removed, the portions underneath will not be removed and will remain. Therefore, the increase in contact resistance between the oxide semiconductor layers 4A and 4D and the source / drain electrodes 8A, 8D, 9A, and 9D can be suppressed.

[0355] Thus, in the active matrix substrate 2000, the oxide semiconductor layer 4A of TFT100 and the oxide semiconductor layer 4D of TFT400 can have first contact regions 4As, 4Ds and second contact regions 4Ad, 4Dd with a stacked structure, and the structures of the first regions 4Ac, 4Dc containing the channel region can be made different from each other. Therefore, the increase in contact resistance with the source / drain electrodes can be suppressed, and the characteristics of TFT400 and TFT100 can be made different.

[0356] The mobility of the upper oxide semiconductor film 42 can be higher or lower than that of the lower oxide semiconductor film 41. The choice between the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42 as the high-mobility oxide semiconductor film can be made depending on the application of the TFTs 100 and 400.

[0357] When the upper oxide semiconductor film 42 has a higher mobility than the lower oxide semiconductor film 41, the following advantages are achieved.

[0358] By placing the high-mobility oxide semiconductor film closer to the gate electrode 7A, the threshold voltage of the TFT100 can be increased.

[0359] Furthermore, if a high-mobility oxide semiconductor film is made low-resistivity, a low-resistivity region with lower resistivity can be obtained compared to making a low-mobility oxide semiconductor film low-resistivity. Therefore, if the high-mobility oxide semiconductor film is removed from the second region of the oxide semiconductor layer, the resistivity of the second region may increase, and the effective conduction current of the TFT may decrease. In contrast, in Figure 8A In the example shown, TFT400, like TFT100, has its entire second region in its oxide semiconductor layer 4D, which is not covered by the gate electrode 7D when viewed from the normal direction of the substrate 1, comprising an upper oxide semiconductor film 42 as a high-mobility oxide semiconductor film in the uppermost layer. Therefore, compared to the case where the second region does not contain a high-mobility oxide semiconductor film (e.g., Figure 2 The TFT 200 shown can reduce the resistivity of the low-resistivity region, thus suppressing the decrease in the effective conduction current of the TFTs 100 and 400. When the interlayer insulating layer 10 is an insulating layer capable of reducing the oxide semiconductor, the upper surface of the upper oxide semiconductor film 42 can also be in direct contact with the interlayer insulating layer 10. This further reduces the resistivity of the low-resistivity region.

[0360] On the other hand, when the lower oxide semiconductor film 41 has a higher mobility than the upper oxide semiconductor film 42, the following advantages are available.

[0361] When openings 10As, 10Ad, 10Bs, and 10Bd are formed in the interlayer insulating layer 10 to connect the source and drain electrodes to the oxide semiconductor layers 4A and 4B, the surface portions of the oxide semiconductor layers 4A and 4B are sometimes etched. Even in this case, the lower oxide semiconductor film 41, which is a high-mobility semiconductor film, is not etched and remains, thus the contact resistance between the source and drain electrodes and the oxide semiconductor layers 4A and 4B can be kept low.

[0362] Furthermore, when using an insulating layer that can reduce oxide semiconductors as the lower insulating layer 3, and utilizing the film of the lower insulating layer 3 to reduce the resistance of oxide semiconductor layers 4A and 4B, by configuring the lower oxide semiconductor film 41 with high mobility to contact the lower insulating layer 3, the resistance of the low resistance region can be further reduced.

[0363] <Manufacturing Method of Active Matrix Substrate 2000>

[0364] Next, an example of a manufacturing method for the active matrix substrate 2000 will be described with reference to the accompanying drawings. Hereinafter, the materials, thicknesses, and forming processes of each layer will be compared with those of the active matrix substrate 1000 (see attached drawings). Figures 4A to 4M If the same conditions are met, the description is omitted. These figures show the TFT forming region R1 that forms TFT100 and the TFT forming region R4 that forms TFT400.

[0365] Figures 9A to 9E This is a schematic cross-sectional view illustrating the manufacturing method of the active matrix substrate 2000.

[0366] like Figure 9A As shown, a lower conductive layer 2A, a lower conductive layer 2D, and a lower insulating layer 3 are formed on substrate 1. Next, as... Figure 9B As shown, a lower oxide semiconductor film 41 and an upper oxide semiconductor film 42 are sequentially formed on the lower insulating layer 3, and a pattern of a stacked film including the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42 is performed. Thus, an oxide semiconductor layer 4A having a stacked structure including the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42 is formed in the TFT formation region R1. A stacked body 4D' including the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42 is formed in the TFT formation region R4.

[0367] Here, an In-Ga-Zn-O semiconductor film with a thickness of, for example, 10 nm (e.g., In:Ga:Zn = 5:1:4) can be formed as the film with higher mobility (high-mobility oxide semiconductor film) between the upper oxide semiconductor film 42 and the lower oxide semiconductor film 41, and an In-Ga-Zn-O semiconductor film with a thickness of, for example, 40 nm (e.g., In:Ga:Zn = 1:1:1) can be formed as the low-mobility oxide semiconductor film. The patterning of the stacked films can be performed, for example, by wet etching using a PAN-based etchant or an oxalic acid-based etchant. This allows for the simultaneous etching of both the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42.

[0368] Alternatively, an oxide semiconductor film containing Sn, such as an In-Sn-Zn-O semiconductor film (e.g., In₂O₃-SnO₂-ZnO) with a thickness of 10 nm, can be formed as a high-mobility oxide semiconductor film, while an oxide semiconductor film without Sn, such as an In-Ga-Zn-O semiconductor film with a thickness of 40 nm, can be formed as a low-mobility oxide semiconductor film. Even in this case, it is possible to simultaneously etch the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42 using an oxalic acid-based etchant.

[0369] Next, as Figure 9C As shown, in the TFT formation region R4, a portion of the upper oxide semiconductor film 42 is removed, exposing a portion of the lower layer (first layer) 4L, which includes the lower oxide semiconductor film 41. Here, upper layers (second layers) 4Us and 4Ud are formed from the upper oxide semiconductor film 42, spaced apart from each other. The exposed portion of the lower oxide semiconductor film 41 becomes the lower layer p1. Thus, an oxide semiconductor layer 4D comprising the first layer 4L and the second layers 4Us and 4Ud is formed in the TFT formation region R4.

[0370] The etching of the upper oxide semiconductor film 42 is performed under the method and conditions in which the upper oxide semiconductor film 42 is selectively removed and the lower oxide semiconductor film 41 is not removed and remains.

[0371] When the upper oxide semiconductor film 42 is a high-mobility oxide semiconductor film, the etching method of the upper oxide semiconductor film 42 can be the same as that used in the reference method. Figure 4D The etching method for the upper oxide semiconductor film 42 described herein is the same.

[0372] If the upper oxide semiconductor film 42 is a low-mobility oxide semiconductor film, and both the upper oxide semiconductor film 42 and the lower oxide semiconductor film 41 are In-Ga-Zn-O based semiconductor films, wet etching can be performed using a PAN-based etchant or an oxalic acid-based etchant. To prevent the lower oxide semiconductor film 41 from being removed, the upper oxide semiconductor film 42 can be etched by controlling conditions such as etching time.

[0373] If the upper oxide semiconductor film 42 is an oxide semiconductor film that does not contain Sn and the lower oxide semiconductor film 41 is an oxide semiconductor film that contains Sn, then the upper oxide semiconductor film 42 can be selectively etched by using a PAN-based etching solution.

[0374] The etching process in this step is not limited to wet etching; it can also be performed by dry etching. In this case, the surface portion of the lower oxide semiconductor film 41 may sometimes be etched (over-etched).

[0375] The composition of each oxide semiconductor film is illustrated in Table 1. When etching the stack of films containing these oxide semiconductor films together ( Figure 9B The etching solution used, and when etching only the upper oxide semiconductor film ( Figure 9C The etching solution used. When both oxide semiconductor films are In-Ga-Zn-O semiconductor films, the relationship between the In ratio (or Ga ratio) of the lower oxide semiconductor film 41 and the In ratio (or Ga ratio) of the upper oxide semiconductor film 42 is also shown in Table 1.

[0376] Table 1

[0377]

[0378] Next, as Figure 9D As shown, gate insulating layers 5A and 5D and gate electrodes 7A and 7D are formed on a portion of oxide semiconductor layers 4A and 4D. Viewed from the normal direction of substrate 1, the gate electrode 7D is configured to span the lower layer p1 in the oxide semiconductor layer 4D, covering the end of the second layers 4Us and 4Ud on the lower layer p1 side. Then, as... Figure 9E As shown, an interlayer insulating layer 10 is formed. Here, the interlayer insulating layer 10 is in contact only with the upper oxide semiconductor film 42 in the oxide semiconductor layers 4A and 4D, and is not in contact with the lower oxide semiconductor film 41.

[0379] Subsequently, source electrodes and drain electrodes are formed in the same manner as in the active matrix substrate 1000 to obtain the active matrix substrate 2000.

[0380] In this embodiment, the upper oxide semiconductor film 42 and the lower oxide semiconductor film 41 may not be etched simultaneously. In the case where these semiconductor films are etched separately, as shown in the reference... Figure 20A and Figure 20B As explained, the side surface of the lower oxide semiconductor film 41 may not be aligned with the side surface of the upper oxide semiconductor film 42.

[0381] As an example, another scenario could be where the upper oxide semiconductor film 42 is an In-Ga-Zn-O semiconductor film and the lower oxide semiconductor film 41 is an oxide semiconductor film containing Sn. Figure 9B In the patterning process of the laminated film shown, firstly, the upper oxide semiconductor film 42 is selectively etched using a PAN-based etchant, and then the lower oxide semiconductor film 41 is etched using an oxalic acid-based etchant.

[0382] Alternatively, it can be replaced Figure 9B and Figure 9CThe process shown is as follows to form oxide semiconductor layers 4A and 4D. First, as... Figure 21A As shown, after forming the stacked films, only the upper oxide semiconductor film 42 is selectively etched. Thus, the second layer of oxide semiconductor layer 4A and the second layers 4Us and 4Ud of oxide semiconductor layer 4D are formed from the upper oxide semiconductor film 42. For example, if the upper oxide semiconductor film 42 does not contain Sn and the lower oxide semiconductor film 41 is an oxide semiconductor film containing Sn, it is advantageous to selectively etch only the upper oxide semiconductor film 42 by using a PAN-based etching solution (see Table 1). Next, as... Figure 21B As shown, the lower oxide semiconductor film 41 is etched to form the first layer of oxide semiconductor layers 4A and 4D.

[0383] Moreover, although not shown in the diagram, it can be used as a substitute. Figure 9B and Figure 9C The process shown involves forming and patterning the lower oxide semiconductor film 41, and after forming the first layer of oxide semiconductor layers 4A and 4D, forming and patterning the upper oxide semiconductor film 42.

[0384] <Variation Example 2>

[0385] Figure 10A This is a schematic cross-sectional view showing the first TFT 100 and the second TFT 500 in another active matrix substrate 1002 in this embodiment. Figure 10B This is a schematic top view of the TFT500. Figure 10A The cross-section of the TFT500 shown is Figure 10B The cross section of the Xa-Xa' line.

[0386] The first TFT100 in Modified Example 2 has the same as Figure 2 The TFT100 shown has the same structure, so its description is omitted.

[0387] Like TFTs 100 and 400, TFT 500 has: an oxide semiconductor layer 4E; a gate electrode 7E disposed on a portion of the oxide semiconductor layer 4E with a gate insulating layer 5E in between; and a source electrode 8E and a drain electrode 9E. TFT 500 may also have a lower conductive layer 2E on the substrate 1 side of the oxide semiconductor layer 4E.

[0388] In TFT500, the entire range of region 4Ec is the lower layer p1 that includes the lower oxide semiconductor film 41 but does not include the upper oxide semiconductor film 42, which is consistent with... Figure 8A and Figure 8BThe TFT400 shown is different. The first contact region 4Es and the second contact region 4Ed in the oxide semiconductor layer 4E are both stacked portions pa that include the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42. In addition, a portion of the oxide semiconductor layer 4E that does not overlap with the gate electrode 7E when viewed from the normal direction of the substrate 1 (the second region) may not include the upper oxide semiconductor film 42.

[0389] In the illustrated example, in the oxide semiconductor layer 4E, two second layers 4Us and 4Ud, including an upper oxide semiconductor film 42, are disposed on a first layer 4L, including a lower oxide semiconductor film 41, and are positioned opposite each other at a distance. The portion of the first layer 4L located between the second layers 4Us and 4Ud is called the "lower layer p1". The width of the channel of the gate electrode 7D in the length direction is smaller than the width of the gap between the second layers 4Us and 4Ud (i.e., the width of the lower layer p1). When viewed from the normal direction of the substrate 1, the gate electrode 7E is disposed on a portion of the lower layer p1 and does not overlap with the second layers 4Us and 4Ud. The second region in the oxide semiconductor layer 4E that does not overlap with the gate electrode 7E when viewed from the normal direction of the substrate 1 includes a portion of the lower layer p1 and the stacked portion pa. The structure other than the active layer is the same as that of the TFT 400 in the aforementioned embodiment.

[0390] In this modified example, the increase in contact resistance between the oxide semiconductor layers 4A, 4E and the source / drain electrodes 8A, 8E, 9A, 9E in TFTs 100 and 500 can also be suppressed, and the characteristics of these TFTs can be made different. Similarly, in this modified example, the mobility of the lower oxide semiconductor film 41 can be higher or lower than that of the upper oxide semiconductor film 42. The relationship between the threshold voltages of TFTs 100 and TFT 500 is the same as that of the active matrix substrate 2000.

[0391] Furthermore, in the case where the upper oxide semiconductor film 42 is a high-mobility oxide semiconductor film, a portion of the second region of the TFT 500 also contains a high-mobility oxide semiconductor film. Therefore, with... Figure 2 Compared to the TFT200 shown, the second region (low-resistance region) can be made smaller, thus suppressing the decrease in effective on-current. Furthermore, from the viewpoint of ensuring effective on-current, as... Figure 8A and Figure 8B It is more preferable that the entire second region, as shown in the TFT400, has a structure containing a high-mobility oxide semiconductor film.

[0392] The active matrix substrate 2001 of this variant can be manufactured using the same method as the active matrix substrate 2000. However, the second layers 4Us and 4Ud are configured with a spacing that is sufficiently large than the width of the gate electrode. In addition, the gate insulating layer 5E and the gate electrode 7E are disposed on a portion of the area of ​​the lower oxide semiconductor film 41 exposed from the upper oxide semiconductor film 42.

[0393] <Variation Example 3>

[0394] The active matrix substrate of this embodiment may include a plurality of second TFTs in which the proportion W1 of the lower layer p1 in the first region of the oxide semiconductor layer is different from each other.

[0395] Figure 11 This is a cross-sectional view showing three oxide semiconductor TFTs in the active matrix substrate 2002 of Modified Example 3.

[0396] exist Figure 11 In the example shown, the active matrix substrate 2002 includes: a TFT 100 (W1 = 0); a TFT 400 (W1: for example, more than 1 / 3 and less than 9 / 10) in which only a portion of the first region of the oxide semiconductor layer is the lower layer p1; and a TFT 500 (W1 = 1) in which the entire first region is the lower layer p1. TFTs 400 and 500 each have a reference... Figure 8A , 8B as well as Figure 10A , 10B The aforementioned structure and characteristics. Although not illustrated, it can also be used instead of TFT500. Figure 2 TFT 200 (W1=1) illustrated in A.

[0397] When the lower oxide semiconductor film has a lower mobility than the upper oxide semiconductor film, a larger ratio W1 results in a lower overall mobility of the first region, and therefore a greater shift of the threshold voltage in the positive direction. In this example, TFT100 (W=0) has the lowest threshold voltage, and the threshold voltage increases in the order of TFT400 and TFT500. On the other hand, when the lower oxide semiconductor film has a higher mobility than the upper oxide semiconductor film, a larger ratio W1 results in a higher overall mobility of the first region, and therefore a greater shift of the threshold voltage in the negative direction. In this example, TFT100 (W=0) has the highest threshold voltage, and the threshold voltage decreases in the order of TFT400 and TFT500.

[0398] Thus, according to this modified example, three TFTs with different characteristics can be fabricated separately using the same process as the active matrix substrates 2000 and 2001 (without adding a masking process). Furthermore, in this specification, when the active matrix substrate has two second TFTs with different active layer structures, one of the two second TFTs is sometimes referred to as the "third TFT".

[0399] (Third Implementation)

[0400] Hereinafter, the active matrix substrate of the third embodiment will be described with reference to the accompanying drawings. In the following description, the differences from the second embodiment will be mainly explained, and the same configurations as the second embodiment will be omitted from the description.

[0401] Figure 12A This is a schematic cross-sectional view showing the first TFT 100 and the second TFT 600 in the active matrix substrate 3000 of this embodiment. Figure 12B This is a schematic top view of the TFT600. Figure 12A The cross-section of the second TFT600 shown is Figure 12B The cross section of line XIIa-XIIa'.

[0402] In the active matrix substrate 3000, the second TFT 600 has an active layer structure including the upper layer p2, which is different from the active matrix substrate 2000 of the aforementioned embodiment. Figure 8A , Figure 8B ) is different. Furthermore, the first TFT100 has the same characteristics as... Figure 2 The TFT100 shown has the same active layer structure.

[0403] Like TFT100, TFT600 has: an oxide semiconductor layer 4F; a gate electrode 7F disposed on a portion of the oxide semiconductor layer 4F with a gate insulating layer 5F in between; and a source electrode 8F and a drain electrode 9F. TFT600 may also have a lower conductive layer 2F on the substrate 1 side of the oxide semiconductor layer 4F.

[0404] In the TFT600, the oxide semiconductor layer 4F has: an upper portion p2, which includes an upper oxide semiconductor film 42 but does not include a lower oxide semiconductor film 41; and a stacked portion pa, which includes a lower oxide semiconductor film 41 and an upper oxide semiconductor film 42. Here, a portion of the first region 4Fc of the oxide semiconductor layer 4F is the upper portion p2, and another portion is the stacked portion pa. Furthermore, the first contact region 4Fs and the second contact region 4Fd in the oxide semiconductor layer 4F are both stacked portions pa. As shown, the entire range of the second region in the oxide semiconductor layer 4F can be the stacked portion pa.

[0405] In the illustrated example, in the oxide semiconductor layer 4F, two first layers 4Ls and 4Ld, including the lower oxide semiconductor film 41, are arranged opposite each other with a spaced interval. A second layer 4U, including the upper oxide semiconductor film 42, is formed to cover the first layers 4Ls and 4Ld and their intervals. The portion of the second layer 4U located between the first layers 4Ls and 4Ld is called the "upper layer p2". The width of the channel of the gate electrode 7F in the length direction is greater than the width of the interval between the first layers 4Ls and 4Ld (i.e., the width of the upper layer p2). When viewed from the normal direction of the substrate 1, the gate electrode 7F is configured to cover the upper layer p2 and the end of the first layers 4Ls and 4Ld on the upper layer p2 side. The structure other than the active layer is the same as that of the TFT 400 in the aforementioned embodiment.

[0406] The same oxide semiconductor film as in the aforementioned embodiment can be used as the upper oxide semiconductor film 42 and the lower oxide semiconductor film 41. In this embodiment, the mobility of the upper oxide semiconductor film 42 can be higher or lower than that of the lower oxide semiconductor film 41.

[0407] <Effect>

[0408] When the upper oxide semiconductor film 42 is a high-mobility oxide semiconductor film and the lower oxide semiconductor film 41 is a low-mobility oxide semiconductor film, the Vg-Id characteristics of TFT100 and TFT600 respectively have the same characteristics as... Figure 6 The illustrated TFTs 100 and 300 exhibit the same tendency. Specifically, the threshold voltage of TFT 600 is shifted negatively compared to TFT 100. This is conceivable because a portion of the first region 4Fc of the oxide semiconductor layer 4F of TFT 600 contains a high-mobility oxide semiconductor film and no low-mobility oxide semiconductor film. Therefore, compared to the entire first region 4Ac, which contains a low-mobility oxide semiconductor film, the overall mobility of the first region is higher. In this case, TFT 100 can be used, for example, as a pixel TFT, and TFT 600 can be used, for example, as a TFT for SSD circuits.

[0409] On the other hand, when the upper oxide semiconductor film 42 is a low-mobility oxide semiconductor film and the lower oxide semiconductor film 41 is a high-mobility oxide semiconductor film, the Vg-Id characteristics of TFT100 and TFT600 respectively have the same characteristics as... Figure 3The illustrated TFTs 100 and 200 exhibit the same tendency. That is, the threshold voltage of TFT 600 is shifted in the positive direction compared to TFT 100. In this case, TFT 100 can be used, for example, as a pixel TFT, and TFT 600 can be used, for example, as a TFT for a driving circuit. TFT 100 can have depletion characteristics or enhancement characteristics. TFT 600 preferably has enhancement characteristics.

[0410] The ratio W2 of the width of the upper layer p2 in the channel length direction to the width of the first region 4Fc in the channel length direction (the width of the gate electrode 7F) is not particularly limited, and can be, for example, more than 1 / 3 and less than 9 / 10. Alternatively, the width of the lower layer p2 in the channel length direction can be more than 3μm and less than 30μm. By adjusting the ratio W2 or the width of the upper layer p2, the threshold voltage of the TFT600 can be controlled.

[0411] In this embodiment, the first contact regions 4As, 4Fs and the second contact regions 4Ad, 4Fd of the oxide semiconductor layers 4A, 4F in TFTs 100 and 600 are all stacked portions p1 and are thicker than the upper layer p2. Therefore, the increase in contact resistance between the oxide semiconductor layers 4A, 4F and the source / drain electrodes 8A, 8F, 9A, 9F can be suppressed. Thus, the contact resistance in TFTs 100 and 600 can be suppressed, and the characteristics of TFTs 100 and 600 can be made different.

[0412] In the aforementioned embodiments, when only the upper oxide semiconductor film 42 is etched, it is preferable to select the materials of the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42 based on the etching method. In contrast, in this embodiment, as described later, by first etching only the lower oxide semiconductor film 41, and then etching both the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42, oxide semiconductor layers 4A and 4F can be formed. Therefore, the step of etching only the upper oxide semiconductor film 42 is unnecessary, allowing for greater freedom in selecting the composition and composition ratio of the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42.

[0413] <Manufacturing Method of Active Matrix Substrate 3000>

[0414] Next, an example of a manufacturing method for the active matrix substrate 3000 will be described with reference to the accompanying drawings. Hereinafter, the materials, thicknesses, and forming processes of each layer will be compared with those of the active matrix substrate 1001 (see attached drawing). Figures 7A to 7C If the same conditions are met, the description is omitted. These figures show the TFT forming region R1 that forms TFT100 and the TFT forming region R6 that forms TFT600.

[0415] Figures 13A to 13D This is a schematic cross-sectional view illustrating the manufacturing method of the active matrix substrate 3000.

[0416] like Figure 13A As shown, a lower conductive layer 2A, a lower conductive layer 2F, and a lower insulating layer 3 are formed on substrate 1. Next, as... Figure 13B As shown, a lower oxide semiconductor film 41 is formed on the lower insulating layer 3, and the lower oxide semiconductor film 41 is patterned. This removes a portion of the lower oxide semiconductor film 41 located in the TFT formation region R6, forming an opening 41p. The width x of the opening 41p defines the width of the upper layer. The patterning of the lower oxide semiconductor film 41 can be performed by wet etching or dry etching. Wet etching can use oxalic acid-based etching solutions or PAN-based etching solutions.

[0417] Next, an upper oxide semiconductor film 42 is formed to cover the lower oxide semiconductor film 41. The upper oxide semiconductor film 42 is formed on the lower insulating layer 3, on the lower oxide semiconductor film 41, and within the opening 41p. Then, the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42 are patterned. The lower oxide semiconductor film 41 and the upper oxide semiconductor film 42 can also be etched simultaneously. When etching is performed simultaneously, the same etching solution as in the aforementioned embodiment can be used (Table 1). Thus, as... Figure 13C As shown, an oxide semiconductor layer 4A with a stacked structure including a lower oxide semiconductor film 41 and an upper oxide semiconductor film 42 is formed in the TFT formation region R1. In the TFT formation region R6, an oxide semiconductor layer 4F is obtained having two lower layers (first layers) 4Ls and 4Ld formed by the lower oxide semiconductor film 41, and an upper layer (second layer) 4U formed by the upper oxide semiconductor film 42. A portion of the second layer 4U is disposed at the interval between the first layers 4Ls and 4Ld, forming the upper layer portion p2.

[0418] Next, as Figure 13D As shown, gate insulating layers 5A and 5F, and gate electrodes 7A and 7F are formed on a portion of oxide semiconductor layers 4A and 4F. When viewed from the normal direction of substrate 1, gate electrode 7F is configured to span the lower layer p2 in oxide semiconductor layer 4F and cover the end of the lower layer p2 side of the first layers 4Ls and 4Ld.

[0419] Subsequently, the interlayer insulating layer, source electrode, and drain electrode are formed in the same manner as the active matrix substrate 1000 to obtain the active matrix substrate 3000.

[0420] Furthermore, in this embodiment, similarly to the aforementioned embodiments, in Figure 13C In the etching process of the stacked film shown, the upper oxide semiconductor film 42 and the lower oxide semiconductor film 41 can also be etched separately.

[0421] Alternatively, it can be replaced Figure 13B and Figure 13C The process shown is as follows to form oxide semiconductor layers 4A and 4B. First, as... Figure 22A As shown, the lower oxide semiconductor film 41 is formed and patterned to form the first layer of oxide semiconductor layer 4A and the first layers 4Ls and 4Ld of oxide semiconductor layer 4B. Next, as... Figure 22B As shown, after forming the upper oxide semiconductor film 42 to cover the lower oxide semiconductor film 41, only the upper oxide semiconductor film 42 is selectively etched. This forms the second layer of oxide semiconductor layers 4A and 4B. For example, if the upper oxide semiconductor film 42 is an In-Ga-Zn-O based semiconductor film and the lower oxide semiconductor film 41 is an oxide semiconductor film containing Sn, it is advantageous to selectively etch only the upper oxide semiconductor film 42 using a PAN-based etchant (see Table 1). Figure 22B In the case of the substrate 1, when viewed from the normal direction, the side of the upper oxide semiconductor film 42 is located inside the side of the lower oxide semiconductor film 41 (the side opposite to the channel in the first layer 4Ls, 4Ld).

[0422] Furthermore, during the etching of the upper oxide semiconductor film 42, it is also possible to... Figure 22C As illustrated, the upper oxide semiconductor film 42 is formed in such a way that it covers the upper surface and side surfaces of the lower oxide semiconductor film 41. That is, when viewed from the normal direction of the substrate 1, the lower oxide semiconductor film 41 may also be located inside the upper oxide semiconductor film 42.

[0423] <Variation Example 4>

[0424] Figure 14A This is a schematic cross-sectional view showing the first TFT 100 and the second TFT 700 in another active matrix substrate 3001 in this embodiment. Figure 14B This is a schematic top view of the TFT700. Figure 14A The cross-section of the TFT700 shown is Figure 14B The cross section of the XIVa-XIVa' line.

[0425] The first TFT100 in Modification Example 4 has the same as Figure 2 The TFT100 shown has the same active layer structure, so its description is omitted.

[0426] Like TFTs 100 and 600, TFT 700 has: an oxide semiconductor layer 4G; a gate electrode 7G disposed on a portion of the oxide semiconductor layer 4G with a gate insulating layer 5G in between; and a source electrode 8G and a drain electrode 9G. TFT 700 may also have a lower conductive layer 2G on the substrate 1 side of the oxide semiconductor layer 4G.

[0427] In TFT700, the entire extent of the first region 4Gc of the oxide semiconductor layer 4G is the upper layer p2 that includes the upper oxide semiconductor film 42 but does not include the lower oxide semiconductor film 41, which is consistent with... Figure 12A and Figure 12B The TFT600 shown is different. The first contact region 4Gs and the second contact region 4Gd in the oxide semiconductor layer 4G are both stacked portions pa that include the lower oxide semiconductor film 41 and the upper oxide semiconductor film 42. In addition, a portion of the oxide semiconductor layer 4G that does not overlap with the gate electrode 7G when viewed from the normal direction of the substrate 1 (the second region) may not include the lower oxide semiconductor film 41.

[0428] In the illustrated example, in the oxide semiconductor layer 4G, two first layers 4Ls and 4Ld, including a lower oxide semiconductor film 41, are arranged opposite each other with a spaced interval. A second layer 4U, including an upper oxide semiconductor film 42, is formed to cover the first layers 4Ls and 4Ld and their intervals. The portion of the second layer 4U located between the first layers 4Ls and 4Ld is called the "upper layer p2". The width of the channel of the gate electrode 7G in the length direction is smaller than the width of the interval between the first layers 4Ls and 4Ld (the width of the upper layer p2). When viewed from the normal direction of the substrate 1, the gate electrode 7G is disposed on a portion of the upper layer p2 and does not overlap with the second layers 4Us and 4Ud. The second region in the oxide semiconductor layer 4G that does not overlap with the gate electrode 7G when viewed from the normal direction of the substrate 1 includes a portion of the upper layer p2 and the stacked portion pa. The structure other than the active layer is the same as that of the TFT 600 in the aforementioned embodiment.

[0429] In this modified example, the increase in contact resistance between the oxide semiconductor layers 4A, 4G and the source / drain electrodes 8A, 8G, 9A, 9G in TFTs 100 and 700 can also be suppressed, and the characteristics of these TFTs can be made different. Similarly, in this modified example, the mobility of the lower oxide semiconductor film 41 can be higher or lower than that of the upper oxide semiconductor film 42. The relationship between the threshold voltages of TFTs 100 and TFT 700 is the same as that of the active matrix substrate 3000.

[0430] The active matrix substrate 3001 of this modified example can be manufactured using the same method as the active matrix substrate 3000. However, the width of the channel in the longitudinal direction of the opening 41p formed in the lower oxide semiconductor film 41 is set to be sufficiently larger than the width of the gate electrode 7F. In addition, the gate insulating layer 5E and the gate electrode 7F are disposed on a portion of the upper layer p2 of the upper oxide semiconductor film 42.

[0431] <Variation Example 5>

[0432] The active matrix substrate of this embodiment may include a plurality of second TFTs in which the proportion W2 of the upper layer p2 in the first region of the oxide semiconductor layer is different from each other.

[0433] Figure 15 This is a cross-sectional view showing three oxide semiconductor TFTs in the active matrix substrate 3002 of Modified Example 5.

[0434] exist Figure 15 In the example shown, the active matrix substrate 3002 includes: a TFT 100 (W2 = 0); a TFT 600 (W2: for example, more than 1 / 3 and less than 9 / 10) in which only a portion of the first region of the oxide semiconductor layer is the upper layer p2; and a TFT 700 (W2 = 1) in which the entire first region is the upper layer p2. TFTs 600 and 700 each have a reference... Figure 12A and Figure 14A The aforementioned structure and characteristics. Although not illustrated, it can also be used instead of TFT700. Figure 5 TFT300 (W2=1) illustrated in A.

[0435] When the upper oxide semiconductor film has a higher mobility than the lower oxide semiconductor film, the larger the ratio W2, the higher the overall mobility of the first region, and therefore the greater the negative shift of the threshold voltage. In this example, TFT100 (W=0) has the highest threshold voltage, and the threshold voltage decreases in the order of TFT600 and TFT700.

[0436] Thus, according to this modified example, three TFTs with different characteristics can be fabricated separately using the same process as the active matrix substrates 3000 and 3001 (without adding a mask process).

[0437] (Fourth implementation)

[0438] The active matrix substrate of this embodiment has three or more oxide semiconductor TFTs with different active layer structures.

[0439] In this embodiment, the active matrix substrate includes a TFT including an upper layer p2 and a TFT including a lower layer p1 as a second TFT, which is different from the previous embodiment.

[0440] Figure 16 This is a schematic cross-sectional view illustrating three oxide semiconductor TFTs in the active matrix substrate 4000 of this embodiment.

[0441] The active matrix substrate 4000 includes: a TFT 100 as a first TFT; a TFT 700 having an upper layer p2 in a first region; and a TFT 200 having a lower layer p1 in a first region. TFTs 100, 700, and 200 have the same structure and characteristics as TFTs 100, 700, and 200 in the aforementioned embodiments and can be used for the same purposes.

[0442] The active matrix substrate 4000 can be manufactured using the same method as in the aforementioned embodiments. However, an etching process for forming the oxide semiconductor layer of each TFT is added. Specifically, in this embodiment, after etching the lower oxide semiconductor film, an upper oxide semiconductor film is formed, and both the lower and upper oxide semiconductor films are etched together. Next, only the upper oxide semiconductor film is etched. The etching methods and conditions can be the same as in the aforementioned embodiments.

[0443] Figure 17 This diagram illustrates the Id-Vg characteristics of TFTs 100, 700, and 200 when the lower oxide semiconductor film has a lower mobility than the upper oxide semiconductor film. The threshold voltage of TFT 700, which has the highest overall mobility in Region 1, is shifted negatively compared to TFT 100, while the threshold voltage of TFT 200, which has the lowest overall mobility in Region 1, is shifted positively compared to TFT 100.

[0444] In the active matrix substrate used in a liquid crystal display device, for example, TFT100 can be used as a pixel TFT, TFT700 can be used as a TFT for the SDD circuit, and TFT200 can be used as a TFT for the driving circuit. In addition to TFT200, the TFT for the driving circuit can also include TFT700 as an output transistor.

[0445] In the active matrix substrate used in organic EL display devices, for example, TFT100 can be used as a TFT for driving circuit, TFT700 can be used as a TFT for selecting pixel circuit, and TFT200 can be used as a TFT for driving pixel circuit.

[0446] Furthermore, when the lower oxide semiconductor film has a higher mobility than the upper oxide semiconductor film, the threshold voltage of TFT700 is shifted in the positive direction compared to TFT100, and the threshold voltage of TFT200 is shifted in the negative direction compared to TFT100.

[0447] Figure 18 and Figure 19 These are schematic cross-sectional views of three oxide semiconductor TFTs in another active matrix substrate 4001 and 4002, illustrating this embodiment.

[0448] Figure 18 The active matrix substrate 4001 shown includes: a TFT 100; a TFT 700 having an upper layer p2 in the first region of the oxide semiconductor layer; and a TFT 400 having a lower layer p1 in the first region of the oxide semiconductor layer.

[0449] Figure 19 The active matrix substrate 4002 shown includes: TFT 100; TFT 300 with an upper layer p2 in the first region of the oxide semiconductor layer; and TFT 200 with a lower layer p1 in the first region of the oxide semiconductor layer.

[0450] The TFTs included in the active matrix substrate of this embodiment are not limited to the examples shown in the figure, and various TFTs described above can be used in combination.

[0451] <Circuit configuration using TFT>

[0452] Hereinafter, an example of the circuit configuration formed monolithically on the active matrix substrate of the first to fourth embodiments will be described.

[0453] • Structure and operation of the gate drive circuit

[0454] The gate drive circuitry includes a shift register. The shift register contains multiple unit shift registers connected in multiple stages.

[0455] Figure 24 This is a diagram illustrating a shift register circuit.

[0456] The shift register circuit has multiple unit shift register circuits SR1 to SRz (z: an integer greater than or equal to 2) (hereinafter collectively referred to as "unit shift register circuits SR"). Each unit shift register circuit SR has a set terminal S for receiving a set signal, an output terminal Z for outputting an output signal, a reset terminal R for receiving a reset signal, and clock input terminals CK1 and CK2 for receiving clock signals GCK1 and GCK2. In unit shift register circuit SRα (α≥2), the set terminal S is input to the output signal of the previous unit shift register circuit SR. The set terminal S of the first-stage unit shift register circuit SR1 is input to the gate start pulse signal GSP. In addition, each unit shift register circuit SR outputs its output signal to the corresponding gate bus GL located in the display area. The reset terminal R is input to the output signal of the next-stage unit shift register circuit. The reset terminal R of the last-stage unit shift register circuit SRz is input to the clear signal.

[0457] Two clock input terminals, GCK1 and GCK2, are provided as two-phase clock signals. One clock input terminal receives clock signal GCK1, and the other clock input terminal receives clock signal GCK2. The clock signals input to the clock input terminals are configured to alternate between adjacent stages.

[0458] Figure 25 This diagram illustrates an example of a unit shift register circuit SR. In this example, the unit shift register circuit SR includes four TFTs 31-34 and a capacitor section Cap.

[0459] TFT31 is the input transistor. The gate and drain of TFT31 are connected to the set terminal, and the source of TFT31 is connected to the gate of TFT34. TFT34 is the output transistor. The drain of TFT34 is connected to the clock input terminal CK1, and the source is connected to the output terminal Z. That is, TFT34 acts as a transmission gate, allowing or blocking the clock signal input to the clock input terminal CK1.

[0460] The capacitor Cap is connected between the gate and source of the TFT34, which serves as the output transistor. In this specification, the node connected to the gate of the TFT34 is referred to as "node netA", and the node connected to the output terminal Z is referred to as "node Z". One electrode of the capacitor Cap is connected to the gate of the TFT34 and node netA, and the other electrode is connected to the source of the TFT34 and node Z.

[0461] TFT32 is positioned between the Low power input terminal and node netA. TFT32 is a pull-down transistor used to lower the potential of node netA. The gate of TFT32 is connected to the reset terminal, the drain is connected to node netA, and the source is connected to the Low power input terminal.

[0462] Node Z is connected to TFT33. The gate of TFT33 is connected to the clock signal input terminal CK2, the drain is connected to node Z, and the source is connected to the Low power input terminal.

[0463] In embodiments of this disclosure, for example, TFTs having a lower mobility than TFTs used in SSD circuits or pixel TFTs and having enhanced characteristics can be used as TFTs 31 to 34.

[0464] Alternatively, two types of TFTs with different characteristics can be mixed within the driving circuit depending on the application. For example, at least some of the TFTs, including TFT34 (output transistor), can use TFTs with high current driving force (high mobility), while other TFTs can use TFTs with lower mobility than TFT34.

[0465] Furthermore, the configuration of the driving circuit is not limited to the configuration shown in the figure. For example, a unit shift register circuit may have more than five TFTs, including an output transistor.

[0466] • SSD circuit structure and operation

[0467] Figure 26 This is a diagram illustrating SSD circuit 70.

[0468] An SSD circuit 70 is configured between the source driver SD and the display area DR. The SSD circuit 600 includes multiple SSD unit circuits 71(1) to 71(i) (i is an integer greater than 2) (sometimes collectively referred to as "SSD unit circuits 71") and control signal lines SW1 to SWn (n is an integer greater than 2, here n = 3). The SSD circuit 600 and the source driver SD are controlled by a control circuit located in the non-display area FR. The control signal lines SW1 to SWn are connected to the control circuit.

[0469] The output terminals V(1) to V(i) (hereinafter, sometimes collectively referred to as "V terminals") of the source driver SD are each connected to any one of the multiple video signal lines DO(1) to DO(i) (sometimes collectively referred to as "video signal lines DO"). The n grouped source buses SL correspond to one video signal line DO. Between the video signal line DO and the grouped source buses SL, an SSD unit circuit 71 is provided on a per-video signal-line basis. The SSD unit circuit 71 distributes video data from one video signal line DO to the n source buses SL.

[0470] In this embodiment, the Nth video signal line among the multiple video signal lines DO(1) to DO(i) is set as DO(N) (N is an integer from 1 to i), and the SSD unit circuit 71 and the source bus SL corresponding to the video signal line DO(N) are set as 71(N), SL(N-1) to SL(Nn), respectively. The source buses SL(N-1) to SL(Nn) can, for example, correspond to R, G, and B pixels (i.e., n = 3).

[0471] Each SSD unit circuit 71(N) has at least n (3 in this case) thin film transistors (TFTs for SSD circuits) 72(1) to 72(n) (sometimes collectively referred to as "TFTs for SSD circuits 72").

[0472] The SSD circuit uses a TFT72 as a selection switch. The gate electrode of the TFT72 is electrically connected to one of the n control signal lines SW1 to SWn. The source electrode of the TFT72 is electrically connected to the branch line of the video signal line DO(N). The drain electrode of the TFT72 is connected to one of the source buses SL(N-1) to SL(N-3).

[0473] A selection signal (control signal) is supplied to the gate electrode of the TFT 72 in the SSD circuit from one of the control signal lines SW1 to SW3. The control signal specifies the on-time of the selection switch within the same group and is synchronized with the time-series signal output from the source driver SD. The SSD unit circuit 71(N) writes the data potential obtained by time-division multiplexing the output of the video signal line DO(N) into multiple source buses SL(N-1) to SL(Nn) in a time sequence (time-division driving). As a result, the number of V terminals of the source driver SD can be reduced, and therefore, the area of ​​the non-display area FR can be further reduced (narrow bezel).

[0474] For TFTs 72 used in SSD circuits, a high current driving force is required. If a TFT with a low current driving force is used in the TFT 72 for SSD circuits, it may be difficult to charge the source bus within a predetermined time. Furthermore, if the channel width of the TFT is increased to ensure the desired current driving force, the size of the TFT increases, potentially preventing the achievement of a narrow bezel. According to embodiments of this disclosure, a TFT with a higher mobility than other circuit TFTs or pixel TFTs, i.e., a higher current driving force, can be used as the TFT 72 for SSD circuits. The TFT 72 for SSD circuits can also have depletion characteristics.

[0475] Furthermore, the configuration of the SSD circuit is not limited to the configuration shown in the figure. The configuration and operation of the SSD circuit are disclosed in, for example, Japanese Patent Application Publication No. 2008-225036, Japanese Patent Application Publication No. 2006-119404, and International Patent Application Publication No. 2011 / 118079. In this specification, for reference, the entire contents of Japanese Patent Application Publication No. 2008-225036, Japanese Patent Application Publication No. 2006-119404, and International Patent Application Publication No. 2011 / 118079 are cited.

[0476] Here, Table 2 illustrates preferred characteristics of pixel TFTs, driving circuit TFTs, and SSD circuit TFTs in a liquid crystal display device. The characteristics and numerical ranges listed in Table 2 are illustrative and do not limit the characteristics of each TFT.

[0477] Table 2

[0478]

[0479] • The structure and operation of pixel circuits

[0480] In an active matrix substrate used as a backplane for an organic EL device, pixel circuits are present in each pixel region.

[0481] Figure 27 This is a diagram illustrating pixel circuit 80.

[0482] The pixel circuit 80 includes a driving TFT 81, a selection TFT 82, and a capacitor element (holding capacitor) 83. The driving TFT 81 and the selection TFT 82 are oxide semiconductor TFTs supported on the substrate 1.

[0483] The gate electrode of TFT 82 is selected to be connected to the gate bus GL. The source electrode of TFT 82 is selected to be connected to the source bus SL. The drain electrode of TFT 82 is selected to be connected to the gate electrode of the driving TFT 81 and the capacitor element 83. The source electrode of the driving TFT 81 is connected to the current supply line CL. The drain electrode of the driving TFT 81 is connected to the OLED (organic light-emitting diode) 84 formed on the active matrix substrate.

[0484] When a turn-on signal is supplied from the gate bus GL to the gate electrode of the select TFT 82, the select TFT 82 becomes on. Therefore, the signal voltage from the source bus SL (corresponding to the desired luminance of the OLED 84) is applied to the gate electrodes of the capacitor element 83 and the driving TFT 81 via the select TFT 82. When the driving TFT 81 becomes on by the signal voltage, the current from the current supply line CL flows to the OLED 84 via the driving TFT 81, and the OLED 84 emits light.

[0485] According to embodiments of this disclosure, multiple oxide semiconductor TFTs (here, driving TFT 81 and selection TFT 82) with different required characteristics can be fabricated separately within the pixel circuit 80. For example, a TFT with a lower mobility than the selection TFT 82 (which shifts the threshold voltage in the positive direction) can be used as the driving TFT 81.

[0486] Furthermore, the composition of pixel circuits is not limited to... Figure 27 The illustrated configuration. Each pixel circuit may also have three or more TFTs, including a driving TFT 81 and a selection TFT 82.

[0487] Table 3 illustrates preferred characteristics of the driving TFT, the selection TFT, and the driving circuit TFT in an organic EL display device. The characteristics and numerical ranges listed in Table 3 are illustrative and do not limit the characteristics of each TFT.

[0488] Table 3

[0489]

[0490] <Oxide Semiconductor>

[0491] In this embodiment, the oxide semiconductor included in the oxide semiconductor layer of each TFT can be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. Examples of crystalline oxide semiconductors include polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, and crystalline oxide semiconductors whose c-axis is oriented substantially perpendicular to the layer.

[0492] The oxide semiconductor layer can have a stacked structure of two or more layers. When the oxide semiconductor layer has a stacked structure, it can include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. Alternatively, it can include multiple crystalline oxide semiconductor layers with different crystal structures. Additionally, it can include multiple amorphous oxide semiconductor layers. When the oxide semiconductor layer has a two-layer structure including an upper layer and a lower layer, the bandgap of the oxide semiconductor layer located on the gate electrode side (the lower layer if it's a bottom-gate structure, and the upper layer if it's a top-gate structure) can be smaller than the bandgap of the oxide semiconductor layer located on the opposite side of the gate electrode (the upper layer if it's a bottom-gate structure, and the lower layer if it's a top-gate structure). However, when the difference in bandgap between these layers is relatively small, the bandgap of the oxide semiconductor layer located on the gate electrode side can also be larger than the bandgap of the oxide semiconductor layer located on the opposite side of the gate electrode.

[0493] Materials, structures, film-forming methods, and compositions of oxide semiconductor layers with stacked structures for amorphous oxide semiconductors and the aforementioned crystalline oxide semiconductors are described, for example, in Japanese Patent Application Publication No. 2014-007399. For reference, the entire disclosure of Japanese Patent Application Publication No. 2014-007399 is incorporated herein by reference.

[0494] The oxide semiconductor layer may, for example, contain at least one metal element selected from In, Ga, and Zn. In this embodiment, the oxide semiconductor layer contains, for example, an In-Ga-Zn-O semiconductor (e.g., indium gallium zinc oxide). Here, the In-Ga-Zn-O semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited, for example, In:Ga:Zn = 2:2:1, In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:1:2, etc. This oxide semiconductor layer can be formed from an oxide semiconductor film containing an In-Ga-Zn-O semiconductor.

[0495] In-Ga-Zn-O semiconductors can be either amorphous or crystalline. For crystalline In-Ga-Zn-O semiconductors, those with the c-axis oriented approximately perpendicular to the layer are preferred.

[0496] Furthermore, the crystal structure of crystalline In-Ga-Zn-O semiconductors is disclosed, for example, in Japanese Patent Application Publication Nos. 2014-007399, 2012-134475, and 2014-209727. For reference, the entire disclosures of Japanese Patent Application Publication Nos. 2012-134475 and 2014-209727 are incorporated herein by reference. TFTs having an In-Ga-Zn-O semiconductor layer have high mobility (more than 20 times that of a-Si TFTs) and low leakage current (less than one percent that of a-Si TFTs), and are therefore suitable for use as driving TFTs (e.g., TFTs included in driving circuits disposed around a display area containing multiple pixels on the same substrate as the display area) and pixel TFTs (TFTs disposed in pixels).

[0497] The oxide semiconductor layer can also contain other oxide semiconductors instead of the In-Ga-Zn-O semiconductor. For example, it can contain In-Sn-Zn-O semiconductors (e.g., In2O3-SnO2-ZnO; InSnZnO). The In-Sn-Zn-O semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer may also include In-Al-Zn-O semiconductors, In-Al-Sn-Zn-O semiconductors, Zn-O semiconductors, In-Zn-O semiconductors, Zn-Ti-O semiconductors, Cd-Ge-O semiconductors, Cd-Pb-O semiconductors, CdO (cadmium oxide), Mg-Zn-O semiconductors, In-Ga-Sn-O semiconductors, In-Ga-O semiconductors, Zr-In-Zn-O semiconductors, Hf-In-Zn-O semiconductors, Al-Ga-Zn-O semiconductors, Ga-Zn-O semiconductors, In-Ga-Zn-Sn-O semiconductors, In-W-Zn-O semiconductors, etc.

[0498] Industrial availability

[0499] The embodiments of the present invention are applicable to active matrix substrates with peripheral circuits formed on a single ground plane. Such active matrix substrates are used in various electronic devices such as liquid crystal display devices, organic electroluminescent (EL) display devices, and inorganic electroluminescent display devices, as well as imaging devices such as image sensor devices, image input devices, fingerprint reading devices, and semiconductor memories.

Claims

1. An active matrix substrate, comprising a display area including multiple pixel areas and a non-display area disposed around the display area, characterized in that, have: Substrate; and A plurality of oxide semiconductor TFTs, supported on the substrate, are disposed in the display area or the non-display area. Each of the plurality of oxide semiconductor TFTs has: an oxide semiconductor layer; a gate electrode disposed on a portion of the oxide semiconductor layer with respect to a gate insulating layer; and a source electrode and a drain electrode. The aforementioned oxide semiconductor layer includes a first region covered by the gate electrode through the aforementioned gate insulating layer, and a first contact region and a second contact region located on both sides of the first region. The first contact region is electrically connected to the aforementioned source electrode, and the second contact region is electrically connected to the aforementioned drain electrode. The aforementioned plurality of oxide semiconductor TFTs include a first TFT and a second TFT. In the first TFT described above, the oxide semiconductor layer has a stacked structure throughout its entirety, comprising a lower oxide semiconductor film and an upper oxide semiconductor film disposed on the lower oxide semiconductor film, wherein the mobility of the upper oxide semiconductor film and the lower oxide semiconductor film are different from each other. In the second TFT described above, the first contact region and the second contact region of the oxide semiconductor layer have the aforementioned stacked structure, but at least a portion of the first region includes one of the lower oxide semiconductor film and the upper oxide semiconductor film, and does not include the other oxide semiconductor film. Each of the aforementioned plurality of oxide semiconductor TFTs further comprises an insulating layer covering the aforementioned oxide semiconductor layer and the aforementioned gate electrode. The source electrode is in contact with the first contact region within the first opening formed in the insulating layer, and the drain electrode is in contact with the second contact region within the second opening formed in the insulating layer.

2. The active matrix substrate according to claim 1, wherein, At least a portion of the first region in the second TFT includes the lower oxide semiconductor film but does not include the upper oxide semiconductor film.

3. The active matrix substrate according to claim 1, wherein, At least a portion of the first region in the second TFT includes the upper oxide semiconductor film but does not include the lower oxide semiconductor film.

4. The active matrix substrate according to any one of claims 1 to 3, wherein, In the second TFT, a portion of the first region of the oxide semiconductor layer has the aforementioned stacked structure, and another portion contains one of the aforementioned oxide semiconductor films but does not contain the other of the aforementioned oxide semiconductor films.

5. The active matrix substrate according to any one of claims 1 to 3, wherein, In the second TFT, the entire extent of the first region of the oxide semiconductor layer includes one of the oxide semiconductor films but does not include the other oxide semiconductor film.

6. The active matrix substrate according to any one of claims 1 to 3, wherein, The mobility of the upper oxide semiconductor film is higher than that of the lower oxide semiconductor film.

7. The active matrix substrate according to any one of claims 1 to 3, wherein, The mobility of the upper oxide semiconductor film is lower than that of the lower oxide semiconductor film.

8. The active matrix substrate according to any one of claims 1 to 3, wherein, In the first TFT described above, the gate insulating layer is in contact with the upper surface of the upper oxide semiconductor film. In the second TFT described above, the gate insulating layer is in contact with the upper surface of the oxide semiconductor film described above.

9. The active matrix substrate according to any one of claims 1 to 3, wherein, The aforementioned plurality of oxide semiconductor TFTs also include a third TFT. In the second TFT described above, the entire range of the first region includes one of the lower oxide semiconductor film and the upper oxide semiconductor film, but does not include the other oxide semiconductor film. In the third TFT, the first contact region and the second contact region of the oxide semiconductor layer, as well as a portion of the first region, have the aforementioned stacked structure. Another portion of the first region contains one of the oxide semiconductor films and does not contain the other oxide semiconductor film.

10. The active matrix substrate according to any one of claims 1 to 3, wherein, The aforementioned plurality of oxide semiconductor TFTs also include a third TFT. In the third TFT, at least a portion of the first region in the oxide semiconductor layer includes the other oxide semiconductor film, and does not include the other oxide semiconductor film.

11. The active matrix substrate according to any one of claims 1 to 3, wherein, The first TFT is disposed in each of the plurality of pixel regions. The second TFT mentioned above is included in the peripheral circuitry disposed in the non-display area.

12. The active matrix substrate according to any one of claims 1 to 3, wherein, Each of the aforementioned pixel regions has a pixel circuit that includes at least a driving TFT, a selection TFT, and a capacitor element. One of the aforementioned first TFT and the aforementioned second TFT is the aforementioned driving TFT, and the other TFT is the aforementioned selection TFT.

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