Display substrate and display device

Abstract

A display substrate and a display device. The display substrate includes a substrate, a plurality of first color sub-pixels located on the substrate, a plurality of data lines, and a plurality of first power signal lines. Each first color sub-pixel includes an organic light-emitting element, and the organic light-emitting element includes a first electrode, a light-emitting layer, and a second electrode that are sequentially stacked. The data lines are located between the second electrode and the substrate and extend in a second direction. The first power signal lines are disposed on the same layer as the data lines and extend in the second direction. The display substrate further includes a first spacer, which is disposed on the same layer as the data lines and extends in the second direction; in a third direction perpendicular to the substrate, the second electrode of each first color sub-pixel overlaps with the data lines, the first power signal lines, and the first spacer, and the first power signal lines and the first spacer are located on both sides of the data lines. In the embodiment of the present disclosure, the first spacer overlaps with the second electrode, which can prevent color deviation of the first color sub-pixels.

Description

Technical Field

[0001] At least one embodiment of the present disclosure relates to a display substrate and a display device. Background Art

[0002] With the development of organic light-emitting diode display technology, such as active-matrix organic light-emitting diode (AMOLED) display technology, people's requirements for display effects are getting higher and higher. The performance specifications of organic light-emitting diode display products may include power consumption, brightness, color deviation, etc. The factors affecting color deviation in the backplane included in organic light-emitting diode display products may include the flatness of the anode. Summary of the Invention

[0003] Embodiments of the present disclosure provide a display substrate and a display device.

[0004] A display substrate provided according to an embodiment of the present disclosure includes: a substrate; a plurality of first color sub-pixels located on the substrate, each of the first color sub-pixels including an organic light-emitting element, the organic light-emitting element including a first electrode, a light-emitting layer, and a second electrode stacked in sequence, the first electrode being located on a side of the second electrode away from the substrate; a plurality of data lines located between the second electrode and the substrate and arranged along a first direction and extending along a second direction; a plurality of first power signal lines provided on the same layer as the data lines and extending along the second direction. The display substrate further includes a plurality of first pads provided on the same layer as the data lines; along a third direction perpendicular to the substrate, the second electrode of each of the first color sub-pixels overlaps with the data lines, the first power signal lines, and the first pads, and among the overlapping portions of the data lines, the first power signal lines, and the first pads with the second electrode, the first power signal lines and the first pads are located on both sides of the data lines.

[0005] For example, in an embodiment of the present disclosure, along the third direction, a center line extending along the second direction in the light-emitting region of each of the first color sub-pixels overlaps with the data lines.

[0006] For example, in an embodiment of the present disclosure, a positive projection of the center line on the substrate is located within a positive projection of the data lines on the substrate.

[0007] For example, in an embodiment of the present disclosure, among the data lines, the first power signal lines, and the first pads overlapping with the second electrode of the first color sub-pixels, a ratio between a distance between edges of the first pads close to the data lines and a distance between edges of the first power signal lines close to the data lines is approximately 0.9 to 1.1.

[0008] For example, in an embodiment of the present disclosure, along the third direction, a portion where the second electrode overlaps with the first power signal line is a first overlapping portion, and a portion where the second electrode overlaps with the first spacer is a second overlapping portion. The dimension of the first overlapping portion along the second direction is greater than the dimension of the second overlapping portion along the second direction.

[0009] For example, in an embodiment of the present disclosure, the maximum dimension of the second electrode of the first color sub-pixel along the second direction is greater than the maximum dimension along the first direction, and the maximum dimension of the first spacer along the second direction is greater than the maximum dimension along the first direction.

[0010] For example, in an embodiment of the present disclosure, the display substrate further includes: a plurality of second spacers, which are arranged on the same layer as the plurality of first spacers. Along the third direction, the second electrode of each first color sub-pixel overlaps with the second spacer, and a straight line extending along the second direction passes through the first spacer and the second spacer.

[0011] For example, in an embodiment of the present disclosure, among the data line, the first power signal line, and the second spacer that overlap with the second electrode, the ratio of the distance between the edges of the second spacer and the data line that are close to each other to the distance between the edges of the first power signal line and the data line that are close to each other is approximately 0.9 to 1.1.

[0012] For example, in an embodiment of the present disclosure, the second spacer includes a first portion and a second portion that are connected to each other. The first portion is located on a side of the second portion away from the first spacer, and a straight line extending along the second direction passes through the first portion of the second spacer and the first spacer.

[0013] For example, in an embodiment of the present disclosure, the maximum dimension of the second spacer along the second direction is greater than the maximum dimension along the first direction.

[0014] For example, in an embodiment of the present disclosure, among the first spacer and the second spacer that overlap with the second electrode of each first color sub-pixel, the first spacer and the second spacer are arranged along the second direction.

[0015] For example, in an embodiment of the present disclosure, along the second direction, the center of the first spacer and the center of the second spacer are located on both sides of the center of the light-emitting region of the first color sub-pixel.

[0016] For example, in an embodiment of the present disclosure, the display substrate further includes: a plurality of scan signal lines, which extend along the first direction, and the plurality of scan signal lines are located between the film layer where the data line is located and the substrate; the first spacer overlaps with the scan signal line.

[0017] For example, in an embodiment of the present disclosure, the display substrate further includes: a plurality of second power signal lines extending along the first direction, located between the film layer where the first power signal line is located and the film layer where the scan signal line is located, and the second power signal line is electrically connected to the first power signal line. The first spacer overlaps with the second power signal line.

[0018] For example, in an embodiment of the present disclosure, among the data line and the first spacer overlapping with the second electrode, the first spacer includes a strip-shaped main body and a protruding portion connected to each other, the protruding portion is located on a side of the strip-shaped main body away from the data line, and a portion of the protruding portion close to the main body portion is electrically connected to the second power signal line through a first connection hole penetrating through an insulating layer located between the second power signal line and the first power signal line.

[0019] For example, in an embodiment of the present disclosure, the first power signal line is electrically connected to the second power signal line through a second connection hole penetrating through the insulating layer located between the second power signal line and the first power signal line, and the first connection hole and the second connection hole are located on a straight line extending along the first direction.

[0020] For example, in an embodiment of the present disclosure, the orthographic projections of the first connection hole and the second connection hole on the substrate are located within the orthographic projection of the second electrode on the substrate, and the orthographic projections of the first connection hole and the second connection hole on the substrate are located outside the orthographic projection of the light-emitting region included in the first color sub-pixel on the substrate.

[0021] For example, in an embodiment of the present disclosure, the display substrate further includes: a plurality of reset control signal lines extending along the first direction and arranged on the same layer as the scan signal lines. A first portion of the second spacer overlaps with the reset control signal line, and the first spacer does not overlap with the reset control signal line.

[0022] For example, in an embodiment of the present disclosure, the display substrate further includes: a plurality of reset power signal lines extending along the first direction and arranged on the same layer as the second power signal lines. The second spacer is electrically connected to the reset power signal line.

[0023] For example, in an embodiment of the present disclosure, the display substrate further includes: a plurality of second color sub-pixel pairs and a plurality of third color sub-pixels located on the substrate, and the plurality of first color sub-pixels, the plurality of second color sub-pixel pairs, and the plurality of third color sub-pixels are arranged into a plurality of repeating units. Each of the repeating units includes a first color sub-pixel, a second color sub-pixel pair, and a third color sub-pixel arranged in sequence along a first direction, and the two second color sub-pixels included in the second color sub-pixel pair are arranged along a second direction. The plurality of repeating units are arranged along the first direction to form a plurality of repeating unit groups, the plurality of repeating unit groups are arranged along the second direction, and adjacent repeating unit groups in the plurality of repeating unit groups are offset from each other along the first direction.

[0024] For example, in an embodiment of the present disclosure, each of the sub-pixels includes the pixel circuit, and the pixel circuit includes a data writing transistor, a driving transistor, a storage capacitor, a threshold compensation transistor, a first light-emitting control transistor, a second light-emitting control transistor, a first reset transistor, and a second reset transistor; a first pole of the data writing transistor is electrically connected to a first pole of the driving transistor, a second pole of the data writing transistor is electrically connected to the data line to receive a data signal, and a gate of the data writing transistor is electrically connected to the scan signal line to receive a scan signal; a first pole of the storage capacitor is electrically connected to the first power supply signal line, and a second pole of the storage capacitor is electrically connected to a gate of the driving transistor; a first pole of the threshold compensation transistor is electrically connected to a second pole of the driving transistor, a second pole of the threshold compensation transistor is electrically connected to the gate of the driving transistor, and a gate of the threshold compensation transistor is electrically connected to the scan signal line to receive a compensation control signal; a first pole of the first reset transistor is electrically connected to the reset power supply signal line to receive a first reset signal, a second pole of the first reset transistor is electrically connected to the gate of the driving transistor, and a gate of the first reset transistor is electrically connected to the reset control signal line to receive a first sub-reset control signal; a first pole of the second reset transistor is electrically connected to the reset power supply signal line to receive a second reset signal, a second pole of the second reset transistor is electrically connected to a second electrode of the organic light-emitting element, and a gate of the second reset transistor is electrically connected to the reset control signal line to receive a second sub-reset control signal; a first pole of the first light-emitting control transistor is electrically connected to the first power supply signal line, a second pole of the first light-emitting control transistor is electrically connected to the first pole of the driving transistor, and a gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line to receive a first light-emitting control signal; a first pole of the second light-emitting control transistor is electrically connected to the second pole of the driving transistor, a second pole of the second light-emitting control transistor is electrically connected to the second electrode of the organic light-emitting element, and a gate of the second light-emitting control transistor is electrically connected to the light-emitting control signal line to receive a second light-emitting control signal. The display substrate further includes a first connection portion, a second connection portion, and a third connection portion that are disposed on the same layer as the data line, wherein the first connection portion is configured to connect the second pole of the threshold compensation transistor and the gate of the driving transistor, the second connection portion is configured to connect the reset power supply signal line and the first pole of the second reset transistor, and the third connection portion is configured to connect the second electrode of the organic light-emitting element and the second pole of the second light-emitting control transistor.

[0025] For example, in an embodiment of the present disclosure, the third connection portion and the first spacer are located on the same side of the data line.

[0026] For example, in an embodiment of the present disclosure, the threshold compensation transistor includes two gates, and a part of the strip-shaped main body of the first spacer block close to the second spacer block overlaps with the active semiconductor layer between the two gates of the threshold compensation transistor in the orthographic projection on the substrate.

[0027] For example, in an embodiment of the present disclosure, the data line includes a data line main body portion extending along the second direction and a data line connection portion. The data line connection portion is located on a side of the data line main body portion close to the second spacer block. The data line connection portion is electrically connected to the second pole of the data writing transistor through a via hole in an insulating layer located between the film layer where the data line is located and the film layer where the second pole of the data writing transistor is located; in the second direction, there is a gap between the first part of the second spacer block and the strip-shaped main body of the first spacer block, and the orthographic projection of the data line connection portion on a straight line extending along the second direction does not overlap with the orthographic projections of the first spacer block and the first part of the second spacer block on this straight line.

[0028] For example, in an embodiment of the present disclosure, the first part of the second spacer block is closer to the data line main body portion than the second part of the second spacer block, and the orthographic projection of the data line connection portion on a straight line extending along the second direction overlaps with the orthographic projection of the second part of the second spacer block on this straight line.

[0029] For example, in an embodiment of the present disclosure, the second spacer block is electrically connected to the reset power signal line through the second connection portion.

[0030] For example, in an embodiment of the present disclosure, the second spacer block and the second connection portion are integrally formed.

[0031] For example, in an embodiment of the present disclosure, both the second color sub-pixel and the third color sub-pixel include an organic light-emitting element, and the organic light-emitting element included in each sub-pixel includes the first electrode, the light-emitting layer, and the second electrode; along a direction perpendicular to the substrate, one of the two second electrodes included in the second color sub-pixel pair overlaps with the data line, the first power signal line, the second connection portion, and the third connection portion, and a first center line of the light-emitting layer of the second color sub-pixel pair in the second direction overlaps with the third connection portion, the second connection portion and the first power signal line are located on one side of the first center line, and the data line is located on the other side of the first center line; along a direction perpendicular to the substrate, the other of the two second electrodes included in the second color sub-pixel pair overlaps with the data line, the first power signal line, the first connection portion, and the third connection portion, and the first center line overlaps with the third connection portion, the first connection portion and the first power signal line are located on one side of the first center line, and the data line is located on the other side of the first center line; along a direction perpendicular to the substrate, the second electrode included in the third color sub-pixel overlaps with the data line, the first power signal line, the first connection portion, the second connection portion, and the third connection portion, and the data line is located on one side of a second center line extending in the second direction of the light-emitting region of the third color sub-pixel, and the first connection portion, the second connection portion, and the third connection portion are located on the other side of the second center line.

[0032] For example, in an embodiment of the present disclosure, the first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel.

[0033] A display device provided according to another embodiment of the present disclosure includes the above display substrate. Description of the Drawings

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0035] Figure 1 It is a schematic partial cross-sectional structure diagram of a display substrate;

[0036] Figure 2 It is a schematic partial cross-sectional structure diagram of another display substrate;

[0037] Figure 3 It is a schematic partial planar structure diagram of a pixel arrangement structure and wiring on a display substrate;

[0038] Figure 4 The partial cross-sectional structure diagram cut along the Figure 3 AA' line shown;

[0039] Figure 5 The pixel arrangement structure diagram of the display substrate provided according to an embodiment of the present disclosure;

[0040] Figure 6 It is Figure 5 The partial planar structure diagram of the display substrate shown;

[0041] Figure 7A The partial cross-sectional structure diagram cut along the Figure 6 BB' line of the display substrate in an example shown;

[0042] Figure 7B The partial cross-sectional structure diagram cut along the Figure 6 II' line of the display substrate in another example shown;

[0043] Figure 8 The schematic diagram of the pixel circuit included in each sub-pixel and connected to the organic light-emitting element;

[0044] Figures 9A - 10 The schematic diagram of each layer of a pixel circuit provided according to an embodiment of the present disclosure;

[0045] Figure 11 The partial planar structure diagram of the source-drain metal layer in the display substrate provided according to another embodiment of the present disclosure;

[0046] Figure 12 It is Figure 11 The schematic diagram of the relative position relationship between the source-drain metal layer shown and the second electrode of the first color sub-pixel and the light-emitting region;

[0047] Figure 13 It is Figure 11 The schematic diagram of the stacked structure of each film layer in the display substrate shown;

[0048] Figure 14 The partial cross-sectional structure diagram cut along the Figure 10 and Figure 6 CC' line shown;

[0049] Figure 15 The partial cross-sectional structure diagram cut along the Figure 13 DD' line cut;

[0050] Figure 16 The partial planar structure diagram of the source-drain metal layer of the display substrate provided according to another embodiment of the present disclosure;

[0051] Figure 17 The Figure 16 structural schematic diagram of the source-drain metal layer and the second electrode of the first color sub-pixel stacked;

[0052] Figure 18 The Figure 16 structural schematic diagram of the stacked film layers of the display substrate shown;

[0053] Figure 19 The Figure 10 and Figure 6 structural schematic diagram of the cross-sectional structure taken along the FF' line shown;

[0054] Figure 20 The Figure 18 structural schematic diagram of the cross-sectional structure taken along the EE' line shown;

[0055] Figure 21 The Figure 18 partial cross-sectional structural schematic diagram taken along the HH' line;

[0056] Figure 22 The Figure 18 partial cross-sectional structural schematic diagram taken along the GG' line; and

[0057] Figure 23 The Figure 16 magnified schematic diagram of the second spacer in the display substrate shown. Detailed implementation manners

[0058] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0059] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. The terms such as "include" or "comprise" mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items.

[0060] Figure 1 The Figure 1As shown in the figure, the display substrate includes a film layer 10, and the film layer 10 includes a substrate, an active semiconductor layer located on the substrate, and at least one conductive layer located on the side of the active semiconductor layer away from the substrate. The display substrate further includes a source-drain metal layer 11 located on the film layer 10. For example, the source-drain metal layer 11 may include traces such as data lines and power signal lines. The display substrate further includes a planarization layer 12 located on the side of the source-drain metal layer 11 away from the film layer 10, an anode 13 located on the side of the planarization layer 12 away from the source-drain metal layer 11, and a pixel defining layer 14 located on the side of the anode 13 away from the planarization layer 12. The pixel defining layer 14 includes a plurality of openings 15-17 for defining the light-emitting regions of the sub-pixels. The plurality of openings 15-17 expose a part of the anode 13. When the subsequent organic light-emitting layer is formed in the openings 15-17 of the pixel defining layer 14, the organic light-emitting layer is in contact with the anode 13, so that this part can drive the organic light-emitting layer to emit light.

[0061] As Figure 1 shown, the source-drain metal layer 11 has a relatively large thickness. For example, the thickness can be 0.6-0.9 um, which will cause the surface of the planarization layer 12 located on the source-drain metal layer 11 facing the anode 13 to be uneven. For example, the distance between the surface of the planarization layer 12 away from the film layer 10 directly above the source-drain metal layer 11 (such as data lines, power signal lines, and patterns of the same layer and the same material as them) and the surface of the film layer 10 away from the planarization layer 12 is h1, and the distance between the surface of the planarization layer 12 away from the film layer 10 directly above the area where the source-drain metal layer 11 is not provided and the surface of the film layer 10 away from the planarization layer 12 is h2, and h1>h2.

[0062] As Figure 1As shown, within the opening 16, a source-drain metal layer 11 is disposed directly below a part of the flat layer 12, and no source-drain metal layer 11 is disposed directly below another part. As a result, the surface of the flat layer 12 facing the anode 13 within the opening 16 is uneven, causing the surface of the anode 13 located on the flat layer 12 to also be uneven. For example, for the anode 13 within the opening 16, the distance between the surface of the anode 13 away from the film layer 10 directly above the source-drain metal layer 11 and the surface of the film layer 10 away from the anode 13 is h3, and the distance between the surface of the anode 13 away from the film layer 10 at the position where no source-drain metal layer 11 is disposed and the surface of the film layer 10 away from the anode 13 is h4, and h3 > h4. Thus, the anode 13 within the opening 16 is "tilted". Similarly, the anode 13 within the opening 15 will also be "tilted", and due to the difference in the position of the source-drain metal layer 11, the "tilt direction" of the anode 13 within the opening 15 is different from the "tilt direction" of the anode 13 within the opening 16, resulting in inconsistent light emission intensities in different directions for the sub-pixels corresponding to the openings 15 and 16. Taking the direction indicated by the arrow in the X direction as the right, the light intensities emitted from the sub-pixel light-emitting regions defined by the openings 15 and 16 to the left and right sides are inconsistent. No source-drain metal layer 11 is disposed directly below the anode 13 within the opening 17. Therefore, the surface of the anode 13 within the opening 17 is basically flat and not "tilted", and the light emission intensities in different directions for the sub-pixel light-emitting region defined by the opening 17 are consistent. For the light-emitting regions of three adjacent sub-pixels of different colors defined by the openings 15 - 17, the anode 13 within the opening 15 is "tilted" to the left, the anode 13 within the opening 16 is "tilted" to the right, and the anode 13 within the opening 17 is not tilted. Thus, the "tilt" directions of the anodes 13 of different color sub-pixels are different, resulting in mismatched light emission intensities from the light-emitting regions of the three sub-pixels to the left and right sides. A display device using such a display substrate will exhibit large viewing angle color shift. When viewed by the human eye, a color shift phenomenon similar to red on one side and cyan on the other side appears.

[0063] Figure 2 It is a schematic cross-sectional structure diagram of a part of another display substrate. Figure 2 The shown display substrate includes Figure 1 the shown film layer 10, source-drain metal layer 11, flat layer 12, anode 13, and pixel defining layer 14. As Figure 2 shown, the flat layer 12 in the display substrate includes a via 18 to enable the anode 13 to be electrically connected to the source-drain metal layer 11. The pixel defining layer 14 includes an opening 19 to expose a part of the anode 13. When the subsequent organic light-emitting layer is formed in the opening 19, the organic light-emitting layer contacts the anode 13 to form a light-emitting region.

[0064] As Figure 2As shown, the via 18 is located outside the light-emitting region. Since the anode 13 around the via 18 is inclined, a certain distance should be set between the light-emitting region and the via 18 to ensure the flatness of the anode 13 in the light-emitting region, thereby avoiding color shift on the display substrate.

[0065] As Figures 1 - 2 shown, the positional relationship between the source-drain metal layer 11 and the anode 13, and the positional relationship between the via 18 provided in the planarization layer 12 and the anode 13 will both affect the flatness of the anode 13 in the light-emitting region, thereby causing color shift to easily occur on the display substrate.

[0066] Figure 3 is a schematic diagram of the local planar structure of the pixel arrangement and the wiring on a display substrate. Figure 4 is along Figure 3 shown in the AA' line of the local cross-sectional structure schematic diagram. As Figure 3 shown, the display substrate includes a plurality of red sub-pixels 21, a plurality of green sub-pixel pairs (each green sub-pixel pair includes two green sub-pixels 22 and 23), and a plurality of blue sub-pixels 24. The plurality of red sub-pixels 21 and the plurality of blue sub-pixels 24 are alternately arranged along the X direction and the Z direction. The plurality of green sub-pixels are arranged in an array along the X direction and the Z direction, and every four green sub-pixels surround a red sub-pixel 21 or a blue sub-pixel 24. The shapes of the red sub-pixel 21 and the blue sub-pixel 24 are both rhombuses, and the two diagonals of the rhombus extend along the X direction and the Z direction respectively. The sides of the red sub-pixel 21 adjacent to the green sub-pixels are substantially parallel to each other, and the sides of the green sub-pixels adjacent to the blue sub-pixel 24 are substantially parallel to each other. Due to process limitations, the shapes of the red sub-pixels and the blue sub-pixels may not be strictly rhombuses, but approximately rhombuses, such as rounded rhombuses. A rounded rhombus is a shape formed by rounding the corners of a rhombus. Similarly, the shape of the green sub-pixels may not be a strictly rectangle, but an approximately rectangle, such as a rounded rectangle. A rounded rectangle is a shape formed by rounding the corners of a rectangle.

[0067] Each of the above-mentioned red sub-pixels, green sub-pixels, and blue sub-pixels includes, for example, an anode and a cathode, and a light-emitting layer located between the two electrodes. For example, since the light-emitting layer only emits light effectively at the part where it contacts the anode, the shape of the sub-pixel is approximately the shape of the part where the light-emitting layer contacts the anode, or the shape of the sub-pixel is substantially the same as the shape of the opening of the corresponding pixel defining layer.

[0068] Each of the above-mentioned red sub-pixels, green sub-pixels, and blue sub-pixels includes a pixel circuit, and the pixel circuit may include a 7T1C (i.e., seven transistors and one capacitor) structure, for example, including a driving transistor, a data writing transistor, a storage capacitor, a threshold compensation transistor, a first reset transistor, a second reset transistor, a first light-emitting control transistor, and a second light-emitting control transistor.

[0069] As shown in Figures 3 - 4 , the film layer 8 of the display substrate may include a substrate, an active semiconductor layer located on the substrate, and at least one conductive layer located on the side of the active semiconductor layer away from the substrate. The display substrate further includes a source-drain metal layer 2 located on the film layer 8. For example, the source-drain metal layer 2 may include a data line 26, a power supply signal line 25, a first connection portion 28, a second connection portion 27, and a third connection portion 29. The data line 26 is connected to the driving transistor; the power supply signal line 25 is connected to the first light-emitting control transistor; both ends of the first connection portion 28 are respectively connected to the threshold compensation transistor and the gate of the driving transistor; both ends of the second connection portion 27 are respectively connected to the reset power supply signal line and the second reset transistor; the first part 291 of the third connection portion is connected to the second light-emitting control transistor.

[0070] As shown in Figures 3 - 4 , the display substrate further includes a planarization layer 7 located on the side of the source-drain metal layer 2 away from the film layer 8, an anode 3 located on the side of the planarization layer 7 away from the source-drain metal layer 2, and a pixel defining layer 6 located on the side of the anode 3 away from the planarization layer 7. The anode 3 is connected to the second part 292 of the third connection portion through a via 1 in the planarization layer 7 to achieve connection with the second light-emitting control transistor. The second part 292 of the third connection portion and the first part 291 are of an integral structure. The first part 291 is the source-drain metal layer at a position directly opposite to the source or drain of the second light-emitting control transistor, and the second part 292 is the source-drain metal layer at a position directly opposite to the via 1 of the planarization layer 7. The pixel defining layer 6 includes an opening for defining the light-emitting region of the sub-pixel. The opening exposes a part of the anode 3. When the subsequent organic light-emitting layer is formed in the opening of the pixel defining layer 6, the organic light-emitting layer contacts the anode 3, so that this part can drive the organic light-emitting layer to emit light to form the light-emitting region 4.

[0071] As shown in Figures 3 - 4 , the distance a between adjacent data lines 26 is the width of the pixel circuit of a sub-pixel, and the pixel circuits of each sub-pixel are arranged repeatedly in the X direction and the Z direction. Among the sub-pixels arranged in the X direction, the distance along the X direction between the center of the red sub-pixel 21 and the center of the adjacent green sub-pixel 23 is b, the distance along the X direction between the center of the green sub-pixel 23 and the center of the adjacent blue sub-pixel 24 is c, the distance along the X direction between the center of the blue sub-pixel 24 and the center of the adjacent green sub-pixel 22 is d, and the distance along the X direction between the center of the green sub-pixel 22 and the center of the adjacent red sub-pixel 21 is e, and a = b = c = d = e. The above "center" refers to the geometric center of the planar shape of the light-emitting region of each color sub-pixel.

[0072] As shown in Figures 3 - 4As shown, the centers of the light-emitting regions of the above sub-pixels are arranged at equal intervals, and this interval is approximately equal to the width of the pixel circuit of each sub-pixel. At this time, the light-emitting region of the green sub-pixel overlaps with the first part 291 of the third connection portion. In order not to affect the flatness of the anode in the light-emitting region, a relatively large distance is required between the position of the via 1 in the planarization layer 7 and the first part 291 of the third connection portion 29. Thus, relative to the position of the source-drain electrodes of the second light-emitting control transistor for connecting to the anode, the position of the via in the planarization layer in the figure is greatly adjusted in the Z direction, which has a greater impact on the overall pixel circuit structure. In addition, as Figures 3 - 4 shown, in the cross-sectional view taken along the center line AA' of the light-emitting region of the blue sub-pixel 24 (only the positional relationship between the source-drain metal layer 2 and the anode 3 is schematically shown in the figure, and there will be unevenness problems with the anode 3 located on the source-drain metal layer 2 in the actual product), along the Z direction, there is no source-drain metal layer 2 directly below the middle position of the anode 3 of the blue sub-pixel 24, while source-drain metal layers 2 are provided below the two side positions of the anode 3 of the blue sub-pixel 24, thus affecting the flatness of the anode 3 of the blue sub-pixel 24 in the Z direction, and further causing color deviation to easily occur when the blue sub-pixel 24 is displaying.

[0073] Embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a substrate; a plurality of first-color sub-pixels, a plurality of data lines, and a plurality of first power signal lines located on the substrate. Each first-color sub-pixel includes an organic light-emitting element, and the organic light-emitting element includes a first electrode, a light-emitting layer, and a second electrode that are sequentially stacked, and the first electrode is located on the side of the second electrode away from the substrate. The plurality of data lines are located between the second electrode and the substrate, and are arranged in a first direction and extend in a second direction. The plurality of first power signal lines are provided on the same layer as the data lines and extend in the second direction. The display substrate further includes a plurality of first pads, provided on the same layer as the data lines and extending in the second direction; along a third direction perpendicular to the substrate, the second electrode of each first-color sub-pixel overlaps with the data lines, the first power signal lines, and the first pads, and among the overlapping portions of the data lines, the first power signal lines, and the first pads with the second electrode, the first power signal lines and the first pads are located on both sides of the data lines. By providing the first pads in the embodiments of the present disclosure, and the first pads overlapping with the second electrode of the first-color sub-pixels, the height difference between the second electrodes located on both sides of the data lines from the substrate can be minimized as much as possible, thereby preventing color deviation from occurring when the first-color sub-pixels are displaying.

[0074] The display substrate and the display device provided by the embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0075] Figure 5 It is a schematic diagram of the pixel arrangement structure of a display substrate according to an embodiment of the present disclosure, Figure 6 For Figure 5Schematic partial planar structure diagram of the display substrate shown. For the convenience of showing the positional relationship, Figure 6 only two film layers, namely the second electrode and the source-drain metal layer, are shown. As Figures 5 - 6 shown, the display substrate includes a substrate 100 and a plurality of repeating units 200 located on the substrate 100. Each repeating unit 200 includes a first color sub-pixel 210, a pair of second color sub-pixels 220, and a third color sub-pixel 230 arranged along a first direction (the X direction shown in the figure). The pair of second color sub-pixels 220 includes two second color sub-pixels 2210 and 2220 arranged along a second direction (the Z direction shown in the figure, a direction different from the first direction). The plurality of repeating units 200 are arranged along the first direction to form a plurality of repeating unit groups 2000, and the plurality of repeating unit groups 2000 are arranged along the second direction. Moreover, adjacent repeating unit groups 2000 among the plurality of repeating unit groups 2000 are offset from each other along the first direction, that is, there is a certain offset amount between adjacent repeating unit groups 2000 along the first direction. Therefore, the sub-pixels of the same color in adjacent repeating unit groups 2000 are not aligned in the second direction. The pixel arrangement patterns in odd-row repeating unit groups 2000 are the same, and the pixel arrangement patterns in even-row repeating unit groups 2000 are the same.

[0076] For example, the offset amount between adjacent repeating unit groups 2000 in the first direction is approximately half of the size of the repeating unit 200 in the first direction. For example, the size of the repeating unit 200 in the first direction is the pitch of the repeating unit 200 in the first direction. Here, the pitch refers to the distance between the centers of the light-emitting regions of two first color sub-pixels 210 in two adjacent repeating units 200 along the first direction, and the center of the light-emitting region here refers to the geometric center of the planar shape of the light-emitting region.

[0077] The above-mentioned first direction and second direction are respectively two mutually perpendicular directions in the same plane. For example, this plane is the plane in which the pixels are arranged. The repeating unit here only refers to the repetition of sub-pixels, and other structures may or may not be the same. In addition, the above-mentioned repetition means that the approximate positions, shapes, and sizes are similar. In some cases, for the need of wiring or opening holes, the shape may be slightly different, such as having openings at different positions.

[0078] As Figures 5 - 6As shown, in each repeating unit 200, the distance in the first direction between the center of the third color sub-pixel 230 and the center of the second color sub-pixel pair 220 is the first distance f. That is, in each repeating unit 200, the distance between the center line extending in the second direction of the third color sub-pixel 230 and the center line extending in the second direction of the second color sub-pixel pair is the first distance. In the embodiments of the present disclosure, the center of each sub-pixel refers to the geometric center of the shape of the light-emitting region of each sub-pixel, and the center line extending in the second direction of each sub-pixel refers to the center line passing through the geometric center of the light-emitting region. In the embodiments of the present disclosure, the center of the second color sub-pixel pair refers to the midpoint of the connection line between the centers of the two light-emitting regions of the two second color sub-pixels.

[0079] As Figures 5 - 6 shown, two repeating units 200 located in the same repeating unit group 2000 and adjacent to each other include a first repeating unit 201 and a second repeating unit 202. The third color sub-pixel 230 of the first repeating unit 201 is adjacent to the first color sub-pixel 210 of the second repeating unit 202. The repeating unit 200 that is adjacent to both the first repeating unit 201 and the second repeating unit 202 and is located in the adjacent repeating unit group 2000 is the third repeating unit 203. The above "the repeating unit 200 that is adjacent to both the first repeating unit 201 and the second repeating unit 202 and is located in the adjacent repeating unit group 2000 is the third repeating unit 203" means that there are no other repeating units between the third repeating unit 203 and the first repeating unit 201, and there are no other repeating units between the third repeating unit 203 and the second repeating unit 202.

[0080] As Figures 5 - 6 shown, the distance in the first direction between the center of the third color sub-pixel 230 in the first repeating unit 201 and the center of the second color sub-pixel pair 220 in the third repeating unit 203 is the second distance g. That is, the distance between the center line extending in the second direction of the third color sub-pixel 230 in the first repeating unit 201 and the center line extending in the second direction of the second color sub-pixel pair 220 in the third repeating unit 203 is the second distance.

[0081] As Figures 5 - 6 shown, the first distance is not equal to the second distance. By setting the distance between the center lines extending in the second direction of each sub-pixel in the embodiments of the present disclosure, it is possible to minimize the occurrence of color deviation while ensuring that the position of the vias in the planarization layer is not significantly adjusted to reduce the impact on the overall pixel circuit structure.

[0082] For example, as Figures 5 - 6 shown, the first distance is greater than the second distance. Thus, it is possible to minimize the occurrence of color deviation while ensuring that the position of the vias in the planarization layer is not significantly adjusted to reduce the impact on the overall pixel circuit structure.

[0083] For example, the ratio of the first distance to the second distance can be 1.5 to 2.3. For example, the ratio of the first distance to the second distance can be 1.8 to 2.0.

[0084] For example, as Figures 5 - 6 shown, the pixel size of the pixel circuit (described later) of each sub-pixel in the first direction is a, the ratio of the first distance to the pixel size a is about 1.3, and the ratio of the second distance to the pixel size a is about 0.7. The size of the above pixel circuit can refer to the distance between adjacent data lines (described later).

[0085] For example, as Figures 5 - 6 described, the distance in the first direction between the center of the first color sub-pixel 210 in the second repeating unit 202 and the center of the second color sub-pixel pair 220 in the third repeating unit 203 is the third distance h. That is, the distance between the center line extending in the second direction of the first color sub-pixel 210 in the second repeating unit 202 and the center line extending in the second direction of the second color sub-pixel pair 220 in the third repeating unit 203 is the third distance.

[0086] For example, as Figures 5 - 6 shown, the third distance is approximately equal to the second distance. Here and hereinafter, "approximately equal" means that the ratio of the two is in the range of 0.9 to 1.1. In some embodiments, the size of the light-emitting region of the first color sub-pixel 210 in the second repeating unit 202 in the Z direction is larger than the size of the light-emitting region of the third color sub-pixel 230 in the first repeating unit 201 in the Z direction. To ensure that the distance (PDL gap) between the boundaries of the light-emitting regions of different color sub-pixels is consistent, the third distance can be slightly larger than the second distance.

[0087] For example, as Figures 5 - 6 shown, the distance in the first direction between the center of the first color sub-pixel 210 and the center of the second color sub-pixel pair 220 in each repeating unit 200 is the fourth distance i, that is, the distance between the center line extending in the second direction of the first color sub-pixel 210 and the center line extending in the second direction of the second color sub-pixel pair 220 is the fourth distance. The fourth distance is approximately equal to the first distance. In some embodiments, in the same repeating unit 200, the size of the light-emitting region of the first color sub-pixel 210 in the X direction is smaller than the size of the light-emitting region of the third color sub-pixel 230 in the X direction. To ensure that the distance (PDL gap) between the boundaries of the light-emitting regions of different color sub-pixels is consistent, the first distance is slightly larger than the fourth distance. The consistency of the PDL gap between the boundaries of the light-emitting regions of the above different color sub-pixels can ensure that under certain process precision conditions, the product resolution and aperture ratio are maximized.

[0088] For example, asFigures 5 - 6 As shown, the distance between the centers of the first color sub-pixels 210 and the centers of the third color sub-pixels 230 in each repeating unit 200 is i + f, and the distance between the centers of the first color sub-pixels 210 and the centers of the third color sub-pixels 230 that are adjacent to each other in two adjacent repeating units 200 within the same repeating unit group 2000 is g + h. The ratio of these two distances is 1.5 to 2.3. For example, the distance between the centerlines of the first color sub-pixels 210 in the Z direction and the centerlines of the third color sub-pixels 230 in the Z direction in each repeating unit 200 is i + f, and the distance between the centerline of the third color sub-pixel 230 in the Z direction in the first repeating unit 201 and the centerline of the first color sub-pixel 210 in the Z direction extending in the second repeating unit 202 is g + h. The ratio of these two distances is 1.5 to 2.3. For example, the ratio of these two distances can be 1.8 to 2.0. For example, within the same repeating unit group 2000, the distances between the centerlines of the two third color sub-pixels 230 that are closest to the first color sub-pixel 210 and extending in the Z direction are i + f and g + h respectively. For example, within the same repeating unit group 2000, the ratio of the distances between the centerlines of the two third color sub-pixels 230 that are closest to the first color sub-pixel 210 and extending in the Z direction is 1.5 to 2.3, for example, 1.8 to 2.0. For example, within the same repeating unit group 2000, the distances between the centerlines of the two first color sub-pixels 210 that are closest to the third color sub-pixel 230 and extending in the Z direction are i + f and g + h respectively. For example, within the same repeating unit group 2000, the ratio of the distances between the centerlines of the two first color sub-pixels 210 that are closest to the third color sub-pixel 230 and extending in the Z direction is 1.5 to 2.3, for example, 1.8 to 2.0.

[0089] For example, in an example of the embodiment of the present disclosure, the first color sub-pixel 210 is a red sub-pixel, and the third color sub-pixel 230 is a blue sub-pixel. Relative to Figure 3 In the shown display substrate, in the case where the distances from the red sub-pixel to the two blue sub-pixels that are closest to the red sub-pixel along the X direction are equal, the embodiment of the present disclosure can, while ensuring that the positions of the vias in the planarization layer are not adjusted significantly to reduce the impact on the overall pixel circuit structure, avoid the occurrence of color deviation as much as possible by adjusting the distance relationship between the red sub-pixels and the blue sub-pixels arranged along the X direction.

[0090] Figure 7A For the Figure 6 partial cross-sectional structure schematic diagram intercepted by the line BB' as shown. As Figure 7AAs shown, each sub-pixel, such as the third-color sub-pixel, includes an organic light-emitting element. The organic light-emitting element includes a first electrode 231, a second electrode 232, and a light-emitting layer 233 located between the first electrode 231 and the second electrode 232. The second electrode 232 is located between the first electrode 231 and the substrate 100. The display substrate further includes a pixel defining layer 130. The pixel defining layer 130 includes an opening for defining the light-emitting region of each sub-pixel. The shape of the light-emitting region of the sub-pixel can be defined by the opening of the pixel defining layer. For example, taking the third-color sub-pixel as an example, the second electrode 232 of the organic light-emitting element can be disposed between the pixel defining layer 130 and the substrate 100. The opening of the pixel defining layer 130 for defining the sub-pixel exposes a part of the second electrode 232. When the light-emitting layer 233 is formed in the opening of the pixel defining layer 130, the light-emitting layer 233 is in contact with the second electrode 232, so that this part can drive the light-emitting layer 233 to emit light. The opening of the pixel defining layer 130 defines the shape of the light-emitting region 2300 of the third-color sub-pixel 230. Similarly, the opening of the pixel defining layer also defines the shapes of the light-emitting regions of the first-color sub-pixel and the second-color sub-pixel.

[0091] For example, as Figures 5 - 7A shown, each sub-pixel includes a light-emitting region. The shapes of the light-emitting regions 2100 of the first-color sub-pixels 210 and 2300 of the third-color sub-pixels 230 include a hexagon or an ellipse. The shapes of the light-emitting regions 2200 of each of the second-color sub-pixels 2210 and 2220 in the second-color sub-pixel pair 220 include a pentagon, a circle, or a teardrop shape.

[0092] For example, as Figures 5 - 7A shown, the shapes of the light-emitting regions 2100 of the first-color sub-pixels 210 and 2300 of the third-color sub-pixels 230 are both hexagons. The three pairs of opposite sides in the hexagon are parallel, and the light-emitting regions 2100 of the first-color sub-pixels 210 and 2300 of the third-color sub-pixels 230 include sides parallel to the second direction. The shape of the light-emitting region 2200 of each second-color sub-pixel 2210 (or 2220) is a pentagon. The pentagon includes a pair of parallel opposite sides (parallel to the second direction) and a vertical side (parallel to the first direction). The vertical side is perpendicular to the pair of parallel opposite sides. The two vertical sides of the light-emitting regions 2200 in each second-color sub-pixel pair 220 are adjacent to each other.

[0093] In addition, although in Figures 5 - 6The shape of the light-emitting region of each sub-pixel in [it] includes a strict angle formed by two line segments. However, in some embodiments, the shape of the light-emitting region of each sub-pixel can be a rounded-corner graphic, such as a circle or a teardrop shape. That is, based on the above various graphic shapes, the corners of the light-emitting regions of each sub-pixel are rounded. For example, when forming the opening of the pixel defining layer, the part at the corner of the opening may form a rounded-corner shape, so that the shape of the formed light-emitting region may be a rounded-corner shape.

[0094] For example, in the embodiments of the present disclosure, the first color sub-pixel 210 is taken as a red sub-pixel, the second color sub-pixel 220 is taken as a green sub-pixel, and the third color sub-pixel 230 is taken as a blue sub-pixel for description. However, it is not limited thereto, and the colors can be interchanged.

[0095] Figure 8 It is a schematic diagram of the pixel circuit included in each sub-pixel and connected to the organic light-emitting element. As Figure 8 shown, the pixel circuit 0221 of each sub-pixel may include a driving circuit 0222, a first light-emitting control circuit 0223, a second light-emitting control circuit 0224, a data writing circuit 0226, a storage circuit 0227, a threshold compensation circuit 0228, and a reset circuit 0229. The driving circuit 0222 includes a control terminal, a first terminal, and a second terminal, and is configured to provide a driving current for driving the organic light-emitting element 0220 to emit light to the organic light-emitting element 0220.

[0096] For example, the first light-emitting control circuit 0223 is respectively connected to the first voltage terminal VDD and the first terminal of the driving circuit 0222, and is configured to realize the connection conduction or disconnection between the driving circuit 0222 and the first voltage terminal VDD. The second light-emitting control circuit 0224 is respectively electrically connected to the second terminal of the driving circuit 0222 and the first electrode of the organic light-emitting element 0220, and is configured to realize the connection conduction or disconnection between the driving circuit 0222 and the organic light-emitting element 0220. The data writing circuit 0226 is electrically connected to the first terminal of the driving circuit 0222, and is configured to write a data signal into the storage circuit 0227 under the control of a scanning signal. The storage circuit 0227 is respectively electrically connected to the control terminal of the driving circuit 0222 and the first voltage terminal VDD, and is configured to store the data signal. The threshold compensation circuit 0228 is respectively electrically connected to the control terminal and the second terminal of the driving circuit 0222, and is configured to perform threshold compensation on the driving circuit 0222. The reset circuit 0229 is electrically connected to the control terminal of the driving circuit 0222 and the first electrode of the organic light-emitting element 0220, and is configured to reset the control terminal of the driving circuit 0222 and the first electrode of the organic light-emitting element 0220 under the control of a reset control signal.

[0097] For example, as Figure 8As shown, the driving circuit 0222 includes a driving transistor T1. The control terminal of the driving circuit 0222 includes the gate of the driving transistor T1. The first terminal of the driving circuit 0222 includes the first pole of the driving transistor T1. The second terminal of the driving circuit 0222 includes the second pole of the driving transistor T1. The data writing circuit 0226 includes a data writing transistor T2. The storage circuit 0227 includes a capacitor C. The threshold compensation circuit 0228 includes a threshold compensation transistor T3. The first light emission control circuit 0223 includes a first light emission control transistor T4. The second light emission control circuit 0224 includes a second light emission control transistor T5. The reset circuit 0229 includes a first reset transistor T6 and a second reset transistor T7. The reset control signal may include a first sub-reset control signal and a second sub-reset control signal.

[0098] For example, as Figure 8As shown, a first pole of a data writing transistor T2 is electrically connected to a first pole of a driving transistor T1. A second pole of the data writing transistor T2 is configured to be electrically connected to a data line Vd to receive a data signal. A gate of the data writing transistor T2 is configured to be electrically connected to a first scan signal line Ga1 to receive a scan signal; a first pole of a capacitor C is electrically connected to a first power supply terminal VDD, and a second pole of the capacitor C is electrically connected to a gate of the driving transistor T1; a first pole of a threshold compensation transistor T3 is electrically connected to a second pole of the driving transistor T1, a second pole of the threshold compensation transistor T3 is electrically connected to a gate of the driving transistor T1, and a gate of the threshold compensation transistor T3 is configured to be electrically connected to a second scan signal line Ga2 to receive a compensation control signal; a first pole of a first reset transistor T6 is configured to be electrically connected to a first reset power supply terminal Vinit1 to receive a first reset signal, a second pole of the first reset transistor T6 is electrically connected to a gate of the driving transistor T1, and a gate of the first reset transistor T6 is configured to be electrically connected to a first reset control signal line Rst1 to receive a first sub-reset control signal; a first pole of a second reset transistor T7 is configured to be electrically connected to a second reset power supply terminal Vinit2 to receive a second reset signal, a second pole of the second reset transistor T7 is electrically connected to a first electrode of an organic light-emitting element 0220, and a gate of the second reset transistor T7 is configured to be electrically connected to a second reset control signal line Rst2 to receive a second sub-reset control signal; a first pole of a first light-emitting control transistor T4 is electrically connected to a first power supply terminal VDD, a second pole of the first light-emitting control transistor T4 is electrically connected to a first pole of the driving transistor T1, and a gate of the first light-emitting control transistor T4 is configured to be electrically connected to a first light-emitting control signal line EM1 to receive a first light-emitting control signal; a first pole of a second light-emitting control transistor T5 is electrically connected to a second pole of the driving transistor T1, a second pole of the second light-emitting control transistor T5 is electrically connected to a second electrode of the organic light-emitting element 0220, and a gate of the second light-emitting control transistor T5 is configured to be electrically connected to a second light-emitting control signal line EM2 to receive a second light-emitting control signal; a first electrode of the organic light-emitting element 0220 is electrically connected to a second power supply terminal VSS.

[0099] For example, one of the first power supply terminal VDD and the second power supply terminal VSS is a high voltage terminal, and the other is a low voltage terminal. For example, as Figure 8 shown in the embodiment, the first power supply terminal VDD is a voltage source to output a constant first voltage, and the first voltage is a positive voltage; while the second power supply terminal VSS can be a voltage source to output a constant second voltage, and the second voltage is a negative voltage, etc. For example, in some examples, the second power supply terminal VSS can be grounded.

[0100] For example, as Figure 8As shown, the scan signal and the compensation control signal can be the same. That is, the gates of the data writing transistor T2 and the threshold compensation transistor T3 can be electrically connected to the same signal line, such as the first scan signal line Ga1, to receive the same signal (e.g., the scan signal). At this time, the display substrate may not be provided with the second scan signal line Ga2, reducing the number of signal lines. For another example, the gates of the data writing transistor T2 and the threshold compensation transistor T3 can also be electrically connected to different signal lines respectively. That is, the gate of the data writing transistor T2 is electrically connected to the first scan signal line Ga1, and the gate of the threshold compensation transistor T3 is electrically connected to the second scan signal line Ga2, and the signals transmitted by the first scan signal line Ga1 and the second scan signal line Ga2 are the same.

[0101] It should be noted that the scan signal and the compensation control signal can also be different, so that the gates of the data writing transistor T2 and the threshold compensation transistor T3 can be separately controlled, increasing the flexibility of controlling the pixel circuit.

[0102] For example, as Figure 8 shown, the first light emission control signal and the second light emission control signal can be the same. That is, the gates of the first light emission control transistor T4 and the second light emission control transistor T5 can be electrically connected to the same signal line, such as the first light emission control signal line EM1, to receive the same signal (e.g., the first light emission control signal). At this time, the display substrate may not be provided with the second light emission control signal line EM2, reducing the number of signal lines. For another example, the gates of the first light emission control transistor T4 and the second light emission control transistor T5 can also be electrically connected to different signal lines respectively. That is, the gate of the first light emission control transistor T4 is electrically connected to the first light emission control signal line EM1, and the gate of the second light emission control transistor T5 is electrically connected to the second light emission control signal line EM2, and the signals transmitted by the first light emission control signal line EM1 and the second light emission control signal line EM2 are the same.

[0103] It should be noted that when the first light emission control transistor T4 and the second light emission control transistor T5 are transistors of different types, for example, the first light emission control transistor T4 is a P-type transistor and the second light emission control transistor T5 is an N-type transistor, the first light emission control signal and the second light emission control signal can also be different, and the embodiments of the present disclosure do not limit this.

[0104] For example, the first sub-reset control signal and the second sub-reset control signal can be the same. That is, the gates of the first reset transistor T6 and the second reset transistor T7 can be electrically connected to the same signal line, such as the first reset control signal line Rst1, to receive the same signal (for example, the first sub-reset control signal). At this time, the display substrate may not be provided with the second reset control signal line Rst2, reducing the number of signal lines. For another example, the gates of the first reset transistor T6 and the second reset transistor T7 can also be electrically connected to different signal lines respectively. That is, the gate of the first reset transistor T6 is electrically connected to the first reset control signal line Rst1, and the gate of the second reset transistor T7 is electrically connected to the second reset control signal line Rst2, while the signals transmitted by the first reset control signal line Rst1 and the second reset control signal line Rst2 are the same. It should be noted that the first sub-reset control signal and the second sub-reset control signal can also be different.

[0105] For example, in some examples, the second sub-reset control signal can be the same as the scan signal. That is, the gate of the second reset transistor T7 can be electrically connected to the scan signal line Ga to receive the scan signal as the second sub-reset control signal.

[0106] For example, the sources of the first reset transistor T6 and the second reset transistor T7 are respectively connected to the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2. The first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be DC reference voltage terminals to output a constant DC reference voltage. The first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be the same. For example, the sources of the first reset transistor T6 and the second reset transistor T7 are connected to the same reset power supply terminal. The first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be high voltage terminals or low voltage terminals, as long as they can provide the first reset signal and the second reset signal to reset the gate of the driving transistor T1 and the first electrode of the light-emitting element 0220. The present disclosure does not limit this. For example, the sources of the first reset transistor T6 and the second reset transistor T7 can both be connected to the reset power supply signal line Init.

[0107] It should be noted that Figure 8 The driving circuit 0222, data writing circuit 0226, storage circuit 0227, threshold compensation circuit 0228, and reset circuit 0229 in the pixel circuit shown are only schematic. The specific structures of circuits such as the driving circuit 0222, data writing circuit 0226, storage circuit 0227, threshold compensation circuit 0228, and reset circuit 0229 can be set according to actual application requirements, and the embodiments of the present disclosure do not specifically limit this.

[0108] For example, according to the characteristics of transistors, transistors can be divided into N-type transistors and P-type transistors. For the sake of clarity, the embodiments of the present disclosure take the transistor as a P-type transistor (for example, a P-type MOS transistor) as an example to elaborate on the technical solution of the present disclosure. That is to say, in the description of the present disclosure, the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6, and the second reset transistor T7 can all be P-type transistors. However, the transistors of the embodiments of the present disclosure are not limited to P-type transistors. Those skilled in the art can also use N-type transistors (for example, N-type MOS transistors) according to actual needs to implement the functions of one or more transistors in the embodiments of the present disclosure.

[0109] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polycrystalline silicon thin film transistors, etc. The source and drain of the transistor may be symmetrical in structure, so the source and drain may be indistinguishable in physical structure. In the embodiments of the present disclosure, in order to distinguish transistors, except for the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other electrode is directly described as the second electrode, so the first electrode and the second electrode of all or part of the transistors in the embodiments of the present disclosure can be interchangeable as needed.

[0110] It should be noted that, in the embodiment of the present disclosure, the pixel circuit of the sub-pixel can be Figure 8 In addition to the 7T1C structure (ie, seven transistors and one capacitor) shown, a structure including other numbers of transistors may also be used, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, which is not limited in the embodiments of the present disclosure.

[0111] Figures 9A - 10 Schematic diagram of each layer of a pixel circuit provided in some embodiments of the present disclosure. Figures 9A - 10 Describe the positional relationship of each circuit in the pixel circuit on the backplane. Figures 9A - 10 The example shown takes the pixel circuit 0221 of four adjacent sub-pixels as an example, and illustrates the positions of the transistors of the pixel circuit included in one sub-pixel, and the positions of the components included in the pixel circuits of other sub-pixels are roughly the same as the positions of the transistors included in the sub-pixel. Figure 9A As shown, the pixel circuit 0221 of the sub-pixel includes Figure 8 The driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6 and the second reset transistor T7, and the capacitor C are shown.

[0112] For example, Figure 9A The active semiconductor layer 310 of the pixel circuit in the display substrate is shown. The active semiconductor layer 310 can be formed by patterning a semiconductor material. The active semiconductor layer 310 can be used to fabricate the active layers of the driving transistor T1, data writing transistor T2, threshold compensation transistor T3, first light-emitting control transistor T4, second light-emitting control transistor T5, first reset transistor T6, and second reset transistor T7 described above. The active semiconductor layer 310 includes the active layer patterns (channel regions) and doping region patterns (source / drain doping regions) of the transistors in each sub-pixel, and the active layer patterns and doping region patterns of the transistors in the same pixel circuit are integrally provided.

[0113] It should be noted that the active layer can include an integrally formed low-temperature polysilicon layer, and the source region and drain region can be made conductive through doping or the like to achieve electrical connection of each structure. That is, the active semiconductor layer of each transistor in each sub-pixel is an integral pattern formed of p-silicon, and each transistor in the same pixel circuit includes a doping region pattern (i.e., source region and drain region) and an active layer pattern, and the active layers of different transistors are separated by a doping structure.

[0114] For example, the active semiconductor layer 310 can be fabricated using amorphous silicon, polysilicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities.

[0115] For example, the active semiconductor layers in the pixel circuits of different color sub-pixels arranged in the first direction have no connection relationship and are disconnected from each other. The active semiconductor layers in the pixel circuits of the sub-pixels arranged in the second direction can be integrally provided or can be disconnected from each other.

[0116] Figures 9A - 10 The scan signal lines Ga (including the first scan signal line Ga1 and the second scan signal line Ga2), reset control signal lines Rst (including the first reset control signal line Rst1 and the second reset control signal line Rst2), reset power signal line Init of the reset power supply terminal Vinit (including the first reset power signal line Init1 of the first reset power supply terminal Vinit1 and the second reset power signal line Init2 of the second reset power supply terminal Vinit2), light-emitting control signal lines EM (including the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2), data line Vd, and power supply signal lines VDD (including the first power supply signal line VDD1 and the second power supply signal line VDD2) electrically connected to the pixel circuits 0121 of each color sub-pixel are also shown. The first power supply signal line VDD1 and the second power supply signal line VDD2 are electrically connected to each other.

[0117] It should be noted that inFigures 9A to 10 In the example shown, the first scan signal line Ga1 and the second scan signal line Ga2 are the same scan signal line Ga, the first reset power supply signal line Init1 and the second reset power supply signal line Init2 are the same reset power supply signal line Init, the first reset control signal line Rst1 and the second reset control signal line Rst2 are the same bit control signal line Rst, and the first light emission control signal line EM1 and the second light emission control signal line EM2 are the same light emission control signal line EM, but are not limited thereto.

[0118] For example, the gate metal layer of the pixel circuit may include a first conductive layer and a second conductive layer. A gate insulating layer ( Figure 7A the shown gate insulating layer 160) is formed on the above-mentioned active semiconductor layer 310 for insulating the above-mentioned active semiconductor layer 310 from the subsequently formed gate metal layer. Figure 9B The first conductive layer 320 included in the display substrate is shown. The first conductive layer 320 is disposed on the side of the gate insulating layer away from the active semiconductor layer 310, so as to be insulated from the active semiconductor layer 310. The first conductive layer 320 may include the second pole CC2 of the capacitor C, the scan signal line Ga, the reset control signal line Rst, the light emission control signal line EM, and the gates of the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6, and the second reset transistor T7.

[0119] For example, as Figure 9B shown, the gate of the data writing transistor T2 may be the overlapping part of the scan signal line Ga and the active semiconductor layer 310; the gate of the first light emission control transistor T4 may be the first overlapping part of the light emission control signal line EM and the active semiconductor layer 310, and the gate of the second light emission control transistor T5 may be the second overlapping part of the light emission control signal line EM and the active semiconductor layer 310; the gate of the first reset transistor T6 may be the first overlapping part of the reset control signal line Rst and the active semiconductor layer 310, and the gate of the second reset transistor T7 may be the second overlapping part of the reset control signal line Rst and the active semiconductor layer 310; the threshold compensation transistor T3 may be a thin film transistor with a double gate structure. The first gate of the threshold compensation transistor T3 may be the overlapping part of the scan signal line Ga and the active semiconductor layer 310, and the second gate of the threshold compensation transistor T3 may be the overlapping part of the protruding structure P protruding from the scan signal line Ga and the active semiconductor layer 310. As Figure 8 and 9B shown, the gate of the driving transistor T1 may be the second pole CC2 of the capacitor C.

[0120] It should be noted that Figure 9AEach dashed rectangular box therein shows the overlapping parts of the first conductive layer 320 and the active semiconductor layer 310. As the channel regions of the respective transistors, the active semiconductor layers on both sides of each channel region are made conductive through processes such as ion doping to form the first and second poles of the respective transistors.

[0121] For example, as Figure 9B shown, the scan signal line Ga, the reset control signal line Rst, and the emission control signal line EM are arranged along the second direction Z. The scan signal line Ga is located between the reset control signal line Rst and the emission control signal line EM.

[0122] For example, in the second direction Z, the second pole CC2 of the capacitor C (i.e., the gate of the driving transistor T1) is located between the scan signal line Ga and the emission control signal line EM. The protruding structure P protruding from the scan signal line Ga is located on the side of the scan signal line Ga away from the emission control signal line EM.

[0123] For example, as Figure 9A and Figure 9B shown, in the second direction Z, the gates of the data writing transistor T2, the threshold compensation transistor T3, and the first reset transistor T6 are all located on the first side of the gate of the driving transistor T1, and the gates of the first emission control transistor T4, the second emission control transistor T5, and the second reset transistor T7 are all located on the second side of the gate of the driving transistor T1. For example, Figures 9A - 9B in the example shown, the first side and the second side of the gate of the driving transistor T1 of the pixel circuit of the sub-pixel are the opposite sides of the gate of the driving transistor T1 in the second direction Z. For example, as Figures 9A - 9B shown, in the XZ plane, the first side of the gate of the driving transistor T1 of the pixel circuit of the sub-pixel can be the upper side of the gate of the driving transistor T1, and the second side of the gate of the driving transistor T1 of the pixel circuit of the sub-pixel can be the lower side of the gate of the driving transistor T1. The lower side, for example, the side of the display substrate for bonding the IC is the lower side of the display substrate, and the lower side of the gate of the driving transistor T1 is the side of the gate of the driving transistor T1 closer to the IC. The upper side is the opposite side of the lower side, for example, the upper side is the side of the gate of the driving transistor T1 farther from the IC.

[0124] For example, in some embodiments, as Figures 9A - 9B shown, in the first direction X, the gates of the data writing transistor T2 and the first emission control transistor T4 are both located on the third side of the gate of the driving transistor T1, and the first gate of the threshold compensation transistor T3, the gates of the second emission control transistor T5, and the second reset transistor T7 are all located on the fourth side of the gate of the driving transistor T1. For example, Figures 9A - 9BIn the example shown, the third side and the fourth side of the gate of the driving transistor T1 of the pixel circuit of the sub-pixel are two opposite sides of the gate of the driving transistor T1 in the first direction X. For example, as Figures 9A - 9B shown, the third side of the gate of the driving transistor T1 of the pixel circuit may be the right side of the gate of the driving transistor T1 of the pixel circuit, and the fourth side of the gate of the driving transistor T1 of the pixel circuit may be the left side of the gate of the driving transistor T1 of the pixel circuit. The left side and the right side are opposite sides. For example, among the data line Vd and the first power supply signal line VDD1 connected to the same pixel circuit, the data line Vd is on the right side of the first power supply signal line VDD1, and the first power supply signal line VDD1 is on the left side of the data line Vd.

[0125] It should be noted that the structure of each pixel circuit may be Figures 9A - 10 the mirror structure shown, that is, the structures of each layer of each pixel circuit are based on the channel region of the driving transistor T1, and the structures on the left and right sides are flipped. Therefore, the relationship between the left side and the right side described above may be opposite.

[0126] For example, a first insulating layer (such as the first insulating layer 150 shown in Figure 7A ) is formed on the above-mentioned first conductive layer 320 to insulate the first conductive layer 320 from the second conductive layer 330 formed subsequently. Figure 9C The second conductive layer 330 of the pixel circuit is shown. The second conductive layer 330 includes the first pole CC1 of the capacitor C, the reset power supply signal line Init, the second power supply signal line VDD2, and the light-shielding portion S. The second power supply signal line VDD2 and the first pole CC1 of the capacitor C may be integrally formed. Through the second power supply signal line VDD2 and the first pole CC1 of the capacitor C, multiple first power supply signal lines VDD1 (described later) extending in the Z direction are connected to form a grid-shaped wiring to reduce the resistance. The first pole CC1 of the capacitor C and the second pole CC2 of the capacitor C at least partially overlap to form the capacitor C.

[0127] For example, as Figure 9CAs shown, when the dual-gate threshold compensation transistor T3 is turned off, the active semiconductor layer between the two channels of the dual-gate threshold compensation transistor T3 is in a floating state and is susceptible to jumping due to the influence of the surrounding circuit voltage, which will affect the leakage current of the threshold compensation transistor T3 and thus affect the emission brightness. In order to keep the voltage of the active semiconductor layer between the two channels of the threshold compensation transistor T3 stable, a light-shielding portion S is designed to form a capacitor with the active semiconductor layer between the two channels of the threshold compensation transistor T3. The light-shielding portion S can be connected to the first power signal line VDD1 to obtain a constant voltage, so that the voltage of the active semiconductor layer in the floating state can be kept stable. The light-shielding portion S overlaps with the active semiconductor layer between the two channels of the dual-gate threshold compensation transistor T3, and can also prevent the active semiconductor layer between the two gates from being illuminated and changing its characteristics. For example, it can prevent the voltage of this part of the active semiconductor layer from changing to prevent crosstalk.

[0128] For example, a second insulating layer (such as Figure 7A the second insulating layer 140 shown) is formed on the above-mentioned second conductive layer 330 to insulate the above-mentioned second conductive layer 330 from the source-drain metal layer 340 formed subsequently. Figure 9D The source-drain metal layer 340 of the pixel circuit is shown. The source-drain metal layer 340 includes a data line Vd and a first power signal line VDD1. The above-mentioned data line Vd and the first power signal line VDD1 both extend in the Z direction.

[0129] For example, the source-drain metal layer 340 further includes a first connection portion 341, a second connection portion 342, and a third connection portion 343. Figure 9D Exemplary positions of a plurality of vias are also shown. The source-drain metal layer 340 is connected to a plurality of film layers located between the source-drain metal layer 340 and the substrate through the plurality of vias shown. As Figure 9D shown, vias filled with different materials indicate that the source-drain metal layer 340 is connected to different film layers through them. For example, the white-filled via indicates that the source-drain metal layer 340 is connected to Figure 9A the active semiconductor layer 310 shown through it, and the black-filled via indicates that the source-drain metal layer 340 is connected to Figure 9C the second conductive layer 330 shown through it, and the via 385 indicates that the source-drain metal layer 340 is connected to Figure 9B the first conductive layer 320 shown through it.

[0130] For example, as Figure 7A 、 Figures 9A - 9DAs shown, the data line Vd is electrically connected to the second pole of the data writing transistor T2 through a via 381 that penetrates the gate insulating layer 160, the first insulating layer 150, and the second insulating layer 140. The first power supply signal line VDD1 is electrically connected to the first pole of the first light-emitting control transistor T4 through a via 382 that penetrates the gate insulating layer 160, the first insulating layer 150, and the second insulating layer 140. The first power supply signal line VDD1 and the data line Vd are alternately arranged in the first direction. The first power supply signal line VDD1 is electrically connected to the second power supply signal line VDD2 (the first pole CC1 of the storage capacitor) through a via 3832 that penetrates the second insulating layer 140. The first power supply signal line VDD1 extends in the second direction Z, and the second power supply signal line VDD2 extends in the first direction X. The first power supply signal line VDD1 and the second power supply signal line VDD2 are grid-wired on the display substrate. That is, on the entire display substrate, the first power supply signal line VDD1 and the second power supply signal line VDD2 are arranged in a grid pattern, so that the resistance of the signal line of the power supply terminal VDD is small and the voltage drop is low, and thus the stability and uniformity of the power supply voltage provided by the power supply terminal VDD can be improved. The first power supply signal line VDD1 is electrically connected to the light-shielding portion S through a via 3833 that penetrates the second insulating layer to provide a constant voltage to the light-shielding portion S. One end of the first connection portion 341 is electrically connected to the second pole of the threshold compensation transistor T3 through a via 384 in the gate insulating layer 160, the first insulating layer 150, and the second insulating layer 140, and the other end of the first connection portion 341 is electrically connected to the gate of the driving transistor T1 (i.e., the second pole CC2 of the capacitor C) through a via 385 in the first insulating layer 150 and the second insulating layer 140. One end of the second connection portion 342 is electrically connected to the reset power supply signal line Init through a via 386 in the second insulating layer 140, and the other end of the second connection portion 342 is electrically connected to the first pole of the second reset transistor T7 through a via 387 in the gate insulating layer 160, the first insulating layer 150, and the second insulating layer 140. The third connection portion 343 includes a first portion 3431 and a second portion 3432. The first portion 3431 of the third connection portion 343 is electrically connected to the second pole of the second light-emitting control transistor T5 through a via 352 in the gate insulating layer 160, the first insulating layer 150, and the second insulating layer 140.

[0131] For example, a planarization layer (such as the planarization layer 120 shown Figure 7A as) is formed on the above-mentioned source-drain metal layer 340 to protect the above-mentioned source-drain metal layer 340. As Figure 9DAs shown, the flat layer 120 includes vias 354. The second electrodes of the organic light-emitting elements of each sub-pixel can be disposed on the side of the flat layer 120 away from the substrate 100, and the second electrodes of the organic light-emitting elements are electrically connected to the second part 3432 of the third connection portion 343 through the vias 354 to achieve electrical connection to the second pole of the second light-emitting control transistor T5.

[0132] For example, Figure 7B In an example of an embodiment of the present disclosure, along Figure 6 The partial cross-sectional structure schematic diagram cut along the II' line shown. As Figure 7B As shown, a passivation layer 170 is further disposed between the flat layer 120 and the third connection portion 343. The passivation layer 170 can be disposed at the position where the power signal line is located at the boundary between the peripheral area and the display area to protect the source-drain metal layer 340. The passivation layer 170 can be an inorganic layer, and the flat layer 120 can be an organic layer, and the thickness of the organic layer is thicker than that of the inorganic layer such as the passivation layer.

[0133] For example, as Figure 7B As shown, the second electrode 212 of the organic light-emitting element of the first color sub-pixel is connected to the third connection portion 343 through the nested via 1271 (i.e., via 354) located in the flat layer 120 and the passivation layer 170, and then connected to the second light-emitting control transistor. Similarly, the second electrodes of the organic light-emitting elements of the second color sub-pixels and the second electrodes of the organic light-emitting elements of the third color sub-pixels can all be connected to the corresponding third connection portions through the nested vias located in the flat layer and the passivation layer. For example, the nested via 1271 includes a via 121 in the flat layer 120 and a via 171 in the passivation layer 170. The position of the via 121 in the flat layer 120 is opposite to that of the via 171 in the passivation layer 170, and the orthographic projection of the via 121 in the flat layer 120 on the substrate 100 is located within the orthographic projection of the via 171 in the passivation layer 170 on the substrate 100. Of course, the embodiment of the present disclosure is not limited thereto. For example, the positions of the flat layer 120 and the passivation layer 170 can be interchanged, that is, the passivation layer can be located on the side of the flat layer away from the source-drain metal layer, or only the flat layer is provided without the passivation layer.

[0134] Figure 9E To correspond to Figures 9A - 9D The planar schematic diagram of the organic light-emitting elements corresponding to the pixel circuit structures shown one by one. As Figures 5 - 6 And Figures 9A - 9EAs shown, the second electrode 212 of the first color sub-pixel 210 includes a first main electrode 2121 and a first connection electrode 2122. The first main electrode 2121 and the first connection electrode 2122 may be an integral structure, and the first connection electrode 2122 is connected to the second part 3432 of the third connection portion 343 through a first via 3541 to connect to the second pole of the second light-emitting control transistor T5 of the first color sub-pixel 210. The second electrodes 222 of the second color sub-pixels in the second color sub-pixel pair 220 include a second main electrode 2221 and a second connection electrode 2222. The second main electrode 2221 and the second connection electrode 2222 may be an integral structure, and the second connection electrode 2222 of the second color sub-pixel is connected to the second part 3432 of the third connection portion 343 through a second via 3543 to connect to the second pole of the second light-emitting control transistor T5 of the second color sub-pixel. The second electrode 232 of the third color sub-pixel 230 includes a third main electrode 2321 and a third connection electrode 2322. The third main electrode 2321 and the third connection electrode 2322 may be an integral structure, and the third connection electrode 2322 is connected to the second part 3432 of the third connection portion 343 through a third via 3543 to connect to the second pole of the second light-emitting control transistor T5 of the third color sub-pixel 130.

[0135] For example, as Figures 5 - 6 and Figure 9E shown, the shape of the main electrode of each sub-pixel is substantially the same as the shape of the light-emitting region. For example, the shapes of the first main electrode 2121 of the first color sub-pixel 210 and the third main electrode 2321 of the third color sub-pixel 230 are substantially hexagonal or elliptical, and the shapes of the second main electrodes 2221 of each of the second color sub-pixels 2210 and 2220 in the second color sub-pixel pair 220 are substantially pentagonal, circular or droplet-shaped.

[0136] For example, in the first color sub-pixel 210, the center of the light-emitting region 2100 substantially coincides with the geometric center of the shape of the first main electrode 2121, and the centerline of the light-emitting region 2100 extending in the second direction substantially coincides with the centerline of the second main electrode 2121 extending in the second direction. Thus, the geometric center of the shape of the first main electrode 2121 is the center of the first color sub-pixel 210. In the second color sub-pixel pair 220, the center of the light-emitting region 2200 substantially coincides with the geometric center of the shape of the second main electrode 2221, and the centerline of the light-emitting region 2200 extending in the second direction substantially coincides with the centerline of the second main electrode 2221 extending in the second direction. Thus, the midpoint of the line connecting the geometric centers of the two second main electrodes 2221 included in the second color sub-pixel pair 220 is the center of the second color sub-pixel pair 220. In the third color sub-pixel 230, the center of the light-emitting region 2300 substantially coincides with the geometric center of the shape of the third main electrode 2321, and the centerline of the light-emitting region 2300 extending in the second direction substantially coincides with the centerline of the third main electrode 2321 extending in the second direction. Thus, the geometric center of the shape of the third main electrode 2321 is the center of the third color sub-pixel 230. In each repeating unit 200, the distance in the first direction between the center of the third main electrode 2321 and the center of the second main electrode 2221 may be a first distance. The distance in the first direction between the center of the third main electrode 2321 in the first repeating unit 201 and the center of the second main electrode 2221 in the third repeating unit 203 may be a second distance. The distance in the first direction between the center of the first main electrode 2121 in the second repeating unit 202 and the center of the second main electrode 2221 in the third repeating unit 203 may be a third distance. The distance in the first direction between the center of the first main electrode 2121 and the center of the second main electrode 2221 in each repeating unit 200 may be a fourth distance.

[0137] For example, as Figure 9D and Figure 9E shown, the fourth vias 352 in the pixel circuit arranged in the X direction are located on a straight line extending in the X direction and are equally spaced.

[0138] For example, the fourth vias 352 of the second color sub-pixels do not overlap with their light-emitting regions, and the fourth vias 352 of the second color sub-pixels are located on the side of the second vias 3542 of the second color sub-pixels close to the first vias 3541 of the first color sub-pixels 310, and the fourth vias 352 of the second color sub-pixels overlap with the positive projection of the second vias 3542 on a straight line extending in the second direction. Thus, the position of the second vias 3542 in the planarization layer is not significantly adjusted in the second direction (Z direction) relative to the position of the fourth vias 352 penetrating through the gate insulating layer, the first insulating layer, and the second insulating layer, thereby reducing the impact on the overall pixel circuit structure. For example, the fourth vias 352 of the second color sub-pixels are arranged in the first direction with the second vias 3542.

[0139] For example, among the two second color sub-pixels included in the second color sub-pixel pair 220, the relative positional relationship between the second vias 3452 and the fourth vias 352 corresponding to the same sub-pixel is the same. For example, among the two second color sub-pixels included in the second color sub-pixel pair 220, the two corresponding second vias are located on a straight line extending in the second direction, and the two corresponding fourth vias are located on another straight line extending in the second direction, and the two straight lines do not coincide.

[0140] For example, the fourth vias 352 of the first color sub-pixels 210 do not overlap with their light-emitting regions, and the fourth vias 352 of the first color sub-pixels are located on the side of the first vias 3542 of the first color sub-pixels away from their light-emitting regions, and the fourth vias 352 overlap with the positive projection of the first vias 3541 on a straight line extending in the first direction. For example, the fourth vias of the first color sub-pixels are arranged in the second direction with the first vias.

[0141] For example, the fourth vias 352 of the third color sub-pixels 230 do not overlap with their light-emitting regions, and the fourth vias 352 of the third color sub-pixels are located on the side of the third vias 3543 of the third color sub-pixels away from their light-emitting regions, and the fourth vias 352 overlap with the positive projection of the third vias 3543 on a straight line extending in the first direction. For example, the fourth vias of the third color sub-pixels are arranged in the second direction with the third vias.

[0142] Figure 10 is Figures 9A - 9E a planar schematic diagram after the lamination of the indicated film layers. As Figures 9E - 10As shown, for example, the first connection electrode 2122 of the first color sub-pixel 210 is located on the side away from the reset control signal line Rst of the pixel circuit connecting this sub-pixel at the center of the first main electrode 2121 in the Z direction, and is located on the side close to the data line Vd of the pixel circuit connecting this sub-pixel at the center of the first main electrode 2121 in the X direction. For example, the first connection electrode 2122 and the first main electrode 2121 of the first color sub-pixel 210 are arranged in the Z direction, and the first connection electrode 2122 is located at the lower right corner of the first main electrode 2121. For example, the two second connection electrodes 2222 in the second color sub-pixel pair 220 are located on both sides of the two second main electrodes 2221 in the Z direction. For example, the two second connection electrodes 2222 and the two second main electrodes 2221 of the second color sub-pixel pair 220 are arranged in the Z direction. In one second color sub-pixel, the second connection electrode 2222 is located at the upper right corner of the second main electrode 2221, and in the other second color sub-pixel, the second connection electrode 2222 is located at the lower right corner of the second main electrode 2221. For example, the third connection electrode 2322 of the third color sub-pixel 230 is located on the side away from the reset control signal line Rst of the pixel circuit connecting this sub-pixel at the center of the third main electrode 2321 in the Z direction, and is located on the side close to the first power supply signal line VDD1 of the pixel circuit connecting this sub-pixel at the center of the third main electrode 2321 in the X direction. For example, the third connection electrode 2322 and the third main electrode 2321 of the third color sub-pixel 230 are arranged in the Z direction, and the third connection electrode 2322 is located at the lower left corner of the third main electrode 2321.

[0143] For example, the orthographic projection of the opening of the pixel defining layer on the substrate is located within the orthographic projection of the main electrode of the corresponding second electrode on the substrate.

[0144] For example, the orthographic projection of the opening of the pixel defining layer on the substrate is located within the orthographic projection of the corresponding light-emitting layer on the substrate, that is, the light-emitting layer covers the opening of the pixel defining layer. For example, the area of the light-emitting layer is larger than the area of the corresponding opening of the pixel defining layer, that is, in addition to the part located inside the opening of the pixel defining layer, the light-emitting layer at least further includes the part covering the solid structure of the pixel defining layer. Usually, the light-emitting layer covers the solid structure of the pixel defining layer at each boundary of the opening of the pixel defining layer. It should be noted that the above description of the pattern of the light-emitting layer is based on the organic light-emitting layer of each patterned sub-pixel formed by, for example, the fine metal mask (FMM) process. In addition to the FMM manufacturing process, there are also some light-emitting layers that form an integral film layer in the entire display area using an open mask process, and its shape is continuous in the orthographic projection on the substrate. Therefore, there must be a part located inside the opening of the pixel defining layer and a part located on the solid structure of the pixel defining layer.

[0145] For example, asFigures 5 - 6 and Figures 9E - 10 As shown in Figures 9E - 10 , in the first color sub-pixel 210, the second electrode 212 is connected to the corresponding light-emitting control transistor (i.e., the second light-emitting control transistor T5) through the first via 3541 located in the planar layer; in the second color sub-pixel pair 220, the two second electrodes 222 of the two second color sub-pixels are respectively connected to the two corresponding second light-emitting control transistors T5 through the two second vias 3542 located in the planar layer; in the third color sub-pixel 230, the second electrode 232 is connected to the corresponding second light-emitting control transistor T5 through the third via 3543 located in the planar layer.

[0146] In the embodiments of the present disclosure (as shown in Figures 5 - 6 Figures 5 - 6 and Figures 9A - 9E shown), in the first color sub-pixel 210 in each repeating unit 200, one second color sub-pixel in the second color sub-pixel pair 220, and the third color sub-pixel 230, the via 352 connecting the first part 3431 of the third connection part 343 and the second light-emitting control transistor T5 is located on a straight line extending in the first direction, and the distance in the first direction between two adjacent vias 352 is the sub-pixel width. That is, the first part 3431 of the third connection part 343 in the first color sub-pixel 210, one second color sub-pixel in the second color sub-pixel pair 220, and the third color sub-pixel 230 in each repeating unit 200 is located on a straight line extending in the first direction.

[0147] Figure 3 In the pixel arrangement structure shown, the light-emitting region of the green sub-pixel 23 overlaps with the first part 291 of the third connection part, and the position of the via in the planar layer is greatly adjusted in the Z direction relative to the position of the via connecting the second pole of the second light-emitting control transistor and the first part of the third connection part. Relative to Figure 3In the above - mentioned situation, embodiments of the present disclosure design the shapes of the sub - pixels and the distances between the centers of the sub - pixels in the first direction, so that the distance from the light - emitting region of each sub - pixel to the via connecting the third connection portion and the second light - emitting control transistor is large (that is, the distance from the light - emitting region of each sub - pixel to the first part of the third connection portion is large), that is, the light - emitting region does not overlap with the first part of the third connection portion. When setting the via (i.e., the second part of the third connection portion) in the planarization layer for connecting the second electrode of the organic light - emitting element and the third connection portion, its position can be set near the via connecting the third connection portion and the second light - emitting control transistor, and they are not directly opposite. For example, in any second - color sub - pixel of the second - color sub - pixel pair, the second via connecting the second electrode of the organic light - emitting element and the third connection portion and the fourth via connecting the third connection portion and the second light - emitting control transistor overlap in the Z direction. The position of the via in the planarization layer does not need to be adjusted significantly in the Z direction, which can not only reduce the impact on the overall pixel circuit structure but also avoid the occurrence of color shift as much as possible.

[0148] For example, as Figures 5 - 6 and Figures 9A - 9E shown, in each repeating unit 200, the two second vias 3542 include a first sub - via 3542 - 1 and a second sub - via 3542 - 2. The first via 3541, the second sub - via 3542 - 2, and the third via 3543 in the first repeating unit 201 and the first sub - via 3542 - 1 in the third repeating unit 203 are substantially located on a first straight line extending in the first direction.

[0149] For example, as Figures 5 - 6 and Figure 9D shown, the vias 352 connecting the third connection portion 343 and the second light - emitting control transistor T5 in the first - color sub - pixel 210, one second - color sub - pixel in the second - color sub - pixel pair 220, and the third - color sub - pixel 230 in each repeating unit 200 are located on a second straight line extending in the first direction. The distance between this second straight line and the above - mentioned first straight line is small, so as to reduce the impact on the overall pixel circuit structure and have higher process stability.

[0150] For example, as Figures 5 - 6As shown, along the second direction, in the second color sub-pixel pair 220, the two light-emitting regions 2200 included in the two second color sub-pixels are located between the first sub-via 3542-1 and the second sub-via 3542-2, so that the light-emitting regions of the second color sub-pixels can be prevented from overlapping with the first part of the third connection portion. For example, along the second direction, in the second color sub-pixel pair 220, the centers of the two light-emitting regions 2200 included in the two second color sub-pixels are substantially on the same straight line, the first sub-via 3542-1 and the second sub-via 3542-2 of the two second color sub-pixels are substantially on the same straight line, and are not coincident with the straight line where the centers of the two light-emitting regions 2200 are located. For example, the straight line where the first sub-via 3542-1 and the second sub-via 3542-2 of the two second color sub-pixels are located is on the side close to the first color sub-pixel 210 of the straight line where the centers of the two light-emitting regions 2200 are located.

[0151] For example, as Figures 5 - 6 and Figures 9E - 10 As shown, in the same repeating unit 200, the first via 3541 of the first color sub-pixel 210 is located on the side close to the second color sub-pixel pair 220 of the center line extending along the second direction of its light-emitting region, and the third via 3543 of the third color sub-pixel 230 is located on the side close to the second color sub-pixel pair 220 of the center line extending along the second direction of its light-emitting region. For example, in the same repeating unit 200, the first via 3541 of the first color sub-pixel 210 is located at the lower right corner of its second electrode 212, and the third via 3543 of the third color sub-pixel 230 is located at the lower left corner of its second electrode 232. For example, with the channel region of the driving transistor T1 as a reference, after the structures on the left and right sides are flipped, the "left" and "right" relationships described above can be opposite.

[0152] For example, in each repeating unit 200, the first sub-via 3542-1 of one second color sub-pixel of the second color sub-pixel pair 220 is located on the side close to the third color sub-pixel 230 of the center line extending along the second direction of its light-emitting region, and the second sub-via 3542-2 of the other second color sub-pixel of the second color sub-pixel pair 220 is located on the side close to the third color sub-pixel 230 of the center line extending along the second direction of its light-emitting region. For example, in each repeating unit 200, the first sub-via 3542-1 of one second color sub-pixel of the second color sub-pixel pair 220 is located at the upper right corner of its second electrode, and the second sub-via 3542-2 of the other second color sub-pixel of the second color sub-pixel pair 220 is located at the lower right corner of its second electrode.

[0153] For example, in each repeating unit 200, the second sub-via 3542-2 of the second color sub-pixel pair 220 and the third via 3543 of the third color sub-pixel 230 are close to each other. For example, in the same repeating unit group 2000, the third via 3543 of the third color sub-pixel 230 in the first repeating unit 201 and the first via 3541 of the first color sub-pixel 210 in the second repeating unit 202 are far from each other. For example, in adjacent repeating unit groups 2000, the third via 3543 of the third color sub-pixel 230 in the first repeating unit 201 and the first sub-via 3542-1 of the second color sub-pixel of the third repeating unit 203 are far from each other.

[0154] For example, as Figures 5 - 6 and Figures 9E - 10 shown, in each repeating unit 200, the distance in the first direction between the second sub-via 3542-2 and the third via 3543 is the fifth distance j, and the fifth distance is less than the first distance.

[0155] For example, the ratio of the fifth distance to the first distance is 0.6 to 0.7.

[0156] For example, as Figures 5 - 6 and Figures 9E - 10 shown, the second distance is less than the fifth distance.

[0157] For example, as Figures 5 - 6 and Figures 9E - 10 shown, the distance between the third via 3543 in the first repeating unit 201 and the first sub-via 3452-1 in the third repeating unit 203 is greater than the second distance. For example, the distance between the first via 3541 in the second repeating unit 202 and the first sub-via 3542-1 in the third repeating unit 203 is greater than the second distance.

[0158] For example, in the same repeating unit 200, the distance between the first via 3541 and the second sub-via 3452-2 can be 1.15a, and the distance between the second sub-via 3452-2 and the third via 3543 can be 0.85a. The distance between the third via 3543 in the first repeating unit 201 and the first sub-via 3452-1 of the third repeating unit 203 can be 1.15a, and the distance between the third via 3543 of the first repeating unit 201 and the first via 3541 of the second repeating unit 202 can be 0.85a, where a is the sub-pixel width.

[0159] The distance between the above-mentioned vias refers to the distance in the first direction between the geometric centers of the shapes of the vias.

[0160] For example, as Figures 5 - 10As shown, the data line Vd and the first power supply signal line VDD1 are located on the side of the flat layer 120 away from the second electrode of each sub-pixel, and the positive projection of the first center line extending in the second direction in the light-emitting region 2100 of each first color sub-pixel 210 on the substrate 100 is located within the positive projection of the data line Vd on the substrate 100.

[0161] Figure 3 In the pixel arrangement structure shown, there is no source-drain metal layer 2 directly below the center line extending in the second direction of the anode of the red sub-pixel 21, and there is a source-drain metal layer 2 (the first connection portion 28) only on one side of the center line, which will cause the anode of the red sub-pixel 21 to lack symmetry in the first direction. Relative to Figure 3 the positional relationship between the anode of the red sub-pixel and the source-drain metal layer 2 shown, in the embodiment of the present disclosure, a data line is provided directly below the center line extending in the second direction of the light-emitting region of the first color sub-pixel, which can ensure a certain symmetry of its second electrode (such as the anode) in the first direction.

[0162] For example, as Figures 5 - 10 shown, the positive projection of the third center line extending in the second direction in the light-emitting region 2300 of the third color sub-pixel 230 on the substrate 100 is located within the positive projection of the first power supply signal line VDD1 on the substrate 100. As Figure 6 shown in FIGS. 6-7, along the second direction, a first power supply signal line VDD1 is provided directly below the second electrode at the position where the third center line is located. Relative to Figure 3 the positional relationship between the anode and the source-drain metal layer 2 at the position of the center line extending in the second direction of the blue sub-pixel 24 shown, in the embodiment of the present disclosure, the positive projection of the third center line extending in the second direction in the light-emitting region of the third color sub-pixel 230 on the substrate 100 is located within the positive projection of the first power supply signal line VDD1 on the substrate 100, which can ensure the flatness of the second electrode of the third color sub-pixel 230 in the second direction and has a good improvement on the color shift of the display substrate in the second direction.

[0163] For example, as Figures 5 - 10 shown, the positive projection of the second electrode 232 included in the third color sub-pixel 230 on the substrate 100 overlaps with the positive projections of the data line Vd, the first connection portion 341, and the second connection portion 342 on the substrate 100, and the data line Vd is located on one side of the first power supply signal line VDD1, and the first connection portion 341 and the second connection portion 342 are located on the other side of the first power supply signal line VDD1. In the embodiment of the present disclosure, both parts of the second electrode of the third color sub-pixel on both sides of the third center line overlap with the source-drain metal layer, which can ensure that the second electrode has a certain symmetry in the X direction to improve the color shift as much as possible.

[0164] For example, as Figures 5 - 10 shown, the positive projection of the second center line extending in the second direction in the light-emitting region 2200 of the second color sub-pixel pair 220 on the substrate 100 is located between the positive projection of the first power supply signal line VDD1 connected thereto and the positive projection of the data line Vd connected to the adjacent first color sub-pixel 210 on the substrate 100. For example, one of the two second electrodes 222 included in the second color sub-pixel pair 220 has an overlap with the positive projections of the data line Vd and the second connection portion 342 on the substrate 100, and the second connection portion 342 and the data line Vd are located on both sides of the second center line; the other of the two second electrodes 222 included in the second color sub-pixel pair 220 has an overlap with the positive projection of the data line Vd and the positive projection of the first connection portion 341 on the substrate 100, and the first connection portion 341 and the data line Vd are located on both sides of the second center line. In the embodiments of the present disclosure, no source-drain metal layer is provided directly below the second electrode at the position of the second center line extending in the second direction of the second color sub-pixel pair, and the portions of the second electrode located on both sides of the second center line overlap with the source-drain metal layer, which can preferably ensure that the second electrode has a certain symmetry in the X direction to improve color shift.

[0165] For example, as Figures 5 - 10 shown, the second electrode 212 of the first color sub-pixel 210 overlaps with the first power supply signal line VDD1, the data line Vd, and the third connection portion 343, and the first power supply signal line VDD1 and the third connection portion 343 are located on both sides of the data line Vd.

[0166] For example, as Figures 5 - 10 shown, along the direction perpendicular to the substrate 100, one of the two second electrodes 222 included in the second color sub-pixel pair 220 overlaps with the data line Vd, the first power supply signal line VDD1, the second connection portion 342, and the third connection portion 343, and the second center line overlaps with the third connection portion 343, the second connection portion 342 and the first power supply signal line VDD1 are located on one side of the second center line, and the data line Vd is located on the other side of the second center line; along the direction perpendicular to the substrate 100, the other of the two second electrodes 222 included in the second color sub-pixel pair 220 overlaps with the data line Vd, the first power supply signal line VDD1, the first connection portion 341, and the third connection portion 343, and the second center line overlaps with the third connection portion 343, the first connection portion 341 and the first power supply signal line VDD1 are located on one side of the second center line, and the data line Vd is located on the other side of the second center line.

[0167] For example, as Figures 5 - 10As shown, in a direction perpendicular to the substrate 100, the second electrode 232 included in the third color sub-pixel 230 overlaps with the data line Vd, the first power supply signal line VDD1, the first connection portion 341, the second connection portion 342, and the third connection portion 343. The data line Vd is located on one side of the third center line, and the first connection portion 341, the second connection portion 342, and the third connection portion 343 are located on the other side of the third center line.

[0168] Figure 11 FIG. is a partial planar structure schematic diagram of a source-drain metal layer in a display substrate provided by another embodiment of the present disclosure. Figure 12 is Figure 11 a schematic diagram of the relative positional relationship between the source-drain metal layer shown and the second electrode of the first color sub-pixel and the light-emitting region. Figure 13 is a schematic diagram of the stacked structure of each film layer. Figures 11 - 13 The difference between the embodiment shown and Figure 10 the embodiment shown is that Figures 11 - 13 the embodiment shown further includes a first spacer 344. As Figures 11 - 13 shown, the display substrate includes a plurality of first spacers 344 disposed on the same layer as the data line Vd. For example, the first spacer 344 extends in the second direction. In a third direction perpendicular to the substrate 100, the second electrode 212 of the first color sub-pixel 210 overlaps with the data line Vd, the first power supply signal line VDD1, and the first spacer 344. Among the overlapping portions of the data line Vd, the first power supply signal line VDD1, and the first spacer 344 with the second electrode 212, the data line Vd is located between the first power supply signal line VDD1 and the first spacer 344.

[0169] Figure 14 is along Figure 6 and Figure 10 a schematic cross-sectional structure diagram taken along the CC' line shown. Figure 15 is Figure 13 a schematic cross-sectional structure diagram taken along the DD' line shown. As Figure 6 , Figure 10 and Figure 14As shown, the positive projection of the second electrode 212 of the first color sub-pixel 210 on the substrate 100 overlaps with the positive projections of the data line Vd and the first power supply signal line VDD1 on the substrate 100. For example, along the third direction perpendicular to the substrate 100, the center line of the first color sub-pixel 210 extending along the second direction overlaps with the data line Vd, the first power supply signal line VDD1 overlaps with a part of the second electrode 212 located on one side of the center line, and the part of the second electrode 212 located on the other side of the center line does not overlap with the source-drain metal layer. Therefore, the distances from the surfaces of the parts of the second electrode 212 located on both sides of the center line away from the substrate 100 to the substrate 100 are different, and there is a height difference. That is, the distance from the surface of the second electrode 212 located on the first power supply signal line VDD1 away from the substrate 100 to the surface of the substrate 100 is H1, and the distance from the surface of the second electrode 212 located outside the first power supply signal line VDD1 and the data line Vd away from the substrate 100 to the surface of the substrate 100 is H2, and H1 > H2, so there is a height difference. In addition, since the structure between the first power supply signal line VDD1 and the substrate 100 is different from the structure between the data line Vd and the substrate 100, the distance from the surface of the side of the first power supply signal line VDD1 away from the substrate 100 to the surface of the substrate 100 is greater than the distance from the surface of the side of the data line Vd away from the substrate 100 to the surface of the substrate 100. Therefore, along the first direction, the second electrode 212 will have Figure 14 the problem of tilt shown, which easily causes color deviation when the first color sub-pixel is displayed.

[0170] As Figure 13 and Figure 15 shown, a first spacer 344 is provided on the side of the data line Vd away from the first power supply signal line VDD1, and along the third direction perpendicular to the substrate 100, the first spacer 344 overlaps with the second electrode 212 of the first color sub-pixel, which can minimize the height difference between the second electrodes 212 located on both sides of the data line Vd from the substrate 100, thereby preventing color deviation when the first color sub-pixel is displayed.

[0171] For example, along the third direction, the size of the data line Vd is substantially the same as the size of the first spacer 344, that is, the thickness of the data line Vd and the thickness of the first spacer 344 are substantially the same.

[0172] For example, as Figures 11 - 13As shown, in the third direction, the center line along the second direction of the second electrode 212 of the first color sub-pixel 210 overlaps with the data line Vd, and two parts of the second electrode 212 located on both sides of the center line respectively overlap with the first power supply signal line VDD1 and the first spacer 344. In the embodiments of the present disclosure, by setting the center line along the second direction in the light-emitting region of the first color sub-pixel to overlap with the data line, the symmetry of the second electrode along the first direction can be further ensured, so as to further reduce the probability of color deviation.

[0173] For example, the orthographic projection of the center line on the substrate 100 is located within the orthographic projection of the data line Vd on the substrate 100.

[0174] For example, as Figures 11 - 13 shown, among the data line Vd, the first power supply signal line VDD1, and the first spacer 344 that overlap with the second electrode 212, the distance between the edge of the first spacer 344 close to the data line Vd and the edge of the data line Vd is d1, and the distance between the edge of the first power supply signal line VDD1 close to the data line Vd and the edge of the data line Vd is d2. The ratio between the distance d1 and the distance d2 is approximately 0.9 - 1.1.

[0175] For example, the distance d1 and the distance d2 are approximately equal.

[0176] In the embodiments of the present disclosure, by setting the distance between the first spacer and the data line to be approximately equal to the distance between the first power supply signal line and the data line, the height difference between the two parts of the second electrode symmetric with respect to its center line from the substrate can be further ensured to be as small as possible, so that in the first direction, the second electrode has better symmetry, thereby reducing the probability of color deviation.

[0177] For example, as Figures 11 - 13 shown, along the third direction, the part of the second electrode 212 overlapping with the first power supply signal line VDD1 is the first overlapping part, and the part of the second electrode 212 overlapping with the first spacer 344 is the second overlapping part. The dimension of the first overlapping part along the second direction is greater than the dimension of the second overlapping part along the second direction. For example, the area of the first overlapping part is greater than the area of the second overlapping part. For example, the dimension of the first overlapping part along the first direction can be approximately equal to the dimension of the second overlapping part along the first direction. For example, the ratio of the dimension of the first overlapping part along the first direction to the dimension of the second overlapping part along the first direction is approximately 0.8 - 1.2. The sizes of the first overlapping part and the second overlapping part can be adjusted according to the margin of the design space. In addition to increasing the second overlapping part, the size of the first overlapping part can also be reduced, for example, in the first direction, reducing the width of the first power supply signal line VDD1 to reduce the size of the part of the second electrode 212 overlapping with it.

[0178] Refer to Figure 9D andFigure 10 , the data line Vd overlapping with the second electrode 212 of the first color sub-pixel 210 is the data line Vd connected to the second pole of the data writing transistor T2 of the second color sub-pixel 220 adjacent to the first color sub-pixel 210. The data line Vd is electrically connected to the second pole of the data writing transistor T2 through a via hole 381 (second connection hole) penetrating through the gate insulating layer 160, the first insulating layer 150, and the second insulating layer 140. As Figures 11 - 13 shown, the data line Vd includes a data line main body portion Vdm extending in the first direction and a data line connection portion Vdl connected to the data line main body portion Vdm. The data line connection portion Vdl is located on the side of the data line main body portion Vdm close to the first spacer 344. The portion of the data line connection portion Vdl close to the data line main body portion Vdm is electrically connected to the second pole of the data writing transistor of the second color sub-pixel through the via hole 381. In addition, the third connection portion 343 and the first spacer 344 connected to the second electrode 212 of the first color sub-pixel 210 are located on the same side of the data line Vd, and a straight line extending in the second direction passes through the first spacer 344 and the third connection portion 343. Therefore, the end of the first spacer 344 close to the third connection portion 343 cannot be connected to the third connection portion 343, the end of the first spacer 344 far from the third connection portion 343 cannot be connected to the data line connection portion Vdl either, and the dimension of the first spacer 344 in the second direction cannot be designed to be large. For example, the length of the first spacer 344 in the second direction can be 20 - 30 micrometers. For example, the distance between the mutually close edges of the first spacer 344 and the data line main body portion Vdm, the data line connection portion Vdl, or the third connection portion 343 is greater than 3 micrometers.

[0179] For example, the maximum dimension of the second electrode 212 of the first color sub-pixel 210 in the second direction is greater than the maximum dimension in the first direction. The maximum dimension of the second electrode 212 in the second direction refers to the maximum dimension of the overall second electrode 212 including the main electrode and the connection electrode in the second direction.

[0180] For example, the maximum dimension of the first spacer 344 in the second direction is greater than the maximum dimension in the first direction. For example, the dimension of the first spacer 344 in the first direction can be 2.5 - 3 micrometers.

[0181] For example, as Figure 12 shown, the distance between the boundary of the data line connection portion Vdl and the third connection portion 343 in the second direction is greater than the dimension of the first spacer 344 in the second direction.

[0182] For example, as Figures 11 - 13As shown, the first spacer 344 overlaps with the scan signal line Ga. That is, the end of the first spacer 344 away from the third connection portion 343 is located on the side of the scan signal line Ga away from the third connection portion 343. For example, the end of the first spacer 344 away from the third connection portion 343 overlaps with the light-shielding portion S. For example, the first spacer 344 overlaps with the channel region between the double gates of the threshold compensation transistor, that is, overlaps with the active semiconductor layer between the two gates of the threshold compensation transistor T3 to prevent the active semiconductor layer between the two gates from being illuminated and changing its characteristics. For example, to prevent the voltage of this part of the active semiconductor layer from changing to prevent crosstalk. For example, the first spacer 344 does not overlap with the protruding structure P protruding from the scan signal line Ga to prevent affecting the signal in the protruding structure P.

[0183] For example, as Figures 11 - 13 shown, the first spacer 344 overlaps with the first pole CC1 of the storage capacitor C. For example, the edge of the first pole CC1 of the storage capacitor C close to the third connection portion 343 is located on the side of the end of the first spacer 344 close to the third connection portion 343 away from the scan signal line Ga.

[0184] For example, as Figures 11 - 13 shown, the first spacer 344 does not overlap with the reset control signal line Rst.

[0185] For example, as Figures 11 - 13 shown, the first spacer 344 includes a strip-shaped main body 3441 and a protruding portion 3442 connected to each other. The protruding portion 3442 is located on the side of the strip-shaped main body 3441 away from the data line Vd. The portion of the protruding portion 3442 close to the strip-shaped main body portion 3441 is electrically connected to the first pole CC1 of the storage capacitor C through a via 3440 (first connection hole) penetrating the second insulating layer located between the first pole CC1 of the storage capacitor C and the first power supply signal line VDD1. The first spacer in the embodiment of the present disclosure realizes electrical connection with the first power supply signal line through the first pole of the storage capacitor, which can provide a constant electrical signal for the first spacer to prevent the first spacer from being in a floating state and affecting the normal operation of the pixel circuit, and can also better reduce the coupling effect between the threshold compensation transistor and other conductive patterns nearby, making the working performance of the display substrate more stable.

[0186] For example, the via 3440 is located at the connected portion of the strip-shaped main body 3441 and the protruding portion 3442 in the first spacer 344. Because the protruding portion 3442 is equivalent to widening the first spacer 344 in the first direction, the via 3440 has a larger design and process margin during manufacturing and is more reliable.

[0187] For example, as Figures 11 - 13As shown, a part of the bar-shaped main body 3441 is electrically connected to the first pole CC1 of the storage capacitor C through the via 3440. For example, the protruding portion 3442 of the first spacer 344 does not overlap with the opening of the first pole CC1 of the storage capacitor C.

[0188] For example, the orthographic projection of the via 3440 on the substrate 100 is located within the orthographic projection of the second electrode 212 of the first color sub-pixel 210 on the substrate 100 and outside the orthographic projection of the light-emitting region 2100 of the first color sub-pixel 210 on the substrate 100 to prevent affecting the display of the second color sub-pixel.

[0189] For example, as Figures 11 - 13 shown, the second electrode 212 of the first color sub-pixel 210 also covers the via 3832 connecting the first power supply signal line VDD1 and the first pole CC1 (second power supply signal line VDD2) of the storage capacitor C. The via 3832 and the via 3440 are located on a straight line extending along the first direction. For example, the distance between the geometric center of the via 3832 and the data line Vd is approximately equal to the distance between the via 3440 and the data line Vd, or the ratio of the distance between the geometric center of the via 3832 and the data line Vd to the distance between the geometric center of the via 3440 and the data line Vd is 0.8 - 1.2 to ensure a certain symmetry of the second electrode 212 along the first direction.

[0190] For example, one edge of the light-emitting region 2100 of the first color sub-pixel 210 along the second direction overlaps with the first power supply signal line VDD1, and the other edge overlaps with the first spacer 344 to ensure a certain symmetry of the light-emitting region 2100 along the first direction.

[0191] Figure 16 It is a partial planar structure schematic diagram of the source-drain metal layer of the display substrate provided by another embodiment of the present disclosure. Figure 17 is Figure 16 a schematic diagram of the positional relationship between the source-drain metal layer shown and the second electrode and the light-emitting region of the first color sub-pixel. Figure 18 is a schematic diagram of the stacked structure of each film layer. Figures 16 - 18 The difference between the embodiment shown and Figures 11 - 13 the embodiment shown is that Figures 16 - 18 the embodiment shown further includes a second spacer 345. As Figures 16 - 18As shown, the display substrate further includes a plurality of second pads 345 disposed on the same layer as the plurality of first pads 344. Along a third direction perpendicular to the substrate, two portions of the second electrode 212 of the first color sub-pixel 210 located on both sides of the center line respectively overlap with the first power supply signal line VDD1 and the second pad 345. Among the data line Vd, the first power supply signal line VDD1, and the second pad 345 that overlap with the second electrode 212, the distance between the edges of the second pad 345 and the data line Vd that are close to each other is approximately equal to the distance between the edges of the first power supply signal line VDD1 and the data line Vd that are close to each other. In the embodiments of the present disclosure, while the first pad is provided, the second pad is also provided, which can better prevent color deviation when the first color sub-pixel is displayed.

[0192] Figure 19 For Figure 6 and Figure 10 a schematic cross-sectional structure diagram taken along the FF’ line shown, Figure 20 For Figure 16 a schematic cross-sectional structure diagram taken along the EE’ line shown. As Figure 6 , Figure 10 and Figure 19 shown, the positive projection of the second electrode 212 of the second color sub-pixel 210 on the substrate 100 overlaps with the positive projections of the data line Vd and the first power supply signal line VDD1 on the substrate 100. For example, along a third direction perpendicular to the substrate 100, the center line extending in the second direction of the light-emitting region of the second color sub-pixel 210 overlaps with the data line Vd, the first power supply signal line VDD1 overlaps with a portion of the second electrode 212 located on one side of the above center line, and the portion of the second electrode 212 located on the other side of the above center line does not overlap with the source-drain metal layer. Therefore, the distances from the surfaces of the two portions of the second electrode 212 located on both sides of the center line away from the substrate 100 to the substrate 100 are different, and there is a height difference, that is, the distance from the surface of the second electrode 212 located on the first power supply signal line VDD1 away from the substrate 100 to the surface of the substrate 100 is H3, and the distance from the surface of the second electrode 212 located outside the first power supply signal line VDD1 and the data line Vd away from the substrate 100 to the surface of the substrate 100 is H4, H3 > H4, and there is a height difference. Thus, along the first direction, the second electrode 212 will have Figure 19 the problem of inclination shown, which easily causes the problem of color deviation when the first color sub-pixel is displayed.

[0193] As Figure 16 and Figure 20As shown, a second spacer 345 is disposed on a side of the data line Vd away from the first power signal line VDD1, and in a third direction perpendicular to the substrate 100, the second spacer 345 overlaps with the second electrode 212 of the first color sub-pixel 210, so as to minimize the height difference between the second electrodes 212 on both sides of the data line Vd from the substrate 100, thereby preventing color deviation when the first color sub-pixel displays an image.

[0194] For example, in the third direction, the size of the data line Vd is substantially the same as the size of the second spacer 345, that is, the thickness of the data line Vd is substantially the same as the thickness of the second spacer 345.

[0195] For example, as Figures 16 - 18 shown, a straight line FF' extending in the second direction passes through the first spacer 344 and the second spacer 345, which can further increase the symmetry of the second electrode of the first color sub-pixel in the first direction. The embodiments of the present disclosure are not limited thereto, and it may also only include the second spacer and not include the first spacer, as long as the symmetry of the second electrode of the first color sub-pixel in the first direction can be ensured.

[0196] For example, Figure 21 is a schematic diagram of a partial cross-sectional structure intercepted by the HH' line as shown, Figure 18 and Figure 22 is a schematic diagram of a partial cross-sectional structure intercepted by the GG' line as shown. Figure 18 Only the multi-layer structure on the side of the second electrode facing the substrate is shown, and Figures 21 - 22 the cross-sectional diagram shown is a partial cross-sectional diagram of the pixel circuit of the first color sub-pixel 210 including the first spacer 344 and the second spacer 345, Figure 21 and Figure 22 the cross-sectional diagram shown is a partial cross-sectional diagram of the pixel circuit in the second color sub-pixel. In some embodiments, the cross-sectional diagram intercepted at the same position of the pixel circuit of the third color sub-pixel is the same as Figure 22 the cross-sectional diagram shown.

[0197] For example, as Figure 18 , Figure 21 and Figure 22 shown, the pattern of the source-drain metal layer of the pixel circuit of the first color sub-pixel is different from the pattern of the source-drain metal layer of the pixel circuit of the second color sub-pixel and the third color sub-pixel. The pattern of the source-drain metal layer of the second color sub-pixel is the same as the pattern of the source-drain metal layer of the third color sub-pixel, and relative to the pattern of the source-drain metal layer of the second color sub-pixel, the pattern of the source-drain metal layer of the first color sub-pixel further includes the first spacer 344 and the second spacer 345.

[0198] For example, the same repeating unit includes four pixel circuits arranged in the X direction. Only one of the four pixel circuits includes a first spacer and a second spacer. The repeating unit including the above four pixel circuits is arranged in the X direction. That is, among every four pixel circuits arranged in the first direction, one pixel circuit includes a first spacer and a second spacer, and every four pixel circuits are arranged repeatedly.

[0199] For example, as Figures 16 - 18 shown, among the data line Vd, the first spacer 344, and the second spacer 345 that overlap with the second electrode 212 of the first color sub-pixel 210, at least part of the edge of the first spacer 344 close to the data line Vd and the edge of the second spacer 345 close to the data line Vd are substantially on the same straight line. For example, the ratio of the distance between the edges of the second spacer 345 close to each other and the data line Vd to the distance between the edges of the first power supply signal line VDD1 and the data line Vd close to each other is 0.9 to 1.1, that is, the distance between the edges of the second spacer 345 close to each other and the data line Vd is substantially equal to the distance between the edges of the first power supply signal line VDD1 and the data line Vd close to each other, which can further ensure that the height difference between the two parts of the second electrode symmetric with respect to the center line and the substrate is as small as possible, so that in the first direction, the second electrode has better symmetry, thereby reducing the probability of color shift.

[0200] For example, as Figures 16 - 18 shown, there is a gap S0 between the edge of the first spacer 344 and the edge of the second spacer 345 that are substantially on the same straight line, and along the second direction, the size of the gap S0 is not greater than half of the size of the light-emitting region 2100 of the second color sub-pixel 210, so as to ensure that in the first direction, the second electrode has better symmetry as much as possible.

[0201] For example, as Figures 16 - 18 shown, one edge of the light-emitting region 2100 of the first color sub-pixel 210 in the second direction overlaps with the first power supply signal line VDD1, and the other edge overlaps with the second spacer 345 to ensure that the light-emitting region 2100 has better symmetry in the first direction.

[0202] For example, among the first spacer 344 and the second spacer 345 that overlap with the second electrode 212 of each first color sub-pixel 210, the first spacer 344 and the second spacer 345 are arranged in the second direction.

[0203] For example, along the second direction, the center of the first spacer 344 and the center of the second spacer 345 are on both sides of the light-emitting region of the first color sub-pixel 210. Here, the centers of the first spacer and the second spacer refer to the geometric centers of their planar shapes.

[0204] For example, the maximum dimension of the second spacer 345 in the second direction is greater than the maximum dimension in the first direction.

[0205] For example, as Figures 16 - 18 shown, the orthographic projection of the via hole 381 (the second connection hole) on the straight line extending in the second direction is located within the orthographic projection of the gap S0 on this straight line. That is, there is a gap between the first part 3451 (subsequently mentioned) of the second spacer 345 and the bar-shaped main body part 3441 of the first spacer 344, and the orthographic projection of the data line connection part Vdl on the straight line extending in the second direction is located within the orthographic projection of the gap S0 on this straight line, so that neither the first spacer 344 nor the second spacer 345 is in contact with the data line connection part Vdl of the data line Vd, which can prevent the first spacer 344 and the second spacer 345 from affecting the signals in the data line Vd.

[0206] For example, the distance between the second spacer 345 and the data line connection part Vdl is greater than 2.5 micrometers, and the distance between the second spacer 345 and the data line main body part Vdm is greater than 2.5 micrometers.

[0207] For example, as Figure 18 shown, the second spacer 345 does not overlap with the reset power supply signal line Init to prevent the formation of a capacitance between the second spacer 345 and the reset power supply signal line Init.

[0208] For example, as Figure 18 shown, the second spacer 345 is electrically connected to the reset power supply signal line Init, and the reset power supply signal line Init can provide a constant electrical signal to the second spacer 345 to prevent the second spacer 345 from being in a floating state and affecting the normal operation of the pixel circuit.

[0209] For example, as Figure 18 shown, the second spacer 345 and the second connection part 342 are located on the same layer, and the second spacer 345 can be electrically connected to the reset power supply signal line Init through the second connection part 342.

[0210] For example, as Figure 18 shown, the second spacer 345 can be integrally formed with the second connection part 342 to save the manufacturing process.

[0211] For example, as Figures 16 - 18As shown, the second spacer 345 includes a second portion 3452 close to the first spacer 344 and a first portion 3451 away from the first spacer 344. A straight line extending in the second direction passes through the first portion 3451 of the second spacer 345 and the first spacer 344. For example, the edge of the first portion 3451 of the second spacer 345 close to the data line Vd and the edge of the first spacer 344 close to the data line Vd are substantially on the same straight line, that is, the distance between the edge of the first portion 3451 of the second spacer 345 and the edge of the data line Vd close to each other is substantially equal to the distance between the edge of the first spacer 344 and the edge of the data line Vd close to each other. For example, the edge of the second portion 3452 of the second spacer 345 close to the data line Vd is located on the side away from the data line Vd of the edge of the first portion 3451 of the second spacer 345 close to the data line Vd, that is, the first portion 3451 of the second spacer 345 is closer to the data line main body Vdm than the second portion 3452 of the second spacer 345. For example, the distance between the edge of the first portion 3451 of the second spacer 345 and the edge of the data line main body Vdm of the data line Vd close to each other is substantially equal to the distance between the edge of the second portion 3452 of the second spacer 345 and the edge of the data line connection portion Vdl of the data line Vd close to each other, or the ratio of the two distances is 0.8 - 1.2.

[0212] For example, the orthographic projection of the data line connection portion Vdl on the straight line extending in the second direction does not overlap with the orthographic projections of the first spacer 344 and the first portion 3451 of the second spacer 345 on this straight line, and overlaps with the orthographic projection of the second portion 3452 of the second spacer 345 on this straight line.

[0213] For example, as Figure 18 shown, the second portion 3452 of the second spacer 345, the via 381 for connecting the data line Vd and the data writing transistor T2, the via 3833 for connecting the first power signal line VDD1 and the light shielding portion, and the via 387 for connecting the second reset transistor T7 and the reset power signal line Init are substantially on a straight line extending in the X direction.

[0214] For example, along the first direction, the maximum dimension of the first portion 3451 of the second spacer 345 is greater than the maximum dimension of the second portion 3452 of the second spacer 345.

[0215] For example, Figure 23 is Figure 16 an enlarged schematic view of the second spacer in the display substrate shown. Figure 23 In the figure, the white filled part is the second spacer, and the hatched filled part is the second connection portion. As Figure 23As shown, the shape of the first part 3451 of the second spacer 345 can be a regular L shape, and the shape of the second part 3452 of the second spacer 345 can be an inverted L shape to facilitate the integrally formed production with the second connecting portion 342.

[0216] Compared with the shape of the second connecting portion included in the second color sub-pixel or the third color sub-pixel, the shape of the second spacer in this embodiment is the shape of the part structure excluding the second connecting portion in the overall shape of the second spacer and the second connecting portion.

[0217] For example, as Figure 18 shown, the second spacer 345 overlaps with the reset control signal line Rst.

[0218] For example, the portion extending in the second direction in the regular L-shaped structure of the first part 3451 of the second spacer 345 overlaps with the reset control signal line Rst. In order to prevent a large parasitic capacitance from being generated due to a large overlapping area between the second spacer 345 and the reset control signal line Rst, the dimension of this overlapping portion in the X direction should be designed to be small. However, in order to ensure that the second spacer contributes to the flatness and symmetry of the second electrode of the first color sub-pixel, the width of the overlapping portion between the portion extending in the second direction in the regular L-shaped structure and the reset control signal line Rst should not be too small. Considering comprehensively, the width of the overlapping portion between the portion extending in the second direction in the regular L-shaped structure and the reset control signal line Rst can be 2.5 to 3 micrometers. That is, no second spacer is provided in the vacant area between the portion extending in the second direction in the regular L-shaped structure and the second connecting portion 342, which can reduce the parasitic capacitance generated between the second spacer and the reset control signal line Rst.

[0219] For example, the portion extending in the second direction in the regular L-shaped structure of the first part 3451 of the second spacer 345 is substantially the same as the width in the first direction of the bar-shaped main body 3441 of the first spacer 344, for example, 2.5 to 3 micrometers.

[0220] For example, the dimension in the first direction of the second part 3452 of the second spacer 345 and a part of the second connecting portion 342 connected to the second part 3452 is substantially 6 micrometers, and the dimension in the second direction of the portion extending in the second direction in the L-shaped structure of the first part 3451 of the second spacer 345 can be 6 micrometers.

[0221] For example, the distance W1 between the edge of the portion extending in the first direction in the regular L-shaped structure of the first part 3451 of the second spacer 345 away from the second part 3452 of the second spacer 345 and the edge of the second part 3452 of the second spacer 345 close to the first spacer 344 can be 8 micrometers.

[0222] Another embodiment of the present disclosure provides a display device, including any of the above display substrates.

[0223] In the display device provided by the embodiments of the present disclosure, by setting the distance between the centerlines extending in the second direction of each sub-pixel, it is possible to ensure that the positions of the vias in the planarization layer are not adjusted significantly to reduce the impact on the overall pixel circuit structure, while minimizing the occurrence of color shift phenomena.

[0224] In the display device provided by the embodiments of the present disclosure, by setting the centerline extending in the second direction in the light-emitting region of the first-color sub-pixel to overlap with the data line, it is possible to further ensure that the second electrode of the first-color sub-pixel has a certain symmetry along the first direction, thereby further reducing the probability of color shift.

[0225] In the display device provided by the embodiments of the present disclosure, the second electrode of the first-color sub-pixel overlaps with the data line, the first power signal line, and the first spacer block. Among the overlapping portions of the data line, the first power signal line, and the first spacer block with the second electrode, the data line is located between the first power signal line and the first spacer block, which can further ensure that the height difference between the two parts of the second electrode of the first-color sub-pixel that are symmetric with respect to its centerline and the substrate is minimized, so that in the first direction, the second electrode has good symmetry, thereby reducing the probability of color shift.

[0226] In the display device provided by the embodiments of the present disclosure, a second spacer block is provided while the first spacer block is provided. The second spacer block is provided on the same layer as the first spacer block, and the second spacer block and the first spacer block are located on the same side of the data line and overlap with the second electrode of the first-color sub-pixel, which can further ensure that the height difference between the two parts of the second electrode of the first-color sub-pixel that are symmetric with respect to its centerline and the substrate is minimized, increasing the symmetry of the second electrode of the first-color sub-pixel along the first direction, so as to better prevent color shift when the first-color sub-pixel is displaying.

[0227] For example, the display device provided by at least one embodiment of the present disclosure can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0228] The following points need to be noted:

[0229] (1) In the accompanying drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0230] (2) Without conflict, the features in the same embodiment and different embodiments of the present disclosure can be combined with each other.

[0231] The above description is only an exemplary implementation manner of the present disclosure, and is not used to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A display substrate, comprising: A substrate substrate; A plurality of first color sub-pixels located on the substrate substrate, each of the first color sub-pixels including an organic light-emitting element, the organic light-emitting element including a first electrode, a light-emitting layer, and a second electrode that are sequentially stacked, and the first electrode is located on a side of the second electrode away from the substrate substrate; A plurality of data lines located between the second electrode and the substrate substrate and arranged along a first direction and extending along a second direction; A plurality of first power signal lines provided on the same layer as the data lines and extending along the second direction; Wherein, the display substrate further includes a plurality of first pads provided on the same layer as the data lines; along a third direction perpendicular to the substrate substrate, the second electrode of each of the first color sub-pixels overlaps with the data lines, the first power signal lines, and the first pads, and among the portions where the data lines, the first power signal lines, and the first pads overlap with the second electrode, the first power signal line and the first pad are located on two sides of the data line; The display substrate further includes: A plurality of scan signal lines extending along the first direction, the plurality of scan signal lines being located between the film layer where the data lines are located and the substrate substrate; A plurality of second power signal lines extending along the first direction, the plurality of second power signal lines being located between the film layer where the first power signal lines are located and the film layer where the scan signal lines are located, and the second power signal lines are electrically connected to the first power signal lines, Wherein, the first pad overlaps with the scan signal line, the first pad overlaps with the second power signal line, and the first pad is electrically connected to the second power signal line.

2. The display substrate according to claim 1, wherein Along the third direction, the center line extending along the second direction in the light-emitting region of each of the first color sub-pixels overlaps with the data line.

3. The display substrate according to claim 2, wherein, The positive projection of the center line on the substrate substrate is located within the positive projection of the data line on the substrate substrate.

4. The display substrate according to claim 2, wherein, Among the data lines, the first power signal lines, and the first pads that overlap with the second electrode of the first color sub-pixel, the ratio between the distance between the edges of the first pad and the data line that are close to each other and the distance between the edges of the first power signal line and the data line that are close to each other is approximately 0.9 to 1.

1.

5. The display substrate according to claim 2, wherein, Along the third direction, the portion where the second electrode overlaps with the first power signal line is a first overlapping portion, the portion where the second electrode overlaps with the first pad is a second overlapping portion, and the dimension of the first overlapping portion along the second direction is greater than the dimension of the second overlapping portion along the second direction.

6. The display substrate according to claim 5, wherein, The maximum dimension of the second electrode of the first color sub-pixel along the second direction is greater than the maximum dimension along the first direction, and the maximum dimension of the first pad along the second direction is greater than the maximum dimension along the first direction.

7. The display substrate according to claim 5, further comprising: A plurality of second pads provided on the same layer as the plurality of first pads, Among them, along the third direction, the second electrodes of the first color sub-pixels overlap with the second pads, and a straight line extending along the second direction passes through the first pad and the second pad.

8. The display substrate according to claim 7, wherein, Among the data line, the first power signal line, and the second pad that overlap with the second electrode, the ratio of the distance between the edges of the second pad and the data line that are close to each other to the distance between the edges of the first power signal line and the data line that are close to each other is approximately 0.9 to 1.

1.

9. The display substrate according to claim 7, wherein, The second pad includes a first part and a second part connected to each other. The first part is located on the side of the second part away from the first pad, and a straight line extending along the second direction passes through the first part of the second pad and the first pad.

10. The display substrate according to claim 9, wherein, The maximum dimension of the second pad along the second direction is greater than the maximum dimension along the first direction.

11. The display substrate according to claim 9, wherein, Among the first pad and the second pad that overlap with the second electrodes of the first color sub-pixels, the first pad and the second pad are arranged along the second direction.

12. The display substrate according to claim 11, wherein, Along the second direction, the center of the first pad and the center of the second pad are located on both sides of the center of the light-emitting region of the first color sub-pixel.

13. The display substrate according to any one of claims 9-12, wherein, Among the data line and the first pad that overlap with the second electrode, the first pad includes a strip-shaped main body and a protruding portion connected to each other. The protruding portion is located on the side of the strip-shaped main body away from the data line, and a part of the protruding portion close to the strip-shaped main body is electrically connected to the second power signal line through a first connection hole penetrating an insulating layer located between the second power signal line and the first power signal line.

14. The display substrate according to claim 13, wherein, The first power signal line is electrically connected to the second power signal line through a second connection hole penetrating the insulating layer located between the second power signal line and the first power signal line, and the first connection hole and the second connection hole are located on a straight line extending along the first direction.

15. The display substrate according to claim 14, wherein, The orthographic projections of the first connection hole and the second connection hole on the substrate are located within the orthographic projection of the second electrode on the substrate, and the orthographic projections of the first connection hole and the second connection hole on the substrate are located outside the orthographic projection of the light-emitting region included in the first color sub-pixel on the substrate.

16. The display substrate according to any one of claims 9-12, further comprising: A plurality of reset control signal lines extending along the first direction and arranged on the same layer as the scan signal lines, wherein the first part of the second pad overlaps with the reset control signal lines, and the first pad does not overlap with the reset control signal lines.

17. The display substrate according to claim 16, further comprising: A plurality of reset power signal lines extending along the first direction and arranged on the same layer as the second power signal lines, wherein the second pad is electrically connected to the reset power signal lines.

18. The display substrate according to claim 17, further comprising: A plurality of second color sub-pixel pairs and a plurality of third color sub-pixels located on the substrate, and the plurality of first color sub-pixels, the plurality of second color sub-pixel pairs, and the plurality of third color sub-pixels are arranged into a plurality of repeating units. Wherein, each of the repeating units includes a first color sub-pixel, a second color sub-pixel pair, and a third color sub-pixel arranged in sequence along a first direction. The two second color sub-pixels included in the second color sub-pixel pair are arranged along a second direction. The plurality of repeating units are arranged along the first direction to form a plurality of repeating unit groups, and the plurality of repeating unit groups are arranged along the second direction, and adjacent repeating unit groups in the plurality of repeating unit groups are staggered from each other along the first direction.

19. The display substrate according to claim 18, wherein, Each of the sub-pixels includes a pixel circuit, and the pixel circuit includes a data writing transistor, a driving transistor, a storage capacitor, a threshold compensation transistor, a first light-emitting control transistor, a second light-emitting control transistor, a first reset transistor, and a second reset transistor; A first pole of the data writing transistor is electrically connected to a first pole of the driving transistor, a second pole of the data writing transistor is electrically connected to the data line to receive a data signal, and a gate of the data writing transistor is electrically connected to the scan signal line to receive a scan signal; A first pole of the storage capacitor is electrically connected to the first power supply signal line, and a second pole of the storage capacitor is electrically connected to a gate of the driving transistor; A first pole of the threshold compensation transistor is electrically connected to a second pole of the driving transistor, a second pole of the threshold compensation transistor is electrically connected to a gate of the driving transistor, and a gate of the threshold compensation transistor is electrically connected to the scan signal line to receive a compensation control signal; A first pole of the first reset transistor is electrically connected to the reset power supply signal line to receive a first reset signal, a second pole of the first reset transistor is electrically connected to a gate of the driving transistor, and a gate of the first reset transistor is electrically connected to the reset control signal line to receive a first sub-reset control signal; A first pole of the second reset transistor is electrically connected to the reset power supply signal line to receive a second reset signal, a second pole of the second reset transistor is electrically connected to a second electrode of the organic light-emitting element, and a gate of the second reset transistor is electrically connected to the reset control signal line to receive a second sub-reset control signal; A first pole of the first light-emitting control transistor is electrically connected to the first power supply signal line, a second pole of the first light-emitting control transistor is electrically connected to a first pole of the driving transistor, and a gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line to receive a first light-emitting control signal; A first pole of the second light-emitting control transistor is electrically connected to a second pole of the driving transistor, a second pole of the second light-emitting control transistor is electrically connected to a second electrode of the organic light-emitting element, and a gate of the second light-emitting control transistor is electrically connected to the light-emitting control signal line to receive a second light-emitting control signal; Among them, the display substrate further includes a first connection portion, a second connection portion, and a third connection portion that are disposed on the same layer as the data line. Among them, the first connection portion is configured to connect the second pole of the threshold compensation transistor and the gate of the driving transistor, the second connection portion is configured to connect the reset power signal line and the first pole of the second reset transistor, and the third connection portion is configured to connect the second electrode of the organic light-emitting element and the second pole of the second light-emitting control transistor.

20. The display substrate according to claim 19, wherein The third connection portion and the first spacer are located on the same side of the data line.

21. The display substrate according to claim 19, wherein, The threshold compensation transistor includes two gates, and the positive projection of the portion of the strip-shaped main body of the first spacer close to the second spacer on the substrate overlaps the active semiconductor layer between the two gates of the threshold compensation transistor.

22. The display substrate according to claim 19, wherein The data line includes a data line main body portion extending along the second direction and a data line connection portion. The data line connection portion is located on the side of the data line main body portion close to the second spacer. The data line connection portion is electrically connected to the second pole of the data writing transistor through a via hole in the insulating layer between the film layer where the data line is located and the film layer where the second pole of the data writing transistor is located; in the second direction, there is a gap between the first portion of the second spacer and the strip-shaped main body portion of the first spacer, and the positive projection of the data line connection portion on the straight line extending along the second direction does not overlap the positive projections of the first spacer and the first portion of the second spacer on this straight line.

23. The display substrate according to claim 22, wherein, The first portion of the second spacer is closer to the data line main body portion than the second portion of the second spacer, and the positive projection of the data line connection portion on the straight line extending along the second direction overlaps the positive projection of the second portion of the second spacer on this straight line.

24. The display substrate according to claim 19, wherein, The second spacer is electrically connected to the reset power signal line through the second connection portion.

25. The display substrate according to claim 24, wherein, The second spacer and the second connection portion are integrally formed.

26. The display substrate according to claim 19, wherein, Both the second color sub-pixel and the third color sub-pixel include an organic light-emitting element, and the organic light-emitting elements included in each sub-pixel all include the first electrode, the light-emitting layer, and the second electrode; In a direction perpendicular to the substrate, one of the two second electrodes included in the second color sub-pixel pair overlaps with the data line, the first power signal line, the second connection portion, and the third connection portion, and a first center line of the light-emitting layer of the second color sub-pixel pair in the second direction overlaps with the third connection portion. The second connection portion and the first power signal line are located on one side of the first center line, and the data line is located on the other side of the first center line. In a direction perpendicular to the substrate, the other of the two second electrodes included in the second color sub-pixel pair overlaps with the data line, the first power signal line, the first connection portion, and the third connection portion, and the first center line overlaps with the third connection portion. The first connection portion and the first power signal line are located on one side of the first center line, and the data line is located on the other side of the first center line. In a direction perpendicular to the substrate, the second electrode included in the third color sub-pixel overlaps with the data line, the first power signal line, the first connection portion, the second connection portion, and the third connection portion, and the data line is located on one side of a second center line extending in the second direction of the light-emitting region of the third color sub-pixel, and the first connection portion, the second connection portion, and the third connection portion are located on the other side of the second center line.

27. The display substrate according to claim 18, wherein, The first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel.

28. A display device, comprising the display substrate according to any one of claims 1-27.

Images