Data drive

Abstract

A data driver is provided. The data driver includes a plurality of amplifiers configured to output a plurality of data voltages to a plurality of data lines. The amplifiers are configured to output the data voltages to corresponding data lines in a write mode. Only one of the plurality of amplifiers is configured to output a sensed data voltage to the plurality of data lines in a sense mode.

Description

Technical Field

[0001] The present invention relates to a data driver, a display device including the data driver, and a method for sensing a threshold voltage of a pixel using the display device. More particularly, embodiments of the present invention relate to a data driver that uses only one output amplifier to output a sensed data voltage, a display device including the data driver, and a method for sensing a threshold voltage of a pixel using the display device. Background Art

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes multiple gate lines and multiple data lines. The display panel driver includes a gate driver and a data driver. The gate driver outputs gate signals to the gate lines, and the data driver outputs data voltages to the data lines.

[0003] In the write mode, the data driver may output a data voltage to the display panel. In the sense mode, the data driver may output a sense voltage to the display panel. In the sense mode, the data driver may determine a threshold voltage of a switching element of a pixel by sensing a voltage of the pixel.

[0004] The data driver includes a plurality of amplifiers, and an error in a sensed threshold voltage may occur due to a voltage difference between the amplifiers. Due to this error, a display defect may occur in an image displayed on the display panel. Summary of the Invention

[0005] Embodiments of the inventive concept provide a data driver for reducing a sensing error of a threshold voltage of a pixel.

[0006] Embodiments of the inventive concept provide a display device including a data driver.

[0007] Embodiments of the inventive concept provide a method of sensing a threshold voltage of a pixel using a display device.

[0008] In an embodiment of a data driver according to the present inventive concept, the data driver may include a plurality of amplifiers configured to output a plurality of data voltages to a plurality of data lines. The amplifiers are configured to output the data voltages to corresponding data lines in a write mode. Only one of the plurality of amplifiers is configured to output a sense data voltage to the plurality of data lines in a sense mode.

[0009] In an embodiment, the data driver may further include a first amplifier among a plurality of amplifiers connected to a first data line among a plurality of data lines, a switch connected between a second amplifier among the plurality of amplifiers and a second data line among the plurality of data lines, and at least one channel connection switch arranged at a connection path between the first data line and the second data line.

[0010] In an embodiment, the at least one channel connection switch may include a first channel connection switch connected between the first data line and the common node and a second channel connection switch connected between the second data line and the common node.

[0011] In an embodiment, in a write mode, the switch may be turned on and the first channel connection switch and the second channel connection switch may be turned off. In a sense mode, the switch may be turned off and the first channel connection switch and the second channel connection switch may be turned on.

[0012] In an embodiment, the data driver may include a plurality of readout chips. The switch, the first channel connection switch, and the second channel connection switch may be arranged in a first readout chip among the plurality of readout chips. The data driver may further include a first chip connection line connecting the first readout chip and a second readout chip among the plurality of readout chips, and a chip connection switch connected between the first chip connection line and at least one of the data lines.

[0013] In an embodiment, in a write mode, the switch may be turned on, and the first channel connection switch, the second channel connection switch, and the chip connection switch may be turned off. In a sense mode, the switch may be turned off, and the first channel connection switch, the second channel connection switch, and the chip connection switch may be turned on.

[0014] In an embodiment, the data driver may further include a sense amplifier among the plurality of amplifiers and a sense switch connected between the sense amplifier and at least one of the data lines.

[0015] In an embodiment, the data driver further includes a first switch connected between the first amplifier and the first data line, the switch being a second switch, and in a write mode, the first switch and the second switch may be turned on, and the first channel connection switch, the second channel connection switch, and the sensing switch may be turned off. In a sense mode, the first switch and the second switch may be turned off, and the first channel connection switch, the second channel connection switch, and the sensing switch may be turned on.

[0016] In an embodiment, the data driver may include a plurality of readout chips, the plurality of readout chips including a first readout chip and a second readout chip. The first switch, the second switch, the first channel connection switch, and the second channel connection switch may be arranged in the first readout chip. The data driver may further include a first chip connection line connecting the first readout chip and the second readout chip, a chip connection switch connected between the first chip connection line and at least one of the data lines, a sense amplifier among the plurality of amplifiers, and a sense switch connected between the sense amplifier and at least one of the data lines.

[0017] In an embodiment, in a write mode, the first switch and the second switch may be turned on, and the first channel connection switch, the second channel connection switch, the chip connection switch, and the sensing switch may be turned off. In a sense mode, the first switch and the second switch may be turned off, and the first channel connection switch, the second channel connection switch, the chip connection switch, and the sensing switch may be turned on.

[0018] In an embodiment of a display device according to the present invention, the display device includes a display panel and a data driver. The display panel is configured to display an image based on input image data. The display panel includes a plurality of data lines and a plurality of pixels connected to the data lines. The data driver includes a plurality of amplifiers configured to output a plurality of data voltages to the plurality of data lines. The amplifiers are configured to output the data voltages to the corresponding data lines in a write mode. Only one of the plurality of amplifiers is configured to output a sensed data voltage to the plurality of data lines in a sense mode.

[0019] In an embodiment, a pixel may include a first thin film transistor configured to apply a first power supply voltage to a second node in response to a signal at a first node, a second thin film transistor configured to output a data voltage to the first node in response to the first signal, a third thin film transistor configured to output a signal at the second node to a sensing node in response to a second signal, a storage capacitor including a first end connected to the first node and a second end connected to the second node, and a light emitting element including a first electrode connected to the second node and a second electrode configured to receive the second power supply voltage.

[0020] In an embodiment, the data driver may further include a first amplifier connected to the first data line, a switch connected between the second amplifier and the second data line, and at least one channel connection switch arranged at a connection path between the first data line and the second data line.

[0021] In an embodiment, the at least one channel connection switch may include a first channel connection switch connected between the first data line and the common node, and a second channel connection switch connected between the second data line and the common node.

[0022] In an embodiment, the data driver may include a plurality of readout chips. The switch, the first channel connection switch, and the second channel connection switch may be arranged in the first readout chip. The data driver may further include a first chip connection line connecting the first readout chip and the second readout chip, and a chip connection switch connected between the first chip connection line and at least one of the data lines.

[0023] In an embodiment, the data driver may further include a sense amplifier and a sensing switch connected between the sense amplifier and at least one of the data lines.

[0024] In an embodiment, the data driver may include a plurality of readout chips. The switch, the first channel connection switch, and the second channel connection switch may be arranged in the first readout chip. The data driver may further include a first chip connection line connecting the first readout chip and the second readout chip, a chip connection switch connected between the first chip connection line and at least one of the data lines, a sense amplifier, and a sense switch connected between the sense amplifier and the at least one data line.

[0025] In an embodiment of a method for sensing a threshold voltage of a pixel according to the concepts of the present invention, the method includes outputting a plurality of data voltages to a plurality of corresponding data lines connected to a plurality of pixels using a plurality of amplifiers in a write mode, outputting a sensed data voltage to a plurality of data lines using only one amplifier in a sense mode, and receiving a sense signal using a plurality of sense lines connected to the pixels in a sense mode.

[0026] In an embodiment, the first amplifier is connected to the first data line, and in a write mode, a switch connected between the second amplifier and the second data line may be turned on, and a channel connection switch connected between the first data line and the second data line may be turned off.

[0027] In an embodiment, in the sensing mode, the switch may be off and the channel connection switch may be on.

[0028] According to a data driver, a display device, and a method of sensing a threshold voltage of a pixel, only one output amplifier in a single readout chip or in multiple readout chips is used to output a sensing data voltage in a sensing mode so that a sensing error of the threshold voltage of the pixel can be minimized.

[0029] Therefore, display defects due to a sensing error of a threshold voltage of a pixel can be prevented, and the display quality of the display panel can be optimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other features of the present inventive concept will become more apparent by viewing detailed embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0031] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present inventive concept;

[0032] Figure 2 It shows Figure 1 A plan view of a display device;

[0033] Figure 3 It shows Figure 1 The circuit diagram of the pixel;

[0034] Figure 4 is shown in the sensing mode Figure 3A timing diagram of the input signal and output signal of a pixel;

[0035] Figure 5 It shows Figure 2 A plan view of a readout chip and chip connection wires connecting the readout chip;

[0036] Figure 6 is shown in the sensing mode Figure 2 Circuit diagram of the readout chip;

[0037] Figure 7 is shown in write mode Figure 2 Circuit diagram of the readout chip;

[0038] Figure 8 is a circuit diagram illustrating a readout chip of a display device according to an embodiment of the inventive concept;

[0039] Figure 9 is a circuit diagram illustrating a readout chip of a display device according to an embodiment of the inventive concept; and

[0040] Figure 10 is a circuit diagram illustrating a readout chip of a display device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0041] Hereinafter, the inventive concept will be explained in detail with reference to the accompanying drawings.

[0042] Figure 1 A display device 10 according to an embodiment of the inventive concept is shown.

[0043] Reference Figure 1 The display device 10 includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500. The gate driver 300 may be integrally formed in the display panel 100, but is not necessarily integrally formed in the display panel 100.

[0044] For example, the driving controller 200 and the data driver 500 may be integrally formed. For example, the driving controller 200, the gamma reference voltage generator 400, and the data driver 500 may be integrally formed. A driving module including at least the integrally formed driving controller 200 and the data driver 500 may be referred to as a timing controller embedded data driver (TED).

[0045] The display panel 100 has a display area AA displaying an image and a peripheral area PA adjacent to the display area AA.

[0046] For example, in this embodiment, the display panel 100 may be an organic light emitting diode display panel including organic light emitting diodes. Alternatively, the display panel 100 may be a liquid crystal display panel including a liquid crystal layer.

[0047] The display panel 100 includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels P connected to the gate lines GL and the data lines DL. The gate lines GL extend in a first direction D1, and the data lines DL extend in a second direction D2 intersecting the first direction D1.

[0048] The drive controller 200 receives input image data IMG and an input control signal CONT from an external device. The input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0049] The driving controller 200 generates a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0050] The driving controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may further include a vertical start signal and a gate clock signal.

[0051] The driving controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0052] The driving controller 200 generates a data signal DATA based on the input image data IMG and outputs the data signal DATA to the data driver 500 .

[0053] The driving controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400 .

[0054] The gate driver 300 generates a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 outputs the gate signal to the gate line GL. For example, the gate driver 300 may sequentially output the gate signal to a plurality of gate lines GL.

[0055] In the present example embodiment, the gate driver 300 may be integrated on the peripheral area PA of the display panel 100 .

[0056] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA.

[0057] In an embodiment, the gamma reference voltage generator 400 may be disposed in the driving controller 200 , or in the data driver 500 , but is not limited thereto.

[0058] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into an analog data voltage using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage to the data line DL.

[0059] Figure 2 Shown in plan view Figure 1 display device 10.

[0060] Reference Figure 1 and Figure 2 The display device 10 may include a printed circuit board assembly PBA, a first printed circuit P1, and a second printed circuit P2. The printed circuit board assembly PBA may be connected to the first printed circuit P1 and the second printed circuit P2. For example, the driving controller 200 may be disposed on the printed circuit board assembly PBA.

[0061] The display device 10 may further include a plurality of flexible circuits FP connected to the first printed circuit P1 and the display panel 100. The display device 10 may further include another plurality of flexible circuits FP connected to the second printed circuit P2 and the display panel 100.

[0062] The readout chips RSIC of the data driver 500 may be disposed on the flexible circuit FP. Each readout chip RSIC may be an integrated circuit chip.

[0063] Figure 3 Shown for Figure 1 The circuit of pixel P. Figure 4 Shown in sensing mode for Figure 3 The timing of the input signal and output signal of the circuit of pixel P.

[0064] Reference Figures 1 to 4 The pixel P may include a first thin film transistor T1 that applies the first power supply voltage ELVDD to the second node N2 in response to the signal at the first node N1, a second thin film transistor T2 that applies the data voltage VDATA to the first node N1 in response to the first signal S1, a third thin film transistor T3 that applies the signal at the second node N2 to the sensing node NS in response to the second signal S2, a storage capacitor CS having a first end connected to the first node N1 and a second end connected to the second node N2, and a light emitting element EE having a first electrode connected to the second node N2 and a second electrode receiving the second power supply voltage ELVSS.

[0065] Here, the second power voltage ELVSS may be lower than the first power voltage ELVDD. For example, the light emitting element EE may be an organic light emitting diode. The data voltage VDATA may be applied from the amplifier AMP of the data driver 500 to the input electrode of the second thin film transistor T2.

[0066] The pixel P may further include a switch SW that applies the sensing initialization voltage VSEN to the second node N2 via the third thin film transistor T3 . The switch SW may be turned on and off based on a third signal S3 .

[0067] For example, the second signal S2 and the third signal S3 are activated in the sensing initialization step, so that the sensing initialization voltage VSEN may be applied to the second node N2 .

[0068] like Figure 4 As shown in FIG, the first signal S1 is activated in the sensing mode so that the data voltage VDATA may be applied to the first node N1 through the second thin film transistor T2. Herein, the data voltage VDATA may be a sensing data voltage applied to sense the threshold voltage VTH of the first thin film transistor T1.

[0069] The first thin film transistor T1 is turned on by the sensing data voltage applied to the first node N1 in the sensing mode and the sensing initialization voltage VSEN that has been applied to the second node N2 in the sensing initialization step.

[0070] In addition, the second signal S2 is also activated in the sensing mode to turn on the third thin film transistor T3 , and the signal VR at the second node N2 may be output to the sensing node NS through the third thin film transistor T3 in the sensing mode.

[0071] The analog-to-digital converter ADC is connected to the sensing node NS and can convert a signal VR at the sensing node NS into a digital sensing signal to sense the threshold voltage VTH of the first thin film transistor T1.

[0072] In the sensing mode, the third signal S3 is inactivated so that the sensing initialization voltage VSEN is not applied to the sensing node NS after initialization in the sensing mode. In the sensing mode, the second power supply voltage ELVSS has a high level so that the pixel P does not emit light.

[0073] Figure 5 Shown in plan view Figure 2 There are multiple readout chips RSIC1, RSIC2, RSIC3 and RSIC4, and multiple chip connection lines CL1, CL2 and CL3 connecting the multiple readout chips RSIC1, RSIC2, RSIC3 and RSIC4. Figure 6 Shown in the sensing mode include Figure 2 Circuits of multiple readout chips RSIC1, RSIC2, RSIC3 and RSIC4. Figure 7 Shows the inclusion of Figure 2 Circuits of multiple readout chips RSIC1, RSIC2, RSIC3 and RSIC4.

[0074] Reference Figures 1 to 7 The data driver 500 may include a plurality of readout chips RSIC1, RSIC2, RSIC3, and RSIC4. The plurality of readout chips RSIC1, RSIC2, RSIC3, and RSIC4 may be connected to each other in a sensing mode via a plurality of chip connection lines CL1, CL2, and CL3 and a plurality of chip connection switches S17, S27, S37, and S47. In an alternative embodiment, the first chip connection switch S17 may be replaced by a conductive connection.

[0075] Figure 5 The first chip connection line CL1 connecting the first readout chip RSIC1 and the second readout chip RSIC2, the second chip connection line CL2 connecting the second readout chip RSIC2 and the third readout chip RSIC3, and the third chip connection line CL3 connecting the third readout chip RSIC3 and the fourth readout chip RSIC4 are shown. Figure 6As shown in , for example, the first chip connection line CL1 connecting the first readout chip RSIC1 and the second readout chip RSIC2, the second chip connection line CL2 connecting the second readout chip RSIC2 and the third readout chip RSIC3, and the third chip connection line CL3 connecting the third readout chip RSIC3 and the fourth readout chip RSIC4 can be formed as a main connection line with branches, and the branches extend from the main connection line. In this embodiment, the first chip connection line CL1, the second chip connection line CL2, and the third chip connection line CL3 can be as follows Figure 5 , and the first chip connection line CL1, the second chip connection line CL2, and the third chip connection line CL3 may be formed as shown in FIG. Figure 6 As shown in FIG.

[0076] The data driver 500 includes a plurality of amplifiers that output data voltages to the data lines. Figure 6 and Figure 7 As shown in , each of the first readout chip RSIC1 , the second readout chip RSIC2 , the third readout chip RSIC3 , and the fourth readout chip RSIC4 may include an amplifier that outputs a data voltage to a data line.

[0077] The data driver 500 can operate in a writing mode and a sensing mode. In the writing mode, a data voltage for displaying an image can be written into the pixel P of the display panel 100. In the sensing mode, a threshold voltage VTH of the pixel P can be sensed from the pixel P.

[0078] The sensing mode can be operated during a power-on period when the display device 10 starts to boot up, during a black period between activation periods when an image is written to the display panel 100, and during a power-off period when the display device starts to shut down. The drive controller 200 can compensate the data applied to the pixel P based on the sensed threshold voltage VTH of the pixel P and output the compensated data to the data driver 500. The threshold voltage VTH may vary between pixels due to process distribution and may vary between pixels according to usage time. If the threshold voltage VTH of the pixel P is not compensated, a difference in the displayed image of the pixel P may occur, so that the display quality of the display panel 100 may deteriorate.

[0079] In the write mode, the amplifier of the data driver 500 may output a data voltage to a corresponding data line. In the write mode, a plurality of amplifiers and a plurality of data lines may be matched one to one.

[0080] In contrast, in the sensing mode, a single amplifier of the data driver 500 may output a sensing data voltage to a plurality of data lines. In the sensing mode, the single amplifier and the plurality of data lines may be matched one-to-many.

[0081] In this embodiment, for example, in the sensing mode, a sensing data voltage is applied to all of the data lines corresponding to the four readout chips RSIC1, RSIC2, RSIC3, and RSIC4 using a single amplifier A11 of the data driver 500. In alternative embodiments, the single amplifier used in the sensing mode may be different from all of the amplifiers used in the write mode.

[0082] Alternatively, for example, a single amplifier A11 of the data driver 500 may be used to apply the sensing data voltage to the transistors arranged at Figure 2 All of the data lines corresponding to the eight readout chips RSIC at the first printed circuit P1 and the second printed circuit P2.

[0083] like Figure 6 As shown in FIG, the first readout chip RSIC1 may include a first amplifier A11, a second amplifier A12, and a third amplifier A13. Figure 6 , the first readout chip RSIC1 may include many amplifiers other than the three amplifiers A11, A12, and A13. For example, when the number of channels of the first readout chip RSIC1 is 960, the first readout chip RSIC1 may include 960 amplifiers.

[0084] The first readout chip RSIC1 may further include a first switch S11 connected between the first amplifier A11 and the first data line DL11, a second switch S12 connected between the second amplifier A12 and the second data line DL12, and a third switch S13 connected between the third amplifier A13 and the third data line DL13. In an alternative embodiment, the first switch S11 may be replaced by a conductive connection.

[0085] In addition, the first readout chip RSIC1 may further include at least one channel connection switch arranged at a connection path between the first data line DL11 and the second data line DL12. For example, the first readout chip RSIC1 may include a first channel connection switch S14 connected between the first data line DL11 and the common node, and a second channel connection switch S15 connected between the second data line DL12 and the common node.

[0086] In addition, the first readout chip RSIC1 may further include at least one channel connection switch arranged at a connection path between the second data line DL12 and the third data line DL13. For example, the first readout chip RSIC1 may include a second channel connection switch S15 connected between the second data line DL12 and the common node, and a third channel connection switch S16 connected between the third data line DL13 and the common node.

[0087] In addition, the first readout chip RSIC1 may further include a first chip connection switch S17, which is arranged between the first chip connection line CL1 connecting the first and second readout chips RSIC1 and RSIC2 and at least one of the data lines (for example, DL11).

[0088] In this embodiment, in the write mode, the first switch S11 , the second switch S12 , and the third switch S13 may be turned on, and the first channel connection switch S14 , the second channel connection switch S15 , the third channel connection switch S16 , and the first chip connection switch S17 may be turned off.

[0089] Therefore, in the write mode, the first to third amplifiers A11 to A13 and the first to third data lines DL11 to DL13 form a one-to-one connection so that the data voltages are output to the first to third data lines DL11 to DL13 through the first to third amplifiers A11 to A13.

[0090] In contrast, in the sensing mode, the first switch S11 may be turned on; the second switch S12 and the third switch S13 may be turned off; the first channel connecting switch S14, the second channel connecting switch S15, the third channel connecting switch S16, and the first chip connecting switch S17 may be turned on.

[0091] Therefore, in the sensing mode, the first amplifier A11 and the first to third data lines DL11 to DL13 form a one-to-many connection so that substantially the same sensing data voltage is applied to the first to third data lines DL11 to DL13 only through the first amplifier A11.

[0092] In addition, the sensing data voltage of the first amplifier A11 of the first readout chip RSIC1 may be transmitted to the second readout chip RSIC2 through the first chip connection switch S17 and the first chip connection line CL1 .

[0093] Therefore, in the sensing mode, the sensing data voltage may be applied to the plurality of data lines DL21 to DL23 of the second readout chip RSIC2 only through the first amplifier A11 .

[0094] In the same manner, in the sensing mode, the sensing data voltage may be output to the plurality of data lines DL31 to DL33 of the third readout chip RSIC3 and the plurality of data lines DL41 to DL43 of the fourth readout chip RSIC4 through only the first amplifier A11 .

[0095] The second readout chip RSIC2 may include a fourth amplifier A21, a fifth amplifier A22, and a sixth amplifier A23. The second readout chip RSIC2 may also include a fourth switch S21 connected between the fourth amplifier A21 and the fourth data line DL21, a fifth switch S22 connected between the fifth amplifier A22 and the fifth data line DL22, and a sixth switch S23 connected between the sixth amplifier A23 and the sixth data line DL23.

[0096] In addition, the second readout chip RSIC2 may further include a plurality of channel connection switches S24 , S25 , and S26 arranged at connection paths between the fourth to sixth data lines DL21 to DL23 .

[0097] In addition, the second readout chip RSIC2 may further include a second chip connection switch S27 disposed between a second chip connection line CL2 connecting the second readout chip RSIC2 and the third readout chip RSIC3 and at least one of the data lines (eg, DL21 ).

[0098] The third readout chip RSIC3 may include a seventh amplifier A31, an eighth amplifier A32, and a ninth amplifier A33. The third readout chip RSIC3 may also include a seventh switch S31 connected between the seventh amplifier A31 and the seventh data line DL31, an eighth switch S32 connected between the eighth amplifier A32 and the eighth data line DL32, and a ninth switch S33 connected between the ninth amplifier A33 and the ninth data line DL33.

[0099] In addition, the third readout chip RSIC3 may further include a plurality of channel connection switches S34 , S35 , and S36 arranged at connection paths between the seventh to ninth data lines DL31 to DL33 .

[0100] In addition, the third readout chip RSIC3 may further include a third chip connection switch S37 disposed between a third chip connection line CL3 connecting the third readout chip RSIC3 and the fourth readout chip RSIC4 and at least one of the data lines (eg, DL31 ).

[0101] The fourth readout chip RSIC4 may include a tenth amplifier A41, an eleventh amplifier A42, and a twelfth amplifier A43. The fourth readout chip RSIC4 may also include a tenth switch S41 connected between the tenth amplifier A41 and the tenth data line DL41, an eleventh switch S42 connected between the eleventh amplifier A42 and the eleventh data line DL42, and a twelfth switch S43 connected between the twelfth amplifier A43 and the twelfth data line DL43.

[0102] In addition, the fourth readout chip RSIC4 may further include a plurality of channel connection switches S44 , S45 , and S46 arranged at connection paths between the tenth to twelfth data lines DL41 to DL43 .

[0103] In addition, the fourth readout chip RSIC4 may further include a fourth chip connection switch S47 disposed between the third chip connection line CL3 and at least one of the data lines (eg, DL41 ).

[0104] According to the present embodiment, in the sensing mode, only one output amplifier A11 among the plurality of readout chips RSIC1 to RSIC4 is used to output the sensing data voltage, so that a sensing error of the threshold voltage VTH of the pixel P can be reduced.

[0105] Therefore, a display defect due to a sensing error of the threshold voltage VTH of the pixel P may be prevented, and the display quality of the display panel 100 may be optimized.

[0106] Figure 8 A circuit of a readout chip including a display device according to an embodiment of the inventive concept is shown.

[0107] The data driver 500 and the display device 10 according to this embodiment are substantially the same as those of the reference Figures 1 to 7 The data driver 500 of the previously explained embodiment is identical to the display device 10 except that only one output amplifier in each of the plurality of readout chips is used to output the sense data voltage. Therefore, the same reference numerals may be used to refer to the same embodiment. Figures 1 to 7 The same or similar parts as those described in the previous embodiments are described herein, and any repeated explanation regarding the above elements may be omitted.

[0108] Reference Figures 1 to 4 and Figure 8 The display device 10 includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0109] The data driver 500 includes a plurality of amplifiers that output data voltages to the data lines. Figure 8 As shown in , each of the first readout chip RSIC1 , the second readout chip RSIC2 , the third readout chip RSIC3 , and the fourth readout chip RSIC4 may include an amplifier that outputs a data voltage to a data line.

[0110] In the write mode, the amplifier of the data driver 500 may output a data voltage to a corresponding data line. In the write mode, the amplifier and the data line may be matched one to one.

[0111] In contrast, in the sensing mode, a single amplifier of the data driver 500 may output a sensing data voltage to a plurality of data lines. In the sensing mode, the amplifiers and the data lines may be matched one-to-many.

[0112] In this embodiment, for example, a single amplifier (i.e., a corresponding one of A11, A21, A31, and A41) of each of the first read-out chip RSIC1, the second read-out chip RSIC2, the third read-out chip RSIC3, and the fourth read-out chip RSIC4 is used to apply the sensing data voltage to all of the data lines of each of the first read-out chip RSIC1, the second read-out chip RSIC2, the third read-out chip RSIC3, and the fourth read-out chip RSIC4.

[0113] Therefore, the data driver 500 of this embodiment does not need to include the first chip connection line CL1, the second chip connection line CL2, and the third chip connection line CL3 connected between the first readout chip RSIC1, the second readout chip RSIC2, the third readout chip RSIC3, and the fourth readout chip RSIC4, and the first chip connection line CL1, the second chip connection line CL2, and the third chip connection line CL3 connected to the fourth readout chip RSIC4. Figure 6 and Figure 7 17 , a second chip connecting switch S27 , a third chip connecting switch S37 , and a fourth chip connecting switch S47 of the first chip connecting line CL1 , the second chip connecting line CL2 , and the third chip connecting line CL3 shown in FIG.

[0114] According to this embodiment, in the sensing mode, each single readout chip (e.g., each of RSIC1, RSIC2, RSIC3, and RSIC4) uses only one output amplifier (e.g., a corresponding one of A11, A21, A31, and A41) to output the sensing data voltage, so that the sensing error of the threshold voltage VTH of the pixel P can be reduced.

[0115] Therefore, a display defect due to a sensing error of the threshold voltage VTH of the pixel P may be prevented, and the display quality of the display panel 100 may be optimized.

[0116] Figure 9 A circuit of a readout chip including a display device according to an embodiment of the inventive concept is shown.

[0117] The data driver 500 and the display device 10 according to this embodiment are substantially the same as those of the reference Figures 1 to 7 The data driver 500 of the previously explained embodiment is the same as the display device 10 except that the first readout chip RSIC1 further includes a sense amplifier (hereinafter also referred to as an "output amplifier") A0 and a sense switch S0. Therefore, the same reference numerals may be used to refer to the same. Figures 1 to 7The same or similar parts as those described in the previous embodiments are described herein, and any repeated explanation regarding the above elements may be omitted.

[0118] Reference Figures 1 to 4 and Figure 9 The display device 10 includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0119] The data driver 500 includes a plurality of amplifiers that output data voltages to the data lines. Figure 9 As shown in , each of the first readout chip RSIC1 , the second readout chip RSIC2 , the third readout chip RSIC3 , and the fourth readout chip RSIC4 may include an amplifier that outputs a data voltage to a data line.

[0120] In the write mode, the amplifier of the data driver 500 may output a data voltage to a corresponding data line. In the write mode, the amplifier and the data line may be matched one to one.

[0121] In contrast, in the sensing mode, a single sense amplifier A0 of the data driver 500 may output a sense data voltage to a plurality of data lines. In the sensing mode, the amplifier and the data lines may be matched one-to-many.

[0122] In the present embodiment, for example, in the sensing mode, a sensing data voltage is applied to all of the data lines corresponding to the four readout chips RSIC1 , RSIC2 , RSIC3 , and RSIC4 using a single sense amplifier A0 of the data driver 500 .

[0123] Alternatively, for example, a single sense amplifier A0 of the data driver 500 may be used to apply the sense data voltage to the transistors arranged at Figure 2 All of the data lines corresponding to the eight readout chips RSIC at the first printed circuit P1 and the second printed circuit P2.

[0124] In this embodiment, the first readout chip RSIC1 may further include a sense amplifier A0 and a sense switch S0 connected to the sense amplifier A0 and at least one of the data lines (eg, DL11 ).

[0125] In the write mode, the first to third switches S11 to S13 may be turned on, and the first to third channel connecting switches S14 to S16 and the sensing switch S0 may be turned off.

[0126] In the sensing mode, the first to third switches S11 to S13 may be turned off, and the first to third channel connecting switches S14 to S16 and the sensing switch S0 may be turned on.

[0127] In the write mode, the first readout chip RSIC1 can output a data voltage using the first to third amplifiers A11 to A13. In the sense mode, the first readout chip RSIC1 can output a sense data voltage to all of the data lines of the first readout chip RSIC1 using the sense amplifier A0 formed independently of the first to third amplifiers A11 to A13.

[0128] In addition, the sensed data voltage of the sense amplifier A0 of the first readout chip RSIC1 may be transmitted to the second readout chip RSIC2 through the first chip connection switch S17 and the first chip connection line CL1 .

[0129] Therefore, in the sensing mode, the sensing data voltage may be output to only the fourth to sixth data lines DL21 to DL23 of the second readout chip RSIC2 through the sense amplifier A0 .

[0130] In the same manner, in the sensing mode, the sensing data voltage can be output only to the seventh to ninth data lines DL31 to DL33 of the third readout chip RSIC3 and the tenth to twelfth data lines DL41 to DL43 of the fourth readout chip RSIC4 through the sensing amplifier A0.

[0131] According to the present embodiment, in the sensing mode, only one output amplifier A0 among the plurality of readout chips RSIC1 to RSIC4 is used to output the sensing data voltage, so that a sensing error of the threshold voltage VTH of the pixel P can be reduced.

[0132] Therefore, a display defect due to a sensing error of the threshold voltage VTH of the pixel P may be prevented, and the display quality of the display panel 100 may be optimized.

[0133] Figure 10 A circuit diagram of a readout chip including a display device according to an embodiment of the inventive concept is shown.

[0134] The data driver 500 and the display device 10 according to this embodiment are substantially the same as those of the reference Figure 9 The data driver 500 of the previously explained embodiment is identical to the display device 10 except that only one output amplifier in each of the plurality of readout chips is used to output the sense data voltage. Therefore, the same reference numerals may be used to refer to the same embodiment. Figure 9 The same or similar parts as those described in the previous embodiments are described herein, and any repeated explanation regarding the above elements may be omitted.

[0135] Reference Figures 1 to 4 and Figure 10The display device 10 includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0136] The data driver 500 includes a plurality of amplifiers that output data voltages to the data lines. Figure 10 As shown in , each of the first readout chip RSIC1 , the second readout chip RSIC2 , the third readout chip RSIC3 , and the fourth readout chip RSIC4 may include an amplifier that outputs a data voltage to a data line.

[0137] In the write mode, the amplifier of the data driver 500 may output a data voltage to a corresponding data line. In the write mode, the amplifier and the data line may be matched one to one.

[0138] In contrast, in the sensing mode, a single amplifier of the data driver 500 may output a sensing data voltage to a plurality of data lines. In the sensing mode, the amplifiers and the data lines may be matched one-to-many.

[0139] In this embodiment, for example, each of the first read-out chip RSIC1, the second read-out chip RSIC2, the third read-out chip RSIC3 and the fourth read-out chip RSIC4 may also include a sensing amplifier (i.e., a corresponding one of A01, A02, A03 and A04) and a sensing switch (i.e., a corresponding one of S01, S02, S03 and S04) connected to the sensing amplifier (i.e., a corresponding one of A01, A02, A03 and A04) and a corresponding one of the data lines (e.g., DL11, DL21, DL31 or DL41).

[0140] In the write mode, the first to third switches S11 to S13 may be turned on, and the first to third channel connecting switches S14 to S16 and the sensing switch S01 may be turned off.

[0141] In the sensing mode, the first to third switches S11 to S13 may be turned off, and the first to third channel connecting switches S14 to S16 and the sensing switch S01 may be turned on.

[0142] In the write mode, the first readout chip RSIC1 can output a data voltage using the first to third amplifiers A11 to A13. In the sense mode, the first readout chip RSIC1 can output a sense data voltage to all of the data lines of the first readout chip RSIC1 using a sense amplifier A01 formed independently of the first to third amplifiers A11 to A13.

[0143] Similarly, in the sensing mode, the second read-out chip RSIC2 to the fourth read-out chip RSIC4 can use multiple sensing amplifiers A02, A03 and A04 formed independently from the data amplifiers (for example, A11 to A13, A21 to A23, A31 to A33 and A41 to A43) to output the sensing data voltage to all of the data lines of the second read-out chip RSIC2 to the fourth read-out chip RSIC4.

[0144] According to this embodiment, in the sensing mode, only one output amplifier (e.g., a corresponding one of A01, A02, A03, and A04) in each single readout chip (e.g., each of RSIC1, RSIC2, RSIC3, and RSIC4) is used to output the sensing data voltage, so that the sensing error of the threshold voltage VTH of the pixel P can be reduced.

[0145] Therefore, a display defect due to a sensing error of the threshold voltage VTH of the pixel P may be prevented, and the display quality of the display panel 100 may be optimized.

[0146] According to this embodiment, sensing errors can be reduced, so that the display quality of the display panel 100 can be optimized.

[0147] The foregoing is an illustration of the inventive concept and should not be construed as limiting it. Although some embodiments of the inventive concept have been described, it will be readily appreciated by those skilled in the art that many modifications to the embodiments are possible without substantially departing from the teachings of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, means-plus-function clauses are intended to cover structures described herein as performing the functions recited, and not only structural equivalents, but also equivalent structures. Therefore, it will be understood that the foregoing is an illustration of the inventive concept and should not be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments as well as other embodiments are intended to be included within the scope of the appended claims. In the event that equivalents of the claims are included therein, the inventive concept is defined by the appended claims.

Claims

1. A data driver comprising a plurality of amplifiers configured to output a plurality of data voltages to a plurality of data lines, in, The plurality of amplifiers are configured to output the plurality of data voltages to the corresponding plurality of data lines in a write mode, and Wherein, only one of the plurality of amplifiers is configured to output a sensing data voltage to the plurality of data lines in a sensing mode.

2. The data driver according to claim 1, further comprising: a first amplifier of the plurality of amplifiers, the first amplifier connected to a first data line of the plurality of data lines; a switch connected between a second amplifier among the plurality of amplifiers and a second data line among the plurality of data lines; as well as At least one channel connection switch is disposed at a connection path between the first data line and the second data line.

3. The data driver according to claim 2, wherein: The at least one channel connection switch comprises: a first channel connection switch connected between the first data line and a common node; and A second channel connection switch is connected between the second data line and the common node.

4. The data driver according to claim 3, wherein: In the write mode, the switch is turned on, and the first channel connection switch and the second channel connection switch are turned off, and Wherein, in the sensing mode, the switch is turned off, and the first channel connection switch and the second channel connection switch are turned on.

5. The data driver according to claim 3, wherein The data driver includes a plurality of readout chips, wherein the switch, the first channel connection switch, and the second channel connection switch are arranged in a first readout chip among the plurality of readout chips, and The data driver further includes: a first chip connection line connecting the first readout chip and a second readout chip among the plurality of readout chips; and a chip connection switch connected between the first chip connection line and at least one of the plurality of data lines.

6. The data driver according to claim 5, wherein In the write mode, the switch is turned on, and the first channel connection switch, the second channel connection switch, and the chip connection switch are turned off, and In the sensing mode, the switch is turned off, and the first channel connection switch, the second channel connection switch, and the chip connection switch are turned on.

7. The data driver according to claim 3, wherein The switch is a second switch, and the data driver further includes: a first switch connected between the first amplifier and the first data line; and A sense amplifier among the plurality of amplifiers and a sense switch connected between the sense amplifier and at least one of the plurality of data lines.

8. The data driver according to claim 7, wherein In the write mode, the first switch and the second switch are turned on, and the first channel connection switch, the second channel connection switch, and the sensing switch are turned off, and In the sensing mode, the first switch and the second switch are turned off, and the first channel connecting switch, the second channel connecting switch, and the sensing switch are turned on.

9. The data driver according to claim 3, further comprising a first switch connected between the first amplifier and the first data line, in, The switch is a second switch, The data driver includes a plurality of readout chips, and the plurality of readout chips include a first readout chip and a second readout chip. wherein the first switch, the second switch, the first channel connection switch, and the second channel connection switch are arranged in the first readout chip, and The data driver further includes a first chip connection line connecting the first readout chip and the second readout chip, a chip connection switch connected between the first chip connection line and at least one of the multiple data lines, a sensing amplifier among the multiple amplifiers, and a sensing switch connected between the sensing amplifier and at least one of the multiple data lines.

10. The data driver according to claim 9, wherein In the write mode, the first switch and the second switch are turned on, and the first channel connection switch, the second channel connection switch, the chip connection switch, and the sensing switch are turned off, and In the sensing mode, the first switch and the second switch are turned off, and the first channel connecting switch, the second channel connecting switch, the chip connecting switch, and the sensing switch are turned on.

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