Display Substrate, Preparation Method Thereof, and Display Device

Abstract

A display substrate, a method for manufacturing the same, and a display device. The display substrate includes: a plurality of display units; each display unit includes: a driving structure layer, a light-emitting structure layer, and a color filter layer, which are located in a display area and sequentially disposed on a substrate; the light-emitting structure layer includes: a plurality of light-emitting structures; each light-emitting structure includes: a pixel definition layer and an organic light-emitting layer; the organic light-emitting layer is located within an opening area of the pixel definition layer and on the pixel definition layer; the color filter layer includes: a plurality of color filters; the display substrate includes: a spacer area located in the display area, the spacer area is located between the opening areas of the pixel definition layers of adjacent light-emitting structures, and there is an overlapping area between the orthographic projection of the spacer area on the substrate and the orthographic projection of the pixel definition layer on the substrate; there is an overlapping area between the orthographic projections of adjacent color filters on the substrate; and there is an overlapping area between the orthographic projection of the overlapping area of adjacent color filters on the substrate and the orthographic projection of the spacer area on the substrate.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technologies, and particularly relates to a display substrate, a preparation method thereof, and a display device. Background Art

[0002] An organic light-emitting diode (OLED) is an active light-emitting display device, which has the advantages of light emission, ultra-thinness, wide viewing angle, high brightness, high contrast ratio, low power consumption, extremely high response speed, etc. With the continuous development of display technologies, OLED technologies are increasingly applied to flexible display devices and have gradually become the next-generation display technologies with great development prospects. According to different driving methods, OLEDs can be divided into two types: passive matrix driving (PM) type and active matrix driving (AM) type. Among them, AMOLED is a current-driven device, and an independent thin film transistor (TFT) is used to control each sub-pixel, and each sub-pixel can be continuously and independently driven to emit light.

[0003] With the continuous development of display technologies, OLED technologies are increasingly applied to transparent displays. Transparent display is an important personalized display field in display technologies, which refers to image display in a transparent state. Viewers can not only see the images in the display device, but also see the scenes behind the display device, and can realize virtual reality (VR), augmented reality (AR), and 3D display functions. A transparent display device using AMOLED technology usually divides each pixel into a display area and a transparent area. The display area is provided with a pixel driving circuit and a light-emitting element to realize image display, and the transparent area realizes light transmission. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this document. This overview is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, the present disclosure provides a display substrate, including a substrate and a plurality of display units disposed on the substrate; each display unit includes: a display area and a transparent area; each display unit includes: a driving structure layer, a light-emitting structure layer, and a color filter layer that are sequentially disposed on the substrate in the display area; the light-emitting structure layer includes: a plurality of light-emitting structures; each light-emitting structure includes: a pixel definition layer, a first electrode, an organic light-emitting layer, and a second electrode; the organic light-emitting layer is located in the opening area of the pixel definition layer and on the pixel definition layer; the color filter layer includes: a plurality of color filters.

[0006] The display substrate includes: a spacer region located in the display region, the spacer region being located between the opening regions of the pixel definition layers of adjacent light-emitting structures, and there being an overlapping region between the orthographic projection of the spacer region on the substrate and the orthographic projection of the pixel definition layer on the substrate;

[0007] There is an overlapping region between the orthographic projections of adjacent color filters on the substrate; there is an overlapping region between the orthographic projection of the overlapping region of adjacent color filters on the substrate and the orthographic projection of the spacer region on the substrate.

[0008] In some possible implementation manners, the multiple light-emitting structures include: a first light-emitting structure, a second light-emitting structure, a third light-emitting structure, and a fourth light-emitting structure; the first light-emitting structure and the second light-emitting structure are arranged along a first direction, and the third light-emitting structure and the fourth light-emitting structure are arranged along the first direction; the first light-emitting structure and the third light-emitting structure are arranged along a second direction, and the second light-emitting structure and the fourth light-emitting structure are arranged along the second direction;

[0009] The multiple color filters include: a first color filter, a second color filter, and a third color filter; the color filters of three colors are respectively disposed on three of the four light-emitting structures.

[0010] Wherein, the first direction is the arrangement direction of the transparent region and the display region within one display unit; the second direction is perpendicular to the first direction, and the first color, the second color, and the third color are one of red, blue, and green, and the three colors are different from each other.

[0011] In some possible implementation manners, the driving structure layer includes: multiple first scan lines and second scan lines extending along the first direction, multiple first power lines, second power lines, data lines, and compensation lines extending along the second direction, and first driving structures, second driving structures, third driving structures, and fourth driving structures arranged along the first direction;

[0012] The first driving structure is located on a side of the second driving structure close to the transparent region, and the fourth driving structure is located on a side of the third driving structure away from the transparent region;

[0013] The first power line is located on a side of the fourth driving structure away from the third driving structure; the second power line is located on a side of the first driving structure away from the second driving structure; the compensation line is located between the second driving structure and the third driving structure;

[0014] The data lines include: a first data line, a second data line, a third data line, and a fourth data line;

[0015] The first data line is connected to the first driving structure and is located on a side of the first driving structure close to the second driving structure; the second data line is connected to the second driving structure and is located on a side of the second driving structure close to the first driving structure; the third data line is connected to the third driving structure and is located on a side of the third driving structure close to the fourth driving structure; the fourth data line is connected to the fourth driving structure and is located on a side of the fourth driving structure close to the third driving structure;

[0016] The first scanning line and the second scanning line are respectively located on two sides of the driving structure layer;

[0017] The length of the first power line in a first direction is greater than the length of the compensation line or the data line in the first direction, and the length of the second power line in the first direction is greater than the length of the compensation line or the data line in the first direction.

[0018] In some possible implementation manners, the first driving structure and the fourth driving structure are mirror-symmetrical with respect to the compensation line, and the second driving structure and the third driving structure are mirror-symmetrical with respect to the compensation line.

[0019] In some possible implementation manners, each driving structure includes: a pixel driving circuit, and the pixel driving circuit includes: a first transistor, a second transistor, a third transistor, and a storage capacitor; the second transistor is a driving transistor; the storage capacitor includes: a first electrode plate, a second electrode plate, and a third electrode plate;

[0020] The gate electrode of the first transistor is connected to the first scanning line, the first pole of the first transistor is connected to the data line, the second pole of the first transistor is connected to the gate electrode of the second transistor, the first pole of the second transistor is connected to the first power line, the second pole of the second transistor is connected to the first electrode of the light-emitting structure, the gate electrode of the third transistor is connected to the second scanning line, the first pole of the third transistor is connected to the compensation line through a compensation connection line, the second pole of the third transistor is connected to the second pole of the second transistor, and the second electrode of the light-emitting structure is connected to the second power line; the first electrode plate and the third electrode plate are connected to the second pole of the second transistor, and the second electrode plate is connected to the gate electrode of the second transistor;

[0021] The driving structure layer further includes: a power connection line, an auxiliary power line, and a compensation connection line;

[0022] The first pole of the second transistor is connected to the first power line through the power connection line; the power connection line is arranged on the same layer as the first scan line and the second scan line, the first power line is connected to the power connection line through a via, and a double-layer trace is formed between the gate electrode of the first transistor and the gate electrode of the third transistor;

[0023] The auxiliary power line is arranged on the same layer as the first scan line and the second scan line, the second power line is connected to the auxiliary power line through a via, and a double-layer trace is formed between the gate electrode of the first transistor and the gate electrode of the third transistor;

[0024] The compensation connection line is arranged on the same layer as the first electrode plate, and the compensation connection line is connected to the compensation line through a via.

[0025] In some possible implementation manners, the driving structure layer includes: a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer, a second metal layer, a third insulating layer, a third metal layer, a fourth insulating layer and a planarization layer which are sequentially stacked;

[0026] The first metal layer includes a first electrode plate and a compensation connection line, the metal oxide layer includes a second electrode plate and the active layers of all transistors, the second metal layer includes a first scan line, a second scan line, a power connection line, an auxiliary power line and the gate electrodes of all transistors; the third metal layer includes: a first power line, a second power line, a compensation line, a data line, a third electrode plate and the source-drain electrodes of all transistors; the planarization layer is provided with a via exposing the second pole of the second transistor;

[0027] The orthographic projection of the first electrode plate on the substrate and the orthographic projection of the second electrode plate on the substrate have an overlapping area to form a first storage capacitor, the orthographic projection of the third electrode plate on the substrate and the orthographic projection of the second electrode plate on the substrate have an overlapping area to form a second storage capacitor, and the third electrode plate is connected to the first electrode plate through a via.

[0028] In some possible implementation manners, the orthographic projection of the first electrode plate on the substrate covers the active layers of the first transistor and the second transistor and the orthographic projection of the second electrode plate on the substrate;

[0029] The length of the first electrode plate along the second direction is greater than the distance between the gate electrode of the first transistor and the gate electrode of the third transistor.

[0030] In some possible implementation manners, an opening is provided in the second electrode plate of the second driving structure and the third driving structure; the opening of the second electrode plate of the second driving structure is disposed on a side of the second driving structure close to the third driving structure, and the opening of the second electrode plate of the third driving structure is disposed on a side of the third driving structure close to the second driving structure;

[0031] The flat layer vias in the first driving structure and the fourth driving structure are located between the third transistor and the second electrode plate; the flat layer vias in the first driving structure and the flat layer vias in the fourth driving structure are mirror-symmetrical with respect to the compensation line;

[0032] The flat layer vias of the second driving structure are located within the opening of the second electrode plate of the second driving structure, and the flat layer vias of the third driving structure are located within the opening of the second electrode plate of the third driving structure; the flat layer vias in the second driving structure and the flat layer vias in the third driving structure are mirror-symmetrical with respect to the compensation line;

[0033] The included angle between the arrangement direction of the flat layer vias in the first driving structure and the flat layer vias in the second driving structure and the first direction is greater than 0 degrees and less than 90 degrees.

[0034] In some possible implementation manners, the first electrode of the first light-emitting structure is connected to the first driving structure through the flat layer via in the first driving structure, the first electrode of the second light-emitting structure is connected to the fourth driving structure through the flat layer via in the fourth driving structure, the first electrode of the third light-emitting structure is connected to the second driving structure through the flat layer via in the second driving structure, and the first electrode of the fourth light-emitting structure is connected to the third driving structure through the flat layer via in the third driving structure;

[0035] The opening regions of the pixel definition layer of the first light-emitting structure and the opening regions of the pixel definition layer of the third light-emitting structure are located between the first power supply line and the compensation line, and the orthographic projections on the substrate overlap with the orthographic projections of the first driving structure and the second driving structure on the substrate;

[0036] The opening regions of the pixel definition layer of the second light-emitting structure and the opening regions of the pixel definition layer of the fourth light-emitting structure are located between the compensation line and the second power supply line, and the orthographic projections on the substrate overlap with the orthographic projections of the third driving structure and the fourth driving structure on the substrate.

[0037] In some possible implementation manners, the orthographic projection of the flat layer via of the first driving structure on the substrate does not overlap with the orthographic projection of the opening region of the pixel definition layer in the first light-emitting structure on the substrate;

[0038] The orthographic projection of the flat layer vias of the second driving structure on the substrate does not overlap with the opening area of the pixel definition layer in the third light-emitting structure on the substrate;

[0039] The orthographic projection of the flat layer vias of the third driving structure on the substrate does not overlap with the opening area of the pixel definition layer in the fourth light-emitting structure on the substrate;

[0040] The orthographic projection of the flat layer vias of the fourth driving structure on the substrate does not overlap with the opening area of the pixel definition layer in the second light-emitting structure on the substrate.

[0041] In some possible implementation manners, the spacer region includes a first spacer region, a second spacer region, and a third spacer region;

[0042] The first spacer region is located between the opening area of the pixel definition layer of the first light-emitting structure and the opening area of the pixel definition layer of the third light-emitting structure; the second spacer region is located between the opening area of the pixel definition layer of the second light-emitting structure and the opening area of the pixel definition layer of the fourth light-emitting structure; the first spacer region and the second spacer region are arranged along a first direction;

[0043] The first spacer region and the second spacer region are respectively located on both sides of the third spacer region, and the orthographic projection of the third spacer region on the substrate coincides with the orthographic projection of the compensation line located between the first scan line and the second scan line on the substrate;

[0044] The third spacer region includes: a first sub-spacer region, a second sub-spacer region, and a third sub-spacer region that are sequentially arranged along a second direction and are connected end to end; the second sub-spacer region is located between the first sub-spacer region and the third sub-spacer region;

[0045] The first sub-spacer region is located between the opening area of the pixel definition layer of the first light-emitting structure and the opening area of the pixel definition layer of the second light-emitting structure; the third sub-spacer region is located between the opening area of the pixel definition layer of the third light-emitting structure and the opening area of the pixel definition layer of the fourth light-emitting structure;

[0046] The second sub-spacer region is located between the first spacer region and the second spacer region and is arranged along the first direction with the first spacer region and the second spacer region.

[0047] In some possible implementation manners, when the filter is located on the first light-emitting structure, the orthographic projection of the filter on the substrate covers the opening area of the pixel definition layer of the first light-emitting structure, the first sub-spacing area, the orthographic projection of the second sub-spacing area on the substrate, and there is an overlapping area with the orthographic projection of a part of the second scanning line and a part of the second power supply line located in the display area on the substrate;

[0048] When the filter is located on the second light-emitting structure, the orthographic projection of the filter on the substrate covers the opening area of the pixel definition layer of the second light-emitting structure, the second spacing area, the orthographic projection of the first sub-spacing area and the second sub-spacing area on the substrate, and there is an overlapping area with the orthographic projection of a part of the second scanning line and a part of the first power supply line located in the display area on the substrate;

[0049] When the filter is located on the third light-emitting structure, the orthographic projection of the filter on the substrate covers the orthographic projection of the opening area of the pixel definition layer of the third light-emitting structure on the substrate, and there is an overlapping area with the orthographic projection of a part of the first spacing area, a part of the third sub-spacing area, a part of the first scanning line and a part of the second power supply line located in the display area on the substrate;

[0050] When the filter is located on the fourth light-emitting structure, the orthographic projection of the filter on the substrate covers the orthographic projection of the opening area of the pixel definition layer of the fourth light-emitting structure on the substrate, and there is an overlapping area with the orthographic projection of a part of the second spacing area, a part of the third sub-spacing area, a part of the first scanning line and a part of the first power supply line located in the display area on the substrate.

[0051] There is no overlapping area between the orthographic projection of the color filter layer on the substrate and the orthographic projection of the via hole of the flat layer in the driving structure layer on the substrate.

[0052] In some possible implementation manners, the display substrate further includes: an occlusion layer;

[0053] The orthographic projection of the occlusion layer on the substrate has an overlapping area with the orthographic projection of the first scanning line located in the transparent area and the orthographic projection of the second scanning line located in the transparent area and a part of the display area on the substrate.

[0054] In some possible implementation manners, the occlusion layer includes: a first occlusion layer and a second occlusion layer; the second occlusion layer is located on the side of the first occlusion layer close to the substrate;

[0055] The first occlusion layer is arranged on the same layer as one of the color filters among the multiple color filters, and the second occlusion layer is arranged on the same layer as another color filter among the multiple color filters.

[0056] In a second aspect, the present disclosure further provides a method for manufacturing a display substrate for manufacturing the above display substrate, the method comprising:

[0057] Providing a substrate;

[0058] Forming a display unit including a display area and a transparent area on the substrate to form a display substrate; the display unit includes: a driving structure layer, a light-emitting structure layer, and a color filter layer that are located in the display area and are sequentially disposed on the substrate; the light-emitting structure layer includes: a plurality of light-emitting structures; each light-emitting structure includes: a pixel definition layer, a first electrode, an organic light-emitting layer, and a second electrode; the organic light-emitting layer is located within the opening area of the pixel definition layer and on the pixel definition layer; the display substrate includes: a spacer area located in the display area, the spacer area is located between the opening areas of the pixel definition layers of adjacent light-emitting structures, and there is an overlapping area with the positive projection of the pixel defining layer on the substrate; the color filter layer includes: a plurality of color filters; there is an overlapping area in the positive projection of adjacent color filters on the substrate; the overlapping area of adjacent color filters in the positive projection on the substrate and the positive projection of the spacer area on the substrate have an overlapping area.

[0059] In some possible implementation manners, forming a display unit including a display area and a transparent area on the substrate includes:

[0060] Forming a first metal layer including a first electrode plate on the substrate in the display area;

[0061] Forming a first insulating layer covering the first metal layer in the display area and the transparent area;

[0062] Forming a metal oxide layer including a second electrode plate on the first insulating layer in the display area, and there is an overlapping area in the positive projection of the second electrode plate on the substrate and the positive projection of the first electrode plate on the substrate to form a first storage capacitor;

[0063] Sequentially forming a second insulating layer and a second metal layer in the display area; the second metal layer includes: a first scan line and a second scan line;

[0064] Forming a third insulating layer covering the second metal layer in the display area and the transparent area;

[0065] Forming a third metal layer in the display area on the third insulating layer, the third metal layer includes a first power line, a second power line, a compensation line, a data line, and a third electrode plate, and there is an overlapping area in the positive projection of the third electrode plate on the substrate and the positive projection of the second electrode plate on the substrate to form a second storage capacitor, and the third electrode plate is connected to the first electrode plate through a via;

[0066] Form a fourth insulating layer and a planarization layer covering the third metal layer in the display area and the transparent area;

[0067] Form a first electrode on the planarization layer;

[0068] Form a pixel definition layer, an organic light-emitting layer, and a cathode in sequence;

[0069] Form a packaging layer;

[0070] Form a color filter layer on the packaging layer.

[0071] In some possible implementation manners, forming the color filter layer on the packaging layer includes:

[0072] Form a color filter layer and a shielding layer on the packaging layer;

[0073] The positive projection of the shielding layer on the substrate overlaps with the positive projections of the first scanning line located in the transparent area and the second scanning line located in the transparent area and part of the display area on the substrate.

[0074] In a third aspect, the present disclosure further provides a display device including the above display substrate.

[0075] Other aspects can be understood after reading the drawings and the detailed description. Description of the Drawings

[0076] The drawings are used to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual proportions, and the purpose is only to schematically illustrate the content of the present disclosure.

[0077] Figure 1A The first top view of the display substrate provided by the embodiment of the present disclosure;

[0078] Figure 1B The second top view of the display substrate provided by the embodiment of the present disclosure;

[0079] Figure 2 For Figure 1B The cross-sectional view along the B-B direction;

[0080] Figure 3 The third top view of the display substrate provided by the embodiment of the present disclosure;

[0081] Figure 4 The equivalent circuit diagram of the pixel driving circuit provided for an exemplary embodiment;

[0082] Figure 5A The schematic diagram after forming the first metal layer;

[0083] Figure 5B is Figure 5A the sectional view taken along the A-A direction in

[0084] Figure 5C is Figure 5A the sectional view taken along the B-B direction in

[0085] Figure 6A the schematic diagram after forming the metal oxide layer;

[0086] Figure 6B is Figure 6A the sectional view taken along the A-A direction in

[0087] Figure 6C is Figure 6A the sectional view taken along the B-B direction in

[0088] Figure 7A the schematic diagram after forming the second metal layer;

[0089] Figure 7B is Figure 7A the sectional view taken along the A-A direction in

[0090] Figure 7C is Figure 7A the sectional view taken along the B-B direction in

[0091] Figure 8A the schematic diagram after forming the third insulating layer;

[0092] Figure 8B is Figure 8A the sectional view taken along the A-A direction in

[0093] Figure 8C is Figure 8A the sectional view taken along the B-B direction in

[0094] Figure 9A the schematic diagram after forming the third metal layer;

[0095] Figure 9B is Figure 9A the sectional view taken along the A-A direction in

[0096] Figure 9C is Figure 9A the sectional view taken along the B-B direction in

[0097] Figure 10A the schematic diagram after forming the fourth insulating layer and the planarization layer;

[0098] Figure 10B is Figure 10A the sectional view taken along the A-A direction in

[0099] Figure 10C is Figure 10ACross-sectional view taken along line B-B;

[0100] Figure 11A Schematic diagram after forming the transparent conductive layer of the present disclosure;

[0101] Figure 11B is Figure 11A Cross-sectional view taken along line A-A;

[0102] Figure 12A Schematic diagram after forming the pixel definition layer;

[0103] Figure 12B is Figure 12A Cross-sectional view taken along line A-A;

[0104] Figure 12C is Figure 12A Cross-sectional view taken along line B-B;

[0105] Figure 13 Schematic diagram after forming the organic light-emitting layer;

[0106] Figure 14A Schematic diagram after forming the cathode;

[0107] Figure 14B is Figure 14A Cross-sectional view taken along line A-A;

[0108] Figure 14C is Figure 14A Cross-sectional view taken along line B-B;

[0109] Figure 15 Schematic diagram after forming the encapsulation layer. Detailed implementation manners

[0110] To make the objectives, technical solutions and advantages of the present disclosure clearer and more understandable, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The implementation manners can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the manners and contents can be transformed into various forms without departing from the gist and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following implementation manners. Without conflict, the embodiments and features in the embodiments of the present disclosure can be combined arbitrarily with each other.

[0111] In the accompanying drawings, sometimes for clarity, the sizes of the respective components, the thicknesses of the layers or the areas are exaggerated. Therefore, the embodiments of the present disclosure are not necessarily limited to such dimensions, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

[0112] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of components, rather than to limit the quantity.

[0113] In this specification, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationship of components changes appropriately according to the directions describing each component. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the circumstances.

[0114] In this specification, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" shall be construed in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, an indirect connection through an intermediate member, or the communication inside two components.

[0115] A transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region where current mainly flows.

[0116] The first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" sometimes swap. Therefore, in this specification, the "source electrode" and "drain electrode" can be swapped with each other.

[0117] In this specification, "electrically connected" includes the case where components are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0118] In this specification, "parallel" means a state where the angle formed by two straight lines is more than -10° and less than 10°, and thus also includes a state where the angle is more than -5° and less than 5°. Additionally, "perpendicular" means a state where the angle formed by two straight lines is more than 80° and less than 100°, and thus also includes a state where the angle is more than 85° and less than 95°.

[0119] In this specification, "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be changed to "conductive film". Similarly, sometimes "insulating film" can be changed to "insulating layer".

[0120] In a transparent display substrate, the metal covered by the pixel defining layer between adjacent light-emitting structures will exhibit a metal reflection phenomenon due to the pixel defining layer being a transparent material, reducing the display effect of the transparent display substrate.

[0121] Figure 1A It is the first top view of the display substrate provided by the embodiment of the present disclosure. Figure 1B It is the second top view of the display substrate provided by the embodiment of the present disclosure. Figure 2 is Figure 1B A cross-sectional view along the B-B direction. As shown in FIGS. 1 and 2, the display substrate provided by the embodiment of the present disclosure includes: a substrate 10 and a plurality of display units disposed on the substrate 10. The display unit includes: a display area 100 and a transparent area 200; the display unit includes: a driving structure layer, a light-emitting structure layer, and a color filter layer that are sequentially disposed on the substrate in the display area 100; the light-emitting structure layer includes: a plurality of light-emitting structures; each light-emitting structure includes: a pixel defining layer 71, a first electrode, an organic light-emitting layer, and a second electrode; the organic light-emitting layer is located in the opening area of the pixel defining layer and on the pixel defining layer 71, and the color filter layer 20 includes: a plurality of color filters.

[0122] As shown in FIG. 1, the display substrate 1 includes: a spaced area A (the dotted area in FIG. 1) in the display area, the spaced area A is located between the opening areas of the pixel defining layers of adjacent light-emitting structures, and there is an overlapping area between the orthographic projection of the spaced area A on the substrate and the orthographic projection of the pixel defining layer 71 on the substrate.

[0123] There is an overlapping area between the orthographic projections of adjacent color filters on the substrate; there is an overlapping area between the orthographic projection of the overlapping area of adjacent color filters on the substrate and the orthographic projection of the spaced area on the substrate.

[0124] The multiple color filters include: the first color, the second color, and the third color, which are one of red, blue, and green, and the three colors are different from each other. The first color can be red, the second color can be blue, and the third color can be green. Or, the first color can be red, the second color can be green, and the third color can be blue. Or the first color can be blue, the second color can be red, and the third color can be green. Or, the first color can be blue, the second color can be green, and the third color can be red. Or the first color can be green, the second color can be red, and the third color can be blue. Or, the first color can be green, the second color can be blue, and the third color can be red.

[0125] The display area is configured to implement image display, and the transparent area is configured to allow light to pass through, so as to achieve image display in a transparent state, that is, transparent display.

[0126] In one exemplary embodiment, the substrate 10 can be a rigid substrate or a flexible substrate. Among them, the rigid substrate can be one or more of, but not limited to, glass and metal foils; the flexible substrate can be one or more of, but not limited to, polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyaryl acid ester, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0127] In one exemplary embodiment, as Figure 1A shown, the multiple light-emitting structures include: a first light-emitting structure, a second light-emitting structure, a third light-emitting structure, and a fourth light-emitting structure; the first light-emitting structure and the second light-emitting structure are arranged along a first direction, and the third light-emitting structure and the fourth light-emitting structure are arranged along the first direction; the first light-emitting structure and the third light-emitting structure are arranged along a second direction, and the second light-emitting structure and the fourth light-emitting structure are arranged along the second direction.

[0128] The first direction is the arrangement direction of the transparent area 200 and the display area 100 within one display unit, and the second direction is perpendicular to the first direction.

[0129] There are intervals between the opening areas 711 of the pixel definition layer of the first light-emitting structure and the opening areas 712 of the pixel definition layer of the second light-emitting structure and the opening areas 713 of the pixel definition layer of the third light-emitting structure respectively. There are intervals between the opening areas 714 of the pixel definition layer of the fourth light-emitting structure and the opening areas 712 of the pixel definition layer of the second light-emitting structure and the opening areas 713 of the pixel definition layer of the third light-emitting structure respectively.

[0130] In one exemplary embodiment, the color filters of the three colors are respectively disposed on three of the four light-emitting structures. Figure 1BFor example, it is described by taking the case where the first color filter is located on the first light-emitting structure, the second color filter is located on the third light-emitting structure, and the third color filter is located on the fourth light-emitting structure.

[0131] In the embodiments of the present disclosure, adjacent overlapping color filters can block the light reflected by the metal in the spacer region, reduce the metal reflection phenomenon, and improve the display effect of the display substrate.

[0132] In an exemplary embodiment, the region B in the display area can be used to form an auxiliary electrode connected to the second electrode of the light-emitting structure layer to provide a low-level signal to the second electrode.

[0133] The display substrate provided by the embodiments of the present disclosure includes a display substrate and a second substrate disposed opposite to each other. The display substrate includes: a substrate and a plurality of display units disposed on the substrate; the display unit includes: a display area and a transparent area; the display unit includes: a driving structure layer, a light-emitting structure layer, and a color film layer that are located in the display area and are sequentially disposed on the substrate; the light-emitting structure layer includes: a plurality of light-emitting structures; each light-emitting structure includes: a pixel defining layer, a first electrode, an organic light-emitting layer, and a second electrode; the organic light-emitting layer is located within the opening area of the pixel defining layer and on the pixel defining layer; the color film layer includes: a plurality of color filters; the display substrate includes: a spacer region in the display area, the spacer region is located between the opening areas of the pixel defining layers of adjacent light-emitting structures, and the orthographic projection of the spacer region on the substrate overlaps with the orthographic projection of the pixel defining layer on the substrate; the orthographic projections of adjacent color filters on the substrate overlap; the orthographic projection of the overlapping region of adjacent color filters on the substrate overlaps with the orthographic projection of the spacer region on the substrate. The technical solution provided by the embodiments of the present disclosure can block the light reflected by the metal in the spacer region by setting the color filters in the color film layer to overlap each other, reduce the metal reflection phenomenon of the display substrate, and improve the display effect of the display substrate.

[0134] In an exemplary embodiment, Figure 3 is the third top view of the display substrate provided by the embodiments of the present disclosure. As Figure 3 shown, the driving structure layer in each display unit includes: a plurality of first scan lines Gn and second scan lines Sn extending in the first direction, a plurality of first power supply lines VDD, second power supply lines VSS, Dn, and compensation lines Se extending in the second direction, and first driving structures P1, second driving structures P2, third driving structures P3, and fourth driving structures P4 arranged in the first direction.

[0135] In an exemplary embodiment, the first power supply line VDD, the second power supply line VSS, Dn, the compensation line Se, and the first driving structure P1, the second driving structure P2, the third driving structure P3, and the fourth driving structure P4 are located in the display area.

[0136] The first driving structure P1 is located on the side of the second driving structure P2 close to the transparent region 200, and the fourth driving structure P4 is located on the side of the third driving structure P3 away from the transparent region 200. Each driving structure includes a pixel driving circuit. The pixel driving circuit is electrically connected to the light-emitting structure.

[0137] In an exemplary embodiment, the first scanning line and the second scanning line are used to define a display row, and the first power supply line and the second power supply line are used to define a display column.

[0138] The first power supply line VDD is located on the side of the fourth driving structure P4 away from the third driving structure P3; the second power supply line VSS is located on the side of the first driving structure P1 away from the second driving structure P2; the compensation line Se is located between the second driving structure P2 and the third driving structure P3.

[0139] In an exemplary embodiment, the data lines include: a first data line, a second data line, a third data line, and a fourth data line. The first data line is connected to the first driving structure and is located on the side of the first driving structure P1 close to the second driving structure P2. The second data line is connected to the second driving structure P2 and is located on the side of the second driving structure P2 close to the first driving structure P1; the third data line is connected to the third driving structure P3 and is located on the side of the third driving structure P3 close to the fourth driving structure P4; the fourth data line is connected to the fourth driving structure P4 and is located on the side of the fourth driving structure P4 close to the third driving structure P3.

[0140] In an exemplary embodiment, the first power supply line VDD, the second power supply line VSS, the compensation line Se, and the four data lines Dn are parallel to each other. Along the direction away from the transparent region 200, the second power supply line VSS, two data lines Dn, the compensation line Se, two data lines Dn, and the first power supply line VDD are arranged in sequence. A driving structure is formed between the first power supply line VDD and the adjacent data line Dn, a driving structure is formed between the second power supply line VSS and the adjacent data line Dn, and two driving structures are respectively formed between the compensation line Se and the adjacent data line Dn. In this way, four driving structures are formed between the first power supply line VDD and the second power supply line VSS by arranging 1 compensation line Se and 4 data lines Dn. Two of the 4 data lines Dn are located between the compensation line Se and the second power supply line VSS, and the other two data lines Dn are located between the compensation line Se and the first power supply line VDD.

[0141] The length of the first power supply line VDD in the first direction is greater than the length of the compensation line Se or the data line Dn in the first direction, and the length of the second power supply line VSS in the first direction is greater than the length of the compensation line Se or the data line Dn in the first direction, which can reduce the resistance of the first power supply line VDD and the second power supply line VSS.

[0142] In an exemplary embodiment, the first scan line Gn and the second scan line Sn are respectively located on both sides of the driving structure layer.

[0143] In an exemplary embodiment, the voltage of the first power supply line VDD can be set to be greater than the voltage of the second power supply line VSS, and the maximum voltage of the data signal transmitted by the data line Dn is less than the maximum voltage of the first scan line and also less than the voltage of the first power supply line VDD.

[0144] In an exemplary embodiment, as Figure 3 shown, the first driving structure P1 and the fourth driving structure P4 are mirror-symmetrical with respect to the compensation line Se, and the second driving structure P2 and the third driving structure P3 are mirror-symmetrical with respect to the compensation line Se.

[0145] Figure 4 This is an equivalent circuit diagram of the pixel driving circuit provided for an exemplary embodiment. As Figure 4 shown, the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor C ST , and the light-emitting structure is an OLED. The first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, the third transistor T3 is a compensation transistor, and the storage capacitor includes: a first electrode plate 41, a second electrode plate 42, and a third electrode plate 43.

[0146] The gate electrode of the first transistor T1 is connected to the first scan line Gn, the first pole of the first transistor T1 is connected to the data line Dn, the second pole of the first transistor T1 is connected to the gate electrode of the second transistor T2. The first transistor T1 is used to receive the data signal transmitted by the data line Dn under the control of the first scan line Gn, so that the gate electrode of the second transistor T2 receives the data signal. The gate electrode of the second transistor T2 is connected to the second pole of the first transistor T1, the first pole of the second transistor T2 is connected to the first power supply line VDD, and the second pole of the second transistor T2 is connected to the first pole of the OLED. The second transistor T2 is used to generate a corresponding current at the second pole under the control of the data signal received by its gate electrode. The gate electrode of the third transistor T3 is connected to the second scan line Sn, the first pole of the third transistor T3 is connected to the compensation line Se, and the second pole of the third transistor T3 is connected to the second pole of the second transistor T2. The third transistor T3 is used to extract the threshold voltage Vth and the mobility of the second transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth. The first pole of the OLED is connected to the second pole of the second transistor T2, and the second pole of the OLED is connected to the second power supply line VSS. The OLED is used to emit light with a corresponding brightness in response to the current at the second pole of the second transistor T2. The storage capacitor C ST has its first pole connected to the gate electrode of the second transistor T2, and the storage capacitor C STThe second pole of which is connected to the second pole of the second transistor T2, and the storage capacitor C ST is used to store the potential of the gate electrode of the second transistor T2.

[0147] In an exemplary embodiment, the positive projection of the first electrode plate 41 on the substrate and the positive projection of the second electrode plate 42 on the substrate have at least an overlapping area to form a first storage capacitor, and the positive projection of the third electrode plate 43 on the substrate and the positive projection of the second electrode plate 42 on the substrate have at least an overlapping area to form a second storage capacitor. The first electrode plate 41 and the third electrode plate 43 are connected through vias so that the potentials of the first electrode plate 41 and the third electrode plate 43 are the same, forming a first storage capacitor and a second storage capacitor in a parallel structure.

[0148] In an exemplary embodiment, the driving structure layer further includes a plurality of connection lines. The plurality of connection lines at least include a compensation connection line 51, a power supply connection line 52, and an auxiliary power supply line.

[0149] In an exemplary embodiment, the compensation connection line 51 is arranged on the same layer as the first electrode plate 41, and the compensation connection line 51 is connected to the compensation line Se through a via.

[0150] In an exemplary embodiment, the first pole of the second transistor is connected to the first power supply line VDD through the power supply connection line 52; the power supply connection line 52 is arranged on the same layer as the first scan line Gn and the second scan line Sn, and the first power supply line VDD is connected to the power supply connection line 52 through a via, forming a double-layer trace between the gate electrode of the first transistor and the gate electrode of the third transistor. Forming a double-layer trace between the gate electrode of the first transistor and the gate electrode of the third transistor ensures the reliability of power signal transmission and reduces the resistance of the first power supply line VDD.

[0151] In an exemplary embodiment, the auxiliary power supply line is arranged on the same layer as the first scan line and the second scan line, and the second power supply line is connected to the auxiliary power supply line through a via, forming a double-layer trace between the gate electrode of the first transistor and the gate electrode of the third transistor; forming a double-layer trace between the gate electrode of the first transistor and the gate electrode of the third transistor ensures the reliability of power signal transmission and reduces the resistance of the second power supply line VSS.

[0152] The compensation connection line 51 is connected to the compensation line Se through vias, so that the compensation line Se provides compensation signals to the four driving structures through the compensation connection line 51. The power supply connection line 52 is connected to the first power supply line VDD through vias, so that the first power supply line VDD provides power supply signals to the four sub-pixels through the power supply connection line 52, forming a one-to-four structure of the first power supply line VDD and the compensation line Se. The first power supply line and the compensation line are designed in a one-to-four structure, saving the number of signal lines, reducing the occupied space, having a simple structure, reasonable layout, making full use of the layout space, improving the space utilization rate, and being beneficial to improving the resolution and transparency.

[0153] In an exemplary embodiment, the first electrode plate 41 is a long rectangular shape. Except for the position of the compensation connection line 51, the first electrode plate 41 completely covers the pixel driving circuit in each driving structure.

[0154] In an exemplary embodiment, the length of the first electrode plate 41 in the second direction is greater than the distance between the gate electrode of the first transistor and the gate electrode of the third transistor formed subsequently. The length of the first electrode plate 41 in the second direction being greater than the distance between the first electrode of the first transistor and the first electrode of the third transistor formed subsequently can achieve effective shielding and prevent light from entering the active layers in all the transistors.

[0155] As shown in FIGS. 1 and 3, in the 4 driving structures in the display area, the pixel driving circuit in each driving structure includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor. The first transistor T1 includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The second transistor T2 includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The third transistor T3 includes a third active layer, a third gate electrode, a third source electrode, and a third drain electrode. The storage capacitor includes a first electrode plate 41, a second electrode plate 42, and a third electrode plate 43. The first electrode plate 41 and the second electrode plate 42 form a first storage capacitor, and the second electrode plate 42 and the third electrode plate 43 form a second storage capacitor. The potentials of the first electrode plate 41 and the third electrode plate 43 are the same. Therefore, the first storage capacitor and the second storage capacitor form a parallel structure, effectively improving the storage capacity.

[0156] In an exemplary embodiment, a first scan line Gn is connected to a first gate electrode of a first transistor T1 in each sub-pixel, a second scan line Sn is connected to a third gate electrode of a third transistor T3 in each sub-pixel, a data line Dn is connected to a first source electrode of the first transistor T1 in each sub-pixel, a compensation connection line 51 is configured to connect a compensation line Se to a third source electrode of the third transistor T3 in each sub-pixel, and a power supply connection line 52 is configured to connect a first power supply line VDD to a second source electrode of a second transistor T2 in each sub-pixel. Taking the pixel driving circuit of the first sub-pixel P1 as an example, the first gate electrode of the first transistor T1 is connected to the first scan line Gn, the first source electrode of the first transistor T1 is connected to the data line Dn, and the first drain electrode of the first transistor T1 is connected to the second gate electrode of the second transistor T2. The second gate electrode of the second transistor T2 is connected to the first drain electrode of the first transistor T1, the second source electrode of the second transistor T2 is connected to the first power supply line VDD through the power supply connection line 52, and the second drain electrode of the second transistor T2 is connected to the third drain electrode of the third transistor T3 and the anode of the light-emitting element. The third gate electrode of the third transistor T3 is connected to the second scan line Sn, the third source electrode of the third transistor T3 is connected to the compensation line Se through the compensation connection line 51, and the third drain electrode of the third transistor T3 is connected to the second drain electrode of the second transistor T2 and the anode of the light-emitting element. A first electrode plate 41 is connected to the second drain electrode of the second transistor T2 and the third drain electrode of the third transistor T3, a second electrode plate 42 is connected to the first drain electrode of the first transistor T1 and the second gate electrode of the second transistor T2, and a third electrode plate 43 is connected to the second drain electrode of the second transistor T2 and the third drain electrode of the third transistor T3.

[0157] In an exemplary embodiment, in a direction perpendicular to the display substrate, the driving structure layer includes a stacked first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer, a second metal layer, a third insulating layer, a third metal layer, a fourth insulating layer, and a planar layer.

[0158] The first metal layer includes a first electrode plate 41 serving as a shielding layer and a compensation connection line 51. The first electrode plate 41 serving as the shielding layer and the compensation connection line 51 are arranged on the same layer and formed by the same patterning process. The metal oxide layer includes a second electrode plate 42 and the active layers of the respective transistors. The second electrode plate 42 and the active layers of the respective transistors are arranged on the same layer and formed by the same patterning process. The second metal layer includes a first scan line Gn, a second scan line Sn, a power connection line 52, and the gate electrodes of the respective transistors. The first scan line Gn, the second scan line Sn, the power connection line 52, and the gate electrodes of the respective transistors are arranged on the same layer and formed by the same patterning process. The third metal layer includes a data line Dn, a compensation line Se, a first power supply line VDD, a second power supply line VSS, a third electrode plate 43, and the source and drain electrodes of the respective transistors. The data line Dn, the first power supply line VDD, the second power supply line VSS, the compensation line Se, the third electrode plate 43, and the source and drain electrodes of the respective transistors are arranged on the same layer and formed by the same patterning process. A via is provided on the planarization layer. The via V in the planarization layer exposes the second pole of the second transistor. The first electrode in the light-emitting structure layer is connected to the driving structure layer through the via in the planarization layer.

[0159] In an exemplary embodiment, the first transistor T1 and the second transistor T2 are located on the side of the second electrode plate 42 close to the first scan line Gn, and the third transistor T3 is located on the side of the second electrode plate 42 close to the second scan line Sn.

[0160] In an exemplary embodiment, the second electrode plate made of a metal oxide material is used as the electrode plate of the storage capacitor. The second electrode plate forms storage capacitors with the first electrode plate in the first metal layer and the third electrode plate in the third metal layer respectively. The first electrode plate and the third electrode plate have the same potential, and the second electrode plate has a potential different from that of the first electrode plate and the third electrode plate. Therefore, two parallel storage capacitors are formed between the first electrode plate, the second electrode plate, and the third electrode plate, effectively increasing the capacitance of the storage capacitor, which is beneficial to realizing high-resolution display. The preparation process of the present disclosure can be realized by using existing mature preparation equipment, has little improvement on the existing process, can be well compatible with the existing preparation process, has a simple process implementation, is easy to implement, has high production efficiency, low production cost, and high yield.

[0161] In an exemplary embodiment, openings are provided in the second electrode plates of the second driving structure and the third driving structure; the opening in the second electrode plate of the second driving structure is provided on the side of the second driving structure close to the third driving structure, and the opening in the second electrode plate of the third driving structure is provided on the side of the third driving structure close to the second driving structure.

[0162] In an exemplary embodiment, the flat layer vias in the first driving structure and the fourth driving structure are located between the third transistor and the second electrode plate; the flat layer vias in the first driving structure and the flat layer vias in the fourth driving structure are mirror-symmetrical with respect to the compensation line; the flat layer vias of the second driving structure are located within the opening of the second electrode plate of the second driving structure, and the flat layer vias of the third driving structure are located within the opening of the second electrode plate of the third driving structure; the flat layer vias in the second driving structure and the flat layer vias in the third driving structure are mirror-symmetrical with respect to the compensation line.

[0163] In an exemplary embodiment, the included angle between the arrangement direction of the flat layer vias in the first driving structure and the flat layer vias in the second driving structure and the first direction is greater than 0 degrees and less than 90 degrees.

[0164] In an exemplary embodiment, the first electrode of the first light-emitting structure is connected to the first driving structure through the flat layer vias in the first driving structure, the first electrode of the second light-emitting structure is connected to the fourth driving structure through the flat layer vias in the fourth driving structure, the first electrode of the third light-emitting structure is connected to the second driving structure through the flat layer vias in the second driving structure, and the first electrode of the fourth light-emitting structure is connected to the third driving structure through the flat layer vias in the third driving structure.

[0165] The opening region 711 of the pixel definition layer of the first light-emitting structure and the opening region 713 of the pixel definition layer of the third light-emitting structure are located between the second power supply line VSS and the compensation line Se, and the orthographic projection on the substrate has an overlapping region with the orthographic projections of the first driving structure and the second driving structure on the substrate.

[0166] The opening region 712 of the pixel definition layer of the second light-emitting structure and the opening region 714 of the pixel definition layer of the fourth light-emitting structure are located between the compensation line Se and the first power supply line VDD, and the orthographic projection on the substrate has an overlapping region with the orthographic projections of the third driving structure and the fourth driving structure on the substrate.

[0167] As shown in FIG. 1, the orthographic projection of the flat layer via V of the first driving structure on the substrate does not have an overlapping region with the orthographic projection of the opening region of the pixel definition layer in the first light-emitting structure on the substrate; the orthographic projection of the flat layer via V of the second driving structure on the substrate does not have an overlapping region with the orthographic projection of the opening region of the pixel definition layer in the third light-emitting structure on the substrate; the orthographic projection of the flat layer via V of the third driving structure on the substrate does not have an overlapping region with the orthographic projection of the opening region of the pixel definition layer in the fourth light-emitting structure on the substrate. The orthographic projection of the flat layer via V of the fourth driving structure on the substrate does not have an overlapping region with the orthographic projection of the opening region of the pixel definition layer in the second light-emitting structure on the substrate.

[0168] In an exemplary embodiment, the transparent region includes a first insulating layer, a third insulating layer, a fourth insulating layer, and a planarization layer stacked on a substrate.

[0169] In an exemplary embodiment, as shown in FIG. 1, the spacer region includes a first spacer region A1, a second spacer region A2, and a third spacer region. The first spacer region A1 is located between the opening region of the pixel defining layer of the first light-emitting structure and the opening region of the pixel defining layer of the third light-emitting structure; the second spacer region A2 is located between the opening region of the pixel defining layer of the second light-emitting structure and the opening region of the pixel defining layer of the fourth light-emitting structure; the first spacer region and the second spacer region are arranged along a first direction. The first spacer region and the second spacer region are respectively located on both sides of the third spacer region, and the orthographic projection of the third spacer region on the substrate coincides with the orthographic projection of the compensation line located between the first scan line and the second scan line on the substrate.

[0170] In an exemplary embodiment, as shown in FIG. 1, the third spacer region includes: a first sub-spacer region A31, a second sub-spacer region A32, and a third sub-spacer region A33 that are sequentially arranged along a second direction and are connected end to end; the second sub-spacer region A32 is located between the first sub-spacer region A31 and the third sub-spacer region A33.

[0171] The first sub-spacer region A31 is located between the opening region of the pixel defining layer of the first light-emitting structure and the opening region of the pixel defining layer of the second light-emitting structure; the third sub-spacer region A33 is located between the opening region of the pixel defining layer of the third light-emitting structure and the opening region of the pixel defining layer of the fourth light-emitting structure. The second sub-spacer region A32 is located between the first spacer region A1 and the second spacer region A2 and is arranged along the first direction with the first spacer region A1 and the second spacer region A2.

[0172] In an exemplary embodiment, as shown in FIG. 1, when the filter is located on the first light-emitting structure, the orthographic projection of the filter on the substrate covers the opening region of the pixel defining layer of the first light-emitting structure, the orthographic projections of the first sub-spacer region and the second sub-spacer region on the substrate, and there is an overlapping region with the orthographic projections of a part of the second scan line and a part of the second power supply line located in the display region on the substrate.

[0173] In an exemplary embodiment, as shown in FIG. 1, when the filter is located on the second light-emitting structure, the orthographic projection of the filter on the substrate covers the opening region of the pixel defining layer of the second light-emitting structure, the orthographic projections of the second spacer region, the first sub-spacer region, and the second sub-spacer region on the substrate, and there is an overlapping region with the orthographic projections of a part of the second scan line and a part of the first power supply line located in the display region on the substrate;

[0174] In an exemplary embodiment, as shown in FIG. 1, when the filter is located on the third light-emitting structure, the orthographic projection of the filter on the substrate covers the orthographic projection of the opening region of the pixel definition layer of the third light-emitting structure on the substrate, and there is an overlapping region with the orthographic projections of a part of the first spacer region, a part of the third sub-spacer region, a part of the first scan line located in the display region, and a part of the second power line on the substrate;

[0175] In an exemplary embodiment, as shown in FIG. 1, when the filter is located on the fourth light-emitting structure, the orthographic projection of the filter on the substrate covers the orthographic projection of the opening region of the pixel definition layer of the fourth light-emitting structure on the substrate, and there is an overlapping region with the orthographic projections of a part of the second spacer region, a part of the third sub-spacer region, a part of the first scan line located in the display region, and a part of the first power line on the substrate.

[0176] In an exemplary embodiment, as Figure 1B shown, there is no overlapping region between the orthographic projection of the color filter layer on the substrate and the orthographic projection of the flat layer vias in the driving structure layer on the substrate, which can ensure that the overlapping region between adjacent filters is reduced to reduce color bleeding.

[0177] In an exemplary embodiment, as Figure 1A and 1B shown, the display substrate further includes: a shielding layer 30. The orthographic projection of the shielding layer 30 on the substrate has an overlapping region with the orthographic projections of the first scan line Gn located in the transparent region and the second scan line Sn located in the transparent region and a part of the display region on the substrate.

[0178] In an exemplary embodiment, the shielding layer 30 includes: a first shielding layer and a second shielding layer; the first shielding layer is located on the side closer to the substrate of the second shielding layer, the first shielding layer is provided on the same layer as one of the color filters among the plurality of color filters, and the second shielding layer is provided on the same layer as the other color filter among the plurality of color filters, which can simplify the manufacturing process of the display substrate.

[0179] The structure of a display substrate provided by an exemplary embodiment will be described below through the preparation process of the display substrate. The "lithography process" includes depositing a film layer, coating a photoresist, mask exposure, development, etching, and photoresist stripping processes. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be any one or more of spraying and spin coating. Etching can be any one or more of dry etching and wet etching. A "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a lithography process throughout the manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" requires a lithography process throughout the manufacturing process, it is called a "thin film" before the lithography process and a "layer" after the lithography process. In the present disclosure, the statement that "A and B are arranged in the same layer" means that A and B are formed simultaneously through the same lithography process.

[0180] Figure 5 to Figure 15 is a schematic diagram of the preparation process of a display substrate provided by an exemplary embodiment, showing the layout structure of a display unit of a top-emission OLED display substrate. Each display unit includes a display area 100 and a transparent area 200. The driving structure layer of the display area 100 includes: four driving structures P1 to P4. The pixel driving circuit of each driving structure includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor.

[0181] (1) Form a first metal layer, including: depositing a first metal thin film on a substrate, patterning the first metal thin film through a lithography process, and forming a first metal layer located in the display area 100 on the substrate 10. The first metal layer includes a first electrode plate 41 and a compensation connection line 51. Each driving structure forms a first electrode plate 41. As shown in Figure 5, Figure 5B is Figure 5A a cross-sectional view taken along the A-A direction in Figure 5C is Figure 5A a cross-sectional view taken along the B-B direction in

[0182] In an exemplary embodiment, the first electrode plate 41 serves both as one electrode plate of the first storage capacitor to form the first storage capacitor with the second electrode plate formed subsequently, and as a shielding layer configured to shield the active layer of the transistor to reduce the light intensity irradiated on the transistor, reduce the leakage current, and thus reduce the influence of light on the transistor characteristics.

[0183] In an exemplary embodiment, the compensation connection line 51 is a strip-shaped structure spanning 4 sub-pixels. The compensation connection line 51 is configured to be connected to the compensation line formed subsequently to supply a compensation signal to the driving structure.

[0184] In an exemplary embodiment, the first metal layer in the first driving structure P1 and the first metal layer in the fourth driving structure P4 are mirror-symmetrical with respect to the vertical axis, and the first metal layer in the second driving structure P2 and the first metal layer in the third driving structure P3 are mirror-symmetrical with respect to the vertical axis. The vertical axis is the midline of the second driving structure and the third driving structure.

[0185] (2) Form a metal oxide layer, including: depositing a first insulating film on the substrate formed with the first metal layer, patterning the first insulating film through a patterning process to form a first insulating layer 61 covering the first metal layer and located in the display area and the transparent area, depositing a metal oxide film on the first insulating layer 61, and patterning the metal oxide film through a patterning process to form a metal oxide layer located in the display area. The metal oxide layer includes a first active layer 11, a second active layer 21, a third active layer 31 provided in each driving structure, and a second electrode plate 42. As shown in FIG. 6, Figure 6B is Figure 6A a cross-sectional view taken along the A-A direction in Figure 6C is Figure 6A a cross-sectional view taken along the B-B direction in

[0186] The first active layer 11 serves as the active layer of the first transistor, the second active layer 21 serves as the active layer of the second transistor, the third active layer 31 serves as the active layer of the third transistor, and the orthographic projection of the second electrode plate 42 on the substrate 10 and the orthographic projection of the first electrode plate 41 on the substrate 10 have an overlapping area. The first electrode plate 41 and the second electrode plate 42 form a first storage capacitor. The second electrode plate 42 serves as both one electrode plate of the first storage capacitor and one electrode plate of the second storage capacitor, and the second electrode plate 42 is configured to form a second storage capacitor with a third electrode plate formed subsequently.

[0187] In an exemplary embodiment, the orthographic projections of the first active layer 11, the second active layer 21, and the third active layer 31 on the substrate 10 and the orthographic projection of the first electrode plate 41 on the substrate 10 have an overlapping area, so that the first electrode plate 41 serving as an occlusion layer can occlude the channel regions of the first transistor, the second transistor, and the third transistor, avoiding the influence of light on the channels and thus avoiding the influence of the display effect caused by the generation of photocurrent leakage in the channels. The orthographic projections of the first active layer 11, the second active layer 21, and the third active layer 31 on the substrate 10 and the orthographic projection of the second electrode plate 42 on the substrate 10 are arranged at intervals, that is, there is no overlapping area between the first active layer 11 and the second electrode plate 42, between the second active layer 21 and the second electrode plate 42, and between the third active layer 31 and the second electrode plate 42, which is beneficial to designing the channel width-to-length ratios of the first transistor, the second transistor, and the third transistor according to relevant requirements.

[0188] The third active layer 31 is located on the side of the second electrode plate 42 close to the compensation connection line 51. The first active layer 11 and the second active layer 21 are located on the side of the second electrode plate 42 far from the compensation connection line 51. The second active layer 21 is located on the side of the first active layer 11 close to the compensation connection line 51.

[0189] In an exemplary embodiment, the metal oxide layer in the first driving structure P1 and the metal oxide layer in the fourth driving structure P4 are mirror-symmetrical with respect to the vertical axis. The metal oxide layer in the second driving structure P2 and the metal oxide layer in the third driving structure P3 are mirror-symmetrical with respect to the vertical axis. There is a gap between the second electrode plate 42 and the third active layer 31 in the first driving structure P1 and the fourth driving structure P4. An opening is provided in the middle of the second electrode plate 42 of the second driving structure P2 and the third driving structure P3.

[0190] (3) Forming the second metal layer, including: depositing a second insulating film on the substrate formed with the metal oxide, patterning the second insulating film through a patterning process to form a second insulating layer 62 located in the display area. Depositing a second metal film on the second insulating layer 62, and patterning the second metal film through a patterning process to form the second metal layer. The second metal layer includes a first scan line Gn, a second scan line Sn, a power connection line 52, and an auxiliary power line 53 formed in each display unit, and a first gate electrode 12, a second gate electrode 22, and a third gate electrode 32 formed in each driving structure, as Figure 7A shown Figure 7B as Figure 7A the cross-sectional view taken along the A-A direction in Figure 7C as Figure 7A the cross-sectional view taken along the B-B direction in.

[0191] In an exemplary embodiment, the first scan line Gn and the second scan line Sn are arranged in parallel and both extend along the first direction. The first scan line Gn and the second scan line Sn are located on both sides of the driving structure layer. The first scan line Gn is provided on the side of the driving structure layer close to the first transistor, and the second scan line Sn is located on the side of the driving structure layer close to the third transistor.

[0192] In an exemplary embodiment, the first gate electrode 12 is an integral structure connected to the first scan line Gn and straddles the first active layer 11. The second gate electrode 22 straddles the second active layer 21 and the second electrode plate 42. The third gate electrode 32 is an integral structure connected to the second scan line Sn and straddles the third active layer 31.

[0193] In an exemplary embodiment, the power supply connection line 52 includes a first connection bar perpendicular to the first scan line Gn and a second connection bar parallel to the first scan line Gn, and one ends of the first connection bar and the second connection bar are connected to each other. The first connection bar is formed in the region where the first power supply line VDD is located in the display unit and is configured to connect the subsequently formed first power supply line VDD. The second connection bar straddles 4 driving structures and is configured to provide a high-level signal to each driving structure.

[0194] In an exemplary embodiment, the auxiliary power supply line 53 is formed in the region where the second power supply line VSS is located in the display unit, is perpendicular to the first scan line Gn, and is configured to connect the subsequently formed second power supply line VSS.

[0195] In an exemplary embodiment, the second insulating layer 62 is the same as the second metal layer, that is, the second insulating layer 62 is located below the second metal layer, and there is no second insulating layer 62 in the region outside the second metal layer.

[0196] In an exemplary embodiment, the second metal layer in the first driving structure P1 and the second metal layer in the fourth driving structure P4 are mirror-symmetrical with respect to the vertical axis, and the second metal layer in the second driving structure P2 and the second metal layer in the third driving structure P3 are mirror-symmetrical with respect to the vertical axis.

[0197] In an exemplary embodiment, this process further includes a conductorization process. The conductorization process is to perform plasma treatment on the metal oxide layer by using the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 as masks after the second metal layer is formed. The metal oxide layer in the region shielded by the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 (that is, the region where the metal oxide layer overlaps with the first gate electrode 12, the second gate electrode 22, and the third gate electrode) serves as the channel region of the transistor, and the metal oxide layer in the region not shielded by the second metal layer is processed into a conductorized layer to form the conductorized second electrode plate 42 and the conductorized source-drain region.

[0198] (4) Forming a third insulating layer. Forming the third insulating layer includes: depositing a third insulating film on a substrate having a second metal layer formed thereon, and patterning the third insulating film through a patterning process to form a third insulating layer 63 located in the display area and the transparent area. The third insulating layer 63 is provided with a plurality of vias, and the plurality of vias include: a first via V1 and a second via V2 located on both sides of the first gate electrode 12, a third via V3 and a fourth via V4 located on both sides of the second gate electrode 22, a fifth via V5 and a sixth via V6 located on both sides of the third gate electrode 32, a seventh via V7 and an eighth via V8 located at the position where the compensation connection line 51 is located, a ninth via V9 located at the overlapping area between the second gate electrode 22 and the second electrode plate 42, a tenth via V10 located at the position where the first electrode plate 41 is located, a plurality of eleventh vias V11 located at the position where the first connecting bar of the power connection line 52 is located, and a plurality of twelfth vias V12 located at the position where the auxiliary power line 53 is located, as shown in FIG. Figure 8A As shown, Figure 8B for Figure 8A The cross-section view along the AA direction. Figure 8C for Figure 8A Cross-sectional view along the BB direction.

[0199] In an exemplary embodiment, the first via hole V1 and the second via hole V2 expose the surfaces of both ends of the first active layer 11. The third via hole V3 is a transfer via hole, which is composed of two half holes, one half hole is formed on the second active layer 21, and the other half hole is formed on the second connecting bar of the power connection line 52. The transfer via hole composed of the two half holes simultaneously exposes the surface of the second active layer 21 and the surface of the second connecting bar of the power connection line 52. The fourth via hole V4 exposes the surface of the second active layer 21. The fifth via hole V5 and the sixth via hole V6 expose the surfaces of both ends of the third active layer 31. The seventh via hole V7 is located at a position where the compensation connection line 51 overlaps with the compensation line formed subsequently, and each driving structure forms an eighth via hole V8, and the seventh via hole V7 and the eighth via hole V8 expose the surface of the compensation connection line 51. The ninth via hole V9 is a transfer via hole, which is composed of two half holes, one half hole is formed on the second gate electrode 22, and the other half hole is formed on the second electrode plate 42. The transfer via hole composed of the two half holes exposes the surface of the second gate electrode 22 and the surface of the second electrode plate 42 at the same time. The tenth via hole V10 exposes the surface of the first electrode plate 41. The eleventh via hole V11 is located at the position where the first connecting bar of the power connection line 52 is located, and multiple eleventh via holes V11 are arranged at intervals, and the eleventh via hole V11 exposes the surface of the first connecting bar of the power connection line 52. The twelfth via hole V12 is located at the position where the auxiliary power line 53 is located, and multiple twelfth via holes V12 are arranged at intervals, and the third insulating layer 63 in the twelfth via hole V12 exposes the surface of the auxiliary power line 53.

[0200] In an exemplary embodiment, the tenth vias V10 in the first driving structure P1 and the fourth driving structure P4 are located within the gap between the second electrode plate 42 and the third active layer 31. The tenth vias V10 in the second driving structure P2 and the third driving structure P3 are located within the opening in the middle of the second electrode plate 42.

[0201] (5) Form a third metal layer, including: depositing a third metal thin film on the substrate formed with the third insulating layer, patterning the third metal thin film through a patterning process, and forming a third metal layer located in the display area 100 on the third insulating layer 63. The third metal layer includes: a first power supply line VDD, a second power supply line VSS, a compensation line Se, and four data lines Dn formed in each display unit, and a first source electrode 13, a first drain electrode 14, a second source electrode 23, a second drain electrode 24, a third source electrode 33, a third drain electrode 34, and a third electrode plate 43 formed in each driving structure. As Figure 9A shown, Figure 9B is Figure 9A a cross-sectional view taken along the A-A direction in Figure 9C and Figure 9A is a cross-sectional view taken along the B-B direction in

[0202] In an exemplary embodiment, the first power supply line VDD, the second power supply line VSS, the compensation line Se, and the data lines Dn are arranged in parallel and extend along the second direction. The second power supply line VSS is disposed on the side of the first driving structure P1 close to the transparent area 200, and the first power supply line VDD is disposed on the side of the fourth driving structure away from the transparent area 200. The compensation line Se is disposed between the first power supply line VDD and the second power supply line VSS and is disposed between the second driving structure P2 and the third driving structure P3. Two data lines Dn are disposed between the second power supply line VSS and the compensation line Se and are disposed between the first driving structure P1 and the second driving structure P2. The other two data lines Dn are disposed between the first power supply line VDD and the compensation line Se and are disposed between the third driving structure P3 and the fourth driving structure P4.

[0203] In an exemplary embodiment, the first power line VDD is connected to the power connection line 52 through a plurality of eleventh vias V11, so that the first power line VDD is respectively connected to the second source electrode 23 of each driving structure through the power connection line 52. The second power line VSS is connected to the auxiliary power line 53 through a plurality of twelfth vias V12, so that the second power line VSS outputs a low-level signal to the cathode of the light-emitting element of each sub-pixel through the auxiliary power line 53. The compensation line Se is connected to the compensation connection line 51 through the seventh via V7, so that the compensation line Se is respectively connected to the third source electrode 33 of each driving structure through the compensation connection line 51. Since the compensation line Se is arranged in the middle of the display area 100, it is connected to the third transistors of the driving structures on both sides through the compensation connection line 51, and the third transistors of the driving structures on the left and right sides are symmetrically arranged relative to the compensation line Se. This symmetrical design allows each display unit to use only one compensation line Se, which can ensure that the RC delay of the compensation signal before writing into the transistor is substantially the same, thereby ensuring display uniformity.

[0204] In an exemplary embodiment, the first source electrode 13 is an integral structure connected to the data line Dn, so that each data line Dn is respectively connected to the first source electrode 13 of the driving structure, the first source electrode 13 is connected to one end of the first active layer 11 through the first via V1, the first drain electrode 14 is connected to the other end of the first active layer 11 through the second via V2, and the first drain electrode 14 is also connected to the second gate electrode 22 and the second electrode plate 42 through the ninth via V9 of the transfer structure, so that the first drain electrode 14, the second gate electrode 22 and the second electrode plate 42 have the same potential.

[0205] In an exemplary embodiment, the second source electrode 23 is connected to the power connection line 52 and one end of the second active layer 21 at the same time through the third via V3 of the transfer structure, thereby realizing the connection between the second source electrode 23 and the first power line VDD, and the second drain electrode 24 is connected to the other end of the second active layer 21 through the fourth via V4.

[0206] In an exemplary embodiment, the third source electrode 33 is connected to one end of the third active layer 31 through the fifth via hole V5, and is connected to the compensation connection line 51 through the eighth via hole V8, thereby realizing the connection between the third source electrode 33 and the compensation line Se, and the third drain electrode 34 is connected to the other end of the third active layer 31 through the sixth via hole V6.

[0207] In an exemplary embodiment, the second drain electrode 24, the third drain electrode 34, and the third plate 43 are integrally connected to each other. The third plate 43 is connected to the first plate 41 through the tenth via V10. Thus, the second drain electrode 24 is simultaneously connected to the first plate 41 and the third plate 43, and the third drain electrode 34 is simultaneously connected to the first plate 41 and the third plate 43, achieving the same potential for the second drain electrode 24, the third drain electrode 34, the first plate 41, and the third plate 43.

[0208] In an exemplary embodiment, the positive projection of the third plate 43 on the substrate 10 overlaps with the positive projection of the second plate 42 on the substrate 10, and the third plate 43 and the second plate 42 form a second storage capacitor.

[0209] In an exemplary embodiment, the third metal layer in the first driving structure P1 and the third metal layer in the fourth driving structure P4 are mirror-symmetrical with respect to the vertical axis, and the third metal layer in the second driving structure P2 and the third metal layer in the third driving structure P3 are mirror-symmetrical with respect to the vertical axis.

[0210] After this patterning process, the third metal layer is formed in the display area 100, and the transparent area 200 includes the first insulating layer 61 and the third insulating layer 63 stacked on the substrate 10.

[0211] (6) Forming a fourth insulating layer and a planarization layer, including: depositing a fourth insulating thin film first and then coating a planarization thin film on the substrate on which the third metal layer is formed. Through the masking, exposure, and development of the planarization thin film, the fourth insulating thin film is etched to form the fourth insulating layer 64 located in the display area and the transparent area, and the planarization layer 65 located on the fourth insulating layer 64 and in the display area and the transparent area. A plurality of vias are formed in the fourth insulating layer 64 and the planarization layer 65. The plurality of vias include: the thirteenth via V13 at the position of the drain electrode of the second transistor T2 in each driving structure, as shown in FIG. 10, Figure 10B is Figure 10A the cross-sectional view taken along the line A-A in Figure 10C is Figure 10A the cross-sectional view taken along the line B-B in. The fourth insulating layer 64 and the planarization layer 65 in the thirteenth via V13 expose the surface of the drain electrode of the second transistor T2.

[0212] The third via V13 is the same via as the planarization layer via V in FIG. 1.

[0213] (7) Form a transparent conductive layer, including: depositing a transparent conductive thin film on a substrate on which a planar layer is formed, patterning the transparent conductive thin film through a patterning process, and forming a transparent conductive layer on the planar layer 65. The transparent conductive layer includes an anode 70, and the anode 70 is formed in each light-emitting structure in the display area 100. The anode 70 is connected to the second pole of the second transistor T2 through the thirteenth via V13, as Figure 15 shown. Since the second pole of the second transistor T2, the first pole of the third transistor T3, and the third electrode plate 43 are integrally connected structures, the thirteenth via V13 can be set at any position on the third electrode plate 43, as shown in FIG. 11, Figure 11B is Figure 11A the cross-sectional view taken along the line A-A in Figure 11A and the cross-sectional view taken along the line B-B in Figure 10C is the same.

[0214] (8) Form a pixel definition layer, including: coating a pixel definition thin film on the substrate on which the transparent conductive layer is formed, and forming a pixel definition layer (Pixel Define Layer) through a mask, exposure, and development process. The pixel definition layer is formed in each light-emitting structure in the display area 100, and an opening area 710 exposing the anode 70 is formed in the pixel definition layer in each light-emitting structure, as shown in FIG. 12, Figure 12B is Figure 12A the cross-sectional view taken along the line A-A in Figure 12C and is Figure 12A the cross-sectional view taken along the line B-B in

[0215] (9) Form an organic light-emitting layer, including: forming an organic light-emitting layer 71 in the opening area of the formed pixel definition layer and on the pixel definition layer. The organic light-emitting layer 71 is connected to the anode 70, as Figure 13 shown.

[0216] (10) Form a cathode, including: coating a cathode thin film on the substrate on which the organic light-emitting layer is formed, and patterning the cathode thin film through a patterning process to form a cathode 73. The cathode is formed in the display area 100 and covers the organic light-emitting layer in each light-emitting structure. In the display area 100, the cathode 73 is connected to the organic light-emitting layer 72, as shown in FIG. 14, Figure 14B is Figure 14A the cross-sectional view taken along the line A-A in Figure 14C and is Figure 14A the cross-sectional view taken along the line B-B in

[0217] (11) Form an encapsulation layer. The encapsulation layer is formed on the substrate where the cathode is formed. The encapsulation layer is formed on the encapsulation layers of the display area 100 and the transparent area 200. The encapsulation layer of the display area 100 includes a first encapsulation layer 74 of inorganic material, a second encapsulation layer 75 of organic material, and a third encapsulation layer 76 of inorganic material. The first encapsulation layer 74 is disposed on the cathode 73, the second encapsulation layer 75 is disposed on the first encapsulation layer 74, and the third encapsulation layer 76 is disposed on the second encapsulation layer 75, forming a stacked structure of inorganic material / organic material / inorganic material. The encapsulation layer of the transparent area 200 includes a first encapsulation layer 74 of inorganic material and a third encapsulation layer 76 of inorganic material. The first encapsulation layer 74 is disposed on the cathode 73, and the third encapsulation layer 76 is disposed on the first encapsulation layer 74, forming a stacked structure of inorganic material / inorganic material, as Figure 15 shown.

[0218] (12) Form a color filter layer and a blocking layer on the encapsulation layer, as Figure 1B shown.

[0219] In an exemplary embodiment, the first metal layer, the second metal layer, and the third metal layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). It can be a single layer, a multi-layer, or a composite layer. The first insulating layer is called a buffer layer, which is used to improve the water and oxygen resistance of the substrate. The second insulating layer is called a gate insulating (GI) layer. The third insulating layer is called an interlayer insulating (ILD) layer. The fourth insulating layer is called a passivation (PVX) layer. The thickness of the second insulating layer is less than the thickness of the third insulating layer, and the thickness of the first insulating layer is less than the sum of the thicknesses of the second insulating layer and the third insulating layer. On the premise of ensuring the insulation effect, the capacitance of the storage capacitor is increased. The planarization layer can be made of an organic material. The transparent conductive film can be indium tin oxide ITO or indium zinc oxide IZO. The pixel defining layer can be made of polyimide, acrylic, or polyethylene terephthalate. The second electrode can be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or can be an alloy made of any one or more of the above metals.

[0220] In an exemplary embodiment, the thickness of the first insulating layer is from 3000 angstroms to 5000 angstroms, the thickness of the second insulating layer is from 1000 angstroms to 2000 angstroms, the thickness of the third insulating layer is from 4500 angstroms to 7000 angstroms, and the thickness of the fourth insulating layer is from 3000 angstroms to 5000 angstroms.

[0221] In an exemplary embodiment, the thickness of the first metal layer is from 80 angstroms to 1200 angstroms, the thickness of the second metal layer is from 3000 angstroms to 5000 angstroms, and the thickness of the third metal layer is from 3000 angstroms to 9000 angstroms.

[0222] In an exemplary embodiment, the metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, an oxide containing indium, gallium and zinc, etc. The metal oxide layer may be a single layer, or may be a double layer, or may be a multi-layer.

[0223] The structure shown in the present disclosure and its preparation process are only an exemplary illustration. In the exemplary embodiment, the corresponding structure can be changed according to actual needs, and the patterning process can be increased or decreased. For example, the pixel driving circuit can be 5T1C or 7T1C. Again, other electrodes or leads can also be provided in the film layer structure.

[0224] The embodiment of the present disclosure also provides a method for manufacturing a display substrate. The method for manufacturing the display substrate includes:

[0225] Step S1, providing a substrate.

[0226] Step S2, forming a display unit including a display area and a transparent area on the substrate to form a display substrate.

[0227] The display unit includes: a driving structure layer, a light-emitting structure layer, and a color filter layer that are located in the display area and are sequentially arranged on the substrate; the light-emitting structure layer includes: a plurality of light-emitting structures; each light-emitting structure includes: a pixel definition layer, a first electrode, an organic light-emitting layer, and a second electrode; the organic light-emitting layer is located within the opening area of the pixel definition layer and on the pixel definition layer; the display substrate includes: a spacer area located in the display area, the spacer area is located between the opening areas of the pixel definition layers of adjacent light-emitting structures, and there is an overlapping area with the positive projection of the pixel defining layer on the substrate; the color filter layer includes: a plurality of color filters; there is an overlapping area of the positive projection of adjacent color filters on the substrate; the overlapping area of adjacent color filters on the substrate has an overlapping area with the positive projection of the spacer area on the substrate.

[0228] The display substrate is the display substrate provided in the foregoing embodiment, and the implementation principle and implementation effect are similar, and will not be elaborated here.

[0229] In an exemplary embodiment, step S1 includes: forming a first metal layer including a first electrode plate on a substrate in a display area; forming a first insulating layer covering the first metal layer in the display area and a transparent area; forming a metal oxide layer including a second electrode plate on the first insulating layer in the display area, where a positive projection of the second electrode plate on the substrate overlaps with a positive projection of the first electrode plate on the substrate to form a first storage capacitor; sequentially forming a second insulating layer and a second metal layer in the display area; the second metal layer includes: a first scan line and a second scan line; forming a third insulating layer covering the second metal layer in the display area and the transparent area; forming a third metal layer in the display area on the third insulating layer, the third metal layer includes a first power line, a second power line, a compensation line, a data line, and a third electrode plate, where a positive projection of the third electrode plate on the substrate overlaps with a positive projection of the second electrode plate on the substrate to form a second storage capacitor, and the third electrode plate is connected to the first electrode plate through a via; forming a fourth insulating layer and a planarization layer covering the third metal layer in the display area and the transparent area; forming a first electrode on the planarization layer; sequentially forming a pixel definition layer, an organic light-emitting layer, and a cathode; forming a packaging layer; forming a color filter layer on the packaging layer.

[0230] In an exemplary embodiment, forming a color filter layer on the packaging layer includes: forming a color filter layer and a shielding layer on the packaging layer.

[0231] The embodiment of the present disclosure also provides a display device, including the display substrate provided in any of the foregoing embodiments.

[0232] In an exemplary embodiment, the display device may be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0233] The drawings in the present disclosure only relate to the structures involved in the present disclosure, and other structures may refer to the general design. Without conflict, the embodiments of the present disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments.

[0234] Those of ordinary skill in the art should understand that the technical solutions of the present disclosure can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be covered by the scope of the claims of the present disclosure.

Claims

1. A display substrate, comprising: A substrate and a plurality of display units disposed on the substrate; The display unit includes: a display area and a transparent area; the display unit includes: a driving structure layer, a light-emitting structure layer, and a color filter layer that are sequentially disposed on the substrate in the display area; the light-emitting structure layer includes: a plurality of light-emitting structures; each light-emitting structure includes: a pixel defining layer, a first electrode, an organic light-emitting layer, and a second electrode; the organic light-emitting layer is located within the opening area of the pixel defining layer and on the pixel defining layer; the color filter layer includes: a plurality of color filters; The display substrate includes: a spacer area located in the display area, the spacer area is located between the opening areas of the pixel defining layers of adjacent light-emitting structures, and the orthographic projection of the spacer area on the substrate and the orthographic projection of the pixel defining layer on the substrate have an overlapping area; The orthographic projections of adjacent color filters on the substrate have an overlapping area; the overlapping area of adjacent color filters on the substrate and the orthographic projection of the spacer area on the substrate have an overlapping area; The plurality of light-emitting structures includes: a first light-emitting structure, a second light-emitting structure, a third light-emitting structure, and a fourth light-emitting structure; the first light-emitting structure and the second light-emitting structure are arranged along a first direction, and the third light-emitting structure and the fourth light-emitting structure are arranged along the first direction; the first light-emitting structure and the third light-emitting structure are arranged along a second direction, and the second light-emitting structure and the fourth light-emitting structure are arranged along the second direction; The plurality of color filters includes: a first color filter, a second color filter, and a third color filter; the color filters of three colors are respectively disposed on three of the four light-emitting structures; Wherein, the first direction is the arrangement direction of the transparent area and the display area within one display unit, the second direction is perpendicular to the first direction, the first color, the second color, and the third color are one of red, blue, and green, and the three colors are different from each other; The driving structure layer includes: a plurality of first scan lines and second scan lines extending along the first direction, a plurality of first power lines, second power lines, data lines, and compensation lines extending along the second direction, and a first driving structure, a second driving structure, a third driving structure, and a fourth driving structure arranged along the first direction; The first driving structure is located on one side of the second driving structure close to the transparent area, and the fourth driving structure is located on one side of the third driving structure away from the transparent area; The first power line is located on one side of the fourth driving structure away from the third driving structure; the second power line is located on one side of the first driving structure away from the second driving structure; the compensation line is located between the second driving structure and the third driving structure; The data lines include: a first data line, a second data line, a third data line, and a fourth data line; The first data line is connected to the first driving structure and is located on a side of the first driving structure close to the second driving structure; the second data line is connected to the second driving structure and is located on a side of the second driving structure close to the first driving structure; the third data line is connected to the third driving structure and is located on a side of the third driving structure close to the fourth driving structure; the fourth data line is connected to the fourth driving structure and is located on a side of the fourth driving structure close to the third driving structure; The first scanning line and the second scanning line are respectively located on two sides of the driving structure layer; The length of the first power line in a first direction is greater than the length of the compensation line or the data line in the first direction, and the length of the second power line in the first direction is greater than the length of the compensation line or the data line in the first direction.

2. The display substrate according to claim 1, wherein, The first driving structure and the fourth driving structure are mirror-symmetrical with respect to the compensation line, and the second driving structure and the third driving structure are mirror-symmetrical with respect to the compensation line.

3. The display substrate according to claim 2, wherein, Each driving structure includes: a pixel driving circuit, and the pixel driving circuit includes: a first transistor, a second transistor, a third transistor, and a storage capacitor; the second transistor is a driving transistor; the storage capacitor includes: a first electrode plate, a second electrode plate, and a third electrode plate; The gate electrode of the first transistor is connected to the first scanning line, the first pole of the first transistor is connected to the data line, the second pole of the first transistor is connected to the gate electrode of the second transistor, the first pole of the second transistor is connected to the first power line, the second pole of the second transistor is connected to the first electrode of the light-emitting structure, the gate electrode of the third transistor is connected to the second scanning line, the first pole of the third transistor is connected to the compensation line through a compensation connection line, the second pole of the third transistor is connected to the second pole of the second transistor, the second electrode of the light-emitting structure is connected to the second power line; the first electrode plate and the third electrode plate are connected to the second pole of the second transistor, and the second electrode plate is connected to the gate electrode of the second transistor; The driving structure layer further includes: a power connection line, an auxiliary power line, and a compensation connection line; The first pole of the second transistor is connected to the first power line through the power connection line; the power connection line is arranged on the same layer as the first scanning line and the second scanning line, the first power line is connected to the power connection line through a via, and a double-layer routing is formed between the gate electrode of the first transistor and the gate electrode of the third transistor; The auxiliary power line is arranged on the same layer as the first scanning line and the second scanning line, the second power line is connected to the auxiliary power line through a via, and a double-layer routing is formed between the gate electrode of the first transistor and the gate electrode of the third transistor; The compensation connection line is arranged on the same layer as the first electrode plate, and the compensation connection line is connected to the compensation line through a via.

4. The display substrate according to claim 3, wherein, The driving structure layer includes: a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer, a second metal layer, a third insulating layer, a third metal layer, a fourth insulating layer, and a planarization layer, which are sequentially stacked; The first metal layer includes a first electrode plate and a compensation connection line. The metal oxide layer includes a second electrode plate and the active layers of all transistors. The second metal layer includes a first scan line, a second scan line, a power supply connection line, an auxiliary power supply line, and the gate electrodes of all transistors. The third metal layer includes: a first power supply line, a second power supply line, a compensation line, a data line, a third electrode plate, and the source-drain electrodes of all transistors; The planarization layer is provided with a via exposing the second electrode of the second transistor; The orthographic projection of the first electrode plate on the substrate overlaps with the orthographic projection of the second electrode plate on the substrate to form a first storage capacitor. The orthographic projection of the third electrode plate on the substrate overlaps with the orthographic projection of the second electrode plate on the substrate to form a second storage capacitor. The third electrode plate is connected to the first electrode plate through a via.

5. The display substrate according to claim 4, wherein, The orthographic projection of the first electrode plate on the substrate covers the active layers of all transistors and the orthographic projection of the second electrode plate on the substrate; The length of the first electrode plate in the second direction is greater than the distance between the gate electrode of the first transistor and the gate electrode of the third transistor.

6. The display substrate according to claim 5, wherein, The first transistor and the second transistor are located on one side of the second electrode plate close to the first scan line, and the third transistor is located on one side of the second electrode plate close to the second scan line.

7. The display substrate according to claim 6, wherein, The second electrode plates in the second driving structure and the third driving structure are provided with openings; The opening of the second electrode plate in the second driving structure is provided on the side of the second driving structure close to the third driving structure, and the opening of the second electrode plate in the third driving structure is provided on the side of the third driving structure close to the second driving structure; The planarization layer vias in the first driving structure and the fourth driving structure are located between the third transistor and the second electrode plate; The planarization layer vias in the first driving structure and the planarization layer vias in the fourth driving structure are mirror-symmetrical with respect to the compensation line; The planarization layer vias in the second driving structure are located within the opening of the second electrode plate in the second driving structure, and the planarization layer vias in the third driving structure are located within the opening of the second electrode plate in the third driving structure; The planarization layer vias in the second driving structure and the planarization layer vias in the third driving structure are mirror-symmetrical with respect to the compensation line; The arrangement direction of the planarization layer vias in the first driving structure and the planarization layer vias in the second driving structure forms an angle greater than 0 degrees and less than 90 degrees with the first direction.

8. The display substrate according to claim 7, wherein, The first electrode of the first light-emitting structure is connected to the first driving structure through a via hole in the planarization layer of the first driving structure. The first electrode of the second light-emitting structure is connected to the fourth driving structure through a via hole in the planarization layer of the fourth driving structure. The first electrode of the third light-emitting structure is connected to the second driving structure through a via hole in the planarization layer of the second driving structure. The first electrode of the fourth light-emitting structure is connected to the third driving structure through a via hole in the planarization layer of the third driving structure; The opening regions of the pixel definition layer of the first light-emitting structure and the opening regions of the pixel definition layer of the third light-emitting structure are located between the first power line and the compensation line, and there is an overlapping region between their orthographic projections on the substrate and the orthographic projections of the first driving structure and the second driving structure on the substrate; The opening regions of the pixel definition layer of the second light-emitting structure and the opening regions of the pixel definition layer of the fourth light-emitting structure are located between the compensation line and the second power line, and there is an overlapping region between their orthographic projections on the substrate and the orthographic projections of the third driving structure and the fourth driving structure on the substrate.

9. The display substrate according to claim 8, wherein, The orthographic projection of the via hole in the planarization layer of the first driving structure on the substrate does not overlap with the orthographic projection of the opening region of the pixel definition layer in the first light-emitting structure on the substrate; The orthographic projection of the via hole in the planarization layer of the second driving structure on the substrate does not overlap with the orthographic projection of the opening region of the pixel definition layer in the third light-emitting structure on the substrate; The orthographic projection of the via hole in the planarization layer of the third driving structure on the substrate does not overlap with the orthographic projection of the opening region of the pixel definition layer in the fourth light-emitting structure on the substrate; The orthographic projection of the via hole in the planarization layer of the fourth driving structure on the substrate does not overlap with the orthographic projection of the opening region of the pixel definition layer in the second light-emitting structure on the substrate.

10. The display substrate according to claim 9, wherein, The spacer region includes a first spacer region, a second spacer region, and a third spacer region; The first spacer region is located between the opening region of the pixel definition layer of the first light-emitting structure and the opening region of the pixel definition layer of the third light-emitting structure; the second spacer region is located between the opening region of the pixel definition layer of the second light-emitting structure and the opening region of the pixel definition layer of the fourth light-emitting structure; the first spacer region and the second spacer region are arranged along a first direction; The first spacer region and the second spacer region are respectively located on both sides of the third spacer region, and the orthographic projection of the third spacer region on the substrate coincides with the orthographic projection of the compensation line located between the first scan line and the second scan line on the substrate; The third spacer region includes a first sub-spacer region, a second sub-spacer region, and a third sub-spacer region that are arranged in sequence along a second direction and are connected end to end; the second sub-spacer region is located between the first sub-spacer region and the third sub-spacer region; The first sub-spacing region is located between the opening region of the pixel defining layer of the first light-emitting structure and the opening region of the pixel defining layer of the second light-emitting structure; the third sub-spacing region is located between the opening region of the pixel defining layer of the third light-emitting structure and the opening region of the pixel defining layer of the fourth light-emitting structure; The second sub-spacing region is located between the first spacing region and the second spacing region, and is arranged along a first direction with the first spacing region and the second spacing region.

11. The display substrate according to claim 10, wherein, When the filter is located on the first light-emitting structure, the orthographic projection of the filter on the substrate covers the opening region of the pixel defining layer of the first light-emitting structure, the first sub-spacing region, the orthographic projection of the second sub-spacing region on the substrate, and there is an overlapping region with the orthographic projection of a part of the second scan line and a part of the second power line located in the display region on the substrate; When the filter is located on the second light-emitting structure, the orthographic projection of the filter on the substrate covers the opening region of the pixel defining layer of the second light-emitting structure, the second spacing region, the first sub-spacing region, the orthographic projection of the second sub-spacing region on the substrate, and there is an overlapping region with the orthographic projection of a part of the second scan line and a part of the first power line located in the display region on the substrate; When the filter is located on the third light-emitting structure, the orthographic projection of the filter on the substrate covers the orthographic projection of the opening region of the pixel defining layer of the third light-emitting structure on the substrate, and there is an overlapping region with the orthographic projection of a part of the first spacing region, a part of the third sub-spacing region, a part of the first scan line and a part of the second power line located in the display region on the substrate; When the filter is located on the fourth light-emitting structure, the orthographic projection of the filter on the substrate covers the orthographic projection of the opening region of the pixel defining layer of the fourth light-emitting structure on the substrate, and there is an overlapping region with the orthographic projection of a part of the second spacing region, a part of the third sub-spacing region, a part of the first scan line and a part of the first power line located in the display region on the substrate.

12. The display substrate according to claim 11, wherein, The orthographic projection of the color filter layer on the substrate does not overlap with the orthographic projection of the flat layer vias in the driving structure layer on the substrate.

13. The display substrate according to claim 12, wherein, The display substrate further includes: a shielding layer; The orthographic projection of the shielding layer on the substrate has an overlapping region with the orthographic projection of the first scan line located in the transparent region and the second scan line located in the transparent region and a part of the display region on the substrate.

14. The display substrate according to claim 13, wherein The shielding layer includes: a first shielding layer and a second shielding layer; the second shielding layer is located on the side of the first shielding layer close to the substrate; The first shielding layer is provided on the same layer as one of the color filters among the plurality of color filters, and the second shielding layer is provided on the same layer as the other color filter among the plurality of color filters.

15. A method for manufacturing a display substrate for manufacturing the display substrate according to any one of claims 1 to 14, the method comprising: Providing a substrate; Forming a display unit including a display region and a transparent region on the substrate to form a display substrate; The display unit includes: a driving structure layer, a light-emitting structure layer, and a color filter layer that are located in the display area and sequentially disposed on the substrate; the light-emitting structure layer includes: a plurality of light-emitting structures; each light-emitting structure includes: a pixel definition layer, a first electrode, an organic light-emitting layer, and a second electrode; the organic light-emitting layer is located within the opening area of the pixel definition layer and on the pixel definition layer; the display substrate includes: a spacer area located in the display area, the spacer area being located between the opening areas of the pixel definition layers of adjacent light-emitting structures and having an overlapping area with the positive projection of the pixel defining layer on the substrate; the color filter layer includes: a plurality of color filters; the positive projections of adjacent color filters on the substrate have an overlapping area; the overlapping area of adjacent color filters on the substrate has an overlapping area with the positive projection of the spacer area on the substrate.

16. The preparation method according to claim 15, wherein, The formation of the display unit including a display area and a transparent area on the substrate includes: Forming a first metal layer including a first electrode plate on the substrate in the display area; Forming a first insulating layer covering the first metal layer in the display area and the transparent area; Forming a metal oxide layer including a second electrode plate on the first insulating layer in the display area, the positive projection of the second electrode plate on the substrate having an overlapping area with the positive projection of the first electrode plate on the substrate to form a first storage capacitor; Sequentially forming a second insulating layer and a second metal layer in the display area; the second metal layer includes: a first scanning line and a second scanning line; Forming a third insulating layer covering the second metal layer in the display area and the transparent area; Forming a third metal layer in the display area on the third insulating layer, the third metal layer including a first power line, a second power line, a compensation line, a data line, and a third electrode plate, the positive projection of the third electrode plate on the substrate having an overlapping area with the positive projection of the second electrode plate on the substrate to form a second storage capacitor, and the third electrode plate being connected to the first electrode plate through a via; Forming a fourth insulating layer and a planarization layer covering the third metal layer in the display area and the transparent area; Forming a first electrode on the planarization layer; Sequentially forming a pixel definition layer, an organic light-emitting layer, and a cathode; Forming a packaging layer; Forming a color filter layer on the packaging layer.

17. The method according to claim 16, wherein, The formation of the color filter layer on the packaging layer includes: Forming a color filter layer and a shielding layer on the packaging layer; The positive projection of the shielding layer on the substrate has an overlapping area with the positive projection of the first scanning line located in the transparent area and the positive projection of the second scanning line located in the transparent area and a partial display area on the substrate.

18. A display device includes the display substrate according to any one of claims 1 to 14.

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