Physical layer device with sleep mode and partial network support and related systems, methods and devices

Abstract

The present invention describes an architecture for a physical layer device that can be used with a single pair Ethernet in a multi-point bus topology that can operate in sleep mode and control other devices in a network segment to operate in sleep mode. Some embodiments of the physical layer device can support partial networking in multi-point networks and hybrid networks including them.

Description

[0001] Priority declaration

[0002] This application claims the benefit of the priority date of U.S. Provisional Patent Application No. 62 / 861,226, filed on June 13, 2019, entitled “Physical Layer Device with Sleep Mode and Partial Network Support and Related Systems, Methods, and Devices,” the disclosure of which and its contents are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments described herein generally relate to network segments for single-pair Ethernet networks, and more particularly to network segments configured as multipoint network segments. Some embodiments relate to physical layer devices with sleep mode and partial network networking support. Some embodiments relate to sites of network segments coupled to a network. Background Art

[0004] Interconnects are widely used to facilitate communications between network devices. Generally speaking, electrical signals are transmitted over a physical medium (eg, a bus, coaxial cable, differential pair, twisted pair, or other conductor pair, sometimes simply referred to as a "wire") by a device coupled to the physical medium.

[0005] According to the Open Systems Interconnection model (OSI model), Ethernet-based computer networking technology uses baseband transmission (i.e., electrical signals are discrete electrical pulses) to transmit data packets and ultimately transmit messages transmitted between network devices. According to the OSI model, specialized circuits known as physical layer (PHY) devices or controllers are used to interact between the analog domain of the line and the digital domain of the data link layer (or just "link layer") that operates according to packet signaling. Although the data link layer may include one or more sublayers, in Ethernet-based computer networks, the data link layer typically includes at least a media access control (MAC) layer that provides a control abstraction for the physical layer. By way of example, when transmitting data to another device on the network, the MAC controller can prepare frames for the physical medium, add error correction elements, and implement collision avoidance. In addition, when receiving data from another device, the MAC controller can ensure the integrity of the received data and prepare frames for higher layers.

[0006] A typical point-to-point bus topology may implement a line between each device (e.g., dedicated point-to-point) or a line between a device and a switch (e.g., point-to-point without limitation to switching). In a multi-point topology, the physical medium is a shared bus, and each network device is coupled to the shared bus, for example, via a circuit selected based on the physical medium type (e.g., coaxial, twisted pair, differential pair, or other conductor pair, but not limited thereto).

[0007] Point-to-point bus topologies (such as dedicated point-to-point topologies or switched point-to-point topologies) require more wires and more expensive materials than multi-point topologies, in part because of the greater number of links between devices. In some applications (such as automotive and industrial), there may be physical constraints that make it difficult to connect devices directly, so topologies that do not require or need as many direct connections in a network or sub-network (e.g., not limited to multi-point bus topologies) may be less susceptible to such constraints.

[0008] Devices on a baseband network (e.g., not limited to multi-drop networks) share the same physical transmission medium and typically use the entire bandwidth of that medium for transmission (in other words, the digital signals used for baseband transmissions occupy the entire bandwidth of the medium). Thus, only one device on a baseband network can transmit at a given moment. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] While the present disclosure concludes with claims that particularly point out and distinctly claim specific embodiments, the various features and advantages of embodiments within the scope of the present disclosure may be more readily ascertained from the following description when read in conjunction with the accompanying drawings, in which:

[0010] Figure 1 A site according to one or more embodiments is shown.

[0011] Figure 2 A first use case of a network according to one or more embodiments is shown.

[0012] Figure 3 A second use case of a network is shown in accordance with one or more embodiments.

[0013] Figure 4 A third use case of a network is illustrated in accordance with one or more embodiments.

[0014] Figure 5 A network with daisy-chained power slave devices is shown according to one or more embodiments.

[0015] Figure 6 A hybrid daisy-chain network is shown according to one or more embodiments.

[0016] Figure 7 A timing diagram is shown of a first contemplated operation according to one or more embodiments.

[0017] Figure 8 A timing diagram illustrating a second contemplated operation according to one or more embodiments is shown.

[0018] Fig. 9 A swim lane diagram illustrating a wakeup transition process according to one or more embodiments.

[0019] Fig.10 A swim lane diagram illustrating a sleep transition process according to one or more embodiments. DETAILED DESCRIPTION

[0020] In the following detailed description, reference is made to the accompanying drawings which form a part of the present disclosure, and in the accompanying drawings are shown by way of example specific examples of embodiments in which the present disclosure may be implemented. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the present disclosure. However, other embodiments may be utilized, and changes in structure, material, and process may be made without departing from the scope of the present disclosure.

[0021] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations for describing embodiments of the present disclosure. The drawings presented herein are not necessarily drawn to scale. For the convenience of the reader, similar structures or components in the various drawings may retain the same or similar numbering; however, the similarity of numbering does not mean that the structures or components must be identical in size, composition, configuration, or any other attribute.

[0022] It should be readily understood that the components of the embodiments as generally described herein and shown in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following description of some embodiments is not intended to limit the scope of the present disclosure, but is merely representative of some embodiments. Although various aspects of the embodiments may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0023] In addition, the specific embodiments shown and described are examples only and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Elements, circuits, and functions can be shown in block diagram form so as not to obscure the present disclosure with unnecessary details. On the contrary, the specific embodiments shown and described are exemplary only and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. In addition, the partitioning of logic between block definitions and individual blocks is an example of a specific embodiment. It will be apparent to those of ordinary skill in the art that the present disclosure can be practiced through many other partitioning solutions. In most cases, details about timing considerations, etc. have been omitted, where such details are not required to obtain a complete understanding of the present disclosure and are within the capabilities of those of ordinary skill in the relevant art.

[0024] Those of ordinary skill in the art will appreciate that any of a variety of different technologies and techniques may be used to represent information and signals. For clarity of presentation and description, some figures may show signals as a single signal. Those of ordinary skill in the art will appreciate that a signal may represent a signal bus, where the bus may have a variety of bit widths, and that the present disclosure may be implemented on any number of data signals, including a single data signal.

[0025] The various exemplary logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or implemented with a general purpose processor, a special purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to implement the functions described herein. A general purpose processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration. A general purpose computer including a processor is considered a special purpose computer when the general purpose computer is configured to execute computing instructions (e.g., software code) associated with the embodiments disclosed herein.

[0026] Embodiments can be described according to processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although flow charts can describe operational actions as sequential processes, many of these actions can be performed in another sequence, in parallel, or substantially simultaneously. In addition, the order of actions can be rearranged. Processes can correspond to methods, threads, functions, programs, subroutines, subprograms, etc. In addition, the methods disclosed herein can be implemented in hardware, software, or both. If implemented in software, these functions can be stored or transmitted to a computer-readable medium as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, and the communication media include any media that is conducive to transferring a computer program from one location to another.

[0027] Unless such limitations are explicitly stated, any reference to elements herein using names such as "first," "second," etc. does not limit the number or order of those elements. Instead, these names may be used herein as a convenient method of distinguishing between two or more elements or instances of elements. Thus, reference to a first element and a second element does not mean that only two elements can be employed there, or that the first element must precede the second element in some manner. Furthermore, unless otherwise indicated, a group of elements may include one or more elements.

[0028] As used herein, the term "substantially" in reference to a given parameter, attribute, or condition refers to and includes the degree to which a person of ordinary skill in the art would understand that the given parameter, attribute, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances. By way of example, depending on the specific parameter, attribute, or condition that is substantially satisfied, the parameter, attribute, or condition may be satisfied by at least 90%, at least 95%, or even at least 99%.

[0029] Vehicles, such as automobiles, trucks, buses, ships, and / or aircraft, may include a vehicle communication network. The complexity of a vehicle communication network may vary depending on the number of electronic devices and subsystems within the network. For example, an advanced vehicle communication network may include various control modules for, for example, engine control, transmission control, safety control (e.g., anti-lock brakes), and emission control. As another non-limiting example, an advanced vehicle communication network may include modules for supporting, but not limited to, audio and other information and entertainment systems, onboard charging, external cameras, connections for external devices (e.g., universal serial bus connections), and door control (e.g., locks, windows, side view mirrors), and vehicle diagnostics. Similar considerations arise in industrial control, building operating systems, building management systems, residential utility systems, connected lighting systems, and more generally, but not limited to, communication networks in control and sensor networks.

[0030] To support these modules, the automotive industry relies on various communication protocols. 10SPE (i.e., 10Mbps Single Pair Ethernet) was developed by the Institute of Electrical and Electronics Engineers (IEEE) as IEEE Std 802.3cg TM -2020 network technology specification developed. 10SPE can be used to provide collision-free, bounded-delay transmissions (e.g., an upper limit on how long a packet will be delayed before transmission, but not limited to this) on a multi-point bus of a network. Although the current 10SPE draft specification provides PHY requirements for normal operation, there are no requirements for lower power modes or sleep modes (low-power modes, power save modes, and sleep modes are collectively referred to as "sleep modes" in this article).

[0031] As used herein, "wake" and "waking" mean transitioning from a sleep mode to a wake mode.

[0032] Some embodiments generally relate to a PHY for a network segment for Ethernet communications, such as, but not limited to, a network segment of a multipoint network (including, but not limited to, a hybrid segment). In such embodiments, the PHY is configured to automatically and / or selectively enter and exit a sleep mode as described herein. More generally, a network segment including embodiments of such a PHY may also automatically and / or selectively enter and exit a sleep mode.

[0033] Figure 1 A block diagram of a station 100 is shown according to one or more embodiments. Figure 1 In the depicted embodiment, the site 100 includes a site controller 116 in communication with a network segment 146, which includes the physical layer device 102, the shared bus 134, and the devices and connections therebetween. More specifically, the site controller 116 communicates with the physical layer device 102 via a management interface 130 (e.g., a management data input / output (MDIO) interface (but not limited thereto)) and a data interface 132 (e.g., a media independent interface (MII) (but not limited thereto)). The site controller 116 also communicates with the shared bus 134 via the physical layer device 102, which can be understood to serve as an interface between the site controller 116 and the shared bus 134. Although not shown, Figure 1 The embodiment of the site 100 shown in FIG. 1 contemplates a site controller 116 that includes a media access controller (MAC) for communicating with the physical layer device 102 via a management interface 130 and a data interface 132. In other embodiments of the site 100, the MAC may be part of the same device as the physical layer device 102, a separate device from the physical layer device 102 or the site controller 116, and combinations thereof, but is not limited thereto.

[0034] As non-limiting examples, the site controller 116 may be implemented by one or more of a general purpose processor, a microprocessor, any conventional processor, a controller, a microcontroller, and a state machine configured to perform one or more of the functions or features of the site controller discussed herein. The site controllers of the disclosed embodiments (e.g., the site controller 116, but not limited thereto) should be understood to include sites for Ethernet networking, but not limited thereto, and may include other network node controllers.

[0035] In the context of the present disclosure, the shared bus 134 is optional and not necessarily part of the station 100, but is provided in Figure 1 1 is shown to facilitate description of the operation of station 100 and to illustrate network segment 146, which includes physical layer device 102 and shared bus 134. In some cases, a network segment may be understood to include a shared bus and all physical layer devices (e.g., physical layer device 102, but not limited thereto) operatively coupled thereto. In such cases, network segment 146 may be understood to be a network segment portion 146 of a network segment that includes other network segment portions 146.

[0036] Not all sites 100 of a network segment 146 may be necessary in the context of operation of a particular application. If one or more sites 100 of a network segment 146 are not necessary for a portion of time, it may be desirable to power down one or more of those sites 100 to save system power consumption. In an automotive environment, disabling rear object sensing systems when not backing up, and disabling driver parking assistance features when traveling on a highway, are non-limiting examples of such desirable power downs to save system power consumption. In one or more embodiments, the site controller 116 may be configured to control equipment of nodes associated with the network segment 146, including but not limited to controlling power consumption in the aforementioned embodiments and other applications.

[0037] The physical layer device 102 is configured for at least two power domains, a main power domain 104 and an uninterruptible power domain 108. The core operation of the physical layer device 102 (eg, to and from the shared bus 134 (eg, via Figure 1 The core logic 106 (transmit / receive circuits represented as Tx / Rx 142 in the figure) and one or more of sending and receiving data to and from the site controller 116, conflict avoidance, and traffic shaping) is part of the main power domain 104. The power management logic 110, the sensing circuit 114, and the energy detection circuit 112 are part of the uninterruptible power domain 108. It is worth noting that the main power domain 104 and the uninterruptible power domain 108 may include Figure 1 Additional circuitry beyond that shown in .

[0038] The main power domain 104 (and the components as part thereof) is powered by the main power supply 124 from the power supply 120. It is worth noting that the power supply from the main power supply 124 to the main power domain 104 is interruptible. Figure 1 In the illustrated embodiment, the switch 118 is located in the path of the main power supply 124 to the main power domain 104 of the physical layer device 102. Specifically, the switch 118 is located between the power supply 120 and the main power domain 104, in the path of the main power supply 124.

[0039] The site controller 116 also supplies power to the main power supply 124 through the power supply 120 and the switch 118. The site controller 116, the elements of the main power domain 104 of the physical layer device 102, and Figure 1 Other devices, chips, cards and equipment not shown in the figure may be understood as part of the main power domain of the site 100. In the context of the site 100, enabling / disabling power to the main power domain 104 should be understood to more generally include enabling / disabling power to the main power domain of the site 100.

[0040] When one or more outputs of switch 118 are “off”, switch 118 does not provide a path for primary power 124 to be received at primary power domain 104 (and site controller 116 is not enabled at the time of switching). Figure 1 118). When one or more outputs of the switch 118 are "on", the switch 118 provides a path for receiving the main power 124 at the main power domain 104 and / or the controller 116. When the switch 118 is off, the management interface 130 and the data interface 132 between the site controller 116 and the physical layer device 102 are inactive. In some embodiments, portions of the site controller 116 can be powered when one or more outputs of the switch 118 are off through one or more other power paths (not shown).

[0041] In the disclosed embodiment, the switch 118 may be any suitable switching technology known to one of ordinary skill in the art for interrupting the flow of current. As non-limiting examples, the switch 118 may be an analog switch, a digital switch, and combinations thereof, without limitation. Figure 1 In the illustrated embodiment, the switch 118 is controlled (i.e., opened and / or closed) in response to an enable signal 126 provided by the power management logic 110, as described more fully below. In this manner, the power management logic 110 can enable and / or disable the supply of power to the main power domain 104 (the main power domain 104 may also be characterized as an "interruptible power domain").

[0042] The uninterruptible power supply domain 108 and the components as a part thereof are powered by the uninterruptible power supply 122 from the power supply 120. In other words, the path of the uninterruptible power supply 122 from the power supply 120 to the uninterruptible power supply domain 108 is uninterruptible. As a non-limiting example, when the switch 118 is closed, the uninterruptible power supply 122 is still powered to the uninterruptible power supply domain 108. Therefore, in the physical layer device 102, the uninterruptible power supply domain 108 can be powered, while the main power supply domain 104 is not powered (or insufficiently powered).

[0043] It is worth noting that the uninterruptible power supply 122 and the main power supply 124 can operate at the same (ie, substantially the same) or different voltage levels. Figure 1 Not shown, but in some embodiments, voltage regulators, protection circuits, and other electrical components may be added to the path of the main power supply 124 and / or the uninterruptible power supply 122 to, as a non-limiting example, protect the site 100 from unreliable power sources or to provide power to inputs to the site controller 116 and / or physical layer device 102 where the inputs operate at different voltages.

[0044] Power source 120 can be or be powered by any suitable regulated or unregulated power source and combinations thereof. As non-limiting examples, power source 120 can be a generator, a battery, or power provided by a utility (e.g., to a residential or commercial building, but not limited thereto).

[0045] exist Figure 1 , power supply 120 is shown as supplying power to main power domain 104 and uninterruptible power domain 108, however, a common power supply is not required. In some embodiments, main power domain 104 and uninterruptible power domain 108 may be powered by different power supplies and / or power sources. As a non-limiting example, main power domain 104 may be powered by a generator, and uninterruptible power domain 108 may be powered by a battery; and optionally, the battery supplying uninterruptible power domain 108 may store power received from the same generator supplying main power domain 104 or from a different generator.

[0046] The power management logic 110 is generally configured to control the supply of the main power supply 124 to the main power domain 104 and the site controller 116, and more specifically, to open and close the switch 118 by asserting / deasserting the enable signal 126. In the expected operation consistent with the "positive logic component" convention, the deactivated enable signal 126 closes the switch 118 and the main power supply 124 is not provided to the device, including but not limited to the site controller 116 and / or the main power domain 104; and the asserted enable signal 126 opens the switch 118 and the main power supply 124 is provided to the device, including but not limited to the site controller 116 and / or the main power domain 104. Other conventions may be used, including but not limited to the "negative logic component" convention. The power management logic 110 may be configured to deactivate the enable signal 126 to the switch 118 in response to inactivity detected at the shared bus 134 and / or in response to a wake-up signal 128 indicated as a failure of the power management logic 110 by the energy detection circuit 112 and the sensing circuit 114, respectively. Furthermore, the power management logic 110 may be configured to assert an enable signal 126 to the switch 118 in response to bus activity 136 detected at the shared bus 134 or detection of an asserted wake-up signal 128 .

[0047] Additionally or alternatively, the power management logic component 110 may be configured to respond to instructions from the core logic component 106, such as Figure 1 100 to deactivate enable signal 126 in response to sleepctrl signal 140 from core logic 106 to power management logic 110. As a non-limiting example, core logic 106 may be configured to set a power control bit (not separately shown) of a control register of power management logic 110, and power management logic 110 may be configured to deactivate enable signal 126 in response to the power control bit being set at such control register.

[0048] In another embodiment, the energy detection circuit 112 may generally be configured to measure the energy level of the bus activity 136 and provide a value indicative of the measured energy level to the power management logic 110. In some embodiments, the energy detection circuit 112 may be configured to provide a value to the power management logic 110 that may be accumulated over a period of time, and the length of the period of time may be associated with a valid signal to distinguish between intentional activity at the shared bus and noise at the shared bus.

[0049] The power management logic component 110 can be configured to deactivate the enable signal 126 in response to a value received from the energy detection circuit 112 being below a specified inactivity threshold, and can be configured to assert the enable signal 126 in response to a value received from the energy detection circuit 112 being above a specified activity threshold. Additionally or alternatively, the power management logic component 110 can be configured to deactivate the enable signal 126 in response to a value received from the energy detection circuit 112 being below a specified inactivity threshold.

[0050] In one or more embodiments, the thresholds for determining activity and / or inactivity may be specified based on energy levels associated with Ethernet signals. More specifically, in one or more embodiments, the inactivity threshold may be specified as one or more energy levels below or above energy levels associated with Ethernet signals or other valid communication signals (in other words, outside a range of energy levels associated with Ethernet signals), and the activity threshold may be specified as one or more energy levels within a range of energy levels associated with Ethernet signals or other valid communication signals (e.g., equal to, but not limited to, energy levels used to transmit Ethernet frames on a network).

[0051] As discussed herein, multiple stations and / or network segments can be placed into a sleep mode by forcing the network (e.g., forcing the transmission medium, but not limited to such) to be inactive and / or by providing a signal above a threshold for transmitting data on the network (e.g., greater than a threshold for transmitting Ethernet frames).

[0052] In the disclosed embodiment, the energy detection circuit 112 may be configured to perform energy detection using any suitable technique known to those of ordinary skill in the art for detecting whether the shared bus 134 is active or inactive.

[0053] In some embodiments, the site controller 116 may be configured to perform a power-on reset or other reset operation of the site 100 if the main power 124 is interrupted and subsequently restored (i.e., powered) to the site controller 116. For example, if the site 100 is not operating properly, e.g., not communicating on the shared bus 134 for a predetermined period of time, or not sending data or beacons when expected, a master device (not shown) detecting such abnormal behavior may assert a sleep signal (not shown) at the physical layer device 102 to power down the site controller 116, and then assert a wake-up signal 128 to power up, thereby executing its (i.e., the site controller 116) power-on reset routine, which may result in correcting the abnormal behavior of the site 100.

[0054] In some embodiments, the physical layer device 102 may be configured to selectively propagate one or more of the wake-up signals 128 to outputs of the physical layer device 102. In one embodiment, the physical layer device 102 may include one or more outputs for operably coupling (e.g., via a link) to one or more inputs of another physical layer device, wherein the inputs of the other physical layer device are for wake-up signals or sleep signals (sleep signals not shown). In one embodiment, the power management logic component 110 may be configured to assert the wake-up signal 138, including but not limited to in response to assertion of the enable signal 126. As a non-limiting example, the power management logic component 110 may be configured to assert the wake-up signal 138 in response to being configured for daisy-chain operation as described herein. Notably, the present disclosure specifically encompasses embodiments of the physical layer device 102 configured for daisy-chain operation and embodiments of the physical layer device 102 not configured for daisy-chain operation.

[0055] From the perspective of a device configured as physical layer device 102 (e.g., a microcontroller or embedded system (but not limited to such)), wake-up signal 128 can be characterized as a wake-up input signal (e.g., a signal seen at an input of the device, which is associated with wake-up signal 128), and wake-up signal 138 can be characterized as a wake-up output signal (e.g., a signal seen at an output of the device, which is associated with wake-up signal 138).

[0056] Those skilled in the art will appreciate the many benefits, advantages, and use cases of a physical layer device for a multipoint network having two ways to exit sleep mode and two ways to enter sleep mode. As non-limiting examples, design considerations and application constraints may require a physical layer device having one way to enter sleep mode and two ways to be awakened, two ways to enter sleep mode and one way to be awakened, and one way to enter sleep mode and one way to be awakened, and the present disclosure specifically contemplates such embodiments.

[0057] Figure 2 , Figure 3 and Figure 4 A block diagram of a network 200 configured as a multi-point network according to one or more embodiments is shown. As described below, Figure 2 and Figure 3 The embodiment of the network 200 depicted in FIG. 1 is generally configured for partial networking and more generally illustrates a method for Figure 1 Use case of physical layer device 102, network segment 146 and site 100.

[0058] The network 200 may include a power master 202, a power slave 204, a power slave 206, and a power slave 208, which communicate via one or more buses and wired connections, including but not limited to a shared bus 212 (e.g., configured as a multi-drop bus) and wired connections 214, 216, and 218. Each of the power slaves 204, 206, and 208 is configured as a site 100. In some embodiments, the power master 202 may be or be configured as a site 100, a networking switch, or a dedicated power control device for a multi-drop network or a hybrid segment of a network, without limitation. The power master 202 may generally be configured to perform one or more operations to implement partial networking as discussed herein.

[0059] The network 200, and more specifically, the power slave devices 204, 206, and 208 can be configured to enter / exit sleep mode in response to a power control signal 210 provided by the power master device 202 to power the power slave devices 204, 206, and 208 via the shared bus 212 or the wired connections 214, 216, and 218. Additionally or alternatively, the network 200 and the power slave devices 204, 206, and 208 can be configured to enter / exit sleep mode in response to the activity level of the shared bus 212, including in response to the power control signal 210 asserted by the power master device 202 at the shared bus 212 and / or data frames transmitted by various networked devices. In some embodiments, the power control signal 210 may include a wake-up signal (e.g., Figure 3 In some embodiments, the power control signal 210 may include a signal asserted by the power master 202 to indicate valid bus activity (e.g., a signal exhibiting an energy level associated with a communication message transmitted over the network 200 (such as, but not limited to, an Ethernet data frame) or invalid bus activity at the shared bus 212 (e.g., a signal exhibiting an energy level different from an energy level associated with a communication message transmitted over the network 200 (such as, but not limited to, an Ethernet frame)).

[0060] In the intended operation of the network 200, the power master device 202 provides a power control signal 210 to the power slave devices 204, 206, and 208. In response to the power control signal 210, a corresponding node controller (e.g., Figure 1 The node controller 116 of the embodiment may instruct the corresponding power management logic component (e.g., Figure 1 The power management logic component 110) provides power or interrupts power, as the case may be, causing such nodes to enter a sleep mode or enter a wake-up mode.

[0061] In some embodiments, the power control signal 210 may include a digital signal including a high voltage and a low voltage representing logical values ​​of 1 and 0, respectively.

[0062] In another envisioned operation, one or more of the power supply slave devices 204, 206, and 208 may enter a sleep mode in response to detecting that the shared bus 212 is inactive (e.g., bus activity 136 is below or above a threshold associated with valid bus activity, but not limited thereto). In some cases, the power supply master device 202 may control the signal level at the shared bus 212 so that the signal level does not correspond to valid bus activity. In other cases, there may be no activity at the shared bus 212 due to a specific operation combined with a specific application of the network 200. Similarly, one or more of the power supply slave devices 204, 206, and 208 may enter a wake-up mode in response to detecting valid bus activity at the shared bus 212 (e.g., bus activity 136 associated with valid activity, such as a specified threshold or Ethernet signal, but not limited thereto). In some cases, the power supply master device 202 may control the signal level at the shared bus 212 so that the signal level corresponds to valid bus activity. In other cases, there may be significant bus activity at the shared bus 212 due to the transmission of data frames across the bus, as a non-limiting example.

[0063] Figure 3 An example use case of a network 200 is shown in accordance with one or more embodiments. Figure 3 In the contemplated operation, power slave device 204 , power slave device 206 , and power slave device 208 have been placed in sleep mode by power master device 202 , or enter sleep mode in response to detecting an inactive shared bus 212 .

[0064] The power master device 202 provides a wake-up signal 220 to the power slave device 204 to wake up the power slave device 204. In some embodiments, the wake-up signal 220 can be transmitted from the power master device 202 to the power slave device 204 via a communication path, the communication path including one or more of the shared bus 212 and the wired connection 214, as non-limiting examples. As a non-limiting example, the wired connection 214 can be a control bus (e.g., wiring, a controller area network (CAN) bus, or a local interconnect network (LIN) bus, but not limited thereto) that is physically separated from the shared bus 212 and / or a combination thereof.

[0065] In response to the wake-up signal 220, the power supply device 204 exits the sleep mode (eg, Figure 3 ), while power slave device 206 and power slave device 208 remain in sleep mode (as shown by the solid black outline in FIG. Figure 3 6 and 6. In the figure, power supply slave device 206 and power supply slave device 208 are shown by dashed outlines).

[0066] Figure 4 An example use case of a network 200 is shown in accordance with one or more embodiments. Figure 4 In the envisioned operation, power slave device 204, power slave device 206, and power slave device 208 begin in an operational power mode (i.e., not in a sleep mode, also referred to herein as a "wake-up" mode). Power master device 202 asserts sleep signal 222 at power slave device 204 to instruct power slave device 204 to enter sleep mode.

[0067] In some embodiments, the sleep signal 222 can be an analog signal received at the PHY device of the power slave device 204, or a digital signal that carries a command to the node controller of the power slave device 204 to instruct the PHY device to put the power slave device 204 into sleep mode. The sleep signal 222 can be provided on a control bus that is physically separate from the shared bus 212 (e.g., wiring, a controller area network (CAN) bus, or a local interconnect network (LIN) bus, but not limited thereto), and / or a combination thereof. Back Figure 1 , the sleep indication in the sleep signal 222 may correspond to one of the two logic levels of the digital signal (e.g., corresponding to a logic '0' or a logic '1'). In addition, the wake-up indication in the wake-up signal 128 and / or the wake-up signal 138 may correspond to the other of the two logic levels of the digital signal. In the case of analog communication through a direct connection from the power master device 202 to the power slave device 204, the wake-up signal may correspond to a high signal (e.g., 3 volts, but not limited thereto), and the sleep signal 222 may correspond to a low signal.

[0068] In some embodiments, a sleep signal may be provided by the network 200 as a higher level protocol command received by a node controller of the power slave device 204, and the site controller 116 of the power slave device 204 may instruct the power management logic component 110 to place the power slave device 204 into sleep mode by enabling the sleep signal 222 (e.g., by setting a sleep bit of a power management control register, not shown, but not limited to this).

[0069] In response to the sleep signal 222, the power supply device 204 enters a sleep mode (eg, Figure 4 ), and the power supply slave device 206 and the power supply slave device 208 remain in the operating power mode (as shown by the dashed outline in FIG. Figure 4 ). It is worth noting that in the event that the power slave device 204 should remain in the sleep mode, the power master device 202 can continue to assert the sleep signal 222, otherwise activity on the shared bus 212 (e.g., between the power slave device 206 and the power slave device 208) may wake up the power slave device 204.

[0070] For reference Figure 3 and Figure 4 In the manner discussed, the power master device 202 can use the wake-up signal 220 to selectively cause a power slave device of the network 200 to exit the sleep mode while one or more other power slave devices of the network remain in the sleep mode, and can use the sleep signal 222 to selectively cause a power slave device to enter the sleep mode while one or more other power slave devices of the network are awakened. In other words, the network 200 is configured so that a portion of the network can be awakened while another portion of the network is asleep.

[0071] Figure 5 A block diagram of an embodiment of a network 500 is shown in which power slave devices operably coupled to a shared bus 510 are daisy-chained to each other according to one or more embodiments. More specifically, the output of the power slave device 504 is operably coupled (via connection 516) to the input of the power slave device 506 that monitors the wake-up signal, and the output of the power slave device 506 is operably coupled (via connection 518) to the input of the power slave device 508 that monitors the wake-up signal. The power master device 502 is operably connected to each of the power slave devices 504, 506, and 508 via corresponding connections 520, 522, and 524.

[0072] In some embodiments, the wake-up signal 514 (and Figure 1The wake-up signal 138) can be transmitted from the power supply slave device 504 to the power supply slave device 506 via the wired connection 516. As a non-limiting example, in the case of a car network, the wired connection 516 and the wired connection 518 from the power supply slave device 506 to the power supply slave device 508 can be wires in the car wiring harness.

[0073] In this embodiment, when a power manager of a physical layer device (e.g., power management logic 110 similar to physical layer device 102) wakes up the physical layer device and its associated nodes in response to detecting a wake-up signal asserted at an input, then in response to the wake-up, the power manager asserts a wake-up signal at its output coupled to the input of another power slave device in the daisy chain, and so on, until all power slave devices are awakened.

[0074] exist Figure 5 In the contemplated embodiment, power slave device 504, power slave device 506, and power slave device 508 are in sleep mode and are in a daisy-chain configuration as described above. Power master device 502 asserts wake-up signal 512 at power slave device 504. After waking up, power slave device 504 asserts wake-up signal 514 at power slave device 506 via wired connection 516. Although Figure 5 504, 506 and 508. Although not shown in the figure, after waking up, the power slave device 506 will assert a wake-up signal at the power slave device 508 via the wired connection 518. It should be generally understood that the connection between the power slave devices 504, 506 and 508 can be configured for unidirectional communication, as well as configured for bidirectional communication and capable of carrying wake-up signals from the power slave device 506 to the power slave device 504 and from the power slave device 508 to the power slave device 506, depending on the specific implementation.

[0075] In some embodiments, each wired connection 516, 518, and 526 can represent a connection for bidirectional communication between power slave devices 504, 506, and 508. In some embodiments, communications at network 500 can be configured to facilitate wakeup of power slave devices 504, 506, and 508 in any order.

[0076] In one embodiment, to facilitate configuring the wakeup sequence in a daisy-chain configuration, power slave devices 504, 506, and 508 may each include one or more outputs and inputs for operatively connecting to corresponding inputs or outputs of one or more other power slave devices via wired connections 516, 518, and 526. Each such connection may be enabled / disabled for wakeup signal communication according to embodiments described herein.

[0077] In another embodiment, to facilitate configuring the wake-up sequence in a daisy-chain configuration, power slave devices 504, 506, and 508 can each be operably coupled to a bus separate from shared bus 510 (e.g., network 500 can include a bus that includes or is connected to wired connections 516, 518, and 526—such a bus is separate from shared bus 510). Figure 5 ), and the bus supports addressing to enable / disable sending and receiving wake-up signals (e.g., wake-up signal 514, and more generally, wake-up signal 516) transmitted between power slave devices 504, 506, and 508 in any order. Figure 1 As a non-limiting example of configuring the wake-up sequence, each of the power slave devices 504, 506, and 508 can be pre-configured to send the wake-up signal 138 to the power slave device associated with a specific address. As another non-limiting example of configuring the wake-up sequence, the power master device 502 can include a message in the wake-up signal 512, and the message can include address and wake-up sequence information, and the power slave devices 504, 506, and / or 508 can use these addresses and wake-up sequence information to determine the wake-up signal and send the wake-up signal to the next power slave device defined in the wake-up sequence.

[0078] As a non-limiting example, a communication sequence to configure enable / disable according to one or more embodiments may be performed by power master 502, a higher level power master (not shown), or a system architect when deploying network 500.

[0079] In accordance with Figure 5 In the case of the network and network segment use case of the illustrated embodiment, the power master device 502 can wake up the power slave devices in a specific order. Figure 5 In one embodiment of the intended wake-up operation, the wake-up sequence is power slave 504, power slave 506, and power slave 508. In another intended operation, power master 502 may first assert a wake-up signal at power slave 506 via wired connection 522, assert a wake-up signal at power slave 508 via wired connection 518 upon wake-up, and assert a wake-up signal at power slave 504 (through wired connection 526) upon wake-up. A complete communication connection from power master 502 to power slave 506 and power slave 508 is shown to illustrate that in some embodiments, power master 502 may be configured to select a wake-up sequence of slaves 504, 506, and 508, the wake-up sequence starting from the wake-up signal to power slave 506 or 508, as non-limiting examples, based on application requirements of a multi-point or hybrid network, where a particular application may require or prefer a particular node reset sequence.

[0080] Figure 6An embodiment of hybrid network 600 is shown in which network 612 and network 614 are daisy-chained. Figure 6 In the illustrated embodiment, the power supply master 604 of the network 612 and the power supply master 602 of the network 614 include Figure 1 A physical layer device 102 is configured for a daisy chain implementation.

[0081] In intended operation, in accordance with the disclosed embodiments, in response to receiving a wake-up signal 608 (as a non-limiting example, from another network or a higher-level power master device), the power master device 604 of the network 612 wakes up the power slave devices of the network 612 by asserting the wake-up signal or setting an activity level on the shared bus.

[0082] The link 606 provides a communication path between the power master 604 and the power master 602 , and may include one or more of a bus and a wired connection between the power master 604 and the power master 602 .

[0083] The power master 604 asserts a wake-up signal 610 at the power master 602 using the link 606. According to the disclosed embodiment, in response to the wake-up signal 610 being asserted, the power master 602 wakes up the power slaves of the network 614 by asserting the wake-up signal or setting an activity level on the shared bus. If another network that is part of the daisy chain and the network 612 and the network 614 do not receive the wake-up signal, the power master 602 can assert the wake-up signal of the power master of the network, and so on.

[0084] Figure 7 A timing diagram 700 is shown for the expected operation of the site 100 (and more specifically, the network segment 146) according to one or more embodiments. The signals in the timing diagram 700 correspond to Figure 1 , specifically the uninterruptible power supply 122 , the main power supply 124 , the enable signal 126 , the wake-up signal 128 , the optional wake-up signal 138 , and the sleep control signal 140 .

[0085] exist Figure 7 Of the signals shown, the signal associated with an expected wake-up transition (i.e., associated with entering a wake-up mode) is shown. At time 702, the wake-up signal 128 is asserted at the input of the physical layer device 102. In response to detecting the valid wake-up signal 128, at time 704, the power management logic component 110 asserts the enable signal 126. As a non-limiting example, the enable signal 126 may be enabled by Figure 1The sensing circuit 114 detects the wake-up signal 128 and, in response, notifies the power management logic 110 of the valid wake-up signal 128. It is worth noting that the uninterruptible power supply 122 supplies power to the elements of the uninterruptible power domain 108, such as but not limited to the power management logic 110, the energy detection circuit 112, and the sensing circuit 114.

[0086] In some embodiments, the power management logic 110 component and / or the sensing circuit 114 can be configured to detect a valid wake-up signal (in response to detecting that the wake-up signal 128 remains asserted for a specified time period (or at least a specified time period) corresponding to a valid wake-up signal. Figure 7 , corresponding to the time of twip). By specifying a minimum time period for a valid wake-up signal, the network segment will not exit sleep mode in response to some transient signals detected at the input of the physical layer device. In some embodiments, there may be some delay when a valid wake-up signal 128 is detected and the enable signal 126 is asserted at time 704. Figure 7 The time period twin is shown in FIG.

[0087] In response to the assertion of the enable signal 126, at time 706, the main power supply 124 is turned on and supplies power to elements of the network segment, such as, but not limited to, the main power domain 104 of the physical layer device 102 and / or the site controller 116. In some embodiments, when the enable signal 126 is asserted at time 704, and when the main power supply 124 is turned on and supplies power, there may be a delay, Figure 7 The time period tivp is shown in FIG.

[0088] After the main power supply 124 is turned on, at time 708, the wake-up signal 138 is asserted by the core logic component 106 to generate a valid wake-up signal for the next network segment in the daisy chain. In some embodiments, when the main power supply 124 is turned on at time 706, and when the wake-up signal 138 is asserted at time 708, there may be a delay. Figure 7 The time period tvwo is shown in FIG.

[0089] As described above, in some embodiments, a valid wake-up signal may be detected in response to the wake-up signal being asserted for a time period that has been pre-designated to correspond to a valid wake-up signal. Thus, core logic component 106 may be configured to assert wake-up signal 138 for a time period that corresponds to a pre-designated time period used by the next network segment in the daisy chain to detect a valid wake-up signal.

[0090] Figure 7Also shown in FIG. 7 are signals associated with an expected sleep transition (i.e., associated with entering a sleep mode) according to one or more embodiments. At time 710, a control bit of a sleep control register is set for controlling entry / exit of a sleep mode. Figure 7 In the contemplated operation shown, in response to the wake-up signal 128 being deasserted for a pre-specified period of time twis (ie, a time-out condition), the sleep control signal 140 is asserted (ie, a control bit for the sleep control register is set).

[0091] As a non-limiting example, the timeout condition may be that the bus is inactive for a specified period of time, or that a valid wake-up signal is not detected within a specified period of time. In some embodiments, it may be desirable to prevent bus activity timeouts by one or more network segments of the network. The power master device may be configured to periodically cause a signal configured to indicate valid bus activity at the multi-point bus, and detectable as valid bus activity by various network segments in the network.

[0092] At time 712, the power management logic 110 deactivates the enable signal 126 in response to the sleep control signal 140 being asserted within the time period tsti. At time 714, the main power supply 124 is turned off. In some embodiments, there may be a delay when the enable signal 126 is deactivated and the main power supply 125 is turned off. Figure 7 The time period tivp is shown in FIG.

[0093] Notably, after the main power supply 124 is turned off at time 714 , the uninterruptible power supply 122 remains on and powers the elements of the uninterruptible power domain 108 .

[0094] Figure 8 A timing diagram 800 is shown for the expected operation of the network segment 100 according to one or more embodiments. The signals in the timing diagram 800 correspond to Figure 1 , specifically the uninterruptible power supply 122 , the main power supply 124 , the enable signal 126 , the bus activity 136 , the optional wake-up signal 138 , and the sleep control signal 140 . Figure 7 The discussion of the time periods twip, twin, tivp, tvwo, twop, tsti, and tivp applies to Figure 8 A similarly marked time period in .

[0095] exist Figure 8Among the signals shown are signals associated with a wake-up transition (i.e., entering a wake-up mode) according to one or more embodiments. At time 802, bus activity 136 is detected in response to a data frame (here, a pseudo-random binary sequence (PRBS) in a differential Manchester encoded (DME) frame) on the shared bus 134. In response to the bus activity 136, at time 804, the power management logic component 110 asserts the enable signal 126, and in response to the assertion of the enable signal 126, at time 806, the main power supply 124 is turned on and power is supplied to elements of the network segment, such as, but not limited to, the main power domain 104 of the physical layer device 102 and / or the site controller 116.

[0096] In one embodiment, the power management logic 110 and / or the energy detection circuit 112 may be configured to detect valid activity at the shared bus 134 in response to detecting that the bus activity 136 remains active for a specified period of time, and Figure 8 In the example, the specified time period is the time period twip. As a non-limiting example, the time period twip may correspond to the length of a data frame, the length of a control frame, or a time that is understood not to correspond to noise on the bus. By specifying a time period of active activity, the network segment will not exit sleep mode in response to some transient signal on the shared bus 134.

[0097] After the main power supply 124 is turned on at time 806, the wake-up signal 138 is asserted by the core logic component 106 at time 808 to generate a valid wake-up signal for the next network segment in the daisy chain, where the signal has a time period twop.

[0098] It is worth noting that when the data frame 810 arrives, the main power domain 104 is operating normally and is able to receive the data frame.

[0099] Figure 8 8 also shows a signal for anticipating a sleep transition (i.e., entering a sleep mode) according to one or more embodiments. At time 810, a control bit of a control register is set for controlling entry / exit of a sleep mode. As a non-limiting example, the control bit may be set by an inactivity detection logic component of the core logic component 106 or a power management logic component 110 configured to detect a timeout condition. As a non-limiting example, the timeout condition may be that the bus is inactive for a specified period of time, or that a valid wake-up signal is not detected for a specified period of time.

[0100] At time 812, the power management logic 110 deactivates the enable signal 126 in response to the sleep control signal 140 being asserted (i.e., the sleep control bit is set at the sleep control register). At time 814, the main power supply 124 is turned off. It is worth noting that after the main power supply 124 is turned off at time 814, the uninterruptible power supply 122 remains on and powers the elements of the uninterruptible power domain 108.

[0101] Fig. 9 A swim lane diagram of a wakeup transition process 900 is shown according to one or more embodiments.

[0102] In operation 902, process 900 asserts a wake-up signal (e.g., asserted by power master 202) at a direct connection to a power slave device (e.g., power slave 204) or, in the alternative, asserts a signal indicating valid bus activity at a shared bus (e.g., asserted by power master 202). In one embodiment, if the signal indicates valid bus activity, the signal is characterized by an energy level corresponding to an energy level associated with a valid communication signal (e.g., an energy level of an Ethernet data frame, but not limited thereto).

[0103] In operation 904, process 900 observes (e.g., observed by power slave device 204) a wake-up signal at an input of a physical layer device of power slave device 204, or alternatively observes (e.g., observed by power slave device 204) a signal indicating valid bus activity at the shared bus.

[0104] In operation 906 , process 900 asserts an enable signal (eg, by power slave device 204 ), thereby indicating that power should be supplied to the first (eg, master) power domain of the power slave device in response to the observed wake-up signal or alternatively in response to the observed signal indicating valid bus activity.

[0105] In operation 908, process 900, in response to the observed wake-up signal or alternatively in response to the observed signal indicating valid bus activity, supplies power to the first (e.g., primary) power domain of power slave device 204. More specifically, in response to the enable signal asserted in operation 906, power is supplied to the first (e.g., primary) power domain of power slave device 204.

[0106] In operation 910, process 900 optionally asserts a second wake-up signal at an output of a physical layer device of the power slave device 204 (e.g., asserted by the power slave device 204) in response to powering the master power domain. The output is operably coupled to an input of a physical layer device of another power slave device, so the wake-up signal asserted to the output is asserted at the input of the other physical layer device of the other power slave device.

[0107] Fig.10 A swim lane diagram of a sleep transition process 1000 is shown, according to one or more embodiments.

[0108] In operation 1002, process 1000 asserts a sleep signal (e.g., by power master device 202) at a shared bus or at a direct connection with a power slave device (e.g., with power slave device 204), or alternatively asserts a signal indicating bus inactivity on a shared bus (e.g., by power master device 202). In one embodiment, if the signal indicating bus inactivity is asserted, the signal is characterized by an energy level that is different from an energy level associated with an active communication signal (e.g., different from an Ethernet signal, but not limited thereto).

[0109] In operation 1004, process 1000 observes (e.g., observed by power slave device 204) a sleep signal asserted at an input of a physical layer device of power slave device 204 or at a shared bus, or alternatively observes (e.g., observed by power slave device 204) a signal indicating bus inactivity on a shared bus.

[0110] In operation 1006 , process 1000 deactivates an enable signal (eg, by power slave device 204 ) to indicate that the first (eg, master) power domain of the power slave device should not be powered in response to an observed sleep signal, or alternatively in response to observed bus inactivity.

[0111] In operation 1008, process 1000 disables power to a first (eg, master) power domain of power slave device 204 (eg, turns off a power source for transmitting the sleep signal) in response to the observed sleep signal or alternatively in response to observed bus inactivity. Figure 1 More specifically, process 1000 disables power to a first (eg, primary) power domain of power slave device 204 in response to a failed enable signal.

[0112] In operation 1010, process 1000, when disabling power to a first (e.g., primary) power domain of the power slave device, continues to supply power to a second (e.g., uninterrupted) power domain of the power slave device 204 (e.g., by Figure 1 An uninterruptible power supply 122 powered by the power supply 120 in, but not limited to this).

[0113] At operation 1012 , process 1000 monitors (eg, by circuitry associated with a second power domain of power slave device 204 ) an input of a physical layer device of power slave device 204 for a wakeup signal and / or monitors a shared bus for valid bus activity.

[0114] The terms used in this disclosure, especially in the appended claims (e.g., the bodies of the appended claims) are generally intended to be “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” and the term “comprising” should be interpreted as “including but not limited to,” without limitation).

[0115] Additionally, if a specific number of an introduced claim recitation is intended, such intent will be expressly recited in the claim, and in the absence of such recitation, no such intent is present. For example, to aid understanding, the following appended claims may contain usage of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that a claim recitation introduced by the indefinite article "a" or "an" will limit any particular claim containing such introduced claim recitation to embodiments containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article, such as "a" or "an" (e.g., "a" and / or "an" may be interpreted to mean "at least one" or "one or more"); the same is true of the use of definite articles used to introduce claim recitations.

[0116] Furthermore, even if specific numbers of the introduced claim recitations are explicitly recited, those skilled in the art will recognize that such recitations should be interpreted as referring to at least the recited number (e.g., a bare recitation of "two recitations" without other modifiers refers to at least two recitations or two or more recitations). Furthermore, in those cases where a convention similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." is used, such construction is generally intended to include only A, only B, only C, both A and B, both A and C, both B and C, or all three of A, B, and C, etc.

[0117] In addition, any discrete word or phrase presenting two or more additional terms, whether in the specification, claims or drawings, should be understood to include the possibility of one of the terms, either of the two terms, or both of the two terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0118] Additional non-limiting embodiments of the present disclosure include:

[0119] Embodiment 1: A physical layer device for a network segment of a multi-point network, comprising: a core logic component associated with an interruptible power domain, the core logic component being configured to perform one or more operations for interacting with a shared bus; and a power management logic component associated with an uninterruptible power domain, the power management logic component being configured to enable and disable power supply to the interruptible power domain.

[0120] Embodiment 2: The physical layer device according to embodiment 1 further includes: a sensing circuit, wherein the sensing circuit is configured to detect a wake-up signal valid at the input of the physical layer device, and the power management logic component is configured to enable power supply to the interruptible power domain in response to detecting the valid wake-up signal detected by the sensing circuit.

[0121] Embodiment 3: The physical layer device according to any one of Embodiments 1 and 2 further includes: an energy detection circuit, wherein the energy detection circuit is configured to detect bus activity, and the power management logic component is configured to enable power supply to the interruptible power domain in response to the energy detection circuit detecting valid bus activity.

[0122] Embodiment 4: A physical layer device according to any one of embodiments 1 to 3, wherein the power management logic component is configured to enable power supply to the interruptible power domain in response to one or more of the following items: a valid wake-up signal; and valid bus activity.

[0123] Embodiment 5: A physical layer device according to any one of embodiments 1 to 4, wherein the power management logic component is configured to disable power supply to the interruptible power domain in response to one or more of the following items: a sleep control signal; an inactive input assigned to receive a wake-up signal; and an inactive bus.

[0124] Embodiment 6: The physical layer device of any one of embodiments 1 to 5, wherein the core logic component is configured to assert a wake-up signal at an output of the physical layer device in response to waking up from a sleep mode.

[0125] Embodiment 7: A system comprising: a first site controller; and a first physical layer device, wherein the first physical layer device is configured to interact the first site controller with a shared bus of a network segment, wherein the first physical layer device is configured to enable and disable power supply to one or more of interruptible power domains of the first site controller and the physical layer device.

[0126] Embodiment 8: A system according to embodiment 7, wherein the physical layer device comprises: a power management logic component, the power management logic component is associated with an uninterruptible power supply domain of the first physical layer device, and the power management logic component is configured to enable and disable power supply to the first site controller.

[0127] Embodiment 9: The system according to any one of embodiments 7 and 8, wherein the physical layer device comprises: a core logic component, the core logic component is associated with the interruptible power domain of the first physical layer device.

[0128] Embodiment 10: The system of any one of embodiments 7 to 9, wherein the power management logic component is configured to disable power to the first site controller in response to a sleep control signal provided by the core logic component.

[0129] Embodiment 11: The system according to any one of Embodiments 7 to 10 further includes a control bus, which is operably coupled to the first physical layer device and the first site controller, wherein the core logic component is configured to provide the sleep control signal to the power management logic component via the control bus.

[0130] Embodiment 12: The system according to any one of embodiments 7 to 11, further comprising equipment operably coupled to a network through the first network segment.

[0131] Embodiment 13: The system of any one of Embodiments 7 to 12, further comprising: a switch configured to provide an interruptible path for supplying power to the equipment.

[0132] Embodiment 14: The system according to any one of embodiments 7 to 13 further includes: a power master device, which is configured to generate a power control signal for a network, wherein the power master device is configured to selectively reset a site of a network segment of the network by instructing the corresponding site controller of the site to enter a sleep mode.

[0133] Embodiment 15: The system according to any one of Embodiments 7 to 14 further includes: a power master device configured to generate a power control signal for a network, wherein the power master device is configured to force a station of a network segment to enter a sleep mode by enabling the power control signal at the shared bus, and the power control signal exhibits an energy level different from an energy level associated with a communication message transmitted on the network segment.

[0134] Embodiment 16: The system according to any one of embodiments 7 to 15 further includes: a second site controller; and a second physical layer device of the first network segment, wherein the second physical layer device is configured to enable power supply to the second site controller in response to a wake-up signal received from the first physical layer device.

[0135] Embodiment 17: A method comprising: disabling power supply to a first power domain of a power slave device in response to: receiving a sleep control signal; or observing a signal indicating bus inactivity at a shared bus; and continuing to supply power to a second power domain of the power slave device while disabling power supply to a main power domain of the power slave device.

[0136] Embodiment 18: A method according to Embodiment 17, wherein disabling power supply to the first power domain of the power slave device in response to the observed sleep control signal or the observed signal indicating bus inactivity at the shared bus comprises: disabling an enable signal in response to the following items, thereby indicating that power should not be supplied to the first power domain of the power slave device: an observed sleep control signal; or an observed signal indicating bus inactivity at the shared bus.

[0137] Embodiment 19: The method of any one of Embodiments 17 and 18, wherein observing a signal indicative of bus inactivity comprises observing an energy level of the signal and determining that the energy level is different than an energy level associated with an active communication signal.

[0138] Embodiment 20: The method according to any one of embodiments 17 to 19 further includes: supplying power to a first power domain of a power slave device in response to: observing a wake-up signal at an input of a physical layer device of the power slave device; or observing a signal indicating valid bus activity at the shared bus.

[0139] Embodiment 21: The method according to any one of embodiments 17 to 20 further includes: validating an enable signal in response to the following items, thereby indicating that power should be supplied to a first power domain of the power slave device: an observed wake-up signal; or an observed signal indicating valid bus activity at a shared bus; and starting to supply power to the first power domain of the power slave device in response to the validated enable signal.

[0140] Embodiment 22: The method according to any one of embodiments 17 to 21 further includes: in response to powering the main power domain, enabling a second wake-up signal at the output of the physical layer device, the output being operably coupled to the input of another physical layer device.

[0141] Although the present invention is described herein with respect to certain illustrated embodiments, those of ordinary skill in the art will recognize and appreciate that the present invention is not so limited. Rather, many additions, deletions, and modifications may be made to the illustrated embodiments and the described embodiments without departing from the scope of the present invention as claimed below and its legal equivalents. Furthermore, features from one embodiment may be combined with features of another embodiment while still being included within the scope of the present invention as contemplated by the inventor.

Claims

1. A physical layer device for a network segment of a multipoint network, comprising: transmit / receive circuitry associated with the interruptible power domain; a core logic component associated with the interruptible power domain, the core logic component being configured to perform one or more operations of a physical layer for interacting with a shared bus; and a power management logic component associated with the uninterruptible power domain, the power management logic component being configured to enable and disable power supply to the interruptible power domain, The transmitting / receiving circuit and the core logic component respectively present states in response to the state of power supply to the interruptible power domain, and these states include an unpowered state in response to disabling power supply to the interruptible power domain and a powered state in response to enabling power supply to the interruptible power domain.

2. The physical layer device according to claim 1, further comprising: A sense circuit is configured to detect a wake-up signal asserted at an input of the physical layer device, the power management logic component being configured to enable power to the interruptible power domain in response to detecting the asserted wake-up signal detected by the sense circuit.

3. The physical layer device according to claim 2, further comprising: An energy detection circuit is configured to detect bus activity, and the power management logic component is configured to enable power to the interruptible power domain in response to the energy detection circuit detecting valid bus activity.

4. The physical layer device of claim 1 , wherein the power management logic component is configured to enable supply of power to the interruptible power domain in response to one or more of the following: A valid wake-up signal; and Valid bus activity.

5. The physical layer device of claim 1 , wherein the power management logic component is configured to disable power to the interruptible power domain in response to one or more of the following: Sleep control signal; an inactive input assigned to receive a wake-up signal; and Inactive bus.

6. The physical layer device of claim 1, wherein the core logic component is configured to assert a wake-up signal at an output of the physical layer device in response to waking up from a sleep mode.

7. A system comprising: First site controller; and a first physical layer device configured to enable the first site controller to interact with a shared bus of a network segment, Wherein the first physical layer device is configured to enable and disable power supply to the first site controller and to an interruptible power domain of the first physical layer device.

8. The system of claim 7, wherein the first physical layer device comprises: A power management logic component is associated with an uninterruptible power supply domain of the first physical layer device, the power management logic component is configured to enable and disable power to the first site controller.

9. The system of claim 8, wherein the first physical layer device comprises: A core logic component is associated with the interruptible power domain of the first physical layer device.

10. The system of claim 9, wherein the power management logic component is configured to disable power to the first site controller in response to a sleep control signal provided by the core logic component.

11. The system according to claim 10, further comprising: a control bus operatively coupling the first physical layer device and the first site controller, The core logic component is configured to provide the sleep control signal to the power management logic component via the control bus.

12. The system of claim 7, further comprising equipment operably coupled to a network through the network segment.

13. The system of claim 12, further comprising: A switch is configured to provide an interruptible path for supplying power to the equipment.

14. The system of claim 13, further comprising: A power master is configured to generate a power control signal for a network, wherein the power master is configured to selectively reset sites of a network segment of the network by instructing respective site controllers of the sites to enter a sleep mode.

15. The system of claim 13, further comprising: A power master device, the power master device being configured to generate a power control signal for a network, wherein the power master device is configured to force a station of a network segment into a sleep mode by enabling a power control signal at the shared bus, the power control signal exhibiting an energy level different from an energy level associated with a communication message transmitted on the network segment.

16. The system of claim 7, further comprising: Second site controller; and a second physical layer device of the network segment, The second physical layer device is configured to enable power supply to the second site controller in response to a wake-up signal received from the first physical layer device.

17. A method for a physical layer device of a network segment of a multipoint network, comprising: supplying power to a first power domain of a power slave device and a second power domain of the power slave device; disabling supply of power to the first power domain of the power slave device in response to: A sleep control signal is received; or A signal indicating bus inactivity at a shared bus is observed, Wherein, the first power domain of the power slave device includes: The transmit / receive circuitry of the physical layer device, and The core logic components of the physical layer device, wherein the transmitting / receiving circuit and the core logic component respectively present states in response to a state of powering the first power domain, the states comprising an unpowered state in response to disabling powering the first power domain and a powered state in response to enabling powering the first power domain; and The second power domain of the power slave device continues to be supplied with power, while the first power domain of the power slave device is disabled from being supplied with power.

18. The method of claim 17, wherein in response to the sleep control signal or the observed signal indicating bus inactivity at the shared bus, disabling power to the first power domain of the power slave device comprises: deactivating an enable signal to indicate that power should not be supplied to the first power domain of the power slave device in response to: the sleep control signal; or The observed signal indicates bus inactivity at the shared bus.

19. The method of claim 17, wherein observing the signal indicating bus inactivity comprises: An energy level of the signal is observed and a determination is made that the energy level is different than an energy level associated with a valid communication signal.

20. The method of claim 17, further comprising: supplying power to the first power domain of the power slave device in response to: observing a wake-up signal at an input of a physical layer device of the power slave device; or A signal is observed indicating valid bus activity at the shared bus.

21. The method according to claim 20, further comprising: asserting an enable signal to indicate that power should be supplied to the first power domain of the power slave device in response to: the observed arousal signal; or the observed signal indicating valid bus activity at the shared bus; and In response to the asserted enable signal, power is started to be supplied to the first power domain of the power slave device.

22. The method according to claim 20, further comprising: In response to powering the first power domain, a second wake-up signal is asserted at an output of the physical layer device, the output being operably coupled to an input of another physical layer device.

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