Display device and method for manufacturing the same

Abstract

A display device according to an embodiment of the present disclosure includes: pixels disposed in a display area; a first line connected to the pixels; and a first control line disposed near the first line. The pixel includes: a first electrode and a second electrode spaced apart from each other; at least one intermediate electrode including a first intermediate electrode disposed between the first electrode and the second electrode; a plurality of light-emitting elements each connected between a pair of adjacent electrodes among the first electrode, the second electrode, and the at least one intermediate electrode; and a first switching element connected between the first intermediate electrode and the first line and controlled by a signal applied to the first control line.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display device and a method of manufacturing the same. Background Art

[0002] Recently, technologies for manufacturing ultra-small light-emitting elements using materials having a reliable inorganic crystal structure and for manufacturing light-emitting devices using the light-emitting elements have been developed. For example, technologies for manufacturing a plurality of ultra-small light-emitting elements each having a small size corresponding to a range from the nanoscale to the microscale and for forming a light source of various light-emitting devices including pixels of a display device using the ultra-small light-emitting elements have been developed. Summary of the Invention

[0003] Technical Problem

[0004] A technical object of the present disclosure is to provide a display device including a light-emitting element and a method of manufacturing the same.

[0005] Technical Solution

[0006] A display device according to an embodiment of the present disclosure includes: a pixel disposed in a display area; a first line connected to the pixel; and a first control line disposed near the first line. The pixel includes: a first electrode and a second electrode spaced apart from each other; at least one intermediate electrode including a first intermediate electrode between the first electrode and the second electrode; a plurality of light-emitting elements respectively connected between a pair of adjacent electrodes among the first electrode, the second electrode, and the at least one intermediate electrode; and a first switching element connected between the first intermediate electrode and the first line and configured to be controlled by a signal applied to the first control line.

[0007] In an embodiment, the first switching element may include a first active layer that overlaps with the first control line and is electrically connected between the first intermediate electrode and the first line.

[0008] In an embodiment, the display device may further include a second line spaced apart from the first line. The pixel may further include: a second intermediate electrode included in the at least one intermediate electrode and disposed between the first electrode and the first intermediate electrode; and a second switching element connected between the second intermediate electrode and the second line.

[0009] In an embodiment, the second line may be disposed near the first control line. The second switching element may include a second active layer that overlaps with the first control line and is electrically connected between the second intermediate electrode and the second line.

[0010] In an embodiment, the display device may further include a second control line disposed near the second line. The second switching element may include a second active layer that partially overlaps with the second control line and is electrically connected between the second intermediate electrode and the second line.

[0011] In an embodiment, the first line and the first control line may be disposed adjacent to the first ends of the first electrode, the second electrode, and at least one intermediate electrode. The second line and the second control line may be disposed adjacent to the second ends of the first electrode, the second electrode, and at least one intermediate electrode.

[0012] In an embodiment, the display device may further include a third line spaced apart from the first line and the second line. The pixel may further include a third switching element connected between the first electrode and the third line and configured to be turned on simultaneously with the first switching element.

[0013] In an embodiment, the display device may further include a second line spaced apart from the first line. The pixel may further include a second switching element connected between the first electrode and the second line.

[0014] In an embodiment, the pixel may further include a second switching element connected between the first electrode and the second electrode and configured to be turned on simultaneously with the first switching element.

[0015] In an embodiment, the first electrode, at least one intermediate electrode, and the second electrode may be continuously arranged in a first direction in the emission region of the pixel.

[0016] In an embodiment, the first line and the first control line may be disposed adjacent to the first ends of the first electrode, at least one intermediate electrode, and the second electrode, and each may extend in the first direction and be commonly connected to the pixels of a horizontal line, and the pixels of the horizontal line are disposed on the horizontal line.

[0017] In an embodiment, the display region may include a plurality of horizontal lines, and each of the plurality of horizontal lines includes a plurality of pixels. The first line and the first control line connected to the pixels of any one of the horizontal lines may be disposed opposite to the first line and the first control line connected to the pixels of the subsequent horizontal line, and the pixels of any one of the horizontal lines and the pixels of the subsequent horizontal line are disposed between the first line and the first control line connected to the pixels of any one of the horizontal lines and the first line and the first control line connected to the pixels of the subsequent horizontal line.

[0018] In an embodiment, the first switching element included in the pixels of any one of the horizontal lines and the first switching element included in the pixels of the subsequent horizontal line may have symmetric shapes with respect to each other.

[0019] In an embodiment, the first electrode, the second electrode, and the intermediate electrode included in the pixels of any one of the horizontal lines and the first electrode, the second electrode, and the intermediate electrode included in the pixels of the subsequent horizontal line may have symmetric shapes with respect to each other.

[0020] In an embodiment, the first electrode and the second electrode may be electrically connected to a first power supply and a second power supply, respectively. At least one intermediate electrode may be electrically connected between the first electrode and the second electrode through a light-emitting element.

[0021] In an embodiment, the pixel may further include a pixel circuit connected between the first power supply and the first electrode. The display region may include: a circuit layer in which circuit elements of the pixel circuit are disposed; and a display layer stacked on the circuit layer, and the first electrode, the second electrode, at least one intermediate electrode, and the light-emitting element are disposed in the display layer.

[0022] In an embodiment, the circuit layer may further include at least one of a first power line connected to the first power supply, a second power line connected to the second power supply, an active layer of a first switching element, a first line, and a first control line.

[0023] In an embodiment, the display layer may further include at least one of a first line and a first control line.

[0024] In an embodiment, the pixel may further include at least one of the following: a plurality of bank patterns respectively disposed under the first electrode, the second electrode, and at least one intermediate electrode; and a plurality of contact electrodes respectively disposed on the first electrode, the second electrode, and at least one intermediate electrode.

[0025] A display device according to an embodiment of the present disclosure includes: a plurality of electrodes and a light-emitting element disposed in an emission region of each pixel; a switching element connected to any one of the plurality of electrodes; and an alignment line connected to the switching element. A method of manufacturing a display device includes the steps of: forming a switching element, an alignment line, and a plurality of electrodes; supplying a light-emitting element to the emission region; aligning the light-emitting element between the plurality of electrodes by driving the switching element and supplying a corresponding alignment signal to the plurality of electrodes; and electrically connecting the light-emitting element between the plurality of electrodes.

[0026] Advantageous Effects

[0027] According to various embodiments of the present disclosure, the process of manufacturing a display device including a light-emitting element can be simplified. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1a and Figure 1b are a perspective view and a cross-sectional view showing a light-emitting element according to an embodiment of the present disclosure, respectively.

[0029] Figure 2a and Figure 2b are a perspective view and a cross-sectional view showing a light-emitting element according to an embodiment of the present disclosure, respectively.

[0030] Figure 3a and Figure 3bare a perspective view and a cross-sectional view showing a light-emitting element according to an embodiment of the present disclosure, respectively.

[0031] Figure 4a and Figure 4b are a perspective view and a cross-sectional view showing a light-emitting element according to an embodiment of the present disclosure, respectively.

[0032] Figure 5 is a plan view showing a display device according to an embodiment of the present disclosure.

[0033] Figures 6a to 6g are circuit diagrams each showing a pixel according to an embodiment of the present disclosure.

[0034] Figures 7a to 7f are circuit diagrams each showing a pixel according to an embodiment of the present disclosure, and show different embodiments of a pixel including a switching unit, for example.

[0035] Figures 8a to 8c each show an example of an alignment signal according to an embodiment of the present disclosure.

[0036] Figures 9a to 9d are plan views each showing a pixel according to an embodiment of the present disclosure.

[0037] Figure 10 is a plan view showing a pixel according to an embodiment of the present disclosure, and shows, for example, Figure 9a a modification of the pixel.

[0038] Figures 11a to 11d are cross-sectional views each showing a pixel according to an embodiment of the present disclosure, and show different embodiments of a cross-section corresponding to line I-I' of the pixel, for example, Figure 10 with respect to.

[0039] Figure 12a and Figure 12b are cross-sectional views each showing a pixel according to an embodiment of the present disclosure, and show different embodiments of a cross-section corresponding to line II-II' of the pixel, for example, Figure 10 with respect to.

[0040] Figures 13 to 18 are plan views each showing a display area according to an embodiment of the present disclosure, and show different embodiments related to an arrangement structure of alignment lines and pixels, for example. DETAILED DESCRIPTION

[0041] Now, various embodiments of the present disclosure will be described in detail. Specific examples of the present disclosure are shown in the drawings and described below. However, since the embodiments of the present disclosure can be variously modified in many different forms, the present disclosure is not limited to the following embodiments and can be modified into various forms.

[0042] Some elements that are not directly related to the features of the present disclosure may be omitted in the drawings to clearly explain the present disclosure. In addition, the dimensions, ratios, etc. of some elements in the drawings may be slightly exaggerated. It should be noted that throughout the drawings, the same reference numerals are used to denote the same or similar elements, and repeated descriptions will be omitted.

[0043] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. It will also be understood that when the terms "comprising", "including", "having", etc. are used in this specification, they indicate the presence of the stated features, wholes, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or combinations thereof. In addition, when a first component or a first part is disposed on a second component or a second part, not only can the first component or the first part be directly on the second component or the second part, but also a third component or a third part can be disposed between them. In addition, the terms "position", "direction", etc. used in the following description are defined in relative terms, and it should be noted that they may be changed to opposite positions or directions according to the perspective or direction. In addition, as long as it is not specifically mentioned in the sentence, the singular form may include the plural form.

[0044] Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b are a perspective view and a cross-sectional view respectively showing a light-emitting element LD according to an embodiment of the present disclosure. Although Figures 1a to 3b shows a cylindrical rod-shaped light-emitting element LD, the type and / or shape of the light-emitting element LD according to the present disclosure is not limited thereto.

[0045] Referring to Figure 1a and Figure 1b , a light-emitting element LD according to an embodiment of the present disclosure may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light-emitting element LD may include a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13 that are continuously stacked in the longitudinal direction.

[0046] In an embodiment, the light-emitting element LD may be provided in the form of a bar extending in one direction. If the direction along which the light-emitting element LD extends is defined as the longitudinal direction, the light-emitting element LD may have a first end EP1 and a second end EP2 with respect to the longitudinal direction. The first end EP1 and the second end EP2 may be regions including surfaces disposed at opposite ends of the light-emitting element LD with respect to the longitudinal direction, and may be regions including not only the surfaces of the opposite ends but also a predetermined region formed around the surfaces.

[0047] In an embodiment, one of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at the first end EP1 of the light-emitting element LD. The other of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at the second end EP2 of the light-emitting element LD.

[0048] In an embodiment, the light-emitting element LD may be a rod-shaped light-emitting element (also referred to as a "rod-shaped light-emitting diode") manufactured in the form of a bar by an etching process or the like. In the description of the embodiments of the present disclosure, the term "rod-shaped" includes a rod shape and a strip shape (such as a cylindrical shape and a prismatic shape extending along the longitudinal direction (i.e., having an aspect ratio greater than 1)), and the cross-sectional shape thereof is not limited to a specific shape. For example, the length L of the light-emitting element LD may be greater than its diameter D (or the width of its cross-section).

[0049] In an embodiment, the light-emitting element LD may have a small size ranging from the nanoscale to the microscale. For example, each light-emitting element LD may have a diameter D (or width) and / or a length L ranging from the nanoscale to the microscale. However, in the present disclosure, the size of the light-emitting element LD is not limited thereto. For example, the size of the light-emitting element LD may be changed in various ways according to the design conditions of various devices (such as a display device using the light-emitting device including the light-emitting element LD as a light source).

[0050] The first semiconductor layer 11 may be formed of a first-conductive semiconductor layer. For example, the first semiconductor layer 11 may include at least one N-type semiconductor layer. For example, the first semiconductor layer 11 may include an N-type semiconductor layer doped with a first-conductive dopant (such as Si, Ge, or Sn) and including any one of semiconductor materials such as InAlGaN, GaN, AlGaN, InGaN, AlN, and InN. However, the constituent material of the first semiconductor layer 11 is not limited thereto, and the first semiconductor layer 11 may be formed of various other materials.

[0051] The active layer 12 may be disposed on the first semiconductor layer 11 and have a single quantum well or multiple quantum well (MQW) structure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed above and / or below (or beneath) the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, materials such as AlGaN or AlInGaN may be used to form the active layer 12, and various other materials may be used to form the active layer 12.

[0052] The second semiconductor layer 13 may be disposed on the active layer 12 and formed of a second conductive semiconductor layer having a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one P-type semiconductor layer. For example, the second semiconductor layer 13 may include a P-type semiconductor layer including any one of semiconductor materials such as InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a second conductive dopant (such as, Mg). However, the material used to form the second semiconductor layer 13 is not limited thereto, and the second semiconductor layer 13 may be formed of various other materials.

[0053] When a voltage having a predetermined voltage or higher is applied between opposite ends (e.g., a first end EP1 and a second end EP2) of the light-emitting element LD, the light-emitting element LD emits light through the recombination of electron-hole pairs in the active layer 12. Since the light emission of the light-emitting element LD can be controlled based on the foregoing principle, the light-emitting element LD can be used not only as a light source for a pixel of a display device but also as a light source for various light-emitting devices.

[0054] In an embodiment, the light-emitting element LD may further include an insulating film INF disposed on the surface of the light-emitting element LD. The insulating film INF may be formed on the surface of the light-emitting element LD to surround at least the outer peripheral surface of the active layer 12 and may also surround a predetermined region of the first semiconductor layer 11 and the second semiconductor layer 13. Here, the insulating film INF may allow opposite ends of the light-emitting element LD having different polarities to be exposed to the outside. For example, the insulating film INF may expose the first end EP1 and the second end EP2 disposed at the respective opposite ends of the light-emitting element LD with respect to the longitudinal direction (e.g., as Figure 1a and Figure 1b shown, the top surface and the bottom surface corresponding to the two base sides of the cylinder of the light-emitting element LD may be exposed), without covering the first end EP1 and the second end EP2.

[0055] In an embodiment, the insulating film INF may include at least one insulating material such as silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), and titanium dioxide (TiO2), but is not limited thereto. In other words, the material forming the insulating film INF is not limited to a specific material, and the insulating film INF may be formed of various known insulating materials.

[0056] In an embodiment, in addition to the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and / or the insulating film INF, the light-emitting element LD may further include additional other components. For example, the light-emitting element LD may further include at least one fluorescent layer, at least one active layer, at least one semiconductor layer, and / or at least one electrode layer provided on one end of the first semiconductor layer 11, the active layer 12, and / or the second semiconductor layer 13.

[0057] For example, as Figure 2a and Figure 2b shown, the light-emitting element LD may further include at least one electrode layer 14 provided on one end of the second semiconductor layer 13. For example, the light-emitting element LD may further include an electrode layer 14 provided at the first end EP1.

[0058] In an embodiment, as Figure 3a and Figure 3b shown, the light-emitting element LD may further include at least one electrode layer 15 provided on one end of the first semiconductor layer 11. For example, the light-emitting element LD may include electrode layers 14 and 15 provided at the first end EP1 and the second end EP2, respectively.

[0059] Each of the electrode layers 14 and 15 may be a contact electrode configured to connect each light-emitting element LD to other circuit elements, lines, and / or electrodes, etc., but the present disclosure is not limited thereto. In an embodiment, each of the electrode layers 14 and 15 may include a metal or a metal oxide. For example, each of the electrode layers 14 and 15 may be formed of chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), their oxides or alloys, and / or a transparent electrode material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO) alone or in combination. In an embodiment, the electrode layers 14 and 15 may be substantially transparent or semi-transparent. Thus, the light generated from the light-emitting element LD can be emitted to the outside after passing through the electrode layers 14 and 15.

[0060] The insulating film INF may at least partially surround the outer peripheral surfaces of the electrode layers 14 and 15, or may not surround their outer peripheral surfaces. In other words, the insulating film INF may be formed to selectively cover the surfaces of the electrode layers 14 and 15. In addition, the insulating film INF may be formed to expose opposite ends of the light-emitting element LD having different conductivity types (e.g., P-type and N-type, respectively). For example, the insulating film INF may expose at least a predetermined region of the electrode layers 14 and 15 at the first end EP1 and the second end EP2 of the light-emitting element LD. Optionally, in an embodiment, the insulating film INF may not be provided in the light-emitting element LD.

[0061] If the insulating film INF is provided to cover the surface of the light-emitting element LD (specifically, the outer peripheral surface of the active layer 12), then a short circuit between the active layer 12 and at least one electrode (e.g., the first electrode or the second electrode of a pixel) not shown can be prevented. Accordingly, the electrical stability of the light-emitting element LD can be ensured. In the description of each embodiment of the present disclosure, the term "connect (or couple)" may comprehensively refer to physical connection (or coupling) and / or electrical connection (or coupling). In addition, the term "connect (or couple)" may comprehensively refer to direct connection (or coupling) or indirect connection (or coupling) and integral connection (or coupling) or non-integral connection (or coupling).

[0062] In addition, due to the insulating film INF formed at the surface of the light-emitting element LD, the occurrence of defects on the surface of the light-emitting element LD can be minimized, whereby the lifespan and efficiency of the light-emitting element LD can be improved. Additionally, if the insulating film INF is formed at the surface of each light-emitting element LD, then even when a plurality of light-emitting elements LD are arranged adjacent to each other, an undesired short circuit of the light-emitting elements LD can be prevented.

[0063] In an embodiment of the present disclosure, a surface treatment process may be performed to fabricate the light-emitting element LD. For example, each light-emitting element LD may be surface-treated such that when a plurality of light-emitting elements LD are mixed with a fluid solution (or solvent) and then supplied to each emission region (e.g., the emission region of each pixel), the light-emitting elements LD can be uniformly dispersed rather than unevenly aggregated in the solution.

[0064] In a non-limiting embodiment related thereto, the insulating film INF itself may be formed of a hydrophobic film using a hydrophobic material, or an additional hydrophobic film formed of a hydrophobic material may be formed on the insulating film INF. In an embodiment, the hydrophobic material may be a fluorine-containing material to exhibit hydrophobicity. In an embodiment, the hydrophobic material may be coated onto the light-emitting element LD in the form of a self-assembled monolayer (SAM). In this case, the hydrophobic material may include octadecyltrichlorosilane, fluoroalkyltrichlorosilane, perfluoroalkyltriethoxysilane, etc. In addition, the hydrophobic material may be a commercially available fluorine-containing material (such as TeflonTM or Cytop TM or corresponding materials).

[0065] The above-described light-emitting element LD can be used as a light source in different types of light-emitting devices including pixels of a display device. For example, at least one ultra-small light-emitting element LD (e.g., a plurality of ultra-small light-emitting elements LD each having a size ranging from the nanoscale to the microscale) can be disposed in each pixel region of a display panel for forming a screen of a display device, and the ultra-small light-emitting element LD is used to form a light source (or a light source unit) of a corresponding pixel. In addition, the application field of the light-emitting element LD according to the present disclosure is not limited to display devices. For example, the light-emitting element LD can also be used in other types of devices that require a light source (such as a lighting device).

[0066] Figure 4a and Figure 4b are a perspective view and a cross-sectional view showing a light-emitting element LD according to an embodiment of the present disclosure. According to the embodiment, Figure 4a and Figure 4b show a light-emitting element LD having a structure different from the structure of the light-emitting element LD shown in Figures 1a to 3b , for example, a light-emitting element having a core-shell structure. In other words, the type, structure, and / or shape of the light-emitting element LD according to an embodiment of the present disclosure can be changed in various ways. In the description of the embodiments of Figure 4a and Figure 4b , the same reference numerals are used to denote components similar or identical (or corresponding) to the components of the embodiment of Figures 1a to 3b , and their detailed description will be omitted.

[0067] Referring to Figure 4a and Figure 4b , the light-emitting element LD according to an embodiment of the present disclosure can include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. In the embodiment, the first semiconductor layer 11 can be disposed in a central region of the light-emitting element LD, and the active layer 12 can be disposed on a surface of the first semiconductor layer 11 to surround at least one region of the first semiconductor layer 11. The second semiconductor layer 13 can be disposed on a surface of the active layer 12 to surround at least one region of the active layer 12.

[0068] The light-emitting element LD may also selectively include an electrode layer 14 configured to surround at least one region of the second semiconductor layer 13 and / or an insulating film INF provided at the outermost surface of the light-emitting element LD. For example, the light-emitting element LD may also include an electrode layer 14 provided on the surface of the second semiconductor layer 13 to surround at least one region of the second semiconductor layer 13 and an insulating film INF provided on the surface of the electrode layer 14 to surround at least one region of the electrode layer 14.

[0069] In an embodiment, the insulating film INF may be provided at the surface of the light-emitting element LD to cover a part of the outer peripheral surface of the first semiconductor layer 11 and the outer peripheral surface of the electrode layer 14. The insulating film INF may include a transparent insulating material.

[0070] In an embodiment, after forming the insulating film INF to cover the entire outer peripheral surface of the electrode layer 14 included in the light-emitting element LD, the insulating film INF may be partially removed to expose a region of the electrode layer 14 for electrical connection to an electrode (e.g., the first electrode of a pixel) not shown.

[0071] The light-emitting element LD according to the foregoing embodiments may be a core-shell light-emitting element (also referred to as a “core-shell light-emitting diode”) manufactured by a growth process or the like. For example, the light-emitting element LD may have a core-shell structure including a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, an electrode layer 14, and an insulating film INF continuously provided in the direction from the center to the periphery. In an embodiment, the light-emitting element LD may not include at least one of the electrode layer 14 and the insulating film INF.

[0072] In an embodiment, the light-emitting element LD may have a multi-pyramid shape extending in one direction. For example, at least one region of the light-emitting element LD may have a hexagonal pyramid shape. However, the shape of the light-emitting element LD may be changed in various ways.

[0073] If the direction in which the light-emitting element LD extends is defined as the longitudinal direction, the light-emitting element LD may have a first end EP1 and a second end EP2 with respect to the longitudinal direction. In an embodiment, one of the first semiconductor layer 11 and the second semiconductor layer 13 (or an electrode layer configured to surround any one of the first semiconductor layer 11 and the second semiconductor layer 13) is provided at the first end EP1 of the light-emitting element LD. The other of the first semiconductor layer 11 and the second semiconductor layer 13 (or an electrode layer configured to surround the other of the first semiconductor layer 11 and the second semiconductor layer 13) may be provided at the second end EP2 of the light-emitting element LD.

[0074] In an embodiment of the present disclosure, the light-emitting element LD may be a light-emitting diode and have an ultra-small size. The light-emitting diode has a core-shell structure, and the first end EP1 protrudes in a polyhedral shape (e.g., a hexagonal pyramid shape). For example, the light-emitting element LD may have a shape corresponding to a combination of a hexagonal pyramid and a hexagonal prism and a small size ranging from the nanoscale to the microscale (e.g., a width W and / or a length L corresponding to the nanoscale or the microscale). Here, the size and shape of the light-emitting element LD may be changed according to the design conditions of various devices (e.g., a display device) using the light-emitting element LD as a light source.

[0075] In an embodiment, opposite ends of the first semiconductor layer 11 may have a shape protruding in the longitudinal direction of the light-emitting element LD. The protruding shapes of the opposite ends of the first semiconductor layer 11 may be different from each other. For example, disposed at an upper position, a first end of the opposite ends of the first semiconductor layer 11 may have a pyramidal shape (e.g., a hexagonal pyramid shape), and the width of the pyramidal shape decreases upward to converge to one vertex. In addition, disposed at a lower position, a second end of the opposite ends of the first semiconductor layer 11 may have a prismatic shape (e.g., a hexagonal prism shape), and the prismatic shape has a constant width, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the first semiconductor layer 11 may have a polygonal cross-section or a stepped cross-section whose width gradually decreases downward. The shape of the opposite ends of the first semiconductor layer 11 may be changed in various ways according to the embodiment.

[0076] The first semiconductor layer 11 may be disposed in the core of the light-emitting element LD (i.e., the central (or middle) portion of the light-emitting element LD). In addition, the light-emitting element LD may have a shape corresponding to the shape of the first semiconductor layer 11. For example, if the first semiconductor layer 11 has a hexagonal pyramid shape at its upper end, the light-emitting element LD may have a hexagonal pyramid shape at its upper end (e.g., the first end EP1).

[0077] The active layer 12 may be disposed and / or formed in a shape surrounding the outer peripheral surface of the first semiconductor layer 11. For example, the active layer 12 may be disposed and / or formed in a shape surrounding an area of the first semiconductor layer 11 except for one end (e.g., the lower end) of the first semiconductor layer 11 in the longitudinal direction of the light-emitting element LD.

[0078] The second semiconductor layer 13 may be disposed and / or formed in a shape surrounding the outer peripheral surface of the active layer 12 and includes a semiconductor layer having a type different from the type of the first semiconductor layer 11. For example, in the case where the first semiconductor layer 11 includes an N-type semiconductor layer, the second semiconductor layer 13 may include a P-type semiconductor layer.

[0079] In an embodiment, the light-emitting element LD may further include an electrode layer 14 surrounding the outer peripheral surface of the second semiconductor layer 13. The electrode layer 14 may be a contact electrode electrically connected to the second semiconductor layer 13, but the present disclosure is not limited thereto.

[0080] As described above, the light-emitting element LD may have a core-shell structure with opposite ends protruding outward, and may include a first semiconductor layer 11 disposed in its central portion, an active layer 12 surrounding the first semiconductor layer 11, and a second semiconductor layer 13 surrounding the active layer 12. In addition, the light-emitting element LD may further selectively include an electrode layer 14 surrounding the second semiconductor layer 13. One end of the electrode layer 14 may be disposed at the first end EP1 of the light-emitting element LD, and one end of the first semiconductor layer 11 may be disposed at the second end EP2 of the light-emitting element LD.

[0081] The above-described light-emitting element LD may be used as a light source in different types of light-emitting devices including pixels. For example, at least one ultra-small light-emitting element LD (e.g., a plurality of ultra-small light-emitting elements LD each having a size ranging from the nanoscale to the microscale) may be disposed in each pixel region of the display panel to form a light source (or a light source unit) of the corresponding pixel using the ultra-small light-emitting element LD.

[0082] In an embodiment, each pixel may include at least one rod-shaped light-emitting element LD or at least one core-shell light-emitting element LD, or a combination of a rod-shaped light-emitting element LD and a core-shell light-emitting element LD. In an embodiment, each pixel may include other light-emitting elements having a type and / or shape different from the type and / or shape of the rod-shaped light-emitting element LD or the core-shell light-emitting element LD.

[0083] Figure 5 is a plan view of a display device according to an embodiment of the present disclosure. In an embodiment, Figure 5 shows an example of an electronic device using Figures 1a to 4b the light-emitting element LD described in the embodiments as a light source, specifically, a display panel PNL disposed in the display device. For example, each of the pixels PXL in the display panel PNL may have at least one light-emitting element LD.

[0084] For illustrative purposes, Figure 5 the structure of the display panel PNL according to an embodiment is simply shown, focusing on the display area DA. In some embodiments, although not shown, at least one driving circuit (e.g., at least one of a scan driver and a data driver) and / or a plurality of lines may also be disposed in the display panel PNL.

[0085] Referring to Figure 5, a display panel PNL according to an embodiment of the present disclosure may include a substrate layer BSL and a plurality of pixels PXL disposed on the substrate layer BSL. In an embodiment, each pixel PXL may be a first color pixel configured to emit light having a first color (e.g., red), a second color pixel configured to emit light having a second color (e.g., green), and a third color pixel configured to emit light having a third color (e.g., blue). The type and / or arrangement structure of the pixels PXL may be changed in various ways according to the embodiment.

[0086] The display panel PNL and the substrate layer BSL for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA other than the display area DA. The pixels PXL may be disposed in the display area DA on the substrate layer BSL.

[0087] In an embodiment, the display area DA may be disposed in a central area of the display panel PNL, and the non-display area NDA may be disposed in a peripheral area of the display panel PNL so as to surround the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may be changed. The display area DA may form a screen on which an image is displayed.

[0088] The substrate layer BSL may form a substrate of the display panel PNL. In an embodiment, the substrate layer BSL may be a rigid or flexible substrate or film, and the material or property of the substrate layer BSL is not particularly limited. For example, the substrate layer BSL may be a rigid substrate made of glass or strengthened glass, a flexible substrate (or film) formed of plastic or metal, or at least one insulating layer, and the material and / or property of the substrate layer BSL is not particularly limited.

[0089] In addition, the substrate layer BSL may be transparent, but the present disclosure is not limited thereto. For example, the substrate layer BSL may be a transparent, translucent, opaque, or reflective substrate.

[0090] An area on the substrate layer BSL may be defined as the display area DA in which the pixels PXL are disposed, and another area of the substrate layer BSL may be defined as the non-display area NDA. For example, the substrate layer BSL may include the display area DA and the non-display area NDA disposed around the display area DA, and the display area DA includes a plurality of pixel areas in which the corresponding pixels PXL are formed. Various lines and / or internal circuits connected to the pixels PXL in the display area DA may be disposed in the non-display area NDA.

[0091] Multiple pixels PXL can be dispersed and arranged in the display area DA. For example, multiple pixels PXL can be regularly arranged in the display area DA in a stripe or PenTile (or "five-tile") arrangement or the like. The arrangement structure of the pixels PXL is not limited thereto, and the pixels PXL can be arranged in the display area DA in various structures and / or schemes.

[0092] Each pixel PXL can include at least one light source driven by a predetermined control signal (e.g., a scan signal and a data signal) and / or a predetermined power supply (e.g., a first power supply and a second power supply). In an embodiment, each pixel PXL can include at least one light-emitting element LD (e.g., at least one ultra-small rod-shaped light-emitting element LD manufactured by an etching process to have a small size corresponding to the nanoscale or microscale) according to any one of the embodiments of Figures 1a to 3b In an embodiment, each pixel PXL can include at least one light-emitting element LD (e.g., at least one ultra-small core-shell light-emitting element LD manufactured by a growth process to have a small size corresponding to the nanoscale or microscale) according to the embodiments of Figure 4a and Figure 4b In addition, different types of light-emitting elements LD can be used as the light source of the pixel PXL.

[0093] In an embodiment, each pixel PXL can be formed by an active pixel. However, the type, structure, and / or driving scheme of the pixel PXL applicable to the display device according to the present disclosure are not particularly limited. For example, each pixel PXL can have the same structure as the pixels of a passive or active light-emitting display device having various known structures and / or operable in various known driving schemes.

[0094] Figures 6a to 6g are circuit diagrams each showing a pixel PXL according to an embodiment of the present disclosure. For example, Figures 6a to 6g shows different embodiments of the pixel PXL applicable to an active display device. However, the type of the pixel PXL and the display device to which the embodiments of the present disclosure can be applied is not limited thereto. In an embodiment, Figures 6a to 6g each pixel PXL shown in Figure 5 can be any one of the pixels PXL provided in the display panel PNL of

[0095] Referring to Figure 6a , the pixel PXL according to an embodiment of the present disclosure can include a light source unit LSU configured to generate light having a luminance corresponding to a data signal. The pixel PXL can also selectively include a pixel circuit PXC configured to drive the light source unit LSU.

[0096] In an embodiment, the light source unit LSU may include at least one light-emitting element LD (e.g., a plurality of light-emitting elements LD) connected between a first power supply (or first power supply) VDD and a second power supply (or second power supply) VSS. For example, the light source unit LSU may include a first electrode ET1 (also referred to as a "first pixel electrode") connected to the first power supply VDD via a pixel circuit PXC and a first power line PL1, a second electrode ET2 connected to the second power supply VSS via a second power line PL2, and a plurality of light-emitting elements LD connected in parallel to each other in the same direction between the first electrode ET1 and the second electrode ET2. In an embodiment, the first electrode ET1 may be an anode electrode, and the second electrode ET2 may be a cathode electrode.

[0097] In an embodiment, each of the light-emitting elements LD may include a first end (e.g., a P-type end) connected to the first power supply VDD through the first electrode ET1 and / or the pixel circuit PXC and a second end (e.g., an N-type end) connected to the second power supply VSS through the second electrode ET2. In an embodiment, the light-emitting elements LD may be connected in parallel in the forward direction between the first electrode ET1 and the second electrode ET2. Thus, each of the light-emitting elements LD connected in the forward direction between the first power supply VDD and the second power supply VSS may form an effective light source. A set of effective light sources may form the light source unit LSU of the pixel PXL.

[0098] In an embodiment, the first power supply VDD and the second power supply VSS may have different potentials so that the light-emitting element LD can emit light. For example, the first power supply VDD may be set as a high-potential power supply, and the second power supply VSS may be set as a low-potential power supply. Here, at least during the emission period of the pixel PXL, the potential difference between the first power supply VDD and the second power supply VSS may be set to a voltage equal to or greater than the threshold voltage of the light-emitting element LD.

[0099] In an embodiment, one end (e.g., the first end) of the light-emitting element LD forming each light source unit LSU may be commonly connected to the pixel circuit PXC through an electrode of the light source unit LSU (e.g., the first electrode ET1 (also referred to as the "first pixel electrode" or "first alignment electrode") of each pixel PXL) and connected to the first power supply VDD through the pixel circuit PXC and the first power line PL1. The other end (e.g., the second end) of the light-emitting element LD may be commonly connected to the second power supply VSS through another electrode of the light source unit LSU (e.g., the second electrode ET2 (also referred to as the "second pixel electrode" or "second alignment electrode") of each pixel PXL) and the second power line PL2.

[0100] The light-emitting element LD of the light source unit LSU can emit light having a brightness corresponding to the drive current supplied thereto through the pixel circuit PXC. For example, during each frame period, the pixel circuit PXC can supply a drive current corresponding to the gray value of the data of the corresponding frame to the light source unit LSU. The drive current supplied to the light source unit LSU can be divided into portions flowing through the light-emitting elements LD connected in the forward direction. Accordingly, each of the light-emitting elements LD can emit light having a brightness corresponding to the current applied thereto, such that the light source unit LSU can emit light having a brightness corresponding to the drive current.

[0101] In an embodiment, the light source unit LSU can include at least one ineffective light source in addition to the light-emitting elements LD forming each effective light source. For example, at least one reverse light-emitting element LDrv can also be connected between the first electrode ET1 and the second electrode ET2 of the light source unit LSU.

[0102] Each reverse light-emitting element LDrv can be connected in parallel with the light-emitting elements LD forming the effective light source between the first electrode ET1 and the second electrode ET2, and can be connected between the first electrode ET1 and the second electrode ET2 in a direction opposite to that of the light-emitting element LD. For example, the second end (e.g., N-type end) of the reverse light-emitting element LDrv can be connected to the first power supply VDD via the first electrode ET1 and the pixel circuit PXC. The first end (e.g., P-type end) of the reverse light-emitting element LDrv can be connected to the second power supply VSS via the second electrode ET2. Even when a predetermined drive voltage (e.g., a drive voltage in the forward direction) is applied between the first electrode ET1 and the second electrode ET2, the reverse light-emitting element LDrv remains deactivated. Accordingly, current substantially does not flow through the reverse light-emitting element LDrv.

[0103] The pixel circuit PXC can be connected to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, if the pixel PXL is provided on the i-th (i is a natural number) horizontal line (row) and the j-th (j is a natural number) vertical line (column) of the display area DA, the pixel circuit PXC of the pixel PXL can be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. In an embodiment, the pixel circuit PXC can include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0104] The first transistor T1 (also referred to as "the drive transistor of the pixel PXL") is connected between the first power supply VDD and the light source unit LSU. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 can control the drive current to be supplied to the light source unit LSU in response to the voltage of the first node N1.

[0105] The second transistor T2 may be connected between the data line Dj and the first node N1. The gate electrode of the second transistor T2 is connected to the scan line Si. In the case where a scan signal having a gate-on voltage (e.g., a low-level voltage) is supplied from the scan line Si, the second transistor T2 may be turned on to electrically connect the first node N1 to the data line Dj.

[0106] During each frame period, the data signal DSj corresponding to the frame is supplied to the data line Dj, and the data signal DSj is transmitted to the first node N1 through the second transistor T2 that is turned on during the period when a scan signal SSi having a gate-on voltage is supplied therein. Thus, a voltage corresponding to the data signal DSj is charged into the storage capacitor Cst.

[0107] One electrode of the storage capacitor Cst is connected to the first power supply VDD, and the other electrode of the storage capacitor Cst is connected to the first node N1. During each frame period, the storage capacitor Cst can be charged with a voltage corresponding to the data signal DSj to be supplied to the first node N1.

[0108] Although in Figure 6a it has been shown that the transistors (e.g., the first transistor T1 and the second transistor T2) included in the pixel circuit PXC are formed of P-type transistors, the present disclosure is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0109] For example, as shown in Figure 6b both the first transistor T1 and the second transistor T2 may be formed of N-type transistors. In this case, the gate-on voltage of the scan signal SSi for writing the data signal DSj supplied to the data line Dj in each frame period into the pixel PXL may be a high-level voltage (also referred to as "gate high voltage"). Similarly, the voltage of the data signal DSj for turning on the first transistor T1 may be a voltage having a level opposite to that of the Figure 6a embodiment. For example, in the Figure 6b embodiment, when the grayscale value to be represented increases, a data signal DSj having a higher voltage may be supplied. In an embodiment, the first transistor T1 and the second transistor T2 may be different conductive transistors. For example, one of the first transistor T1 and the second transistor T2 may be a P-type transistor, and the other may be an N-type transistor.

[0110] In an embodiment, the interconnection position between the pixel circuit PXC and the light source unit LSU may be changed. For example, as shown in Figure 6bAs shown, when both the first transistor T1 and the second transistor T2 forming the pixel circuit PXC are N-type transistors, the pixel circuit PXC can be connected between the light source unit LSU and the second power supply VSS, and the storage capacitor Cst can be connected between the first node N1 and the second power supply VSS. However, the present disclosure is not limited thereto. For example, in an embodiment, even when the pixel circuit PXC is formed of N-type transistors, the pixel circuit PXC can be connected between the first power supply VDD and the light source unit LSU. Similarly, even when the pixel circuit PXC is formed of N-type transistors, the storage capacitor Cst can be connected between the first node N1 and the first power supply VDD.

[0111] Except that the connection positions of some circuit elements and the voltage levels of control signals (e.g., the scan signal SSi and the data signal DSj) change according to the types of the first transistor T1 and the second transistor T2, Figure 6b the pixel PXL shown in Figure 6a is basically similar in configuration and operation to the pixel PXL of Figure 6b Therefore, a detailed description of the pixel PXL of

[0112] The structure of the pixel circuit PXC is not limited to the embodiments shown in Figure 6a and Figure 6b For example, the configuration of the pixel circuit PXC can be similar to the configuration of the embodiments shown in Figure 6c and Figure 6d In other words, the pixel circuit PXC can be formed of a known pixel circuit, and the known pixel circuit can have various structures and / or operate through various driving schemes.

[0113] Referring to Figure 6c the pixel circuit PXC can also be connected to the sense control line SCLi and the sense line SLj. For example, the pixel circuit PXC of the pixel PXL provided on the i-th horizontal line and the j-th vertical line of the display area DA can be connected to the i-th sense control line SCLi and the j-th sense line SLj of the display area DA. The pixel circuit PXC can also include a third transistor T3. In an embodiment, the sense line SLj can be omitted, and the characteristics of the pixel PXL can be detected by detecting the sense signal SENj via the data line Dj. In this case, the third transistor T3 can be connected to the data line Dj.

[0114] The third transistor T3 is connected between the first transistor T1 and the sense line SLj. For example, a first electrode of the third transistor T3 may be connected to an electrode (e.g., a source electrode) of the first transistor T1 that is connected to the first electrode ET1, and a second electrode of the third transistor T3 may be connected to the sense line SLj. In the case where the sense line SLj is omitted, the second electrode of the third transistor T3 may be connected to the data line Dj.

[0115] In an embodiment, a gate electrode of the third transistor T3 is connected to the sense control line SCLi. In the case where the sense control line SCLi is omitted, the gate electrode of the third transistor T3 may be connected to the scan line Si. During a predetermined sensing period, the third transistor T3 may be turned on by a sense control signal SCSi having a gate-on voltage (e.g., a high-level voltage) supplied to the sense control line SCLi, thereby electrically connecting the sense line SLj to the first transistor T1.

[0116] In an embodiment, the sensing period may be a period in which characteristics (e.g., a threshold voltage of the first transistor T1, etc.) of each of the pixels PXL provided in the display area DA are extracted. During the sensing period, the first transistor T1 may be turned on by supplying a predetermined reference voltage capable of turning on the first transistor T1 to the first node N1 via the data line Dj and the second transistor T2, or by connecting each pixel PXL to a current source, etc. In addition, the third transistor T3 may be turned on by supplying a sense control signal SCSi having a gate-on voltage to the third transistor T3, such that the first transistor T1 may be connected to the sense line SLj. Thereafter, a sense signal SENj may be obtained through the sense line SLj, and characteristics including a threshold voltage of the first transistor T1, etc. of each pixel PXL may be detected using the sense signal SENj. Information regarding the characteristics of each pixel PXL may be used to convert image data, such that a deviation in characteristics between the pixels PXL provided in the display area DA may be compensated.

[0117] Although Figure 6c an embodiment is shown in which all of the first transistor T1, the second transistor T2, and the third transistor T3 are N-type transistors, the present disclosure is not limited thereto. For example, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be changed to a P-type transistor. In addition, although Figure 6c an embodiment is shown in which the light source unit LSU is connected between the pixel circuit PXC and the second power supply VSS, the present disclosure is not limited thereto. For example, in an embodiment, the light source unit LSU may be connected between the first power supply VDD and the pixel circuit PXC.

[0118] Refer to Figure 6d, the pixel circuit PXC can be connected not only to the scan line Si of the corresponding horizontal line, but also to at least one other scan line (or control line). For example, the pixel circuit PXC of the pixel PXL disposed on the i-th horizontal line of the display area DA can also be connected to the (i - 1)-th scan line Si-1 and / or the (i + 1)-th scan line Si+1. In an embodiment, the pixel circuit PXC can be connected not only to the first power supply VDD and the second power supply VSS, but also to a third power supply. For example, the pixel circuit PXC can also be connected to the initialization power supply Vint. In an embodiment, the pixel circuit PXC can include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0119] The first transistor T1 can be connected between the first power supply VDD and the light source unit LSU. For example, the first electrode (e.g., source electrode) of the first transistor T1 can be connected to the first power supply VDD through the fifth transistor T5 and the first power line PL1, and the second electrode (e.g., drain electrode) of the first transistor T1 can be connected to the first electrode (e.g., the first pixel electrode of the corresponding pixel PXL) of the light source unit LSU via the sixth transistor T6. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 can control the drive current to be supplied to the light source unit LSU in response to the voltage of the first node N1.

[0120] The second transistor T2 is connected between the data line Dj and the first electrode (e.g., source electrode) of the first transistor T1. The gate electrode of the second transistor T2 is connected to the corresponding scan line Si. When a scan signal SSi having a gate-on voltage is supplied from the scan line Si, the second transistor T2 can be turned on to electrically connect the data line Dj to the first electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal DSj supplied from the data line Dj can be transmitted to the first transistor T1.

[0121] The third transistor T3 can be connected between the second electrode (e.g., drain electrode) of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is connected to the corresponding scan line Si. When a scan signal SSi having a gate-on voltage is supplied from the scan line Si, the third transistor T3 can be turned on to connect the first transistor T1 in a diode form.

[0122] The fourth transistor T4 is connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 is connected to the previous scan line (e.g., the (i - 1)-th scan line Si-1). When a scan signal SSi-1 having a gate-on voltage is supplied to the (i - 1)-th scan line Si-1, the fourth transistor T4 can be turned on so that the voltage of the initialization power supply Vint can be transmitted to the first node N1. In an embodiment, when the first transistor T1 is a P-type transistor, the voltage of the initialization power supply Vint for initializing the gate voltage of the first transistor T1 can be the lowest voltage of the data signal DSj or a voltage lower than that.

[0123] The fifth transistor T5 is connected between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 is connected to the corresponding emission control line (e.g., the i-th emission control line Ei). The fifth transistor T5 can be turned off when an emission control signal ESi having a gate-off voltage (e.g., a high-level voltage) is supplied to the emission control line Ei, and can be turned on in other cases.

[0124] The sixth transistor T6 is connected between the first transistor T1 and the light source unit LSU. The gate electrode of the sixth transistor T6 is connected to the corresponding emission control line (e.g., the i-th emission control line Ei). The sixth transistor T6 is turned off when an emission control signal ESi having a gate-off voltage is supplied to the emission control line Ei, and is turned on in other cases.

[0125] The seventh transistor T7 is connected between the first electrode of the light source unit LSU (e.g., the first pixel electrode ET1 of the corresponding pixel PXL) and the initialization power supply Vint. The gate electrode of the seventh transistor T7 is connected to the scan line for selecting the pixels PXL of the subsequent horizontal line (e.g., the (i + 1)-th scan line Si+1). When a scan signal SSi+1 having a gate-on voltage is supplied to the (i + 1)-th scan line Si+1, the seventh transistor T7 is turned on so that the voltage of the initialization power supply Vint can be supplied to the first electrode of the light source unit LSU (e.g., the first pixel electrode ET1). In this case, during each initialization period in which the voltage of the initialization power supply Vint is transmitted to the light source unit LSU, the voltage of the first electrode of the light source unit LSU can be initialized.

[0126] The control signal for controlling the operation of the seventh transistor T7 can be changed in various ways. For example, in an embodiment, the gate electrode of the seventh transistor T7 can be connected to the scan line of the corresponding horizontal line (i.e., the i-th scan line Si). In this case, when a scan signal SSi having a gate-on voltage is supplied to the i-th scan line Si, the seventh transistor T7 can be turned on, so that the voltage of the initialization power supply Vint can be supplied to the first electrode of the light source unit LSU.

[0127] The storage capacitor Cst is connected between the first power supply VDD and the first node N1. The storage capacitor Cst can store a voltage corresponding to both the data signal DSj applied to the first node N1 during each frame period and the threshold voltage of the first transistor T1.

[0128] Although in Figure 6d all of the transistors (e.g., the first transistor T1 to the seventh transistor T7) included in the pixel circuit PXC have been shown to be formed of P-type transistors, the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 can be changed to an N-type transistor.

[0129] Although Figures 6a to 6d shows an embodiment in which all the effective light sources (i.e., light-emitting elements LD) constituting each light source unit LSU are connected in parallel with each other, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, as shown in Figures 6e to 6g each light source unit LSU of each pixel PXL can be configured to include at least a two-stage series structure. In the following description of the embodiment of Figures 6e to 6g the detailed description of the components (e.g., the pixel circuit PXC) similar or identical to those of the embodiment of Figures 6a to 6d will be omitted.

[0130] Refer to Figure 6e, the light source unit LSU may include at least two light emitting elements connected in series with each other. For example, the light source unit LSU may include a first light emitting element LD1, a second light emitting element LD2, and a third light emitting element LD3. The first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 are connected in series in a forward direction between a first power supply VDD and a second power supply VSS, thereby forming each effective light source. Hereinafter, in the case of representing a specific light emitting element among the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3, the corresponding light emitting element will be referred to as the "first light emitting element LD1", the "second light emitting element LD2", or the "third light emitting element LD3". The term "light emitting element LD" or "plurality of light emitting elements LD" will be used to arbitrarily represent at least one light emitting element among the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3, or to commonly represent the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3.

[0131] A first end (e.g., P-type end) of the first light emitting element LD1 may be connected to the first power supply VDD via a first electrode (i.e., first pixel electrode) ET1 of the light source unit LSU or the like. A second end (e.g., N-type end) of the first light emitting element LD1 may be connected to a first end (e.g., P-type end) of the second light emitting element LD2 through a third electrode (also referred to as "third pixel electrode") ET3. The first end of the second light emitting element LD2 may be connected to the second end of the first light emitting element LD1. A second end (e.g., N-type end) of the second light emitting element LD2 may be connected to a first end (e.g., P-type end) of the third light emitting element LD3 through a fourth electrode (also referred to as "fourth pixel electrode") ET4. Each of the third electrode ET3 and the fourth electrode ET4 may form each intermediate electrode connected between two consecutive series stages. The first end of the third light emitting element LD3 may be connected to the second end of the second light emitting element LD2. A second end (e.g., N-type end) of the third light emitting element LD3 may be connected to the second power supply VSS via a second electrode (i.e., second pixel electrode) ET2 of the light source unit LSU or the like. In this way, the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may be continuously connected in series between the first electrode ET1 and the second electrode ET2 of the light source unit LSU.

[0132] Although an embodiment is shown in Figure 6e where the light emitting element LD is connected to have a three-stage series structure, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, two light emitting elements LD may be connected to have a two-stage series structure, or four or more light emitting elements LD may be connected to have a four-stage or more series structure.

[0133] Assuming that light-emitting elements LD having the same conditions (e.g., the same size and / or quantity) exhibit the same luminance, in a light source unit LSU having a structure in which the light-emitting elements LD are connected in series, compared with a light source unit LSU having a structure in which the light-emitting elements LD are connected in parallel, the voltage to be applied between a first electrode ET1 and a second electrode ET2 can be increased, and the amount of drive current flowing into the light source unit LSU can be decreased. Therefore, when the light source unit LSU of each pixel PXL is formed using a series structure, the panel current flowing through the display panel PNL can be decreased.

[0134] In an embodiment, at least one series stage may include a plurality of light-emitting elements LD connected in parallel with each other. In this case, the light source unit LSU may be formed of a series / parallel combination structure. For example, the light source unit LSU may be configured as shown in the embodiment of Figures 6f to 6g the embodiment.

[0135] Referring to Figure 6f , at least one series stage forming the light source unit LSU may include a plurality of light-emitting elements LD connected in parallel with each other in a forward direction. For example, the light source unit LSU may include at least one first light-emitting element LD1 provided in a first series stage (also referred to as "the first stage" or "the first row"), at least one second light-emitting element LD2 provided in a second series stage (also referred to as "the second stage" or "the second row") behind the first series stage, and at least one third light-emitting element LD3 provided in a third series stage (also referred to as "the third stage" or "the third row") behind the second series stage. At least one of the first series stage, the second series stage, and the third series stage may include a plurality of light-emitting elements LD connected in a forward direction.

[0136] Although a light source unit LSU formed of light-emitting elements LD provided in three series stages has been shown in Figure 6f , the present disclosure is not limited thereto. For example, as shown in Figure 6g , the light source unit LSU may include a plurality of light-emitting elements LD provided in only two series stages (i.e., the first series stage and the second series stage). For example, the light source unit LSU may include at least one first light-emitting element LD1 and at least one second light-emitting element LD2. The at least one first light-emitting element LD1 is provided in the first series stage and includes a first end and a second end respectively connected to the first electrode ET1 and an intermediate electrode IET. The at least one second light-emitting element LD2 is provided in the second series stage and includes a first end and a second end respectively connected to the intermediate electrode IET and the second electrode ET2. At least one of the first series stage and the second series stage may include a plurality of light-emitting elements LD connected in a forward direction.

[0137] In addition, the number of series stages forming the light source unit LSU can be changed in various ways. For example, the light source unit LSU may include a plurality of light emitting elements LD distributed in four or more series stages. In addition, the number of light emitting elements LD connected in the forward direction in each series stage can be changed in various ways. In an embodiment, the number of light emitting elements LD included in the pixels PXL provided in the display area ( Figure 5 DA) can be the same or similar to each other. For example, in the step of supplying the light emitting elements LD to each pixel PXL, the light emitting elements LD can be aligned in such a way that the light emitting element ink (also referred to as "light emitting element solution") including the light emitting elements LD is controlled to be uniformly applied to the emission area of each pixel PXL, and a uniform electric field is controlled to be applied to each pixel PXL. In this way, the light emitting elements LD can be supplied to each pixel PXL relatively uniformly and aligned in each pixel PXL.

[0138] In an embodiment, as Figure 6f and Figure 6g shown, each pixel PXL may further include at least one reverse light emitting element LDrv provided in at least one series stage. For example, at least one of the plurality of series stages may further include at least one reverse light emitting element LDrv connected in a direction opposite to the direction of the light emitting element LD.

[0139] Even when the reverse light emitting element LDrv is connected to at least one series stage, if at least one effective light source (e.g., the first light emitting element LD1, the second light emitting element LD2, and / or the third light emitting element LD3) connected in the forward direction to the series stage is provided, the drive current of the pixel PXL can continuously flow via the series stage. Therefore, the light source unit LSU can emit light with a brightness corresponding to the drive current.

[0140] As described in the foregoing embodiments, each light source unit LSU may include a plurality of light emitting elements LD, which are connected in the forward direction between the first power supply VDD and the second power supply VSS and form corresponding effective light sources. In addition, the connection structure between the light emitting elements LD can be changed in various ways according to the embodiments. For example, the light emitting elements LD can be connected only in series or in parallel with each other, or in a series / parallel combination structure.

[0141] As described above, the pixel PXL may include a pixel circuit PXC and / or a light source unit LSU that can have various structures. The structure applicable to the pixel PXL of the present disclosure is not limited to Figures 6a to 6gThe embodiments shown in [description], and each pixel PXL can have various well-known structures. For example, each pixel circuit PXC can be formed by a well-known pixel circuit, and the well-known pixel circuit can have various structures and / or operate in various driving manners. In the embodiments of the present disclosure, each pixel PXL can be configured in a passive light-emitting display device or the like. In this case, the pixel circuit PXC can be omitted, and each of the first electrode ET1 and the second electrode ET2 of the light source unit LSU can be directly connected to the scan line Si, the data line Dj, the first power line PL1, the second power line PL2, or other signal lines or power lines, etc.

[0142] Figures 7a to 7f are circuit diagrams each showing a pixel PXL according to an embodiment of the present disclosure, and for example, different embodiments of the pixel PXL including a switch unit SWU are shown. For the purpose of illustration, in Figures 7a to 7d the detailed structure illustration of the pixel circuit PXC, which can be implemented in various shapes as an element that can be selectively provided in each pixel PXL, will be omitted. In addition, Figure 7e and Figure 7f show a pixel circuit PXC according to an embodiment (for example, a pixel circuit PXC including a seventh transistor T7 connected to a third power source such as an initialization power source Vint as shown in the embodiment of Figure 6d . In the embodiment, some circuit elements provided in the pixel circuit PXC can be used for applying alignment signals. In the description of the embodiment of Figures 7a to 7f , the same reference numerals will be used to denote components similar or identical to those of the previous embodiment, and their detailed description will be omitted.

[0143] In the description of the embodiments of the present disclosure, the switch unit SWU will be described as being included in each pixel PXL, but the present disclosure is not limited thereto. For example, the switch unit SWU can be connected to each pixel PXL and can be regarded as a separate component provided on the periphery of the pixel PXL.

[0144] Referring to Figures 5 to 7a , a pixel PXL according to an embodiment of the present disclosure can further include a light source unit LSU and a switch unit SWU connected to the light source unit LSU. In addition, the pixel PXL can selectively include a pixel circuit PXC connected between the light source unit LSU and the first power source VDD (or the second power source VSS).

[0145] The pixel circuit PXC may be connected between the first electrode ET1 of the light source unit LSU and the first power line PL1. The position of the pixel circuit PXC may be changed in various ways according to embodiments. For example, in an embodiment, the pixel circuit PXC may be connected between the second electrode ET2 of the light source unit LSU and the second power line PL2. The pixel circuit PXC may supply a driving current corresponding to the data signal DSj to the light source unit LSU during each frame period. During the frame period in which the data signal DSj corresponding to the black gradation is supplied, the pixel circuit PXC may not supply a driving current to the light source unit LSU.

[0146] In an embodiment, the pixel circuit PXC may be a P-type pixel circuit including P-type transistors. However, the present disclosure is not limited thereto. For example, in an embodiment, the pixel circuit PXC may be formed of N-type transistors, or the pixel circuit PXC may include a combination of at least one P-type transistor and at least one N-type transistor.

[0147] The light source unit LSU may include a plurality of light emitting elements LD provided in at least two series stages and at least three electrodes provided to form at least two series stages. For example, in the case where the light source unit LSU is formed of a three-stage series structure or a series / parallel combination structure, the light source unit LSU may include first to fourth electrodes ET1 to ET4 and first, second, and third light emitting elements LD1, LD2, and LD3 connected between the first to fourth electrodes ET1 to ET4.

[0148] The switch unit SWU may include at least one switching element connected to at least one electrode provided in the light source unit LSU. For example, the switch unit SWU may include a first switching element ST1 connected to the fourth electrode ET4 (also referred to as the "first intermediate electrode IET1"), a second switching element ST2 connected to the third electrode ET3 (also referred to as the "second intermediate electrode IET2"), and a third switching element ST3 connected to the first electrode ET1. In an embodiment, the first switching element ST1, the second switching element ST2, and the third switching element ST3 may be driven by the same signal. For example, the first switching element ST1, the second switching element ST2, and the third switching element ST3 may be simultaneously turned on / off by the same switch control signal SWS. In an embodiment, at least one of the first switching element ST1, the second switching element ST2, and the third switching element ST3 may be driven by a different signal.

[0149] Hereinafter, when referring to a specific switching element among the first switching element ST1, the second switching element ST2, and the third switching element ST3, the corresponding switching element will be referred to as the "first switching element ST1", the "second switching element ST2", or the "third switching element ST3". The term "switching element ST" or "plurality of switching elements ST" will be used to arbitrarily represent at least one of the first switching element ST1, the second switching element ST2, and the third switching element ST3, or to represent the first switching element ST1, the second switching element ST2, and the third switching element ST3 together.

[0150] In an embodiment, during the process of manufacturing a display device, in the step of aligning the light-emitting elements LD in the light source unit LSU of each pixel PXL (hereinafter referred to as the "alignment step"), the switching element ST can be simultaneously turned on and used to supply a predetermined alignment signal to each electrode. For example, in the alignment step, the first alignment signal AS1 can be supplied to the second electrode ET2 through the second power line PL2, or the voltage of the second power supply VSS can be transmitted to the second electrode ET2 so that the voltage of the second power supply VSS can be used as the first alignment signal AS1. In addition, the switching element ST can be turned on by supplying a switch control signal SWS having a gate turn-on voltage thereto via the first control line CLI1, so that the second alignment signal AS2, the third alignment signal AS3, and the fourth alignment signal AS4 can be supplied to the fourth electrode ET4, the third electrode ET3, and the first electrode ET1 through the switching element ST, respectively. The first alignment signal AS1 to the fourth alignment signal AS4 can be signals having a voltage difference and / or a phase difference capable of aligning the light-emitting element LD between a pair of electrodes forming each series stage. At least some of the first alignment signal AS1 to the fourth alignment signal AS4 can be AC signals, but the present disclosure is not limited thereto.

[0151] In the case of actually using the display device, a predetermined bias power can be supplied to the switching element ST so that the switching element ST can be kept off. For example, when the display device is actually driven, the first bias voltage VB1 and the second bias voltage VB2 can be supplied to a predetermined electrode and the gate electrode of the switching element ST, respectively, so that the switching element ST can be controlled to be kept off. However, the present disclosure is not limited thereto. For example, even after manufacturing and / or actually using the display device, a predetermined signal can be supplied to each electrode of the light source unit LSU by selectively driving the switching element ST as needed. When the display device is actually driven, a predetermined voltage of the second power supply VSS can be supplied to the second power line PL2. In an embodiment, the second power supply VSS can be a low-potential pixel power supply.

[0152] The first switching element ST1 can be connected between the fourth electrode ET4 and the first line LI1 and is driven by a switching control signal SWS applied to the first control line CLI1. In an embodiment, the first switching element ST1 can be a transistor. The gate electrode of the first switching element ST1 can be connected to the first control line CLI1. For example, when a switching control signal SWS having a gate turn-on voltage (e.g., a low-level voltage) is supplied to the first control line CLI1, the first switching element ST1 can be turned on so that a second alignment signal AS2 supplied through the first line LI1 can be transmitted to the fourth electrode ET4.

[0153] The second switching element ST2 can be connected between the third electrode ET3 and the second line LI2 and is driven by a switching control signal SWS applied to the first control line CLI1. In an embodiment, the second switching element ST2 can be a transistor. The gate electrode of the second switching element ST2 can be connected to the first control line CLI1. For example, when a switching control signal SWS having a gate turn-on voltage is supplied to the first control line CLI1, the second switching element ST2 can be turned on so that a third alignment signal AS3 supplied through the second line LI2 can be transmitted to the third electrode ET3.

[0154] The third switching element ST3 can be connected between the first electrode ET1 and the third line LI3 and is driven by a switching control signal SWS applied to the first control line CLI1. In an embodiment, the third switching element ST3 can be a transistor. The gate electrode of the third switching element ST3 can be connected to the first control line CLI1. For example, when a switching control signal SWS having a gate turn-on voltage is supplied to the first control line CLI1, the third switching element ST3 can be turned on so that a fourth alignment signal AS4 supplied through the third line LI3 can be transmitted to the first electrode ET1.

[0155] In an embodiment, each of the switching elements ST can be a transistor of the same type as at least one transistor forming the pixel circuit PXC. In addition, the switching elements ST can be transistors of different types. For example, when the pixel circuit PXC is formed of P-type transistors, each of the switching elements ST can be formed of P-type transistors. In this case, the pixel circuit PXC and the switching unit SWU can be formed simultaneously on the same layer, so that the process of manufacturing the display device can be simplified. Here, the type, structure, and / or position of each of the switching elements ST can be changed in various ways according to embodiments. For example, in an embodiment, some of the switching elements ST can have different types and / or structures or be arranged on different layers.

[0156] The first line LI1 is connected between the first pad P1 and the first switching element ST1. The first line LI1 can transmit a predetermined power and / or signal applied to the first pad P1 to the first switching element ST1.

[0157] The second line LI2 is connected between the second pad P2 and the second switching element ST2. The second line LI2 can transmit a predetermined power and / or signal applied to the second pad P2 to the second switching element ST2.

[0158] The third line LI3 is connected between the third pad P3 and the third switching element ST3. The third line LI3 can transmit a predetermined power and / or signal applied to the third pad P3 to the third switching element ST3.

[0159] The first control line CLI1 is connected between the control pad CP and the control electrode of the switching element ST (e.g., the corresponding gate electrode of the switching element ST). The first control line CLI1 can transmit a predetermined power and / or signal applied to the control pad CP to the switching element ST.

[0160] The first pad P1 is connected to the first switching element ST1 through the first line LI1. When manufacturing or actually using a display device (e.g., a display panel PNL), a predetermined power and / or signal can be supplied to the first pad P1. For example, during the alignment step in the process of manufacturing the display panel PNL, a second alignment signal AS2 can be applied to the first pad P1. When actually using the display panel PNL, a predetermined bias signal (e.g., the first bias voltage VB1) can be applied to the first pad P1.

[0161] The second pad P2 is connected to the second switching element ST2 through the second line LI2. When manufacturing or actually using a display panel PNL, a predetermined power and / or signal can be supplied to the second pad P2. For example, during the alignment step in the process of manufacturing the display panel PNL, a third alignment signal AS3 can be applied to the second pad P2. When actually using the display panel PNL, a predetermined bias signal (e.g., the first bias voltage VB1) can be applied to the second pad P2.

[0162] The third pad P3 is connected to the third switching element ST3 through the third line LI3. When manufacturing or actually using a display panel PNL, a predetermined power and / or signal can be supplied to the third pad P3. For example, during the alignment step in the process of manufacturing the display panel PNL, a fourth alignment signal AS4 can be applied to the third pad P3. When actually using the display panel PNL, a predetermined bias signal (e.g., the first bias voltage VB1) can be applied to the third pad P3.

[0163] The control pad CP is connected to the gate electrode of the switching element ST through the first control line CLI1. When manufacturing or actually using the display panel PNL, a predetermined power and / or signal can be supplied to the control pad CP. For example, in the alignment step of the process for manufacturing the display panel PNL, a switching control signal SWS for turning on the switching element ST during a predetermined period can be applied to the control pad CP. When actually using the display panel PNL, a predetermined bias signal (e.g., the second bias voltage VB2) can be applied to the control pad CP. In an embodiment, the bias signal (e.g., the first bias voltage VB1 and / or the second bias voltage VB2) to be supplied to the switching element ST can be a signal for keeping the switching element ST off.

[0164] Hereinafter, in order to denote a specific pad among the first pad P1 to the third pad P3 and the control pad CP, the corresponding pad will be referred to as the "first pad P1", the "second pad P2", the "third pad P3", or the "control pad CP". The term "pad P" or "a plurality of pads P" will be used to arbitrarily denote at least one pad among the first pad P1 to the third pad P3 and the control pad CP or to commonly denote the first pad P1 to the third pad P3 and the control pad CP.

[0165] In an embodiment, in order to simultaneously form a plurality of display panels PNL, the pads P can be provided in the non-display area NDA of each display panel PNL and / or in the peripheral area on each mother substrate. In addition, each pad P can be commonly connected to a plurality of first lines LI1, a plurality of second lines LI2, a plurality of third lines LI3, or a plurality of first control lines CLI1 provided on a plurality of horizontal lines of the corresponding display panel PNL.

[0166] For example, the first pad P1 can be commonly connected to a plurality of first lines LI1 provided on the horizontal lines of the corresponding display panel PNL. The second pad P2 can be commonly connected to a plurality of second lines LI2 provided on the horizontal lines of the display panel PNL. Similarly, the third pad P3 can be commonly connected to a plurality of third lines LI3 provided on the horizontal lines of the display panel PNL. The control pad CP can be commonly connected to a plurality of first control lines CLI1 provided on the horizontal lines of the display panel PNL. Therefore, the predetermined power or signal applied to each pad P can be commonly transmitted to any group of lines among the first line LI1, the second line LI2, the third line LI3, and the first control line CLI1.

[0167] As Figure 7bAs shown, the light source unit LSU may include a plurality of light emitting elements LD arranged in only two series stages (i.e., the first series stage and the second series stage). For example, the light source unit LSU may include a first electrode ET1, a second electrode ET2, and an intermediate electrode IET disposed between the first electrode ET1 and the second electrode ET2. At least one first light emitting element LD1 and at least one second light emitting element LD2 may be connected between the first electrode ET1 and the intermediate electrode IET and between the intermediate electrode IET and the second electrode ET2, respectively.

[0168] In the foregoing embodiment, the switch unit SWU may include only two switch elements ST. For example, the switch unit SWU may include a first switch element ST1 connected between the intermediate electrode IET and the first line LI1 and a second switch element ST2 connected between the first electrode ET1 and the second line LI2.

[0169] In an embodiment, the first switch element ST1 and the second switch element ST2 may be driven by a switch control signal SWS supplied to the first control line CLI1. For example, when a switch control signal SWS having a gate turn-on voltage is supplied to the first control line CLI1, the first switch element ST1 and the second switch element ST2 may be turned on so that a second alignment signal AS2 and a third alignment signal AS3 (or a first bias voltage VB1) may be supplied to the intermediate electrode IET and the first electrode ET1, respectively.

[0170] Referring to Figure 7c, the third switching element ST3 can be connected between the first electrode ET1 and the second electrode ET2 and conduct simultaneously with the first switching element ST1 and the second switching element ST2. For example, one electrode of the third switching element ST3 can be connected to the first electrode ET1, and the other electrode of the third switching element ST3 can be connected to the second power line PL2 together with the second electrode ET2. The gate electrode of the third switching element ST3 can be connected to the first control line CLI1. When a switching control signal SWS having a gate turn-on voltage is supplied to the first control line CLI1, the third switching element ST3 can be turned on so that the voltage of the second power supply VSS (or the first alignment signal AS1) supplied through the second power line PL2 can be transmitted to the first electrode ET1. In this case, in the alignment step, substantially the same voltage can be transmitted to the first electrode ET1 and the second electrode ET2. Here, an alignment signal (e.g., the second alignment signal AS2 and / or the third alignment signal AS3) having a voltage and / or phase different from the voltage and / or phase of the first electrode ET1 and the second electrode ET2 can be supplied to at least one intermediate electrode (e.g., the third electrode ET3 and / or the fourth electrode ET4) provided between the first electrode ET1 and the second electrode ET2. Thus, an electric field sufficient to align the light-emitting element LD can be formed between a pair of electrodes forming each series stage.

[0171] According to the foregoing embodiment, the number of lines and / or pads P connected to the pixel PXL can be reduced. For example, compared with an embodiment in which the structure of the light source unit LSU is substantially the same as the structure of the foregoing embodiment Figure 7a , the third line LI3 and the third pad P3 can be removed. In addition, by using only alignment signals whose number is smaller than the number of electrodes forming the light source unit LSU, an electric field can be formed between the electrodes of each series stage so that the light-emitting element LD can be aligned by the electric field.

[0172] Referring to Figure 7d , even in the case where the light source unit LSU shown in the embodiment of Figure 7b includes a plurality of light-emitting elements LD provided in only two series stages (i.e., the first series stage and the second series stage), the number of lines and / or pads P connected to the pixel PXL can also be reduced in a manner similar to that of the embodiment of Figure 7c . For example, the second switching element ST2 can be connected between the first electrode ET1 and the second electrode ET2. Thus, compared with the embodiment of Figure 7b , the second line LI2 and the second pad P2 can be removed, and an electric field can be formed between the electrodes of each series stage with only a smaller number of alignment signals.

[0173] Referring to Figure 7e and Figure 7f, instead of a structure in which a separate switching element is connected to the first electrode ET1 to apply an alignment signal to the first electrode ET1, at least one transistor provided in the pixel circuit PXC can be used to apply the alignment signal to the first electrode ET1. For example, in the alignment step, the first electrode ET1 can be connected to the initialization power supply Vint by driving the seventh transistor T7 of each pixel PXL, and the voltage of the initialization power supply Vint can be used as the alignment signal (e.g., the third alignment signal AS3 or the fourth alignment signal AS4) to be applied to the first electrode ET1. For example, in the alignment step, by commonly supplying a scan signal having a gate-on voltage (or a control signal having a gate-on voltage) to the scan lines provided in the display area DA (or a separate control line connected to the seventh transistor T7), the voltage of the initialization power supply Vint can be transmitted to the first electrode ET1 of the pixel PXL. In the alignment step, an emission control signal having a gate-off voltage can be commonly supplied to the emission control lines provided in the display area DA. Therefore, the influence of the pixel circuit PXC on the alignment process can be minimized. According to Figure 7e and Figure 7f 's embodiments, the structure of the switch unit SWU can be simplified, and the number of alignment signals can be reduced.

[0174] As Figures 7a to 7f shown in the embodiments of, if the switching element ST is connected between the line for applying the alignment signal to the pixel PXL (e.g., it can be at least some of the first line LI1 to the third line LI3 and the first control line CLI1, and are collectively referred to as "alignment lines") and at least one electrode of the light source unit LSU forming each pixel PXL, the connection between the pixel PXL and the alignment lines can be controlled as needed. For example, during the process of aligning the light-emitting elements LD in each pixel PXL, each switching element ST can be turned on so that a predetermined alignment signal can be applied to each light source unit LSU of each pixel PXL. During other periods, the switching element ST can be kept off so that the alignment lines can be isolated from the light source units LSU of each pixel PXL. Therefore, the pixels PXL can be separated from each other to have a shape that can be individually driven without performing an etching process for separating the alignment lines. Therefore, according to the above embodiments, the process of manufacturing a display device (specifically, the display panel PNL) can be further simplified.

[0175] For example, in a comparative embodiment where the switch unit SWU is not provided, the first electrode ET1 of the pixel PXL and the intermediate electrodes of each series stage can be commonly connected to a plurality of pixels PXL and supplied with corresponding alignment signals, and the pixels PXL need to be disconnected from each other so that the pixels PXL can be individually driven after the alignment process is completed. Therefore, after the alignment process is completed, a mask process or the like for separating the alignment lines needs to be performed. However, according to the embodiments of the present disclosure described above, the switch unit SWU can be used to control the connection between each pixel PXL and the alignment lines, so that the etching process for separating the alignment lines can be omitted.

[0176] Although embodiments of the pixel PXL including a light source unit LSU provided with at least two series stages have been described in Figures 7a to 7f , the present disclosure is not limited thereto. For example, the pixel PXL can include a light source unit LSU having a parallel structure as disclosed in the embodiment of Figures 6a to 6d and a switch unit SWU connected between a predetermined alignment line and any one of the first electrode ET1 and the second electrode ET2 of the light source unit LSU. For example, in the embodiment of Figure 7f , the intermediate electrode IET can be removed, all of the light emitting elements LD can be connected in parallel between the first electrode ET1 and the second electrode ET2, and the first switching element ST1 can be connected between the first line LI1 and the first electrode ET1 so that the second alignment signal AS2 can be supplied to the first electrode ET1. In this case, since the first switching element ST1 is used to control the connection between the first line LI1 and the first electrode ET1, the etching process for separating the first line LI1 can also be omitted.

[0177] Figures 8a to 8c Each shows an example of an alignment signal according to an embodiment of the present disclosure. Figures 8a to 8c Shows various embodiments related to the first alignment signal AS1 to the fourth alignment signal AS4 for forming a light source unit LSU having a three-stage structure. Here, the number and / or type of the alignment signals can be changed in various ways according to the structure of the light source unit LSU and the like.

[0178] First, referring to Figures 7a to 8a , the first alignment signal AS1 to the fourth alignment signal AS4 can be respectively supplied to the second electrode ET2, the fourth electrode ET4, the third electrode ET3, and the first electrode ET1 of the light source unit LSU. Therefore, an electric field can be formed between the electrodes of each series stage, so that the light emitting element LD can be aligned between the electrodes.

[0179] Some of the first alignment signal AS1 to the fourth alignment signal AS4 may be AC signals, and the other signals may be DC signals. For example, each of the first alignment signal AS1 to the third alignment signal AS3 may be an AC signal, and the fourth alignment signal AS4 may be a DC signal. However, the present disclosure is not limited thereto. For example, in an embodiment, all of the first alignment signal AS1 to the fourth alignment signal AS4 may be AC signals.

[0180] In an embodiment, the first alignment signal AS1 to the third alignment signal AS3 may be signals having the same amplitude and having a phase difference. For example, the second alignment signal AS2 and the third alignment signal AS3 may be signals generated by phase-modulating the first alignment signal AS1 using a phase shifter (e.g., by continuously delaying the phase). The fourth alignment signal AS4 may be a DC signal having a predetermined potential (e.g., a ground potential). In this case, a voltage difference is caused between the first electrode ET1 to the fourth electrode ET4 by the first alignment signal AS1 to the fourth alignment signal AS4, so that an electric field can be formed between the first electrode ET1 to the fourth electrode ET4.

[0181] Refer to Figure 8b , the second alignment signal AS2 and the third alignment signal AS3 may be signals having the same amplitude and having a phase difference. Each of the first alignment signal AS1 and the fourth alignment signal AS4 may be a DC signal having a predetermined potential. For example, the first alignment signal AS1 and the fourth alignment signal AS4 may both be DC signals having a ground potential and may be substantially the same signal. Since at least one intermediate electrode (e.g., the third electrode ET3 and the fourth electrode ET4) is provided between the first electrode ET1 and the second electrode ET2 to which the first alignment signal AS1 and the fourth alignment signal AS4 are applied, an electric field can be formed between the electrodes of each series stage even when the first alignment signal AS1 and the fourth alignment signal AS4 have the same voltage level. In addition, in an embodiment, the fourth alignment signal AS4 may not be required. For example, in Figure 7c and Figure 7d embodiment cases, the first alignment signal AS1 may be applied to the first electrode ET1 and the second electrode ET2 in the same manner. In Figure 7e and Figure 7f embodiment cases, the voltage of the initialization power supply Vint may be used as the third alignment signal AS3 or the fourth alignment signal AS4.

[0182] Refer to Figure 8c, the first alignment signal AS1 to the third alignment signal AS3 may be signals with different amplitudes. For example, the second alignment signal AS2 and the first alignment signal AS1 may be signals generated by amplitude-modulating the third alignment signal AS3 using a level shifter (e.g., by continuously expanding the amplitude). The fourth alignment signal AS4 may be a DC signal having a predetermined potential (e.g., ground potential). In this case, voltage differences are caused between the first electrode ET1 to the fourth electrode ET4 by the first alignment signal AS1 to the fourth alignment signal AS4, so that an electric field can also be formed between the first electrode ET1 to the fourth electrode ET4.

[0183] As referred to Figures 8a to 8c above, the alignment signals can be generated by various schemes. In addition, multiple alignment signals can be generated by using any one of the embodiments of Figures 8a to 8c alone or by using a combination of at least two of the embodiments of Figures 8a to 8c . For example, multiple AC-type alignment signals can be generated by phase modulation and / or amplitude modulation. In addition, in an embodiment, a DC-type alignment signal (e.g., the fourth alignment signal AS4) can be applied to at least one electrode (e.g., at least the first electrode ET1), so that the characteristics of the pixel circuit PXC can be prevented from affecting the alignment of the light-emitting element LD.

[0184] Figures 9a to 9d are respectively plan views of a pixel PXL according to an embodiment of the present disclosure. In an embodiment, the pixels PXL provided in the display area ( Figure 5 DA) may have substantially the same or similar structures.

[0185] In an embodiment, Figures 9a to 9d shows the structure of the pixel PXL, focusing on the light source unit LSU and the switch unit SWU of the pixel PXL according to each embodiment. For example, Figure 9a and Figure 9b show embodiments of the planar structures of the light source unit LSU and the switch unit SWU that can be respectively provided in the pixel PXLs of Figure 7a and Figure 7b .

[0186] In an embodiment, the pixel PXL may further include forming each pixel circuit (e.g., according to Figures 6a to 7dcircuit elements of the pixel circuit PXC) in any one of the embodiments. In an embodiment, the circuit elements may be disposed on a layer different from the layer of the light source unit LSU. For example, the circuit elements may be disposed in a circuit layer (also referred to as a "pixel circuit layer") on one surface of the substrate layer BSL, and the light source unit LSU may be disposed in a display layer disposed on the circuit layer. In addition, at least some elements of the switch unit SWU may be formed simultaneously on the same layer as the layer of the circuit elements. For example, the active layer of each of the switching elements ST may be formed simultaneously on the same layer as the semiconductor layer (also referred to as the "active layer") of the transistor forming the pixel circuit PXC.

[0187] Referring to Figure 7a and Figure 9a , the pixel PXL may include a plurality of electrodes and a plurality of light emitting elements LD disposed in the emission region EMA, and a plurality of alignment lines may be disposed near the pixel PXL. In addition, the pixel PXL may further include a switch unit SWU connected between at least some of the electrodes and the alignment lines.

[0188] Specifically, each pixel PXL may include a first electrode ET1 and a second electrode ET2 disposed at positions spaced apart from each other in the emission region EMA, and at least one intermediate electrode (e.g., a third electrode ET3 and a fourth electrode ET4) disposed between the first electrode ET1 and the second electrode ET2. For example, the first electrode ET1, the at least one intermediate electrode, and the second electrode ET2 may be continuously arranged in one direction in each emission region EMA. The pixel PXL may include a plurality of light emitting elements LD connected between a pair of adjacent electrodes among the first electrode ET1, the second electrode ET2, and the at least one intermediate electrode. In an embodiment, the emission region EMA may be surrounded by an opaque bank structure (e.g., a pixel defining layer) not shown.

[0189] Hereinafter, in the case of representing a specific electrode among the electrodes (e.g., the first electrode ET1 to the fourth electrode ET4) disposed in the emission region EMA, the corresponding electrode will be referred to as the "first electrode ET1", the "second electrode ET2", the "third electrode ET3", or the "fourth electrode ET4". The term "electrode ET" or "a plurality of electrodes ET" will be used to arbitrarily represent at least one of the first electrode ET1 to the fourth electrode ET4 or to commonly represent the electrodes.

[0190] In an embodiment, the first electrode ET1, the third electrode ET3, the fourth electrode ET4, and the second electrode ET2 may be continuously arranged in the emission area EMA in the first direction DR1 in the mentioned order, and each may extend along the second direction DR2. For example, the first electrode ET1, the third electrode ET3, the fourth electrode ET4, and the second electrode ET2 may each have a rod shape extending along the second direction DR2 and may be continuously arranged in the first direction DR1. In an embodiment, the first direction DR1 may refer to the horizontal direction (or X-axis direction), and the second direction DR2 may refer to the vertical direction (or Y-axis direction), but these may be changed in various ways. For example, in an embodiment, the first direction DR1 and the second direction DR2 may refer to the vertical direction or the horizontal direction respectively, or at least one of the first direction DR1 and the second direction DR2 may refer to the diagonal direction. In an embodiment, at least one region of the electrode ET may have a curved shape (such as a circular shape or an oval shape), and the electrode ET may be arranged in a spiral shape or a concentric circular shape. In other words, the shape and the mutual arrangement structure of the electrode ET may be changed in various ways according to the embodiment.

[0191] In an embodiment, the electrodes ET may be spaced apart from each other at regular intervals. In this case, a uniform electric field may be formed between the electrodes ET, so that the light-emitting elements LD may be more uniformly arranged in the emission area EMA. Here, the intervals between the electrodes ET may be changed in various ways according to the embodiment. For example, in order to densely arrange the light-emitting elements LD in a specific area of the emission area EMA, at least a pair of electrodes spaced apart from each other at an interval compact compared with the intervals in other areas may be arranged in the specific area.

[0192] A pair of adjacent electrodes among the electrodes ET may form the electrodes of each series stage. For example, the first electrode ET1 and the third electrode ET3 may form the electrodes of the first series stage. The third electrode ET3 and the fourth electrode ET4 may form the electrodes of the second series stage. The fourth electrode ET4 and the second electrode ET2 may form the electrodes of the third series stage. Although in the present embodiment, the light source unit LSU has been described as having a structure in which two consecutive series stages share an intermediate electrode, the electrodes of two consecutive series stages may be separated from each other.

[0193] The first electrode ETl can be connected to the first power supply VDD via the first contact hole CHl, the pixel circuit PXC, and / or the first power line PLl, etc. For example, a region of the first electrode ET1 can protrude outside the emission region EMA, and a protruding region can be connected to the first power line PL1 through the first contact hole CH1 and a predetermined circuit element formed under (or below) the first electrode ET1 (for example, at least one transistor of the pixel circuit PXC forming the corresponding pixel PXL). In an embodiment, the first contact hole CH1 can be provided in the emission region EMA. In an embodiment, the first electrode ET1 can be directly connected to the first power line PL1, a predetermined signal line, etc., without passing through the first contact hole CH1 and / or a circuit element, etc.

[0194] During the process of manufacturing the display device, in the step of aligning the light-emitting element LD, a predetermined alignment signal (for example, the fourth alignment signal AS4) can be supplied to the first electrode ET1 through the switch unit SWU, etc. During the driving period when the display device is actually used, the first electrode ET1 can be connected to the first power supply VDD through the pixel circuit PXC, etc.

[0195] The second electrode ET2 can be connected to the second power supply VSS via the connection electrode CNL, the second contact hole CH2, and / or the second power line PL2, etc. For example, the second electrode ET2 can be integrally or non-integrally connected to the connection electrode CNL, and can be connected to the second power line PL2 formed under the second electrode ET2 through the connection electrode CNL and the second contact hole CH2. In an embodiment, when the second electrode ET2 is integrally connected to the connection electrode CNL, the second electrode ET2 and the connection electrode CNL can be regarded as different regions of a single electrode respectively. In an embodiment, the second electrode ET2 can be directly connected to the second power line PL2, a predetermined signal line, etc., without passing through the connection electrode CNL and / or the second contact hole CH2, etc.

[0196] During the process of manufacturing the display device, in the step of aligning the light-emitting element LD, a predetermined alignment signal (for example, the voltage of the second power supply VSS or a predetermined first alignment signal AS1) can be supplied to the second electrode ET2 through the second power line PL2, etc. During the driving period when the display device is actually used, the second electrode ET2 can be connected to the second power supply VSS.

[0197] In an embodiment, the connection electrode CNL may be commonly connected to a plurality of pixels PXL. For example, the connection electrode CNL may be commonly connected to the pixels PXL disposed on at least one horizontal line. In this case, the second electrodes ET2 of the pixels PXL may be connected to each other. In an embodiment, the connection electrode CNL may be disposed outside the emission area EMA of each pixel PXL, but the present disclosure is not limited thereto. For example, in an embodiment, at least one area of the connection electrode CNL may be disposed in the emission area EMA of each pixel PXL.

[0198] The third electrode ET3 and the fourth electrode ET4 may be continuously disposed between the first electrode ET1 and the second electrode ET2, and may form each intermediate electrode. For example, the third electrode ET3 and the fourth electrode ET4 may be disposed at positions spaced apart from each other between the first electrode ET1 and the second electrode ET2, and may be continuously connected between the first electrode ET1 and the second electrode ET2 by the light-emitting element LD.

[0199] During the process of manufacturing the display device, in the step of aligning the light-emitting element LD, a predetermined alignment signal (e.g., a second alignment signal and a third alignment signal) may be supplied to the third electrode ET3 and the fourth electrode ET4 through a switching unit SWU or the like. During the driving period for actual use of the display device, the third electrode ET3 and the fourth electrode ET4 may be electrically connected between the first electrode ET1 and the second electrode ET2 by the light-emitting element LD.

[0200] The light-emitting element LD may be connected between a pair of adjacent electrodes. For example, at least one first light-emitting element LD1 may be connected between the first electrode ET1 and the third electrode ET3. Similarly, at least one second light-emitting element LD2 may be connected between the third electrode ET3 and the fourth electrode ET4, and at least one third light-emitting element LD3 may be connected between the fourth electrode ET4 and the second electrode ET2.

[0201] In an embodiment, each light-emitting element LD may be a light-emitting element made of a material having an inorganic crystal structure and having an ultra-small size (e.g., ranging from the nanoscale to the microscale). For example, each light-emitting element LD may be an ultra-small rod-shaped light-emitting element having a size ranging from the nanoscale to the microscale as shown in Figures 1a to 3b The size, type, shape, etc. of the light-emitting element LD may be changed in various ways. For example, in an embodiment, each light-emitting element LD may be a light-emitting element having a core-shell structure and manufactured by a growth process. Although the light-emitting element having a core-shell structure is a micro light-emitting element having a size ranging from the nanoscale to the microscale, the present disclosure is not limited thereto.

[0202] Although in Figure 9aIn the embodiments, each light-emitting element LD has been shown to be uniformly horizontally disposed in the first direction DR1, but the present disclosure is not limited thereto. For example, at least one of the light-emitting elements LD may be arranged and / or connected diagonally or the like between a pair of electrodes forming each series stage. In an embodiment, at least one light-emitting element that is not completely connected in the forward direction between a pair of electrodes may also be provided in the emission area EMA.

[0203] In an embodiment, the light-emitting element LD may be prepared in a form of diffusion in a predetermined solution and then supplied to each pixel area (e.g., the emission area EMA of each pixel PXL). In an embodiment, the light-emitting element LD may be supplied to each pixel area by an inkjet scheme, a slit coating scheme, or various other schemes. For example, the light-emitting element LD may be mixed with a volatile solvent and supplied to each emission area EMA. Here, if a corresponding alignment signal (or alignment voltage) is applied to the electrode ET, an electric field may be formed between a pair of adjacent electrodes. Accordingly, the light-emitting element LD is aligned between the electrodes ET. After the light-emitting element LD has been aligned, the solvent may be removed by a volatilization scheme or other schemes. In this manner, the light-emitting element LD may be reliably provided in each pixel PXL.

[0204] Each first light-emitting element LD1 may include a first end EP1 (e.g., P-type end) connected to the first electrode ET1 and a second end EP2 (e.g., N-type end) connected to the third electrode ET3. In an embodiment, the first end EP1 of the first light-emitting element LD1 may be in direct contact with the first electrode ET1 and thus connected to the first electrode ET1, or may be connected to the first electrode ET1 through a separate contact electrode (or conductive pattern). Similarly, the second end EP2 of the first light-emitting element LD1 may be in direct contact with the third electrode ET3 and thus connected to the third electrode ET3, or may be connected to the third electrode ET3 through a separate contact electrode (or conductive pattern).

[0205] Each second light-emitting element LD2 may include a first end EP1 (e.g., P-type end) connected to the third electrode ET3 and a second end EP2 (e.g., N-type end) connected to the fourth electrode ET4. In an embodiment, the first end EP1 of the second light-emitting element LD2 may be in direct contact with the third electrode ET3 and thus connected to the third electrode ET3, or may be connected to the third electrode ET3 through a separate contact electrode (or conductive pattern). Similarly, the second end EP2 of the second light-emitting element LD2 may be in direct contact with the fourth electrode ET4 and thus connected to the fourth electrode ET4, or may be connected to the fourth electrode ET4 through a separate contact electrode (or conductive pattern).

[0206] Each third light-emitting element LD3 may include a first end EP1 (e.g., a P-type end) connected to a fourth electrode ET4 and a second end EP2 (e.g., an N-type end) connected to a second electrode ET2. In an embodiment, the first end EP1 of the third light-emitting element LD3 may be in direct contact with and thus connected to the fourth electrode ET4, or may be connected to the fourth electrode ET4 through a separate contact electrode (or conductive pattern). Similarly, the second end EP2 of the third light-emitting element LD3 may be in direct contact with and thus connected to the second electrode ET2, or may be connected to the second electrode ET2 through a separate contact electrode (or conductive pattern).

[0207] A plurality of alignment lines spaced apart from each other may be provided near each pixel PXL. For example, a first control line CLI1 and first to third lines LI1 to LI3 may be provided near each pixel PXL. For example, the first control line CLI1 and the first to third lines LI1 to LI3 may be continuously provided on the upper side of the emission area EMA of the pixel PXL. The respective positions and mutual arrangement structures of the first control line CLI1 and the first to third lines LI1 to LI3 may be changed in various ways according to the embodiment.

[0208] The first to third lines LI1 to LI3 may be connected to at least one adjacent pixel PXL through a switching unit SWU. The first control line CLI1 may be provided near the first to third lines LI1 to LI3. In an embodiment, a predetermined area of the first control line CLI1 may form a control electrode (e.g., a gate electrode) of each of the switching elements ST forming the switching unit SWU. In this case, the first control line CLI1 may be regarded as being connected to the pixel PXL including the switching element ST.

[0209] In an embodiment, at least one of the alignment lines may be repeatedly provided on each horizontal line on which a plurality of pixels PXL are provided. For example, at least one alignment line may extend in a first direction DR1 parallel to each horizontal line and be commonly connected to a plurality of pixels PXL provided on the corresponding horizontal line. In an embodiment, at least one of the alignment lines may be provided with a structure such that pixels PXL provided on a plurality of adjacent (e.g., consecutive) horizontal lines share at least one alignment line.

[0210] In an embodiment, a region of at least one of the alignment lines may be provided in a pixel region in which adjacent pixels PXL are formed (e.g., a region including not only the emission area EMA of each pixel PXL but also a pixel circuit region of a pixel circuit PXC in which the pixel PXL is formed), but the present disclosure is not limited thereto. For example, in an embodiment, the alignment lines may be provided between the pixels PXL without passing through each pixel region.

[0211] The alignment lines can each be provided on the same or a different layer from the layers of the first electrode ET1 to the fourth electrode ET4. For example, in an embodiment, the alignment lines can be provided on the same layer as the layers of the first electrode ET1 to the fourth electrode ET4. In an embodiment, the alignment lines can be provided in the circuit layer of the pixel circuit PXC in which each of the pixels PXL is formed. For example, the alignment lines can be provided on the same layer as the layer of the first transistor electrode and the second transistor electrode (e.g., source electrode and drain electrode) of the transistor forming each pixel circuit PXC or the gate electrode of the transistor. In an embodiment, some of the alignment lines can be provided on the same layer as the layers of the first electrode ET1 to the fourth electrode ET4, and some of the other alignment lines can be provided in the circuit layer.

[0212] The switch unit SWU can include at least one switching element ST connected to at least one electrode ET provided in the emission area EMA. For example, the switch unit SWU can include a first switching element ST1, a second switching element ST2, and a third switching element ST3 respectively connected to the fourth electrode ET4, the third electrode ET3, and the first electrode ET1.

[0213] The first switching element ST1 can be connected between the fourth electrode ET4 (the first intermediate electrode IET1) and the first line LI1. For example, the first switching element ST1 can include a first active layer ACT1 electrically connected between the fourth electrode ET4 and the first line LI1, and a predetermined area of the first active layer ACT1 overlaps with the first control line CLI1. In this case, the predetermined area of the first control line CLI1 that overlaps with the first active layer ACT1 can form the gate electrode of the first switching element ST1. The first switching element ST1 can be controlled by a signal (e.g., a switch control signal SWS or a second bias voltage VB2) applied to the first control line CLI1.

[0214] In an embodiment, the first active layer ACT1 can be provided on a layer different from the layers of the fourth electrode ET4 and the first line LI1 and is electrically connected to the fourth electrode ET4 and the first line LI1 through corresponding contact holes. For example, the first active layer ACT1 can be a semiconductor pattern provided on the same layer as the semiconductor layer of the transistor forming each pixel circuit PXC of the pixel PXL.

[0215] The second switching element ST2 can be connected between the third electrode ET3 (the second intermediate electrode IET2) and the second line LI2. For example, the second switching element ST2 can include a second active layer ACT2 electrically connected between the third electrode ET3 and the second line LI2, and a predetermined region of the second active layer ACT2 overlaps with the first control line CLI1. In this case, the second line LI2 can be disposed near the first control line CLI1 to be adjacent to the first control line CLI1. For example, the second line LI2, together with the first control line CLI1 and the first line LI1, can be disposed in the upper side region of each pixel PXL. In addition, the predetermined region of the first control line CLI1 that overlaps with the second active layer ACT2 can form the gate electrode of the second switching element ST2. The second switching element ST2 can be controlled by a signal (e.g., a switching control signal SWS or a second bias voltage VB2) applied to the first control line CLI1. For example, when a switching control signal SWS having a gate turn-on voltage is supplied to the first control line CLI1, the second switching element ST2 can be turned on simultaneously with the first switching element ST1.

[0216] In an embodiment, the second active layer ACT2 can be disposed on a layer different from the layers of the third electrode ET3 and the second line LI2, and is electrically connected to the third electrode ET3 and the second line LI2 through corresponding contact holes. For example, the second active layer ACT2 can be a semiconductor pattern disposed on the same layer as the semiconductor layer of the transistor of the pixel circuit PXC formed in each of the pixels PXL.

[0217] The third switching element ST3 is connected between the first electrode ET1 and the third line LI3. For example, the third switching element ST3 can include a third active layer ACT3 electrically connected between the first electrode ET1 and the third line LI3, and a predetermined region of the third active layer ACT3 overlaps with the first control line CLI1. In this case, the third line LI3 can be disposed near the first control line CLI1 to be adjacent to the first control line CLI1. For example, the third line LI3, together with the first control line CLI1, the first line LI1, and the second line LI2, can be disposed in the upper side region of each pixel PXL. In addition, the predetermined region of the first control line CLI1 that overlaps with the third active layer ACT3 can form the gate electrode of the third switching element ST3. The third switching element ST3 can be controlled by a signal (e.g., a switching control signal SWS or a second bias voltage VB2) applied to the first control line CLI1. For example, when a switching control signal SWS having a gate turn-on voltage is supplied to the first control line CLI1, the third switching element ST3 can be turned on simultaneously with the first switching element ST1 and the second switching element ST2.

[0218] In an embodiment, the third active layer ACT3 may be disposed on a layer different from the layers of the first electrode ET1 and the third line LI3, and is electrically connected to the first electrode ET1 and the third line LI3 through corresponding contact holes. For example, the third active layer ACT3 may be a semiconductor pattern disposed on the same layer as the semiconductor layer of the transistors of the pixel circuit PXC forming each of the pixels PXL.

[0219] Referring to Figure 7b and Figure 9b , in an embodiment where the light-emitting element LD is disposed in only two series stages, only one intermediate electrode IET shared by the first series stage and the second series stage may be disposed between the first electrode ET1 and the second electrode ET2. In this case, each first light-emitting element LD1 may include a first end EP1 connected to the first electrode ET1 and a second end EP2 connected to the intermediate electrode IET. Similarly, each second light-emitting element LD2 may include a first end EP1 connected to the intermediate electrode IET and a second end EP2 connected to the second electrode ET2.

[0220] In the foregoing embodiment, the switching unit SWU may include a first switching element ST1 connected between the intermediate electrode IET and the first line LI1 and a second switching element ST2 connected between the first electrode ET1 and the second line LI2. For example, the first switching element ST1 may include a first active layer ACT1, and the first active layer ACT1 is stacked with the first control line CLI1 and is electrically connected between the intermediate electrode IET and the first line LI1. For example, the second switching element ST2 may include a second active layer ACT2, and the second active layer ACT2 is stacked with the first control line CLI1 and is electrically connected between the first electrode ET1 and the second line LI2.

[0221] Referring to Figure 7e , Figure 7f , Figure 9c and Figure 9d , in a case where a predetermined alignment signal (e.g., the third alignment signal AS3 or the fourth alignment signal AS4) is applied to the first electrode ET1 using a predetermined transistor (e.g., the seventh transistor T7) provided in the pixel circuit PXC, the number of switching elements ST included in the switching unit SWU can be reduced. For example, each pixel PXL may not include a switching element (e.g., Figure 9a the third switching element ST3 or Figure 9b the second switching element ST2) connected to the first electrode ET1. In this case, since an alignment line (e.g., Figure 9a the third line LI3 or Figure 9b the second line LI2) for applying the alignment signal to the first electrode ET1 can also be removed, the number of alignment lines can also be reduced.

[0222] In an embodiment, even when the number of switching elements ST is maintained, the number of alignment lines can be reduced. For example, as shown in the embodiments of Figure 7c and Figure 7d when a switching element ST (e.g., the third switching element ST3 of Figure 7c or the second switching element ST2 of Figure 7d ) is connected between the first electrode ET1 and the second electrode ET2, there is no need to form a separate alignment line for applying an alignment signal to the first electrode ET1, so that the number of alignment lines can be reduced. The active layer of the switching element ST can be stacked with any adjacent first control line CLI1 or other control lines.

[0223] Figure 10 is a plan view showing a pixel PXL according to an embodiment of the present disclosure, and shows, for example, a modified embodiment of the pixel PXL of Figure 9a . In the description of the embodiment of Figure 10 , detailed descriptions of configurations similar or identical to those of the above embodiments will be omitted.

[0224] Referring to Figure 10 , the pixel PXL may further include a plurality of bank patterns BNK and / or a plurality of contact electrodes CE stacked with corresponding electrodes ET. For example, the pixel PXL may further include a plurality of bank patterns BNK respectively disposed under (or below) the first electrode ET1 to the fourth electrode ET4 and a plurality of contact electrodes CE respectively disposed above the first electrode ET1 to the fourth electrode ET4.

[0225] Each bank pattern BNK may be disposed under a corresponding electrode ET and stacked with a predetermined area of the electrode ET. In an embodiment, each bank pattern BNK may be a separate pattern separated from other bank patterns BNK, but the present disclosure is not limited thereto. For example, in an embodiment, the bank patterns BNK may be integrally connected to each other and have an uneven surface protruding in the height direction in a predetermined area corresponding to the corresponding electrode ET. Therefore, the electrode ET may protrude upward in the area corresponding to the corresponding bank pattern BNK. When the bank pattern BNK may be formed of a reflective material or includes at least one reflective material layer formed on the sidewall of the bank pattern BNK, the light emitted from the light-emitting element LD can be controlled to travel more reliably in the front direction of the display device.

[0226] Each contact electrode CE can be disposed on a corresponding electrode ET and an end of at least one light-emitting element LD adjacent to the electrode ET, such that the electrode ET can be electrically connected to one end of the light-emitting element LD. For example, the contact electrode CE disposed on the first electrode ET1 can be electrically connected to the first electrode ET1 and the first end EP1 of the first light-emitting element LD1. The contact electrode CE disposed on the second electrode ET2 can be electrically connected to the second electrode ET2 and the second end EP2 of the third light-emitting element LD3. Similarly, the contact electrode CE disposed on the third electrode ET3 can be electrically connected to the third electrode ET3, the second end EP2 of the first light-emitting element LD1, and the first end EP1 of the second light-emitting element LD2. The contact electrode CE disposed on the fourth electrode ET4 can be electrically connected to the fourth electrode ET4, the second end EP2 of the second light-emitting element LD2, and the first end EP1 of the third light-emitting element LD3. In the case of forming the contact electrode CE, the light-emitting element LD can be more reliably connected between the electrodes ET.

[0227] Figures 11a to 11d are cross-sectional views each showing a pixel PXL according to an embodiment of the present disclosure, and illustrate, for example, different embodiments of a cross-section corresponding to the line I-I’ of the pixel PXL. In the embodiment, Figure 10 of the line I-I’. In the embodiment, Figures 11a to 11d each show a cross-sectional structure of each pixel PXL, focusing on any one of the first light-emitting elements LD1 and its peripheral region, and the pixel PXL can have a substantially identical or similar cross-sectional structure in a corresponding series stage. In the embodiment, pixels PXL in the display area ( Figure 5 of the DA) can have a substantially identical or similar cross-sectional structure. Hereinafter, embodiments of the cross-sectional structure of each pixel PXL will be described with reference to Figures 11a to 11d and Figures 5 to 10 together.

[0228] Referring to Figures 5 to 11d , a pixel PXL according to an embodiment of the present disclosure and a display device including the pixel PXL can include a circuit layer PCL and a display layer DPL, which are disposed on one surface of a substrate layer BSL so as to overlap each other. For example, the display area DA can include a circuit layer PCL disposed on one surface of the substrate layer BSL and a display layer DPL disposed on the circuit layer PCL. In the embodiment, various lines together with circuit elements of a pixel circuit PXC forming each pixel PXL can be disposed in the circuit layer PCL. Electrodes ET and light-emitting elements LD of a light source unit LSU forming each pixel PXL can be disposed in the display layer DPL. In addition, a switching element ST of a switching unit SWU forming each pixel PXL and an alignment line connected to the switching element ST can be further disposed in the circuit layer PCL and / or the display layer DPL. Embodiments will be described with reference to Figure 12a andFigure 12b Describe the illustrative positions and / or cross-sectional structures of the alignment lines and the switching element ST.

[0229] The circuit layer PCL may include at least one circuit element electrically connected to the light-emitting element LD of each pixel PXL. For example, the circuit layer PCL may include a plurality of transistors T and storage capacitors Cst that form each pixel circuit PXC. In addition, the circuit layer PCL may include a switching element ST (e.g., at least a first switching element ST1 of each pixel PXL) that forms each switching unit SWU or at least some portions of the switching element ST (e.g., the corresponding active layer of the switching element ST).

[0230] In addition, the circuit layer PCL may further include at least one power line, at least one alignment line, and / or various signal lines connected to each pixel circuit PXC, the light source unit LSU, and / or the switching unit SWU. For example, the circuit layer PCL may include at least some of the first power line PL1, the second power line PL2, the scan line Si, and the data line Dj of each pixel PXL, the first switching element ST1 (or the first active layer ACT1 provided in the first switching element ST1) of each pixel PXL, the first line LI1 connected to the first switching element ST1, and the first control line CLI1.

[0231] For illustrative purposes, Figures 11a to 11d only the transistor T among the lines and circuit elements provided in the circuit layer PCL is representatively shown. Here, the planar structure / cross-sectional structure of the circuit layer PCL may be changed in various ways. The position and cross-sectional structure of each transistor T may be changed in various ways according to the embodiment.

[0232] The circuit layer PCL may include a plurality of insulating layers. For example, the circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and / or a passivation layer PSV that are continuously stacked on one surface of the substrate layer BSL. In some embodiments, the circuit layer PCL may further include at least one light-blocking pattern (not shown) provided under (or below) at least some of the transistors T.

[0233] The buffer layer BFL may prevent impurities from diffusing into each circuit element. The buffer layer BFL may be formed of a single layer or may be formed of a multilayer having at least two layers. In the case where the buffer layer BFL has a multilayer structure, the corresponding layers may be formed of the same material or different materials. Various circuit elements (such as transistors T and storage capacitors Cst) and various lines connected to the circuit elements may be provided on the buffer layer BFL. In an embodiment, the buffer layer BFL may be omitted. In this case, at least one circuit element and / or at least one line may be directly provided on one surface of the substrate layer BSL.

[0234] Each transistor T may include a semiconductor layer SCL (also referred to as a "semiconductor pattern" or "active layer"), a gate electrode GE, a first transistor electrode TE1, and a second transistor electrode TE2. Although Figures 11a to 11d an embodiment is shown in which each transistor T includes a first transistor electrode TE1 and a second transistor electrode TE2 formed separately from the semiconductor layer SCL, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the first transistor electrode TE1 and / or the second transistor electrode TE2 provided in at least one transistor T may be integrated with the corresponding semiconductor layer SCL.

[0235] The semiconductor layer SCL may be provided on the buffer layer BFL. For example, the semiconductor layer SCL may be provided between the gate insulating layer GI and the substrate layer BSL on which the buffer layer BFL is formed. The semiconductor layer SCL may include a first region in contact with each first transistor electrode TE1, a second region in contact with each second transistor electrode TE2, and a channel region provided between the first region and the second region. In an embodiment, one of the first region and the second region may be a source region, and the other may be a drain region.

[0236] In an embodiment, the semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, or the like. The channel region of the semiconductor layer SCL may be an intrinsic semiconductor that is an undoped semiconductor pattern. Each of the first region and the second region of the semiconductor layer SCL may be a semiconductor pattern doped with a predetermined impurity.

[0237] In an embodiment, the semiconductor layer SCL of the transistor T forming each pixel circuit PXC may be formed of substantially the same or similar materials. For example, the semiconductor layer SCL of the transistor T may be formed of any one of the same materials among polysilicon, amorphous silicon, and an oxide semiconductor. In an embodiment, some of the transistors T and some of the other transistors T may include semiconductor layers SCL formed of different materials. For example, the semiconductor layer SCL of some of the transistors T may be formed of polysilicon or amorphous silicon, and the semiconductor layer SCL of some of the other transistors T may be formed of an oxide semiconductor.

[0238] The gate insulating layer GI may be provided on the semiconductor layer SCL. For example, the gate insulating layer GI may be provided between the semiconductor layer SCL and the gate electrode GE. The gate insulating layer GI may be formed of a single layer or multiple layers and include at least one inorganic insulating material and / or at least one organic insulating material. For example, the gate insulating layer GI may include various known organic / inorganic insulating materials (including silicon nitride (SiN x ), silicon oxide (SiO x ), etc.). The constituent material of the gate insulating layer GI is not particularly limited.

[0239] The gate electrode GE may be disposed on the gate insulating layer GI. For example, the gate electrode GE may be disposed to overlap with the semiconductor layer SCL, and the gate insulating layer GI is disposed between the gate electrode GE and the semiconductor layer SCL. Although Figures 11a to 11d each shows a transistor T having a top gate structure, in other embodiments, the transistor T may have a bottom gate structure. In this case, the gate electrode GE may be disposed under (or below) the semiconductor layer SCL to overlap with the semiconductor layer SCL.

[0240] The interlayer insulating layer ILD may be disposed on the gate electrode GE. For example, the interlayer insulating layer ILD may be disposed between the gate electrode GE and the first transistor electrode TE1 and the second transistor electrode TE2. The interlayer insulating layer ILD may be formed of a single layer or multiple layers, and includes at least one inorganic insulating material and / or at least one organic insulating material. For example, the interlayer insulating layer ILD may include various known organic / inorganic insulating materials. The constituent material of the interlayer insulating layer ILD is not particularly limited.

[0241] The first transistor electrode TE1 and the second transistor electrode TE2 may be disposed on each semiconductor layer SCL, and at least one interlayer insulating layer ILD is disposed between the first transistor electrode TE1 and the second transistor electrode TE2 and each semiconductor layer SCL. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be disposed on corresponding different ends of the semiconductor layer SCL, and the gate insulating layer GI and the interlayer insulating layer ILD are disposed between the first transistor electrode TE1 and the second transistor electrode TE2 and the corresponding different ends of the semiconductor layer SCL. The first transistor electrode TE1 and the second transistor electrode TE2 may be electrically connected to each semiconductor layer SCL. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be connected to the first region and the second region of the semiconductor layer SCL through corresponding contact holes passing through the gate insulating layer GI and the interlayer insulating layer ILD. In an embodiment, any one of the first transistor electrode TE1 and the second transistor electrode TE2 may be a source electrode, and the other may be a drain electrode.

[0242] At least one transistor T provided in the pixel circuit PXC may be connected to at least one pixel electrode. For example, Figure 6f the first transistor T1 shown in Figure 7e or the sixth transistor T6 and the seventh transistor T7 shown in

[0243] At least one power line, at least one signal line, and / or at least one alignment line provided in the circuit layer PCL together with the transistor T may be provided on the same layer as the layer of a predetermined electrode of a circuit element forming the pixel circuit PXC. For example, the scan line Si of each pixel PXL may be provided on the same layer as the layer of the gate electrode GE. The data line Dj of each pixel PXL may be provided on the same layer as the layer of the first transistor electrode TE1 and the second transistor electrode TE2 of the transistor T. Further, the first power line PL1, the second power line PL2, and / or at least one alignment line may each be provided on the same layer as the layer of the gate electrode GE of the transistor T or the first transistor electrode TE1 and the second transistor electrode TE2.

[0244] In an embodiment, the circuit layer PCL may further include at least one conductive layer (not shown) (for example, any one conductive layer in which an electrode of the storage capacitor Cst is provided and which is provided on a layer different from the gate electrode GE and the source and drain electrodes). In this case, at least one line connected to each pixel PXL may be provided in the conductive layer.

[0245] The passivation layer PSV may be provided over the lines and / or the circuit elements including the transistor T. The passivation layer PSV may be formed of a single layer or multiple layers and include at least one inorganic insulating material and / or at least one organic insulating material. For example, the passivation layer PSV may include at least one organic insulating layer and substantially planarize the surface of the circuit layer PCL. The display layer DPL may be provided over the passivation layer PSV.

[0246] The display layer DPL may include a light source unit LSU of each pixel PXL and selectively include a switch unit SWU and / or alignment lines. For example, the display layer DPL may include a plurality of electrodes ET and a plurality of light-emitting elements LD provided in the emission area EMA of each pixel PXL and forming the corresponding light source unit LSU. For example, the display layer DPL may include a first electrode ET1, a second electrode ET2, and at least one intermediate electrode (for example, a third electrode ET3 and a fourth electrode ET4) of each pixel PXL and a plurality of light-emitting elements LD connected between the electrodes ET.

[0247] Further, the display layer DPL may also selectively include a plurality of bank patterns BNK configured to cause corresponding predetermined areas of the electrodes ET to protrude upward and / or a plurality of contact electrodes CE configured to more reliably connect the light-emitting elements LD between the electrodes ET. Additionally, the display layer DPL may also include, for example, at least one conductive layer and / or at least one insulating layer.

[0248] In an embodiment, the display layer DPL may include a bank pattern BNK continuously provided and / or formed on top of the circuit layer PCL, an electrode ET of each series stage, a first insulating layer INS1, a light-emitting element LD, an insulating pattern INP, a contact electrode CE, and a second insulating layer INS2. In addition, the display layer DPL may further include an overcoat OC on top of the second insulating layer INS2.

[0249] The bank pattern BNK may be provided at positions spaced apart from each other in the emission region of each pixel PXL. The bank pattern BNK may protrude in the height direction of the substrate layer BSL from one surface of the substrate layer BSL on which the circuit layer PCL is formed. In an embodiment, the bank patterns BNK may have substantially the same height, but the present disclosure is not limited thereto.

[0250] In an embodiment, each bank pattern BNK may be provided between the circuit layer PCL and each electrode ET (e.g., any one of the first electrode ET1 to the fourth electrode ET4). In addition, each bank pattern BNK may be provided around at least one adjacent light-emitting element LD to face any one end (e.g., the first end EP1 or the second end EP2 of at least one of the first light-emitting element LD1 to the third light-emitting element LD3) of the at least one light-emitting element LD.

[0251] According to an embodiment, the bank pattern BNK may have various shapes. In an embodiment, each bank pattern BNK may have a trapezoidal cross-section with a width decreasing upward as shown in Figure 11a and Figure 11c . In this case, each bank pattern BNK may have an inclined surface on at least one side surface. In an embodiment, as shown in Figure 11b and Figure 11d , each bank pattern BNK may have a semi-circular or semi-elliptical cross-section with its width gradually decreasing upward. In this case, each bank pattern BNK may have a curved surface on at least one side surface. In addition, the corresponding electrode ET and / or insulating layer provided on the bank pattern BNK may have a shape corresponding to the shape of the bank pattern BNK. For example, the corresponding electrode ET and / or insulating layer provided on the bank pattern BNK may have an inclined surface or a curved surface in a region corresponding to the bank pattern BNK. In other words, in the present disclosure, the shape of the bank pattern BNK is not particularly limited, and it may be changed in various ways. In addition, in some embodiments, at least one of the bank patterns BNK may be omitted, or its position may be changed.

[0252] The bank pattern BNK may include an insulating material, and the insulating material includes at least one inorganic material and / or at least one organic material. For example, the bank pattern BNK may include at least one inorganic layer, and the at least one inorganic layer includes various known inorganic insulating materials (such as silicon nitride (SiNx ) or silicon oxide (SiO x ). Optionally, each of the bank patterns BNK may include at least one organic layer and / or at least one photoresist layer containing various known organic insulating materials, or may form a single-layer or multi-layer insulator containing a combination of organic / inorganic materials. In an embodiment of the present disclosure, the constituent materials in the bank patterns BNK can be changed in various ways.

[0253] In an embodiment, each of the bank patterns BNK can be used as a reflector. For example, the bank pattern BNK together with the first electrode ET1 to the fourth electrode ET4 disposed on the bank pattern BNK can be used as a reflector for guiding the light emitted from each light-emitting element LD in a desired direction, thereby enhancing the light efficiency of the pixel PXL.

[0254] The electrodes ET forming each series stage of the light source unit LSU can be disposed on the bank pattern BNK. In an embodiment, the electrode ET can have a shape corresponding to the respective bank pattern BNK. For example, each electrode ET can have an inclined surface or a curved surface corresponding to the inclined surface or the curved surface of each bank pattern BNK and protrude in the height direction of the substrate layer BSL. In an embodiment where the bank pattern BNK is not formed, each electrode ET can be formed in a substantially planar shape on the passivation layer PSV.

[0255] Each electrode ET may include at least one conductive material. For example, each of the first electrode ET1 to the fourth electrode ET4 may include at least one metal or its alloy among various metal materials (including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc.), at least one material among conductive oxides (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc antimonate (AZO), indium tin zinc oxide (ITZO), tin oxide (SnO2)), and conductive polymers (such as PEDOT), but the present disclosure is not limited thereto. For example, each of the first electrode ET1 to the fourth electrode ET4 may include other conductive materials (such as carbon nanotubes and graphene). In other words, each of the first electrode ET1 to the fourth electrode ET4 may include at least one of various conductive materials to have conductivity, and there is no particular limitation on the constituent material of each of the first electrode ET1 to the fourth electrode ET4. In addition, the first electrode ET1 to the fourth electrode ET4 may have the same conductive material. Optionally, some of the first electrode ET1 to the fourth electrode ET4 may include a conductive material different from that of other electrodes.

[0256] In addition, each electrode ET may be formed of a single layer or multiple layers. For example, each of the first electrode ET1 to the fourth electrode ET4 may include a reflective electrode layer containing a reflective conductive material. Each of the first electrode ET1 to the fourth electrode ET4 may also selectively include at least one transparent electrode layer disposed above and / or below (or beneath) the reflective electrode layer and / or at least one conductive cover layer covering the upper portion of the reflective electrode layer and / or the transparent electrode layer.

[0257] In an embodiment, the reflective electrode layer may be formed of a conductive material having a uniform reflectivity. For example, the reflective electrode layer may include at least one of various metal materials (including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc.) or an alloy thereof, but the present disclosure is not limited thereto. In other words, the reflective electrode layer included in each electrode ET may be formed of various reflective conductive materials. In the case where each electrode ET includes a reflective electrode layer, the electrode ET may enable light emitted from opposite ends (i.e., the first end EP1 and the second end EP2) of each of the light-emitting elements LD to travel in the direction along which the display image is formed (e.g., in the front direction). Specifically, if the corresponding electrode ET has an inclined surface or a curved surface corresponding to the bank pattern BNK and is disposed to face the first end EP1 and the second end EP2 of the light-emitting element LD, the light emitted from the first end EP1 and the second end EP2 of each of the light-emitting elements LD may be reflected by the electrode ET adjacent to the first end EP1 and the second end EP2, and thus more reliably travel in the front direction of the display panel PNL (e.g., in the upward direction of the substrate layer BSL). Accordingly, the efficiency of the light emitted from the light-emitting element LD may be enhanced.

[0258] In addition, the transparent electrode layer may be formed of various transparent conductive materials. For example, the transparent electrode layer may include ITO, IZO, or ITZO, but the present disclosure is not limited thereto. In an embodiment, each electrode ET may have a three-layer structure having a stacked structure of ITO / Ag / ITO. Thus, if each electrode ET is formed of multiple layers having at least two layers, the voltage drop caused by signal delay (RC delay) may be minimized. Therefore, a desired voltage may be effectively transmitted to the light-emitting element LD.

[0259] In addition, each electrode ET may include a conductive capping layer covering the reflective electrode layer and / or the transparent electrode layer. In this case, it is possible to prevent the reflective electrode layer or the like of each electrode ET from being damaged by defects that may occur, for example, during the process of manufacturing the pixel PXL. Here, the conductive capping layer may be selectively included in each electrode ET and may be omitted in some embodiments. Further, the conductive capping layer may be regarded as a component of each electrode ET or a separate component provided on the electrode ET.

[0260] The first insulating layer INS1 may be provided on a predetermined region of each of the electrodes ET. For example, the first insulating layer INS1 may be formed to cover a predetermined region of each of the first electrode ET1 to the fourth electrode ET4 and may include openings to expose another region of each of the first electrode ET1 to the fourth electrode ET4. For example, the first insulating layer INS1 may expose a predetermined region of the electrode ET on the corresponding bank pattern BNK. In an embodiment, the first insulating layer INS1 may be omitted. In this case, the light-emitting element LD may be directly provided on one end of the passivation layer PSV and / or each of the electrodes ET.

[0261] In an embodiment, the first insulating layer INS1 may be formed to first cover the entire surface of the electrode ET. After the light-emitting element LD is supplied and aligned on the first insulating layer INS1, the first insulating layer INS1 may be partially opened to expose a region of each electrode ET in a predetermined region above each bank pattern BNK. In an embodiment, the first insulating layer INS1 may be patterned in the form of a separate pattern, and the separate pattern is only partially provided under (or below) the light-emitting element LD after the supply and alignment of the light-emitting element LD have been completed.

[0262] After the electrodes ET have been formed, the first insulating layer INS1 may be formed to cover the electrodes ET and prevent the electrodes ET from being damaged during subsequent processes. In addition, the first insulating layer INS1 may stably support each light-emitting element LD.

[0263] The first insulating layer INS1 may be formed of a single layer or multiple layers and include at least one inorganic insulating material and / or at least one organic insulating material. For example, the first insulating layer INS1 may include various organic / inorganic insulating materials (including silicon nitride (SiN x ), silicon oxide (SiO x ), aluminum oxide (Al2O3), etc.). There is no particular limitation on the constituent material of the first insulating layer INS1.

[0264] A plurality of light-emitting elements LD can be supplied to each pixel region (specifically, the emission region EMA in which the first insulating layer INS1 is formed in each pixel PXL) and aligned in each pixel region (specifically, the emission region EMA in which the first insulating layer INS1 is formed in each pixel PXL). For example, a plurality of light-emitting elements LD can be supplied to the emission region of each pixel PXL by an inkjet scheme, a slot coating scheme, or various other schemes. The light-emitting elements LD can be directionally aligned between the electrodes ET by a predetermined alignment signal (or alignment voltage) applied to the corresponding electrodes ET.

[0265] In an embodiment, at least some of the light-emitting elements LD can be horizontally or diagonally disposed between a pair of adjacent electrodes such that their opposite ends (i.e., their first end EP1 and second end EP2) overlap with the pair of electrodes. In an embodiment, at least some of the light-emitting elements LD can be disposed between a pair of adjacent electrodes without overlapping with the pair of electrodes and are electrically connected to the pair of electrodes through corresponding contact electrodes CE. Thus, at least one light-emitting element LD can be disposed between a pair of electrodes forming each series stage.

[0266] The insulating pattern INP can be disposed on a predetermined region of the light-emitting element LD. For example, the insulating pattern INP can expose the first end EP1 and the second end EP2 of the light-emitting element LD and is only partially disposed on a predetermined region of the light-emitting element LD, the predetermined region including the corresponding central region of the light-emitting element LD. Although the insulating pattern INP is formed as an independent pattern in the emission region EMA of each pixel PXL, the present disclosure is not limited thereto. According to an embodiment, the insulating pattern INP can be omitted. In this case, the opposite ends of the contact electrode CE can be directly disposed on the first end EP1 and the second end EP2 of the adjacent light-emitting element LD.

[0267] The insulating pattern INP can be formed of a single layer or multiple layers and includes at least one inorganic insulating material and / or at least one organic insulating material. For example, the insulating pattern INP can include various organic / inorganic insulating materials (including silicon nitride (SiN x ), silicon oxide (SiO x ), aluminum oxide (Al2O3), photoresist (PR) materials, etc.). The constituent material of the insulating pattern INP is not particularly limited.

[0268] After the alignment of the light-emitting element LD has been completed, an insulating pattern INP is formed on the light-emitting element LD so that the light-emitting element LD can be prevented from moving away from the alignment position. In addition, when there is a space between the first insulating layer INS1 and the light-emitting element LD, the space can be filled with an insulating material introduced into the space during the process of forming the insulating pattern INP. Thus, the light-emitting element LD can be supported more stably. Here, for example, depending on the material of the first insulating layer INS1, the space may not be completely filled. For example, the insulating pattern INP may be formed only on the light-emitting element LD, or may be formed both on and under (or beneath) the light-emitting element LD.

[0269] Opposite ends (i.e., the first end EP1 and the second end EP2) of the light-emitting element LD that are not covered with the insulating pattern INP may be covered with contact electrodes CE, respectively. For example, corresponding ends of adjacent contact electrodes CE may be disposed on the first end EP1 and the second end EP2 of at least one adjacent light-emitting element LD at positions spaced apart from each other, and the insulating pattern INP is placed between the corresponding ends of the adjacent contact electrodes CE.

[0270] In an embodiment, as Figure 11a and Figure 11b shown, the contact electrodes CE may be formed on the same layer simultaneously on one surface of the substrate layer BSL. Thus, the process of manufacturing the pixel PXL and the display device including the pixel PXL can be simplified.

[0271] In an embodiment, the contact electrodes CE may be divided into multiple groups and formed continuously in different layers on one surface of the substrate layer BSL. For example, as Figure 11c and Figure 11d shown, a pair of adjacent contact electrodes CE may be formed continuously in different layers on one surface of the substrate layer. An additional third insulating layer INS3 may be provided between the pair of contact electrodes CE. In other words, the positions and relative setting relationships of the contact electrodes CE can be changed in various ways.

[0272] In addition, the contact electrodes CE may be disposed on the electrodes ET to cover the corresponding exposed areas of the electrodes ET. For example, the contact electrodes CE may be disposed on at least a predetermined area of the corresponding electrodes ET to contact the corresponding electrodes ET. Thus, the contact electrodes CE can be electrically connected to the electrodes ET respectively disposed thereunder (or beneath). Each of the electrodes ET can be electrically connected to the first end EP1 or the second end EP2 of at least one adjacent light-emitting element LD through the contact electrode CE.

[0273] In an embodiment, the contact electrode CE may be formed of various transparent conductive materials. For example, the contact electrode CE may include at least one of various conductive materials (e.g., ITO, IZO, and ITZO), and may be substantially transparent or semi-transparent to meet a predetermined light transmittance. Thus, light emitted from the light-emitting element LD through the first end EP1 and the second end EP2 may be emitted to the outside of the display device through the contact electrode CE.

[0274] The second insulating layer INS2 may be disposed on the contact electrode CE. For example, the second insulating layer INS2 may be formed and / or disposed on the entire surface of the display area DA to cover the bank pattern BNK, the electrode ET, the light-emitting element LD, the insulating pattern INP, and the contact electrode CE formed in each emission area EMA. The second insulating layer INS2 may include at least one inorganic layer and / or at least one organic layer.

[0275] In an embodiment, the second insulating layer INS2 may include a thin film encapsulation layer having a multilayer structure. For example, the second insulating layer INS2 may be formed of a thin film encapsulation layer having a multilayer structure including at least two inorganic insulating layers and at least one organic insulating layer disposed between the at least two inorganic insulating layers. Here, the constituent materials and / or structures of the second insulating layer INS2 may be changed in various ways. In some embodiments, at least one cover layer OC and / or an encapsulation substrate, etc. may also be disposed on the second insulating layer INS2.

[0276] In an embodiment, the second insulating layer INS2 and the cover layer OC may each be formed of a single layer or multiple layers and include at least one inorganic insulating material and / or at least one organic insulating material. For example, the second insulating layer INS2 and the cover layer OC may each include various known organic / inorganic insulating materials.

[0277] Figure 12a and Figure 12b are cross-sectional views each showing a pixel PXL according to an embodiment of the present disclosure, and show different embodiments of a cross-section corresponding to the line II-II' of the pixel PXL, for example. Specifically, compared with the embodiment of Figure 10 the positions of some alignment lines (e.g., the first line LI1 to the third line LI3) may be changed in the embodiment of Figure 12a In the description of the embodiments of Figure 12b the same reference numerals will be used to denote components similar or identical to those of the previous embodiments, and their detailed descriptions will be omitted. Figure 12a and Figure 12b In the description of the embodiments of

[0278] Referring to Figures 5 to 12b, the alignment lines and the switching element ST can be provided in the circuit layer PCL and / or the display layer DPL. For example, the switching element ST including the first switching element ST1 of each pixel PXL can be provided in the circuit layer PCL. Each alignment line can be provided in the circuit layer PCL or the display layer DPL.

[0279] In an embodiment, as Figure 12a shown, the first control line CLI1 and the switching element ST can be provided in the circuit layer PCL together. The first line LI1 to the third line LI3 and the electrodes ET of the light source unit LSU can be provided in the display layer DPL together. For example, the first control line CLI1 can be formed simultaneously on the same layer as the gate electrode GE of the transistor T, or simultaneously on the same layer as the first transistor electrode TE1 and the second transistor electrode TE2 of the transistor T. The first control line CLI1 can be formed on another conductive layer in the circuit layer PCL.

[0280] In an embodiment, as Figure 12b shown, the first control line CLI1 and the first line LI1 to the third line LI3 can all be provided in the circuit layer PCL. In an embodiment, the first control line CLI1 and the first line LI1 to the third line LI3 can all be provided in the display layer DPL. In other words, the position of each of the alignment lines can be changed in various ways according to the embodiment.

[0281] The circuit layer PCL can include a transistor T (e.g., a plurality of transistors T including the first transistor T1) connected to the first electrode ET1 of each pixel PXL through the first contact hole CH1, and a plurality of circuit elements including the storage capacitor Cst. In addition, the circuit layer PCL can further include at least one switching element (e.g., at least the first switching element ST1) forming each switching unit SWU. For example, the circuit layer PCL can include a plurality of switching elements ST including the first switching element ST1 of the pixel PXL.

[0282] The storage capacitor Cst can include a first capacitor electrode CET1 and a second capacitor electrode CET2 stacked on each other. In an embodiment, each of the first capacitor electrode CET1 and the second capacitor electrode CET2 can be formed of a single layer or multiple layers. In addition, at least one of the first capacitor electrode CET1 and the second capacitor electrode CET2 can be provided on the same layer as at least one electrode of the first transistor T1 or the semiconductor layer SCL.

[0283] For example, the first capacitor electrode CET1 may be formed of a multi-layer electrode including a lower electrode LE disposed on the same layer as the semiconductor layer SCL of the first transistor T1, and an upper electrode UE disposed on the same layer as the first transistor electrode TE1 and the second transistor electrode TE2 of the first transistor T1 and electrically connected to the lower electrode LE. In an embodiment, the lower electrode LE may be a semiconductor pattern doped with a predetermined impurity. The second capacitor electrode CET2 may be formed of a single-layer electrode disposed on the same layer as the gate electrode of the first transistor T1 and stacked with the lower electrode LE and the upper electrode UE of the first capacitor electrode CET1. In this case, in the step of forming the first transistor T1 and the like, the storage capacitor Cst may be formed simultaneously therewith.

[0284] Here, the present disclosure is not limited thereto. The structure and / or position of each of the first capacitor electrode CET1 and the second capacitor electrode CET2 may be changed in various ways. For example, in an embodiment, any one of the first capacitor electrode CET1 and the second capacitor electrode CET2 may include at least one conductive pattern disposed on a layer different from the layers of the electrodes (e.g., the gate electrode GE and the first transistor electrode TE1 and the second transistor electrode TE2) and the semiconductor layer SCL forming the first transistor T1.

[0285] The switching elements ST may have substantially the same or similar cross-sectional structures to each other. In an embodiment, the switching elements ST may have a cross-sectional structure substantially the same or similar to that of the transistor T constituting the pixel circuit PXC. For example, the first switching element ST1 may include a first active layer ACT1 disposed on the same layer as the semiconductor layer SCL of the transistor T. Similarly, the second switching element ST2 and the third switching element ST3 may respectively include a second active layer ACT2 and a third active layer ACT3 disposed on the same layer as the semiconductor layer SCL of the transistor T.

[0286] The first active layer ACT1 may overlap a predetermined region of the first control line CLI1. The predetermined region of the first control line CLI1 may form the gate electrode of the first switching element ST1. Similarly, the second active layer ACT2 and the third active layer ACT3 may overlap other predetermined regions of the first control line CLI1. The other predetermined regions of the first control line CLI1 may form the respective gate electrodes of the second switching element ST2 and the third switching element ST3.

[0287] A predetermined region of the first active layer ACT1 may be electrically connected to the fourth electrode ET4 disposed in the display layer DPL via at least one contact hole or the like. Another predetermined region of the first active layer ACT1 may be connected to the first line LI1 disposed in the display layer DPL via at least another contact hole or the like.

[0288] In an embodiment, as Figure 12a shown in, different predetermined regions of the first active layer ACT1 can be respectively connected to the fourth electrode ET4 and the first line LI1 via corresponding bridging patterns BRP. In an embodiment, as Figure 12b shown in, a predetermined region of the first active layer ACT1 can be connected to the fourth electrode ET4 via the bridging pattern BRP, and another predetermined region of the first active layer ACT1 can be directly connected to the first line LI1. In an embodiment, the bridging pattern BRP can be disposed on the same layer as the layers of the first transistor electrode TE1 and the second transistor electrode TE2, and the position of the bridging pattern BRP can be changed in various ways.

[0289] Similarly, the second active layer ACT2 and the third active layer ACT3 can be respectively connected between the third electrode ET3 and the second line LI2 and between the first electrode ET1 and the third line LI3 either through at least one bridging pattern BRP or without passing through at least one bridging pattern BRP. In other words, the connection structure between each switching element ST and each electrode ET and the alignment line corresponding to the switching element ST can be changed in various ways.

[0290] Figures 13 to 18 are plan views respectively showing a display region DA according to an embodiment of the present disclosure, and show different embodiments related to the mutual arrangement structure of the alignment lines and the pixels PXL, for example. In an embodiment, Figure 13 shows a predetermined region of the display region DA including a pixel PXL according to an embodiment of Figure 9a and Figures 14 to 18 shows Figure 13 a modification of the embodiment of. Each embodiment of the present disclosure can be implemented alone or in combination with at least another embodiment for various combinations of embodiments, and the structure of the pixel PXL can be changed in various ways as described in the above various embodiments. In the following description of the embodiment of Figures 13 to 18 , the detailed description of the configurations similar or identical to those of the above embodiments (for example, the structure of each pixel PXL) will be omitted.

[0291] Referring to Figures 5 to 13 , the display region DA can include a plurality of horizontal lines each including a plurality of pixels PXL. The display region DA can have a structure in which the same structure is repeated for each horizontal line.

[0292] For example, the pixels PXL may have substantially the same structure and be regularly arranged in a first direction DR1 and a second direction DR2. Alignment lines may be provided on each horizontal line. In an alignment step of aligning the light-emitting elements LD, the alignment lines supplied with the same signal may be connected to each other inside and / or outside the display area DA. For example, the first control lines CLI1 repeatedly provided on the corresponding horizontal lines may be connected to each other inside and / or outside the display area DA. Similarly, among the first line LI1, the second line LI2, and the third line LI3 repeatedly provided on the corresponding horizontal lines, the lines supplied with the same signal may be connected to each other.

[0293] Each alignment line may be commonly connected to a plurality of pixels PXL. For example, each of the first control line CLI1, the first line LI1, the second line LI2, and the third line LI3 provided on each horizontal line may be commonly connected to the pixels PXL of at least one horizontal line.

[0294] In an embodiment, the alignment lines may be provided adjacent to a predetermined end (e.g., the upper end) of the first electrode ET1 to the fourth electrode ET4 of the light source unit LSU forming each pixel PXL. For example, the alignment lines may be arranged to be continuously spaced apart from the predetermined ends of the first electrode ET1 to the fourth electrode ET4 in the second direction DR2. Each of the alignment lines may extend along the first direction DR1 along which the pixels PXL of each horizontal line are arranged, and may be commonly connected to the pixels PXL of the corresponding horizontal line.

[0295] Referring to Figure 14 , each third switching element ST3 may be connected between an adjacent connection electrode CNL and the first electrode ET1. For example, as shown in the embodiment of Figure 7c , in the case where each third switching element ST3 is connected between the first electrode ET1 and the second electrode ET2, the third line LI3 shown in the embodiment of Figure 13 may be omitted. The third switching element ST3 may be connected to any one of the adjacent connection electrodes CNL (e.g., the connection electrode CNL of the pixel PXL on the previous horizontal line or the connection electrode CNL of the pixel PXL on the corresponding horizontal line), or may be connected to the second electrode ET2 of an adjacent pixel PXL (e.g., the second electrode ET2 of the pixel PXL provided on the previous horizontal line or the second electrode ET2 of the corresponding pixel PXL). In an embodiment, the second electrodes ET2 of the pixels PXL provided in the display area DA may be connected to each other through the corresponding connection electrodes CNL. The corresponding connection electrodes CNL of the horizontal lines may be connected to each other inside and / or outside the display area DA.

[0296] Referring to Figure 15 , with Figure 13Compared with the embodiment, the third switching element ST3 and the third line LI3 connected to the third switching element ST3 can be omitted. For example, as Figure 7e and Figure 9c In the embodiment shown, when a predetermined alignment signal (e.g., the fourth alignment signal AS4) is applied to the first electrode ET1 through a predetermined transistor (e.g., the seventh transistor T7) provided in each pixel circuit PXC, the third switching element ST3 and the third line LI3 connected to the third switching element ST3 may not be formed.

[0297] Referring to Figure 16 , a pair of consecutive horizontal lines may have a symmetric structure with respect to each other. For example, the alignment lines (e.g., the first control line CLI1 and the first line LI1 to the third line LI3) of the pixels PXL connected to any one horizontal line (e.g., each odd-numbered horizontal line) may be set to be opposite to the alignment lines of the pixels PXL connected to the subsequent horizontal line (e.g., each even-numbered horizontal line), and the pixels PXL of any one horizontal line and the pixels PXL of the subsequent horizontal line are placed therebetween.

[0298] In addition, the switching elements ST included in a pair of horizontal lines may have symmetric shapes and / or structures with respect to each other. For example, the first switching element ST1 included in the pixels PXL of any one horizontal line may have a shape symmetric to the first switching element ST1 included in the subsequent horizontal line.

[0299] In an embodiment, the pixels PXL included in a pair of horizontal lines may also have symmetric shapes and / or structures. For example, the first electrode ET1, the second electrode ET2, and the intermediate electrodes (e.g., the third electrode ET3 and the fourth electrode ET4) included in the pixels PXL of any one horizontal line may have shapes symmetric to the first electrode ET1, the second electrode ET2, and the intermediate electrodes included in the pixels PXL of the subsequent horizontal line. In an embodiment, even if the alignment lines and the switching elements ST corresponding to a pair of horizontal lines have symmetric shapes, the pixels PXL may have shapes and / or structures that are identically repeated on each horizontal line.

[0300] In an embodiment, when the pixels PXL included in a pair of horizontal lines have symmetric shapes and / or structures with respect to each other, only one connection electrode CNL may be provided between the pair of horizontal lines, and the pixels PXL included in the pair of horizontal lines may share one connection electrode CNL. In an embodiment, when the pixels PXL included in a pair of horizontal lines have symmetric shapes and / or structures with respect to each other, each connection electrode CNL corresponding to the pixels PXL of each horizontal line may be formed separately.

[0301] Referring to Figure 17, Alignment lines of pixels PXL connected to at least one horizontal line can be separated and disposed on different sides of the pixels PXL of the horizontal line. For example, the first control line CLI1, the first line LI1, and the third line LI3 of the odd-numbered horizontal lines can be disposed adjacent to the first ends (e.g., upper ends) of the first electrode ET1 to the fourth electrode ET4. The second line LI2 can be disposed adjacent to the second ends (e.g., lower ends) of the first electrode ET1 to the fourth electrode ET4. In addition, the second control line CLI2 can be disposed near the second line LI2. For example, the second control line CLI2 and the second line LI2 together can be disposed adjacent to the second ends (e.g., lower ends) of the first electrode ET1 to the fourth electrode ET4. In this case, the second active layer ACT2 of the second switching element ST2 can be partially overlapped with the second control line CLI2 and is electrically connected between the third electrode ET3 and the second line LI2.

[0302] In an embodiment, the second control line CLI2 can be supplied with a signal same as that of the first control line CLI1 (e.g., the same switching control signal SWS). For example, the second control line CLI2 can be connected to the first control line CLI1 inside and / or outside the display area DA. In this case, the second switching element ST2 can be turned on simultaneously with the first switching element ST1 and the third switching element ST3.

[0303] In addition, pixels PXL disposed on a pair of consecutive horizontal lines can share at least one alignment line. For example, pixels PXL disposed on the second horizontal line can share the second control line CLI2 and the second line LI2 with pixels PXL disposed on the first horizontal line. Additionally, pixels PXL disposed on the second horizontal line can share the first control line CLI1, the first line LI1, and the third line LI3 with pixels PXL disposed on the third horizontal line.

[0304] According to the foregoing embodiments, alignment lines can be disposed in the display area DA more efficiently. In addition, coupling effects that may occur between alignment lines can be prevented or alleviated. For example, in a case where a predetermined alignment signal to be set as an AC signal is applied to the third electrode ET3 and the fourth electrode ET4 respectively and a predetermined alignment signal to be set as a DC signal is applied to the first electrode ET1 and the second electrode ET2 respectively during an alignment step, if the first line LI1 and the second line LI2 for transmitting the corresponding alignment signals to the third electrode ET3 and the fourth electrode ET4 are separated and disposed on corresponding different sides of the pixel PXL, the coupling effects that may occur between the alignment lines can be minimized. Therefore, the alignment signals can be reliably supplied to the corresponding electrodes ET, such that high-quality pixels PXL and a display device including the pixels PXL can be manufactured.

[0305] Refer to Figure 18, at least two of the above embodiments may be combined with each other. For example, in Figure 15 the embodiment of Figure 17 and the combination of the embodiments of

[0306] the third switching element ST3 and the third line LI3 connected to the third switching element ST3 may be removed, and the alignment lines of the pixels PXL connected to at least one horizontal line may be separated and disposed on different sides of the pixels PXL of the horizontal line. In addition, each of the above various embodiments may be implemented alone, or combined with at least another embodiment to perform various combinations of the embodiments.

[0307] Thereafter, a plurality of light-emitting elements LD are supplied to each emission region EMA in which the electrode ET is formed. Thereafter, the switching element ST is driven so that a corresponding alignment signal is supplied to the electrode ET. In an embodiment, after the light-emitting element LD has been supplied, each alignment signal may be continuously supplied for a predetermined time or longer. Accordingly, an electric field may be formed between the electrodes ET so that the light-emitting element LD can be aligned between the electrodes ET. In an embodiment, after the light-emitting element LD is aligned, an insulating pattern INP may be selectively formed on the light-emitting element LD.

[0308] Thereafter, the light-emitting element LD is electrically connected between the electrodes ET. For example, when corresponding contact electrodes CE are formed on the electrodes ET and the first end EP1 and the second end EP2 of the light-emitting element LD, the light-emitting element LD may be electrically connected between the electrodes ET. In an embodiment, after the contact electrode CE is formed, a second insulating layer INS2 and / or a cover layer OC may be formed on the entire surface of the display region DA.

[0309] In the pixel PXL according to the various embodiments of the present disclosure, a display device including the pixel PXL, and a method of manufacturing the display device, a switching element ST may be provided between at least one electrode ET in a light source unit LSU provided in each pixel PXL and a corresponding predetermined alignment line. As needed, the switching element ST is driven so that the at least one electrode ET is selectively connected to each alignment line. Accordingly, in the step of aligning the light emitting element LD, a desired alignment signal can be reliably transmitted to the pixel PXL. When the display device is actually used, the switching element ST may be kept off so that the pixel PXL can be isolated from the corresponding alignment line. According to an embodiment of the present disclosure, an etching process (e.g., a masking process) for separating the alignment lines may be omitted. Accordingly, the process of manufacturing the display device can be further simplified.

[0310] Although the scope of the present disclosure has been described through detailed embodiments, it should be noted that the above embodiments are merely illustrative and should not be considered restrictive. Those skilled in the art should understand that various changes, substitutions, and alterations can be made herein without departing from the scope of the disclosure as defined by the claims.

[0311] The scope of the present disclosure is not limited by the detailed description of this specification and should be defined by the appended claims. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present disclosure.

Claims

1. A display device, the display device comprising: Pixels, disposed in a display area; A first line, connected to the pixels; A first control line, disposed near the first line; A first power line, connected between a first power supply and the pixels; A second power line, connected between a second power supply and the pixels, wherein the pixels include: a first electrode and a second electrode, spaced apart from each other, the first electrode being connected to the first power line, the second electrode being connected to the second power line; at least one intermediate electrode, including a first intermediate electrode between the first electrode and the second electrode; a plurality of light-emitting elements, respectively connected between a pair of adjacent electrodes among the first electrode, the second electrode, and the at least one intermediate electrode; and a first switching element, connected between the first intermediate electrode and the first line, and configured to be controlled by a signal applied to the first control line, wherein the first switching element is configured to: conduct when a signal is applied to the first control line, thereby electrically connecting the first line to the intermediate electrode; and cut off when a signal is not applied to the first control line, thereby electrically isolating the first line from the intermediate electrode.

2. The display device according to claim 1, wherein The first switching element includes a first active layer, the first active layer being stacked with the first control line and electrically connected between the first intermediate electrode and the first line.

3. The display device according to claim 1, the display device further comprising a second line spaced apart from the first line, Among them, the pixels further including: a second intermediate electrode, included in the at least one intermediate electrode, and disposed between the first electrode and the first intermediate electrode; and a second switching element, connected between the second intermediate electrode and the second line.

4. The display device according to claim 3, Among them, the second line is disposed near the first control line, and wherein the second switching element includes a second active layer, the second active layer being stacked with the first control line and electrically connected between the second intermediate electrode and the second line.

5. The display device according to claim 3, the display device further comprising a second control line disposed near the second line, Among them, the second switching element includes a second active layer, the second active layer being partially stacked with the second control line and electrically connected between the second intermediate electrode and the second line.

6. The display device according to claim 5, Among them, the first line and the first control line are disposed adjacent to a first end of the first electrode, the second electrode, and the at least one intermediate electrode, and wherein the second line and the second control line are disposed adjacent to a second end of the first electrode, the second electrode, and the at least one intermediate electrode.

7. The display device according to claim 3, the display device further comprising a third line spaced apart from the first line and the second line, Among them, the pixels further including a third switching element, the third switching element being connected between the first electrode and the third line and configured to conduct simultaneously with the first switching element.

8. The display device according to claim 1, wherein the display device further includes a second line spaced apart from the first line. Among them, The pixel further includes a second switching element connected between the first electrode and the second line.

9. The display device according to claim 1, wherein, The pixel further includes a second switching element connected between the first electrode and the second electrode and configured to be turned on simultaneously with the first switching element.

10. The display device according to claim 1, wherein, The first electrode, the at least one intermediate electrode, and the second electrode are continuously arranged in a first direction in an emission region of the pixel.

11. The display device according to claim 10, wherein, The first line and the first control line are provided adjacent to a first end of the first electrode, the at least one intermediate electrode, and the second electrode, and each extends in the first direction and is commonly connected to pixels of a horizontal line, and the pixels of the horizontal line are provided on the horizontal line.

12. The display device according to claim 1. Among them, The display area includes a plurality of horizontal lines, each of the plurality of horizontal lines includes a plurality of pixels, and wherein the first line and the first control line of the pixels connected to any one of the horizontal lines are provided opposite to the first line and the first control line of the pixels connected to a subsequent horizontal line, and the pixels of any one of the horizontal lines and the pixels of the subsequent horizontal line are disposed between the first line and the first control line of the pixels connected to any one of the horizontal lines and the first line and the first control line of the pixels connected to the subsequent horizontal line.

13. The display device according to claim 12, wherein, The first switching element included in the pixels of any one of the horizontal lines and the first switching element included in the pixels of the subsequent horizontal line have symmetric shapes with respect to each other.

14. The display device according to claim 12, wherein, The first electrode, the second electrode, and the intermediate electrode included in the pixels of any one of the horizontal lines and the first electrode, the second electrode, and the intermediate electrode included in the pixels of the subsequent horizontal line have symmetric shapes with respect to each other.

15. The display device according to claim 1. Among them, The at least one intermediate electrode is electrically connected between the first electrode and the second electrode through the light-emitting element.

16. The display device according to claim 15. Among them, The pixel further includes a pixel circuit connected between the first power supply and the first electrode. wherein the display area includes: a circuit layer in which circuit elements of the pixel circuit are provided; and a display layer stacked with the circuit layer, and the first electrode, the second electrode, the at least one intermediate electrode, and the light-emitting element are provided in the display layer.

17. The display device according to claim 16, wherein, The circuit layer further includes at least one of the first power line connected to the first power supply, the second power line connected to the second power supply, the active layer of the first switching element, the first line, and the first control line.

18. The display device according to claim 16, wherein, The display layer further includes at least one of the first line and the first control line.

19. The display device according to claim 1, wherein, The pixel further includes at least one of the following: a plurality of bank patterns respectively provided under the first electrode, the second electrode, and the at least one intermediate electrode; and A plurality of contact electrodes are respectively disposed over the first electrode, the second electrode, and the at least one intermediate electrode.

20. A method of manufacturing a display device according to any one of claims 1-19, the method comprising the steps of: forming the first switching element, the first line, the first control line, the first power line, the second power line, the first electrode, the second electrode, and the at least one intermediate electrode; supplying the light-emitting element to the emission region of the pixel; aligning the light-emitting element between adjacent electrodes among the first electrode, the second electrode, and the at least one intermediate electrode by applying a signal to drive the first switching element and supplying a corresponding alignment signal to the plurality of electrodes; and electrically connecting the light-emitting element between the adjacent electrodes.

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