A display panel and display device

Abstract

A display panel and a display device, the display panel comprising: a first display area and a second display area located at least one side of the first display area; the first display area comprising: a first region and a second region, the first region being located between the second region and the second display area; the display panel comprising: a substrate and a circuit structure layer and a light-emitting structure layer sequentially stacked on the substrate; the light-emitting structure layer being located in the first display area and the second display area, the light-emitting structure layer comprising: an anode, a light-emitting layer and a cathode; the circuit structure layer at least comprising: a plurality of first dummy driving circuits, the first dummy driving circuits being located in the first region, and the orthographic projection of the first dummy driving circuits on the substrate being located within the orthographic projection range of the anode of the light-emitting structure layer in the first region on the substrate.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to, but are not limited to, the display field, and in particular to a display panel and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices with OLED or QLED as light emitting devices and controlled by thin film transistors (TFT) have become the mainstream products in the current display field.

[0003] At present, the concept of full-screen mobile phone has been widely concerned in the mobile phone market, and it is also the development direction of future mobile phones. In such a full-screen mobile phone, the camera can be hidden to make the front visual area almost all screen, so that the user gets better display effect. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, the present disclosure provides a display panel, comprising: a first display area and a second display area located at least one side of the first display area; the first display area comprises: a first region and a second region, the first region is located between the second region and the second display area;

[0006] The display panel comprises: a substrate and a circuit structure layer and a light emitting structure layer which are sequentially stacked on the substrate;

[0007] The light emitting structure layer is located in the first display area and the second display area, and the light emitting structure layer comprises: an anode, a light emitting layer and a cathode;

[0008] The circuit structure layer at least comprises: a plurality of first dummy driving circuits, the first dummy driving circuit is located in the first region, and the orthographic projection of the first dummy driving circuit on the substrate is located in the orthographic projection range of the anode of the light emitting structure layer in the first region on the substrate.

[0009] In some possible implementation manners, the circuit structure layer further includes a plurality of driving circuits, the driving circuits are located in the second display area, and the driving circuits are configured to drive the light-emitting structure layer in the first display area and the second display area to emit light.

[0010] In some possible implementation manners, the driving circuit at least includes an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, and a third metal layer, which are sequentially stacked on the substrate.

[0011] In some possible implementation manners, the first dummy driving circuit includes at least one film layer in an active layer, a first metal layer, a second metal layer, and a third metal layer, and the first dummy driving circuit is arranged in the same layer as the driving circuit.

[0012] In some possible implementation manners, the first dummy driving circuit includes an active layer, and the active layer of the first dummy driving circuit is arranged in the same layer as the active layer of the driving circuit.

[0013] And / or, the first dummy driving circuit includes a first metal layer, and the first metal layer of the first dummy driving circuit is arranged in the same layer as the first metal layer of the driving circuit.

[0014] And / or, the first dummy driving circuit includes a second metal layer, and the second metal layer of the first dummy driving circuit is arranged in the same layer as the second metal layer of the driving circuit.

[0015] And / or, the first dummy driving circuit includes a third metal layer, and the third metal layer of the first dummy driving circuit is arranged in the same layer as the third metal layer of the driving circuit.

[0016] In some possible implementation manners, an area of an anode of the light-emitting structure layer in the first area is greater than or equal to an area of the first dummy driving circuit.

[0017] In some possible implementation manners, the circuit structure layer further includes a plurality of second dummy driving circuits, the second dummy driving circuits are located in the second area, and a normal projection of the second dummy driving circuits on the substrate is located in a range of a normal projection of an anode of the light-emitting structure layer in the second area on the substrate.

[0018] In some possible implementation manners, the second dummy driving circuit includes at least one film layer in an active layer, a first metal layer, a second metal layer, and a third metal layer, and the second dummy driving circuit is arranged in the same layer as the driving circuit.

[0019] In some possible implementation manners, the second dummy driving circuit comprises an active layer, and the active layer of the second dummy driving circuit is arranged in the same layer as the active layer of the driving circuit.

[0020] And / or, the second dummy driving circuit comprises a first metal layer, and the first metal layer of the second dummy driving circuit is arranged in the same layer as the first metal layer of the driving circuit.

[0021] And / or, the second dummy driving circuit comprises a second metal layer, and the second metal layer of the second dummy driving circuit is arranged in the same layer as the second metal layer of the driving circuit.

[0022] And / or, the second dummy driving circuit comprises a third metal layer, and the third metal layer of the second dummy driving circuit is arranged in the same layer as the third metal layer of the driving circuit.

[0023] In some possible implementation manners, an area of the anode of the light-emitting structure layer located in the second region is greater than or equal to an area of the second dummy driving circuit.

[0024] In some possible implementation manners, the first display region is a transparent display region.

[0025] The resolution of the first display region is the same as or different from the resolution of the second display region.

[0026] In some possible implementation manners, the light-emitting structure layer comprises: a plurality of light-emitting elements, at least one light-emitting element comprising: an anode, an organic light-emitting layer and a cathode; the light-emitting element comprising: an anode, an organic light-emitting layer and a cathode; the light-emitting element emits light of a plurality of different colors.

[0027] The light-emitting area of the light-emitting element of the first display region is less than or equal to the light-emitting area of the light-emitting element of the same color of the second display region.

[0028] In some possible implementation manners, the boundary of the anode of the light-emitting structure layer located in the first display region is a curved boundary, the boundary of the anode of the light-emitting structure layer located in the second display region and close to the edge of the first display region is a curved boundary, and the boundary of the anode of the light-emitting structure layer located in the second display region close to the edge of the first display region is a straight boundary.

[0029] In some possible implementation manners, the circuit structure layer further comprises: a signal connection part, the signal connection part being located in the second display region, and the signal connection part being configured to connect a plurality of the driving circuits.

[0030] The adapter is a transparent adapter at least in the first display area, and the adapter is connected with the driving circuit to drive the light emitting element of the first display area.

[0031] In some possible implementation manners, the circuit structure layer further includes: a fourth insulating layer, a transparent conductive layer and a planarization layer which are sequentially stacked on the third metal layer.

[0032] The transparent conductive layer includes the adapter.

[0033] In a second aspect, the present disclosure further provides a display device including the display panel.

[0034] In some possible implementation manners, the display panel further includes an optical element, and the optical element is located in the first display area of the display panel.

[0035] The present disclosure provides a display panel and a display device, wherein the display panel includes: a first display area and a second display area located at at least one side of the first display area; the first display area includes: a first region and a second region, and the first region is located between the second region and the second display area; the display panel includes: a substrate and a circuit structure layer and a light emitting structure layer which are sequentially stacked on the substrate; the light emitting structure layer is located in the first display area and the second display area, and the light emitting structure layer includes: an anode, an organic light emitting layer and a cathode; the circuit structure layer at least includes: a plurality of first dummy driving circuits, the first dummy driving circuit is located in the first region, and a projection of the first dummy driving circuit on the substrate is located in a projection range of the anode of the light emitting structure layer in the first region on the substrate. The present disclosure sets a plurality of first dummy driving circuits in the first region, the first dummy driving circuit is not connected with a signal, ensures normal exposure of the circuit structure layer of the second display area, and the driving circuit characteristics of the second display area are consistent; the projection of the plurality of first dummy driving circuits of the circuit structure layer in the first region on the substrate is located in the projection range of the anode of the light emitting structure layer in the first region on the substrate, the area occupied by the first dummy driving circuit is reduced, and the diffraction influence of the first dummy driving circuit on the second region is reduced, and the photographing effect of the display panel can be not affected. BRIEF DESCRIPTION OF DRAWINGS

[0036] The accompanying drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and together with the embodiments of the present disclosure are used to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0037] Figure 1 FIG. 1 is a structural schematic diagram of a display panel;

[0038] Figure 2A FIG. 2 is a partial schematic diagram of a display panel provided by an exemplary embodiment;

[0039] Figure 2B Partial view of a display panel according to another exemplary embodiment;

[0040] Figure 2C Partial view of a display panel according to yet another exemplary embodiment;

[0041] Figure 2D Partial view of a display panel according to another exemplary embodiment;

[0042] Figure 3 Cross-sectional view of a display panel according to an exemplary embodiment;

[0043] Figures 4A-4B Arrangement of light emitting elements of a display panel according to an exemplary embodiment;

[0044] Figure 5 Equivalent circuit schematic of a driving circuit;

[0045] Figure 6 Timing diagram of a driving circuit;

[0046] Figure 7A Schematic after formation of an active layer;

[0047] Figure 7B Schematic after formation of an active layer for a driving circuit;

[0048] Figure 8A Schematic after formation of a first metal layer;

[0049] Figure 8B Schematic after formation of a first metal layer for a driving circuit;

[0050] Figure 9A Schematic after formation of a second metal layer;

[0051] Figure 9B Schematic after formation of a second metal layer for a driving circuit;

[0052] Figure 10A Schematic after formation of a third metal layer;

[0053] Figure 10B Schematic after formation of a third metal layer for a driving circuit. DETAILED DESCRIPTION

[0054] For the purpose of making the objects, technical solutions and advantages of the present disclosure clearer, below, the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments can be implemented in multiple different forms. It will be easily understood by those skilled in the art that the modes and details can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other in so far as there is no contradiction in combination unless otherwise mentioned. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed description of some known functions and known components will be omitted in the present disclosure. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed

[0055] In the drawings, the size, the thickness, or the region of each constituent element shown in some cases is exaggerated for clarity in some cases. Thus, one embodiment of the present disclosure is not necessarily limited to such a scale. The shapes and the sizes of the components shown in the drawings and the relative arrangement thereof are not necessarily limited to those shown in the drawings. The drawings provided only ideal examples, and the shape of the embodiments of the present disclosure is not limited to the shape shown in the drawings and the numerical value and the like.

[0056] In this specification, ordinal numbers such as "first", "second", and "third" are used to avoid confusion among the constituent elements, and are not intended to limit the number in the aspect of the quantity.

[0057] In this specification, in order to facilitate the description of the present specification and simplify the description, words of specification indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are used to describe the positional relationship of the constituent elements with reference to the drawings, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0058] In this specification, unless otherwise explicitly specified and limited, the terms "mount", "connected", "connection" should be interpreted in a broad sense. For example, it can be fixedly connected, or removably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected via an intermediate device, or the communication inside two elements. The specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances by those skilled in the art.

[0059] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region means a region where current flows.

[0060] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In the case of using a transistor having opposite polarity or in the case of changing the direction of current flow in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other.

[0061] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0062] In this specification, "parallel" means a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus a state where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, "perpendicular" means a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus a state where the angle is greater than or equal to 85° and less than or equal to 95° is also included.

[0063] In this specification, "film" and "layer" can be interchanged with each other. For example, "a metal layer" can be replaced with "a conductive film". Similarly, "an insulating film" can be replaced with "an insulating layer".

[0064] In the present disclosure, "about" means not strictly limited to the limit, allowing values within the range of process and measurement error.

[0065] For a display device provided with an under-screen camera, in order to ensure the uniformity of display, a dummy driving circuit is arranged around the under-screen camera, which will affect the shooting effect of the display device.

[0066] Figure 1 FIG. 1 is a structural schematic diagram of a display panel, Figure 2A FIG. 2 is a partial schematic diagram of a display panel provided by an example embodiment, Figure 2B FIG. 3 is a partial schematic diagram of a display panel provided by another example embodiment, Figure 2CA partial schematic view of a display panel provided for another example embodiment, Figure 2D A partial schematic view of a display panel provided for another example embodiment, Figure 3 A cross-sectional view of a display panel provided for an example embodiment. As Figure 1 and Figures 2A-2D As shown in the drawings, the display panel provided by the embodiments of the present disclosure includes: a first display area A1 and a second display area A2 located at least one side of the first display area; the first display area A1 includes: a first region A11 and a second region A12, the first region A11 is located between the second region A12 and the second display area A2. The display panel includes: a substrate 10 and a circuit structure layer 20 and a light-emitting structure layer 30 which are sequentially stacked on the substrate 10. The light-emitting structure layer is located in the first display area A1 and the second display area A2, and the light-emitting structure layer includes: an anode, an organic light-emitting layer and a cathode. The circuit structure layer 20 at least includes: a plurality of first dummy driving circuits VPA1. The first dummy driving circuit VPA1 is located in the first region A11, and the orthographic projection of the first dummy driving circuit VPA1 on the substrate 10 is located within the orthographic projection range of the anode of the light-emitting structure layer in the first region A11 on the substrate 10.

[0067] In an example embodiment, the substrate 10 can be a rigid substrate or a flexible substrate, wherein the rigid substrate can be, but is not limited to, one or more of glass, metal foil; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers.

[0068] In an example embodiment, the first display area A1 can be a light-transmitting display area. The light-transmitting display area can display or transmit light.

[0069] In an example embodiment, in a plane parallel to the display panel, the shape of the first display area can be any one or more of: a rectangle, a polygon, a circle and an ellipse. Figure 1 For example, when the shape of the first display area is a circle, the diameter of the circle can be about 3mm to 5mm. For another example, when the shape of the first display area is a rectangle, the side length of the rectangle can be about 3mm to 5mm.

[0070] In an example embodiment, in a plane parallel to the display panel, the shape of the second display area A2 can be any one or more of: a rectangle, a polygon, a circle and an ellipse.

[0071] In an example embodiment, the area of the first display area A1 can be greater than the area of the second display area A2, or the area of the first display area A1 can be equal to the area of the second display area A2, or the area of the first display area A1 can be less than the area of the second display area A2. Figure 1 The first display area is taken as an example in which the area of the first display area is less than the area of the second display area.

[0072] In an example embodiment, the resolution of the first display area A1 and the second display area A2 can be the same or can be different. The resolution (Pixels Per Inch, PPI for short) refers to the number of pixels per unit area, which can be referred to as pixel density. The higher the PPI value, the higher the density at which the display panel displays the picture, and the more detailed the picture.

[0073] In an example embodiment, the resolution of the second display area A2 can be greater than the resolution of the first display area A1, that is, the number of light emitting elements included in the second display area A2 per unit area is greater than the number of light emitting elements included in the first display area A1, or the resolution of the second display area A2 can be less than the resolution of the first display area A1, that is, the number of light emitting elements included in the second display area A2 per unit area is less than the number of light emitting elements included in the first display area A1, or the resolution of the second display area A2 can be equal to the resolution of the first display area A1, that is, the number of light emitting elements included in the second display area A2 per unit area is equal to the number of light emitting elements included in the first display area A1.

[0074] In an example embodiment, the shape of the display area can be a circular polygon, or can be a circle. When the shape of the display area is a circular polygon, the display area can further include a straight line display boundary. Figure 1 The display area is taken as an example in which the display area is a circular rectangle.

[0075] In an example embodiment, the light emitting structure layer can include a plurality of light emitting elements, and at least one light emitting element includes an anode, an organic light emitting layer, and a cathode. The shape of the light emitting element can be any one or more of a triangle, a square, a rectangle, a diamond, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons, which are not limited in the present disclosure.

[0076] In an example embodiment, Figures 4A-4BAn arrangement of light emitting elements of a display panel is provided for an exemplary embodiment. As shown in FIG. 4, the light emitting element P can be any one of a red (R) light emitting element, a green (G) light emitting element, a blue (B) light emitting element, and a white light emitting element, which is not limited in the present disclosure. When the display panel includes the red (R) light emitting element, the green (G) light emitting element, and the blue (B) light emitting element, the three light emitting elements can be arranged in a horizontal parallel, a vertical parallel, or a triangle manner. When the display panel includes the red (R) light emitting element, the green (G) light emitting element, the blue (B) light emitting element, and the white light emitting element, the four light emitting elements can be arranged in a horizontal parallel, a vertical parallel, or an array manner, which is not limited in the present disclosure. Figure 4A is described by taking the four light emitting elements arranged in an array manner as an example, Figure 4B is described by taking the three light emitting elements arranged in an array manner as an example.

[0077] In an exemplary embodiment, the light emitting structure layer 30 can further include a pixel definition layer 34. A normal projection of the pixel definition layer 34 on the substrate 10 has no overlapping area with a normal projection of the first dummy driving circuit VPA1 on the substrate 10.

[0078] In an exemplary embodiment, the light emitting element can be an organic electroluminescence diode (OLED) or a quantum dot light emitting diode (QLED). The anode is connected to the driving circuit through a via, the organic light emitting layer is connected to the anode, and the cathode is connected to the organic light emitting layer. The organic light emitting layer emits light of a corresponding color under the driving of the anode and the cathode.

[0079] In an exemplary embodiment, the organic light emitting layer can include a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL) stacked. In an exemplary embodiment, the hole injection layer of all sub-pixels can be a common layer connected together, the electron injection layer of all sub-pixels can be a common layer connected together, the hole transport layer of all sub-pixels can be a common layer connected together, the electron transport layer of all sub-pixels can be a common layer connected together, the hole block layer of all sub-pixels can be a common layer connected together, the emitting layer of adjacent sub-pixels can have a small amount of overlap or can be isolated, and the electron block layer of adjacent sub-pixels can have a small amount of overlap or can be isolated.

[0080] In an exemplary embodiment, the anode can employ a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0081] In an exemplary embodiment, the cathode can employ any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy of any one or more of the above metals.

[0082] In an exemplary embodiment, the pixel definition layer 34 can employ an organic material such as polyimide, acrylic, or polyethylene terephthalate.

[0083] In an exemplary embodiment, the first dummy drive circuit is not connected to any light emitting element. The present disclosure can ensure the uniformity of the display driven by the drive circuit and improve the display effect of the display panel by providing the first dummy drive circuit.

[0084] The display panel provided by the embodiments of the present disclosure comprises: a first display area and a second display area located at least one side of the first display area; the first display area comprises: a first region and a second region, and the first region is located between the second region and the second display area; the display panel comprises: a substrate and a circuit structure layer and a light-emitting structure layer which are sequentially stacked on the substrate; the light-emitting structure layer is located in the first display area and the second display area, and the light-emitting structure layer comprises: an anode, an organic light-emitting layer and a cathode; the circuit structure layer at least comprises: a plurality of first dummy driving circuits, the first dummy driving circuits are located in the first region, and the orthographic projection of the first dummy driving circuits on the substrate is located in the orthographic projection range of the anode of the light-emitting structure layer in the first region on the substrate. The plurality of first dummy driving circuits are arranged in the first region, the first dummy driving circuits are not connected to signals, the normal exposure of the circuit structure layer in the second display area is ensured, and the characteristics of the driving circuits in the second display area are consistent; the orthographic projection of the plurality of first dummy driving circuits of the circuit structure layer in the first region on the substrate is located in the orthographic projection range of the anode of the light-emitting structure layer in the first region on the substrate, the area occupied by the first dummy driving circuits is reduced, the diffraction influence of the first dummy driving circuits on the second region is reduced, and the photographing effect of the display panel can be unaffected.

[0085] In an example embodiment, the circuit structure layer 20 further comprises: a plurality of driving circuits PA. The driving circuits PA are located in the second display area, and the driving circuits are configured to drive the light-emitting structure layer in the first display area and the second display area to emit light.

[0086] In an example embodiment, the areas of the at least one driving circuit can be the same. The areas of the at least one driving circuit being the same ensures that the loads of the at least one driving circuit are the same, and the risk of abnormal display can be avoided to a large extent.

[0087] In an example embodiment, the circuit structure layer can further comprise: a signal connection part. The signal connection part is located in the second display area, and the signal connection part is configured to connect the plurality of driving circuits.

[0088] In an example embodiment, the signal connection part can comprise: a plurality of data signal lines, a plurality of scanning signal lines and a plurality of light-emitting signal lines, a plurality of first power supply lines, a plurality of reset signal lines and a plurality of initial signal lines.

[0089] In an example embodiment, the first display area and the second display area are collectively referred to as a display area. The display panel can further comprise a non-display area located at least one side of the display area. The display panel can further comprise: a timing controller, a data driving circuit, a scanning driving circuit and a light-emitting driving circuit located in the non-display area.

[0090] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals suitable for the specifications of the data driving circuit to the data driving circuit, can provide clock signals, scanning start signals, etc. suitable for the specifications of the scanning driving circuit to the scanning driving circuit, and can provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driving circuit to the light-emitting driving circuit.

[0091] In one exemplary embodiment, the data driving circuit may generate a data voltage to be provided to the data signal line using a grayscale value and a control signal received from the timing controller. For example, the data driving circuit may sample the grayscale value using a clock signal and apply a data voltage corresponding to the grayscale value to the data signal line in units of pixel rows.

[0092] In one exemplary embodiment, the scan driver circuit may generate a scan signal to be provided to the scan signal line by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan driver circuit may sequentially provide a scan signal having an on-level pulse to the scan signal line. The scan driver circuit may be configured in the form of a shift register and may generate the scan signal by sequentially transmitting the scan start signal provided in the form of an on-level pulse to the next stage circuit under the control of a clock signal.

[0093] In one exemplary embodiment, the light-emitting driver circuit can generate an emission signal to be provided to the light-emitting signal line by receiving a clock signal, an emission stop signal, etc. from a timing controller. The light-emitting driver circuit can sequentially provide emission signals having cut-off level pulses to the light-emitting signal lines. For example, the light-emitting driver circuit can be configured as a shift register and can generate the light-emitting signal by sequentially transmitting the emission stop signal provided in the form of cut-off level pulses to the next-stage circuit under the control of a clock signal. At least one sub-pixel can be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light-emitting signal line.

[0094] In an exemplary embodiment, the driving circuit includes: a plurality of transistors and capacitors, at least one transistor includes: an active layer, a control electrode, a first electrode and a second electrode, and the capacitor includes: a first electrode plate and a second electrode plate.

[0095] In exemplary embodiments, the driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 5 This is a schematic diagram of an equivalent circuit of a driving circuit. Figure 5As shown, the driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7 and 1 storage capacitor C, and the driving circuit is respectively connected to 7 signal lines (data signal line Data, scan signal line Gate, reset signal line Reset, light emitting signal line EM, initial signal line INIT and first power line VDD).

[0096] In an exemplary embodiment, the anode of the light emitting element is connected to the driving circuit, and the cathode of the light emitting element is connected to the second power line VSS.

[0097] In an exemplary embodiment, the second plate C2 of the storage capacitor C is connected to the first power line VDD, and the first plate C1 of the storage capacitor C is connected to the second node N2.

[0098] In an exemplary embodiment, the control electrode of the first transistor T1 is connected to the reset signal line Reset, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the reset signal line Reset, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3 to initialize the amount of charge at the control electrode of the third transistor T3. The control electrode of the second transistor T2 is connected to the scan signal line Gate, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the scan signal line Gate, the second transistor T2 connects the control electrode and the second electrode of the third transistor T3. The control electrode of the third transistor T3 is connected to the second node N2, i.e., the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS according to the potential difference between the control electrode and the first electrode thereof. The control electrode of the fourth transistor T4 is connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line Data, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be referred to as a switching transistor, a scan transistor, etc., and when the on-level scan signal is applied to the scan signal line Gate, the fourth transistor T4 inputs the data voltage of the data signal line DataD to the driving circuit. The control electrode of the fifth transistor T5 is connected to the emission signal line EM, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the emission signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as emission transistors. When the on-level emission signal is applied to the emission signal line EM, the fifth transistor T5 and the sixth transistor T6 cause the light emitting device to emit light by forming a driving current path between the first power line VDD and the second power line VSS. The control electrode of the seventh transistor T7 is connected to the reset signal line Reset, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. When the on-level scan signal is applied to the scan signal line Gate, the seventh transistor T7 transmits the initialization voltage to the first electrode of the light emitting device to initialize the amount of charge accumulated in the first electrode of the light emitting device or release the amount of charge accumulated in the first electrode of the light emitting device.

[0099] In an example embodiment, the first transistor T1 to the seventh transistor T7 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 can include P-type transistors and N-type transistors. When a low level is loaded on the gate electrode of a P-type transistor, the P-type transistor is turned on, and when a high level is loaded on the gate electrode of the P-type transistor, the P-type transistor is turned off. The two levels are also commonly used to turn on and turn off the transistors, respectively, and thus the higher of the two is commonly referred to as a high level, and the lower is commonly referred to as a low level.

[0100] In an example embodiment, the first transistor T1 to the seventh transistor T7 can be low-temperature polysilicon thin film transistors, or can be oxide thin film transistors, or can be low-temperature polysilicon thin film transistors and oxide thin film transistors. The active layer of the low-temperature polysilicon thin film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is made of oxide. The low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. In an example implementation, the low-temperature polysilicon thin film transistor and the oxide thin film transistor can be integrated on one display substrate to form a low-temperature polysilicon oxide (LTPO) display substrate, the advantages of both can be utilized, high resolution (Pixel Per Inch, PPI) can be achieved, low-frequency driving can be achieved, power consumption can be reduced, and display quality can be improved.

[0101] In an example embodiment, the signal of the second power supply line VSS is a low-level signal, and the signal of the first power supply line VDD is a high-level signal that is continuously provided. The scan signal line Gate is a scan signal line in the current display row driving circuit, and the reset signal line Reset is a scan signal line in the previous display row driving circuit, that is, for the n th display row, the reset signal line of the current display row and the scan signal line in the previous display row driving circuit are the same signal line, which can reduce the signal lines of the display panel and achieve a narrow frame of the display panel.

[0102] In an example embodiment, the scan signal line Gate, the reset signal line Reset, the emission signal line E, and the initial signal line INIT extend along the horizontal direction, and the second power supply line VSS, the first power supply line VDD, and the data signal line Data extend along the vertical direction.

[0103] Figure 6Fig. 1 is a timing diagram of the operation of a driving circuit. The operation of the driving circuit will be described below with reference to Figure 5 The operation of the driving circuit of the example illustrates the exemplary embodiments of the present disclosure, Figure 5 The driving circuit in Fig. 1 includes seven transistors (first transistor T1 to sixth transistor T7), one storage capacitor C, and seven signal lines (data signal line D, scan signal line Gate, reset signal line Reset, emission signal line EM, initial signal line INIT, first power supply line VDD, and second power supply line VSS). The seven transistors are P-type transistors.

[0104] In an exemplary embodiment, the operation of the driving circuit can include:

[0105] In the first stage, referred to as the reset stage, the signal of the reset signal line Reset is a low-level signal, and the signals of the scan signal line Gate and the emission signal line EM are high-level signals. The low-level signal of the reset signal line Reset turns on the first transistor T1, and the signal of the initial signal line INIT is provided to the second node N2, initializing the storage capacitor C and clearing the original data voltage in the storage capacitor. The seventh transistor T7 is turned on, and the initial voltage of the initial signal line INIT is provided to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED and clearing the pre-stored voltage in the first electrode, completing the initialization and ensuring that the OLED does not emit light. The high-level signals of the scan signal line Gate and the emission signal line EM turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6, and the OLED does not emit light in this stage.

[0106] In the second stage, called the data writing stage or threshold compensation stage, the signal of the scan signal line Gate is a low level signal, the signals of the reset signal line Reset and the light emitting signal line EM are high level signals, and the data signal line Data outputs a data voltage. In this stage, the first plate of the storage capacitor C is at a low level, so the third transistor T3 is turned on. The low level signal of the scan signal line Gate turns on the second transistor T2 and the fourth transistor T4. The turned-on second transistor T2 and the fourth transistor T4 make the data voltage outputted by the data signal line Data pass through the first node N1, the turned-on third transistor T3, the third node N3, the turned-on second transistor T2, and then be provided to the second node N2, and the difference between the data voltage outputted by the data signal line Data and the threshold voltage of the third transistor T3 is charged into the storage capacitor C, so that the voltage of the second end (the second node N2) of the storage capacitor C is Vd-|Vth|, Vd is the data voltage outputted by the data signal line Data, and Vth is the threshold voltage of the third transistor T3. The high level signal of the reset signal line Reset turns off the first transistor T1 and the seventh transistor T7. The high level signal of the light emitting signal line EM turns off the fifth transistor T5 and the sixth transistor T6.

[0107] In the third stage, called the light emitting stage, the signal of the light emitting signal line EM is a low level signal, and the signals of the scan signal line Gate and the reset signal line Reset are high level signals. The low level signal of the light emitting signal line EM turns on the fifth transistor T5 and the sixth transistor T6, and the power voltage outputted by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, so as to drive the OLED to emit light.

[0108] In the driving process of the driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the gate electrode and the first electrode of the third transistor T3. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0109] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0110] wherein I is the driving current flowing through the third transistor T3, that is, the driving current of the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage outputted by the data signal line Data, and Vdd is the power voltage outputted by the first power supply line VDD.

[0111] In an exemplary embodiment, as shown in FIG. 1, the driving circuit comprises at least: an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer and a third metal layer, which are sequentially stacked on the substrate. Figure 3

[0112] In an exemplary embodiment, the active layer of the driving circuit can comprise: active layers of a plurality of transistors; for example, an active layer T61 of a sixth transistor.

[0113] In an exemplary embodiment, the first metal layer of the driving circuit can comprise: control electrodes of a plurality of transistors and a first plate C1 of a capacitor. A reset signal line, a light-emitting signal line and a scanning signal line are arranged in the same layer as the first metal layer of the driving circuit.

[0114] In an exemplary embodiment, the second metal layer of the driving circuit can comprise: a second plate C2 of a capacitor. An initial signal line is arranged in the same layer as the second metal layer of the driving circuit.

[0115] In an exemplary embodiment, the third metal layer of the driving circuit can comprise: first and second electrodes of a plurality of transistors, for example, a first electrode T63 and a second electrode T64 of a sixth transistor. A data signal line and a first power supply line are arranged in the same layer as the third metal layer of the driving circuit.

[0116] In an exemplary embodiment, the active layer can be a metal oxide layer. The metal oxide layer can be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer can be a single layer, or can be a double layer, or can be a multi-layer.

[0117] In an exemplary embodiment, the first metal layer, the second metal layer and the third metal layer can adopt a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0118] In an exemplary embodiment, the first insulating layer, the second insulating layer and the third insulating layer can adopt any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), which can be a single layer, a multi-layer or a composite layer.

[0119] ​In an example embodiment, the first dummy drive circuit can include at least one film layer of an active layer, a first metal layer, a second metal layer, and a third metal layer. The first dummy drive circuit is arranged in the same layer as the drive circuit. Figures 2A-2D The first dummy drive circuit is described by taking an example that the first dummy drive circuit only includes the active layer, but the disclosure is not limited thereto.

[0120] In an example embodiment, the first dummy drive circuit includes the active layer, and the active layer of the first dummy drive circuit is arranged in the same layer as the active layer of the drive circuit; and / or, the first dummy drive circuit includes the first metal layer, and the first metal layer of the first dummy drive circuit is arranged in the same layer as the first metal layer of the drive circuit; and / or, the first dummy drive circuit includes the second metal layer, and the second metal layer of the first dummy drive circuit is arranged in the same layer as the second metal layer of the drive circuit; and / or, the first dummy drive circuit includes the third metal layer, and the third metal layer of the first dummy drive circuit is arranged in the same layer as the third metal layer of the drive circuit.

[0121] In an example embodiment, as shown in FIG. 1A, the area of the anode of the light-emitting structure layer in the first region can be greater than or equal to the area of the first dummy drive circuit. Figures 2A-2B As shown in FIG. 1A and FIG. 1B, the area of the anode of the light-emitting structure layer in the first region is greater than the area of the first dummy drive circuit. Figure 2A As shown in FIG. 1A and FIG. 1B, the area of the anode of the light-emitting structure layer in the first region is greater than the area of the first dummy drive circuit. Figure 2B As shown in FIG. 1A and FIG. 1B, the area of the anode of the light-emitting structure layer in the first region is greater than the area of the first dummy drive circuit. Figure 2C As shown in FIG. 1A and FIG. 1B, the area of the anode of the light-emitting structure layer in the first region is greater than the area of the first dummy drive circuit. Figure 2D As shown in FIG. 1A and FIG. 1B, the area of the anode of the light-emitting structure layer in the first region is greater than the area of the first dummy drive circuit.

[0122] In an example embodiment, when the area of the anode of the light-emitting structure layer in the first region is equal to the area of the first dummy drive circuit, the orthographic projection of the first dummy drive circuit VPA1 on the substrate can coincide with the orthographic projection of the anode 31 of the light-emitting structure layer in the first region on the substrate.

[0123] In an example embodiment, when the area of the anode of the light-emitting structure layer in the first region is greater than the area of the first dummy drive circuit, and the first dummy drive circuit includes the active layer, the pattern of the active layer of the first dummy drive circuit can be partially the same as the pattern of the active layer of the drive circuit.

[0124] In an example embodiment, when the area of the anode of the light-emitting structure layer in the first region is greater than the area of the first dummy drive circuit, and the first dummy drive circuit includes the first metal layer, the pattern of the first metal layer of the first dummy drive circuit can be partially the same as the pattern of the first metal layer of the drive circuit.

[0125] In an example embodiment, when the area of the anode of the light-emitting structure layer located in the first region is greater than the area of the first dummy drive circuit, and the first dummy drive circuit includes the second metal layer, the pattern of the second metal layer of the first dummy drive circuit can be partially the same as the pattern of the second metal layer of the drive circuit.

[0126] In an example embodiment, when the area of the anode of the light-emitting structure layer located in the first region is greater than the area of the first dummy drive circuit, and the first dummy drive circuit includes the third metal layer, the pattern of the third metal layer of the first dummy drive circuit can be partially the same as the pattern of the third metal layer of the drive circuit.

[0127] In an example embodiment, when the area of the anode of the light-emitting structure layer located in the first region is equal to the area of the first dummy drive circuit, and the first dummy drive circuit includes the active layer, the pattern of the active layer of the first dummy drive circuit can be the same as the pattern of the anode of the light-emitting structure layer located in the first region.

[0128] In an example embodiment, when the area of the anode of the light-emitting structure layer located in the first region is equal to the area of the first dummy drive circuit, and the first dummy drive circuit includes the first metal layer, the pattern of the first metal layer of the first dummy drive circuit is the same as the pattern of the anode of the light-emitting structure layer located in the first region.

[0129] In an example embodiment, when the area of the anode of the light-emitting structure layer located in the first region is equal to the area of the first dummy drive circuit, and the first dummy drive circuit includes the second metal layer, the pattern of the second metal layer of the first dummy drive circuit is the same as the pattern of the anode of the light-emitting structure layer located in the first region.

[0130] In an example embodiment, when the area of the anode of the light-emitting structure layer located in the first region is equal to the area of the first dummy drive circuit, and the first dummy drive circuit includes the third metal layer, the pattern of the third metal layer of the first dummy drive circuit is the same as the pattern of the anode of the light-emitting structure layer located in the first region.

[0131] In an example embodiment, as shown in FIGS. 1A and 1B, the circuit structure layer can further include a plurality of second dummy drive circuits VPA2. The second dummy drive circuits VPA2 are located in the second region A12, and the orthographic projection of the second dummy drive circuits VPA2 on the substrate is located within the orthographic projection range of the anode of the light-emitting structure layer located in the second region on the substrate. Figure 2B Figure 2D In an example embodiment, the orthographic projection of the pixel definition layer on the substrate and the orthographic projection of the second dummy drive circuit on the substrate do not have an overlapping region.

[0132] In an example embodiment, the orthographic projection of the pixel definition layer on the substrate and the orthographic projection of the second dummy drive circuit on the substrate do not have an overlapping region.

[0133] ​In an example embodiment, the second dummy driving circuit is not connected with any light emitting element. The present disclosure can ensure the uniformity of the display driven by the driving circuit by arranging the second dummy driving circuit, and can improve the display effect of the display panel.

[0134] In an example embodiment, the second dummy driving circuit can include at least one film layer of an active layer, a first metal layer, a second metal layer and a third metal layer, and the second dummy driving circuit is arranged in the same layer as the driving circuit. As shown in Figure 2B and Figure 2D The second dummy driving circuit and the active layer are taken as examples for illustration, and the present disclosure is not limited thereto.

[0135] In an example embodiment, the second dummy driving circuit includes an active layer, the active layer of the second dummy driving circuit is arranged in the same layer as the active layer of the driving circuit; and / or, the second dummy driving circuit includes a first metal layer, the first metal layer of the second dummy driving circuit is arranged in the same layer as the first metal layer of the driving circuit; and / or, the second dummy driving circuit includes a second metal layer, the second metal layer of the second dummy driving circuit is arranged in the same layer as the second metal layer of the driving circuit; and / or, the second dummy driving circuit includes a third metal layer, the third metal layer of the second dummy driving circuit is arranged in the same layer as the third metal layer of the driving circuit.

[0136] In an example embodiment, as shown in Figure 2B and Figure 2D The area of the anode 31 of the light emitting structure layer located in the second region can be greater than or equal to the area of the second dummy driving circuit VPA2. Figure 2B As shown in Figure 2D is taken as an example for illustration that the area of the anode of the light emitting structure layer located in the second region is greater than the area of the second dummy driving circuit.

[0137] In an example embodiment, when the area of the anode of the light emitting structure layer located in the second region is equal to the area of the second dummy driving circuit, the orthographic projection of the second dummy driving circuit VPA2 on the substrate can coincide with the orthographic projection of the anode 31 of the light emitting structure layer of the first region on the substrate.

[0138] In an example embodiment, when the area of the anode of the light emitting structure layer located in the second region can be greater than the area of the second dummy driving circuit, and the second dummy driving circuit includes an active layer, the pattern of the active layer of the second dummy driving circuit can be partially the same as the pattern of the active layer of the driving circuit.

[0139] In an exemplary embodiment, when the area of the anode of the light emitting structure layer located in the second region can be greater than the area of the second dummy driving circuit, and the second dummy driving circuit includes a first metal layer, the pattern of the first metal layer of the second dummy driving circuit can be partially the same as the pattern of the first metal layer of the driving circuit.

[0140] In an exemplary embodiment, when the area of the anode of the light emitting structure layer located in the second region can be greater than the area of the second dummy driving circuit, and the second dummy driving circuit includes a second metal layer, the pattern of the second metal layer of the second dummy driving circuit can be partially the same as the pattern of the second metal layer of the driving circuit.

[0141] In an exemplary embodiment, when the area of the anode of the light emitting structure layer located in the second region can be greater than the area of the second dummy driving circuit, and the second dummy driving circuit includes a third metal layer, the pattern of the third metal layer of the second dummy driving circuit can be partially the same as the pattern of the third metal layer of the driving circuit.

[0142] In an exemplary embodiment, when the area of the anode of the light emitting element located in the second region is equal to the area of the second dummy driving circuit, and the second dummy driving circuit includes an active layer, the pattern of the active layer of the second dummy driving circuit can be the same as the pattern of the anode of the light emitting element located in the second region.

[0143] In an exemplary embodiment, when the area of the anode of the light emitting element located in the second region is equal to the area of the second dummy driving circuit, and the second dummy driving circuit includes a first metal layer, the pattern of the first metal layer of the second dummy driving circuit can be the same as the pattern of the anode of the light emitting element located in the second region;

[0144] In an exemplary embodiment, when the area of the anode of the light emitting element located in the second region is equal to the area of the second dummy driving circuit, and the second dummy driving circuit includes a second metal layer, the pattern of the second metal layer of the second dummy driving circuit can be the same as the pattern of the anode of the light emitting element located in the second region;

[0145] In an exemplary embodiment, when the area of the anode of the light emitting element located in the second region is equal to the area of the second dummy driving circuit, and the second dummy driving circuit includes a third metal layer, the pattern of the third metal layer of the second dummy driving circuit can be the same as the pattern of the anode of the light emitting element located in the second region.

[0146] In an exemplary embodiment, as shown in FIG. 1, a light emitting element includes an anode, an organic light emitting layer, and a cathode. The light emitting element emits a plurality of different colors of light. The light emitting area of the light emitting element of a first display region is less than or equal to the light emitting area of the light emitting element of a second display region which emits the same color of light. Figures 2A-2D In an exemplary embodiment, as shown in FIG. 1, a light emitting element includes an anode, an organic light emitting layer, and a cathode. The light emitting element emits a plurality of different colors of light. The light emitting area of the light emitting element of a first display region is less than or equal to the light emitting area of the light emitting element of a second display region which emits the same color of light.

[0147] In an exemplary embodiment, the light emitting element can emit light of at least three colors, which may include: a first color light, a second color light, and a third color light.

[0148] In an exemplary embodiment, when the light-emitting element emits three colors of light, the light-emitting area of ​​the light-emitting element emitting the first color of light located in the first display area is smaller than the light-emitting area of ​​the light-emitting element emitting the first color of light located in the second display area, the light-emitting area of ​​the light-emitting element emitting the second color of light located in the first display area is smaller than the light-emitting area of ​​the light-emitting element emitting the second color of light located in the second display area, and the light-emitting area of ​​the light-emitting element emitting the third color of light located in the first display area is smaller than the light-emitting area of ​​the light-emitting element emitting the third color of light located in the second display area.

[0149] In an exemplary embodiment, the light-emitting area of ​​the light-emitting element emitting the first color light located in the first region is equal to the light-emitting area of ​​the light-emitting element emitting the first color located in the second region, the light-emitting area of ​​the light-emitting element emitting the second color located in the first region is equal to the light-emitting area of ​​the light-emitting element emitting the second color located in the second region, and the light-emitting area of ​​the light-emitting element emitting the third color located in the first region is equal to the light-emitting area of ​​the light-emitting element emitting the third color located in the second region.

[0150] In an exemplary embodiment, the light emitting area of ​​the light emitting element may be greater than or equal to the area of ​​the anode of the light emitting element.

[0151] In an exemplary embodiment, Figures 2A-2D As shown, the boundary of the anode of the light-emitting structure layer located in the first display area can be a curved boundary. The curved boundary of the anode of the light-emitting element located in the first display area can reduce diffraction on the one hand, and on the other hand, reduce the area of ​​the anode of the light-emitting element, thereby improving the transmittance of the first display area.

[0152] In an exemplary embodiment, Figures 2A-2D As shown, the anode boundary of the light-emitting element located in the second display area and near the edge of the first display area is a curved boundary. This curved boundary can serve as a transition and improve the uniformity of the display panel.

[0153] In an exemplary embodiment, Figures 2A-2D As shown, the boundary of the anode of the light-emitting element located in the second display area close to the edge of the first display area is a straight line boundary.

[0154] In an exemplary embodiment, Figure 3As shown, the circuit structure layer further comprises a transfer portion VL. The transfer portion VL is located between the first display area and the second display area.

[0155] In an exemplary embodiment, the transfer portion VL is a transparent transfer portion at least in the first display area.

[0156] In an exemplary embodiment, the transfer portion is connected with the driving circuit and is used to drive the light emitting element in the first display area.

[0157] In an exemplary embodiment, as shown, the circuit structure layer can further comprise a fourth insulating layer 24, a transparent conductive layer and a planar layer 25 which are sequentially stacked on the third metal layer. The transparent conductive layer comprises the transfer portion. Figure 3

[0158] In an exemplary embodiment, the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) and can be a single layer, multiple layers or a composite layer.

[0159] In an exemplary embodiment, the transparent conductive layer can be made of indium tin oxide (ITO) or indium zinc oxide (IZO).

[0160] In an exemplary embodiment, the planar layer can be made of an organic material such as polyimide, acrylic or polyethylene terephthalate.

[0161] In an exemplary embodiment, as shown, Figure 3 The display panel can further comprise an encapsulation layer 40 and a spacer 50.

[0162] In an exemplary embodiment, the encapsulation layer 40 is arranged on the side of the light emitting structure layer 30 away from the substrate 10, and the spacer 50 is arranged on the side of the encapsulation layer 40 away from the substrate 10.

[0163] In an exemplary embodiment, the encapsulation layer 40 can have a stacked structure of inorganic material / organic material / inorganic material, and the organic material layer is arranged between the two inorganic material layers. Exemplarily, the encapsulation layer can comprise a first encapsulation layer, a second encapsulation layer and a third encapsulation layer which are stacked, the first encapsulation layer and the third encapsulation layer can be made of inorganic material, the second encapsulation layer can be made of organic material, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to prevent external water vapor from entering the light emitting device.

[0164] ​The preparation process of the display panel is exemplarily illustrated below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal materials, inorganic materials or transparent conductive materials, and includes coating organic materials, mask exposure and development and the like for organic materials. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate (or substrate substrate) made by deposition, coating or other processes. If the "thin film" does not need a patterning process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" needs a patterning process during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0165] In an exemplary embodiment, the first region includes a first dummy drive circuit. The first dummy drive circuit includes an active layer. The preparation process of the display panel can include the following steps:

[0166] (1) Forming an active layer on a substrate, including: depositing an active layer thin film on a substrate, and patterning the active layer thin film by a patterning process to form an active layer. The active layer includes an active layer of a drive circuit and an active layer of a first dummy drive circuit, as shown in Figure 7A and Figure 7B , and Figure 7A is a schematic diagram after forming the active layer, Figure 7B is a schematic diagram of the drive circuit after forming the active layer.

[0167] In an exemplary embodiment, the active layer of the drive circuit includes an active layer T11 of a first transistor to an active layer T71 of a seventh transistor. For at least one drive circuit, the active layers of all transistors are integrally formed

[0168] (2) forming a first metal layer, comprising: depositing a first insulating film on the substrate on which the active layer is formed, patterning the first insulating film by a patterning process to form a first insulating layer; depositing a first metal film on the first insulating layer, and patterning the first metal film by a patterning process to form a first metal layer. As shown in Figure 8A and Figure 8B , as shown in Figure 8A is a schematic view after forming the first metal layer, Figure 8B is a schematic view of the driving circuit after forming the first metal layer.

[0169] In an exemplary embodiment, the first metal layer comprises: control electrodes of the first to seventh transistors T12-T72, a scan signal line Gate, a reset signal line Reset, a light-emitting signal line EM, and a first plate C1 of a capacitor.

[0170] In an exemplary embodiment, the driving circuits in the same row are connected to the same scan signal line, the driving circuits in the same row are connected to the same reset signal line, and the driving circuits in the same row are connected to the same light-emitting signal line.

[0171] In an exemplary embodiment, the first plate of the capacitor comprises: a first side and a second side arranged opposite to each other. The scan signal line and the reset signal line are located on the first side of the first plate of the capacitor, the reset signal line is located on the side of the scan signal line away from the first plate of the capacitor, and the light-emitting signal line is located on the second side of the first plate of the capacitor.

[0172] In an exemplary embodiment, the control electrode of the first transistor is arranged across the active layer of the first transistor, the control electrode of the second transistor is arranged across the active layer of the second transistor, the control electrode of the third transistor is arranged across the active layer of the third transistor, the control electrode of the fourth transistor is arranged across the active layer of the fourth transistor, the control electrode of the fifth transistor is arranged across the active layer of the fifth transistor, the control electrode of the sixth transistor is arranged across the active layer of the sixth transistor, and the control electrode of the seventh transistor is arranged across the active layer of the sixth transistor.

[0173] In an exemplary embodiment, the control electrode of the first transistor and the control electrode of the seventh transistor are in an integral molding structure with the reset signal line. The control electrode of the second transistor, the control electrode of the fourth transistor, and the scan signal line are in an integral molding structure. The control electrode of the third transistor and the first plate of the capacitor are in an integral molding structure, and the control electrode of the fifth transistor, the control electrode of the sixth transistor, and the light-emitting signal line are in an integral molding structure.

[0174] (3) forming a second metal layer, comprising: depositing a second insulating film on the substrate on which the first metal layer is formed, patterning the second insulating film by a patterning process to form a second insulating layer. Depositing a second metal film on the substrate on which the second insulating layer is formed, patterning the second metal film by a patterning process to form a second metal layer, as shown in Figure 9A and Figure 9B , Figure 9A is a schematic view after forming the second metal layer, Figure 9B is a schematic view after forming the second metal layer of the driving circuit.

[0175] In an exemplary embodiment, the second metal layer comprises: an initial signal line VINT and a second plate C2 of a capacitor.

[0176] In an exemplary embodiment, the initial signal line VINT is located on the side of the reset signal line away from the scan signal line, and the second plate C2 of the capacitor is located between the scan signal line and the light-emitting signal line.

[0177] In an exemplary embodiment, the second plate C2 is provided with a via hole exposing the first plate.

[0178] (4) forming a third metal layer, comprising: depositing a third insulating film on the substrate on which the second metal layer is formed, patterning the third insulating film by a patterning process to form a third insulating layer. Depositing a third metal film on the substrate on which the third insulating layer is formed, patterning the third metal film by a patterning process to form a third metal layer, as shown in Figure 10A and Figure 10B , Figure 10A is a schematic view after forming the third metal layer, Figure 10B is a schematic view after forming the third metal layer of the driving circuit.

[0179] In an exemplary embodiment, the third insulating layer is provided with a plurality of via holes located between the first insulating layer and the third insulating layer.

[0180] In an exemplary embodiment, the third metal layer comprises: a data signal line Data, a first power supply line VDD, a first electrode T13 of a first transistor, a second electrode T14 of the first transistor, a first electrode T23 of a second transistor, a first electrode T43 of a fourth transistor, a first electrode T53 of a fifth transistor, a second electrode T64 of a sixth transistor, a first electrode T73 of a seventh transistor, and a second electrode T74 of the seventh transistor.

[0181] In an exemplary embodiment, the first electrode T13 of the first transistor and the first electrode T73 of the seventh transistor are integrally formed. The second electrode T14 of the first transistor and the first electrode T23 of the second transistor are integrally formed. The first electrode T43 of the fourth transistor and the first power line VDD are integrally formed. The first electrode T53 of the fifth transistor and the data signal line Data are integrally formed. The second electrode T64 of the sixth transistor and the second electrode T74 of the seventh transistor are integrally formed.

[0182] In an exemplary embodiment, part of the active layer is multiplexed as the first electrode T33 of the third transistor, the second electrode T44 of the fourth transistor and the second electrode T54 of the fifth transistor. Part of the active layer is multiplexed as the second electrode T24 of the second transistor, the second electrode T34 of the third transistor and the first electrode T63 of the sixth transistor.

[0183] (5) Forming an anode, comprising: depositing a fourth insulating thin film on a substrate on which a third metal layer is formed, patterning the fourth insulating thin film by a patterning process to form a fourth insulating layer. Coating a first transparent conductive thin film on the substrate on which the fourth insulating layer is formed, patterning the first transparent conductive thin film by a patterning process to form a transparent conductive layer. Coating a planar thin film on the substrate on which the transparent conductive layer is formed, forming a planar layer by mask, exposure and development of the planar thin film. Depositing a second transparent conductive thin film on the substrate on which the planar layer is formed, patterning the second transparent conductive thin film by a patterning process to form an anode. The anode is formed in at least one light emitting element, as shown in Figure 2A .

[0184] (6) Forming a pixel definition layer, comprising: coating a pixel definition thin film on the substrate on which the anode is formed, forming a pixel definition layer (Pixel Define Layer) by a mask, exposure and development process. The pixel definition layer is formed in at least one light emitting element, and the pixel definition layer in the at least one light emitting element is formed with an opening area exposing the anode.

[0185] (7) Forming an organic light emitting layer, comprising: forming an organic light emitting layer in the opening area of the formed pixel definition layer and on the pixel definition layer. The organic light emitting layer is electrically connected with the first electrode.

[0186] (8) Forming a cathode, comprising: coating a conductive thin film on the substrate on which the organic light emitting layer is formed, patterning the conductive thin film by a patterning process to form a cathode. The cathode covers the organic light emitting layer in at least one light emitting element. The cathode is electrically connected with the organic light emitting layer.

[0187] (9) forming an encapsulation layer, forming an encapsulation layer on the substrate on which the second electrode is formed, the encapsulation layer including a first encapsulation layer of inorganic material, a second encapsulation layer of organic material, and a third encapsulation layer of inorganic material, the first encapsulation layer being disposed on the second electrode, the second encapsulation layer being disposed on the first encapsulation layer, and the third encapsulation layer being disposed on the second encapsulation layer, forming a laminated structure of inorganic material / organic material / inorganic material.

[0188] The display device provided by the embodiments of the present disclosure can be an organic light-emitting diode (OLED) display device, an active-matrix organic light-emitting diode (AMOLED) display device, a mobile phone, a tablet computer, a flexible display device, a television, a display, or any product or component with a display function.

[0189] In an example embodiment, the display device can be any product or component with a display function, such as an organic light-emitting diode (OLED) display device, an active-matrix organic light-emitting diode (AMOLED) display device, a mobile phone, a tablet computer, a flexible display device, a television, a display, and the like. The drawings in the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can be referred to general designs.

[0190] The display panel is the display panel provided in any of the above embodiments, and has similar principles and effects, which will not be described here.

[0191] In an example embodiment, the display device can further include an optical element, and the optical element is located in the first display area of the display panel.

[0192] In an example embodiment, the first display area can be rectangular, and the area of the orthographic projection of the optical element on the substrate can be less than or equal to the area of the inscribed circle of the first display area. That is, the size of the area where the optical element is located can be less than or equal to the size of the inscribed circle of the first display area. For example, the size of the area where the optical element is located is equal to the size of the inscribed circle of the first display area, that is, the shape of the area where the optical element is located can be circular, and correspondingly, the area where the optical element is located can also be referred to as a light transmission hole.

[0193] In an example embodiment, the optical element can be an optical sensor such as a fingerprint recognition device, a camera, or a 3D imaging device, which is not limited in the present disclosure.

[0194] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe embodiments of the present disclosure. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intermediate element.

[0195] Although the disclosed embodiments have been fully described above with reference to the attachments, figures, and the accompanying drawings, other embodiments can be utilized and changes can be made without departing from the scope of the disclosure, which is not to be limited by the above-described embodiments. Accordingly, various modifications and changes can be made to the embodiments without departing from the scope of the disclosure as set forth in the claims below. The disclosure is not to be limited to the embodiments set forth herein for the purpose of the practice of the present disclosure.

Claims

1. A display panel, characterized in that: include: a first display area and a second display area located on at least one side of the first display area; The first display area includes: a first region and a second region, the first region is located between the second region and the second display area; The display panel comprises: a substrate, and a circuit structure layer and a light emitting structure layer sequentially stacked on the substrate; The light emitting structure layer is located in the first display area and the second display area, and the light emitting structure layer includes: an anode, a light emitting layer and a cathode; The circuit structure layer includes at least: a plurality of first dummy drive circuits, the first dummy drive circuits are not connected to signals, the first dummy drive circuits are located in the first area, and the orthographic projection of the first dummy drive circuit on the substrate is located within the orthographic projection range of the anode of the light-emitting structure layer in the first area on the substrate.

2. The display panel according to claim 1, wherein: The circuit structure layer further includes: a plurality of driving circuits, wherein the driving circuits are located in the second display area and are configured to drive the light emitting structure layers in the first display area and the second display area to emit light.

3. The display panel according to claim 2, wherein: The driving circuit at least comprises: an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer and a third metal layer stacked in sequence on the substrate.

4. The display panel according to claim 3, wherein: The first dummy driving circuit includes: an active layer, a first metal layer, a second metal layer and at least one film layer of a third metal layer, and the first dummy driving circuit is provided in the same layer as the driving circuit.

5. The display panel according to claim 4, wherein: The first dummy driving circuit includes an active layer, and the active layer of the first dummy driving circuit is provided on the same layer as the active layer of the driving circuit; And / or, the first dummy driving circuit includes a first metal layer, and the first metal layer of the first dummy driving circuit is provided on the same layer as the first metal layer of the driving circuit; And / or, the first dummy driving circuit includes a second metal layer, and the second metal layer of the first dummy driving circuit is provided on the same layer as the second metal layer of the driving circuit; And / or, the first dummy driving circuit includes a third metal layer, and the third metal layer of the first dummy driving circuit is provided on the same layer as the third metal layer of the driving circuit.

6. The display panel according to claim 4, wherein: An area of ​​the anode of the light emitting structure layer in the first region is greater than or equal to an area of ​​the first dummy driving circuit.

7. The display panel according to any one of claims 4 to 6, characterized in that: The circuit structure layer further includes: a plurality of second dummy driving circuits, the second dummy driving circuits are located in the second area, and the orthographic projections of the second dummy driving circuits on the substrate are located within the orthographic projection range of the anode of the light-emitting structure layer in the second area on the substrate.

8. The display panel according to claim 7, wherein: The second dummy driving circuit includes: at least one film layer among an active layer, a first metal layer, a second metal layer and a third metal layer, and the second dummy driving circuit is provided in the same layer as the driving circuit.

9. The display panel according to claim 8, wherein: The second dummy driving circuit includes an active layer, and the active layer of the second dummy driving circuit is arranged on the same layer as the active layer of the driving circuit; And / or, the second dummy driving circuit includes a first metal layer, and the first metal layer of the second dummy driving circuit is provided on the same layer as the first metal layer of the driving circuit; And / or, the second dummy driving circuit includes a second metal layer, and the second metal layer of the second dummy driving circuit is provided on the same layer as the second metal layer of the driving circuit; And / or, the second dummy driving circuit includes a third metal layer, and the third metal layer of the second dummy driving circuit is provided on the same layer as the third metal layer of the driving circuit.

10. The display panel according to claim 8, wherein An area of ​​the anode of the light emitting structure layer located in the second region is greater than or equal to an area of ​​the second dummy driving circuit.

11. The display panel according to claim 1, wherein The first display area is a transparent display area; The resolution of the first display area is the same as the resolution of the second display area, or the resolution of the first display area is different from the resolution of the second display area.

12. The display panel according to claim 1, wherein The light emitting structure layer includes: a plurality of light emitting elements, each of which includes: an anode, an organic light emitting layer and a cathode; and each of which emits light of a plurality of different colors; The light emitting area of ​​the light emitting element in the first display area is smaller than or equal to the light emitting area of ​​the light emitting element in the second display area that emits the same color.

13. The display panel according to claim 1, wherein The boundary of the anode of the light-emitting structure layer in the first display area is a curved boundary, the boundary of the anode of the light-emitting structure layer located in the second display area and close to the edge of the first display area is a curved boundary, and the boundary of the anode of the light-emitting structure layer located in the second display area close to the edge of the first display area is a straight boundary.

14. The display panel according to claim 3, wherein: The circuit structure layer further includes: a signal connection portion, the signal connection portion is located in the second display area, and the signal connection portion is used to connect the plurality of driving circuits; The adapter is located in the first display area and the second display area. The adapter is a transparent adapter at least in the first display area. The adapter is connected to the driving circuit and is used to drive the light-emitting element in the first display area.

15. The display panel according to claim 14, wherein: The circuit structure layer further includes: a fourth insulating layer, a transparent conductive layer and a flat layer stacked sequentially on the third metal layer; The transparent conductive layer includes the transition portion.

16. A display device, characterized in that: include: The display panel according to any one of claims 1 to 15.

17. The display device according to claim 16, wherein: Also includes: An optical element is provided, and the optical element is located in the first display area of ​​the display panel.

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