Semiconductor package device

Abstract

The present disclosure relates to a semiconductor packaging device. The semiconductor packaging device comprises a circuit layer, a pad is arranged on the surface of the circuit layer, a metal particle layer is arranged on the surface of the pad; an electronic element is arranged on the circuit layer, an active surface is electrically connected to the pad by a wire, one end of the wire is bonded to the metal particle layer. By bonding one end of the wire to the metal particle layer, the bonding temperature when the wire is electrically connected to the pad is reduced, thereby improving the problem of pad sagging caused by the bonding temperature softening the dielectric material of the circuit layer when the wire is directly combined with the pad.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, and more specifically to semiconductor packaging apparatus. Background Technology

[0002] Wire bonding on fan-out redistribution layers is a novel packaging technology. In fan-out redistribution layer structures, PI (Polyimide) soft materials are widely used as dielectric and passivation layers. However, during the wire bonding process, the bonding of the wire bonding metal (e.g., copper, Cu) with the redistribution layer pad metal (e.g., Cu) requires high temperatures, typically above 200 degrees Celsius. Therefore, the PI softens due to the high temperature during bonding, causing the redistribution layer pads to sink into the PI, reducing the bonding effect between the wire bonding and the fan-out redistribution layer. Summary of the Invention

[0003] This disclosure provides a semiconductor packaging apparatus and a method for manufacturing the same.

[0004] In a first aspect, this disclosure provides a semiconductor packaging apparatus, comprising:

[0005] The circuit layer has pads on its surface, and a layer of metal particles is disposed on the surface of the pads.

[0006] An electronic component is disposed on the circuit layer, with its active surface electrically connected to the pads via wire bonding, and one end of the wire bonding being bonded to the metal particle layer.

[0007] In some alternative implementations, the metal particle layer comprises a plurality of laid-out metal particles.

[0008] In some alternative implementations, the metal particle layer comprises a plurality of metal particles arranged in a particle matrix.

[0009] In some alternative embodiments, there are gaps between adjacent metal particles in the metal particle layer.

[0010] In some alternative embodiments, the material of the metal particle layer includes copper, silver, or gold.

[0011] In some alternative embodiments, the interface roughness of the metal particle layer ranges from 10 nanometers to 100 nanometers.

[0012] In some alternative implementations, the temperature at which one end of the wire bonded to the metal particle layer is less than 150 degrees Celsius.

[0013] In some alternative embodiments, the tensile strength of one end of the wire bonded to the metal particle layer is greater than 5 grams.

[0014] In some alternative embodiments, the thickness of the metal particle layer includes 50 nanometers to 800 nanometers.

[0015] In some alternative embodiments, the diameter of the metal particles in the metal particle layer ranges from 25 nanometers to 200 nanometers.

[0016] Secondly, this disclosure provides a method for manufacturing a semiconductor packaging device, including:

[0017] Provide a dielectric layer;

[0018] The surface of the dielectric layer is etched to form a rough interface on the surface of the dielectric layer;

[0019] Metal particles are sputtered onto the surface of the dielectric layer to form a metal particle layer;

[0020] A circuit layer is provided, the surface of which is provided with pads;

[0021] The metal particle layer is placed on the circuit layer, and the portion of the metal particle layer corresponding to the non-pad area on the surface of the circuit layer is removed.

[0022] In some alternative embodiments, the thickness of the metal particle layer includes 50 nanometers to 800 nanometers.

[0023] In some optional implementations, the method further includes:

[0024] Provide electronic components;

[0025] The electronic components are disposed on the circuit layer;

[0026] One end of the wire bond is attached to the electronic component, and the other end is attached to the metal particle layer, so that the electronic component is electrically connected to the pad.

[0027] The semiconductor packaging apparatus and manufacturing method disclosed herein are designed to include: a circuit layer with pads on its surface and a metal particle layer on the surface of the pads; and an electronic component disposed on the circuit layer, with its active side electrically connected to the pads via wire bonding, one end of which is bonded to the metal particle layer. By bonding one end of the wire to the metal particle layer, the bonding temperature when the wire is electrically connected to the pad is reduced, thereby mitigating the problem of pad sinking caused by the bonding temperature softening the dielectric material of the circuit layer when the wire is directly bonded to the pad. Attached Figure Description

[0028] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0029] Figure 1AThis is a schematic diagram of a semiconductor packaging apparatus according to an embodiment of the present disclosure;

[0030] Figure 1B It is based on Figure 1A A schematic diagram of the partial structure of the area indicated by the dashed line.

[0031] Figure 1C It is based on Figure 1A The dashed line in the middle corresponds to a magnified view of the bonding interface between the wire bond and the pad.

[0032] Figure 1D It is based on Figure 1A A partial structural diagram of the pads and metal particle layer in the embodiment;

[0033] Figure 1E This is a structural diagram of the metal particle layer under an electron microscope in an actual application according to the embodiments of this disclosure;

[0034] Figure 2A-2L This is a cross-sectional view of a semiconductor packaging device manufactured at various stages according to an embodiment of the present disclosure;

[0035] Figures 3A-3C This is a cross-sectional view of a semiconductor packaging device manufactured at various stages according to yet another embodiment of the present disclosure.

[0036] Symbol explanation:

[0037] 11-Circuit layer; 12-Electronic component; 13-Wire bonding; 14-Pad; 15-Metal particle layer; 151-Metal particle; 152-Gap; 21-First carrier board; 22-Second carrier board; 23-Separation layer; 24-First dielectric layer; 25-Second dielectric layer; 251-Through hole; 26-Photoresist. Detailed Implementation

[0038] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0039] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0040] It should also be noted that the longitudinal section corresponding to the embodiments of this disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0041] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0042] refer to Figure 1A and Figure 1B , Figure 1A This is a longitudinal cross-sectional structural schematic diagram of one embodiment of the semiconductor packaging apparatus according to the present disclosure. Figure 1B yes Figure 1A A magnified schematic diagram of the structure of the area within the dashed line.

[0043] like Figure 1A As shown, the semiconductor packaging device 100A may include a circuit layer 11 and an electronic component 12. Specifically, the circuit layer 11 has pads 14 on its surface, and the electronic component 12 is disposed on the circuit layer 11. The active surface of the electronic component 12 is electrically connected to the pads 14 via wire bonding 13. For further demonstration... Figure 1A The structure of the dashed section is still referenced. Figure 1B ,like Figure 1B As shown, a metal particle layer 15 is provided on the surface of the pad 14, and one end of the wire bonding 13 is bonded to the metal particle layer 15.

[0044] The circuit layer 11 can be a redistribution layer (RDL) composed of conductive traces and dielectric material. It should be noted that the redistribution layer can be formed using currently known or future redistribution layer formation technologies, and this disclosure does not specifically limit it. For example, redistribution layers can be formed using methods including but not limited to photolithography, electroplating, and electroless plating. Here, the dielectric material may include organic and / or inorganic materials. Organic materials may include, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (Pre-prep material, also known as semi-cured resin or semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while inorganic materials may include, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may include, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., while the metal layer may include, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0045] This disclosure does not specifically limit the type of electronic component 12. Electronic component 12 may include, for example, a die, an ASIC (Application Specific Integrated Circuit) chip, a power management integrated circuit (PMIC) chip, or an HBM (High Bandwidth Memory) chip.

[0046] The above embodiment reduces the bonding temperature when the wire 13 is electrically connected to the pad 14 by bonding one end of the wire 13 on the metal particle layer 15, thereby improving the problem of pad 14 sinking caused by the bonding temperature softening the dielectric material of the circuit layer 11 when the wire 13 is directly bonded to the pad 14.

[0047] Continue to refer to Figure 1C and 1D , Figure 1C It is based on Figure 1A The dashed line in the middle is a magnified view of the bonding interface between wire bond 13 and pad 14. Figure 1D It is based on Figure 1AA partial structural diagram of the pad 14 and the metal particle layer 15 in the embodiment is shown below. Figure 1C and 1D As shown, the metal particle layer 15 may include a plurality of metal particles 151.

[0048] In some alternative implementations, a plurality of metal particles 151 are arranged in a flat pattern.

[0049] In some alternative implementations, a plurality of metal particles 151 are arranged in a particle matrix.

[0050] In some alternative implementations, such as Figure 1C As shown, there are gaps 152 between adjacent metal particles 151 in the metal particle layer 15.

[0051] One end of the wire 13 can be bonded into the gap 152 to increase the bonding area between one end of the wire 13 and the metal particle layer 15, thereby increasing the bonding strength.

[0052] In some alternative embodiments, the material of the metal particle layer 15 includes copper, silver, or gold.

[0053] In some alternative embodiments, the interface roughness of the metal particle layer 15 includes 10 nanometers to 100 nanometers.

[0054] In some alternative implementations, the temperature at which one end of the wire bonding 13 is bonded to the metal particle layer 15 is less than 150 degrees Celsius.

[0055] In some alternative embodiments, the tensile strength of one end of the wire 13 bonded to the metal particle layer 15 is greater than 5 grams.

[0056] In some alternative embodiments, the thickness of the metal particle layer 15 includes 50 nanometers to 800 nanometers.

[0057] Continue to refer to Figure 1E , Figure 1E This is a structural diagram of the metal particle layer 15 under an electron microscope in an actual application according to an embodiment of this disclosure. For example... Figure 1E As shown, in some alternative embodiments, the diameter of the metal particles 151 in the metal particle layer 15 includes 25 nanometers to 200 nanometers.

[0058] The following is for reference. Figures 2A to 2L , Figures 2A to 2L This is a longitudinal cross-sectional structural schematic diagram of semiconductor packaging devices 200A, 200B, 200C, 200D, 200E, 200F, 200G, 200H, 200I, 200J, 200K and 200L in the manufacturing stage according to embodiments of the present disclosure.

[0059] refer to Figure 2AA first carrier board 21 is provided, a separation layer 23 is disposed on the first carrier board 21, and a first dielectric layer 24 is disposed on the separation layer 23.

[0060] Here, the separation layer 23 may include a release agent material, and the separation layer 23 can be used to prevent the first carrier 21 from sticking to the semiconductor packaging device when the first carrier 21 is processed in subsequent processes.

[0061] refer to Figure 2B The surface of the first dielectric layer 24 is etched to form a rough interface on the surface of the first dielectric layer 24.

[0062] refer to Figure 2C A metal particle layer 15 is disposed on the first dielectric layer 24.

[0063] Here, a metal particle layer 15 can be formed by sputtering metal particles onto the surface of the first dielectric layer 24.

[0064] The thickness of the metal particle layer 15 ranges from 50 nanometers to 800 nanometers.

[0065] refer to Figure 2D A second dielectric layer 25 is provided on the metal particle layer 15, and a through hole 251 is formed in the second dielectric layer 25 so that a part of the surface of the metal particle layer 15 is exposed through the through hole 251.

[0066] refer to Figure 2E Pads 14 are provided on the metal particle layer 15 through through-hole 251.

[0067] The pads 14 on the metal particle layer 15 can be provided using techniques such as electroplating, electroless plating, or similar techniques.

[0068] refer to Figure 2F Dielectric material and / or conductive traces are applied to pad 14 to form circuit layer 11.

[0069] refer to Figure 2G A second carrier board 22 is placed on the circuit layer 11 and flipped.

[0070] refer to Figure 2H Remove the first carrier plate 21 and the separation layer 23.

[0071] refer to Figure 2I Remove the first dielectric layer 24.

[0072] refer to Figure 2J Corresponding to pad 14, a protective layer 26 is provided on the metal particle layer 15.

[0073] refer to Figure 2KRemove the portion of the metal particle layer 15 that is not covered by the protective layer 26.

[0074] Here, part of the metal particle layer 15 can be removed by etching, and the protective layer 26 can block part of the metal particle layer 15 during the etching process.

[0075] refer to Figure 2L Remove protective layer 26.

[0076] The following is for reference. Figures 3A to 3C , Figures 3A to 3C This is a longitudinal cross-sectional structural diagram of semiconductor packaging devices 300A, 300B and 300C during the manufacturing stage according to embodiments of the present disclosure.

[0077] refer to Figure 3A A circuit layer 11 is provided, and pads 14 are provided on the surface of the circuit layer 11.

[0078] refer to Figure 3B A metal particle layer 15 is provided on the surface of pad 14.

[0079] Here, a rough structure can be formed on the surface of the pad 14 by etching, and metal particles can be sputtered onto the surface of the pad 14 to form a metal particle layer 15.

[0080] This disclosure does not specify the etching method; dry etching or wet etching can be used to etch the surface of pad 14.

[0081] refer to Figure 3C One end of the wire bonding 13 is bonded to the metal particle layer 15.

[0082] exist Figure 3C Based on, combined Figure 1A As shown, in some alternative embodiments, an electronic component 12 is provided and disposed on the circuit layer 11.

[0083] The other end of the wire bond 13 is bonded to the active side of the electronic component 12 so that the electronic component 12 is electrically connected to the pad 14.

[0084] The method for manufacturing semiconductor structures disclosed herein can achieve similar technical effects to the aforementioned semiconductor structures, and will not be described in detail here.

[0085] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent components can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor packaging device, comprising: The circuit layer has pads on its surface, and a metal particle layer is formed on the surface of the pads. The metal particle layer consists of a plurality of flat metal particles and is formed by sputtering. An electronic component is disposed on the circuit layer, with its active side electrically connected to the pad via wire bonding, and one end of the wire bonding is bonded to the metal particle layer. The metal particle layer comprises a plurality of metal particles arranged in a particle matrix; There are gaps between adjacent metal particles in the metal particle layer, and one end of the wire bonding is bonded to the gap. The material of the metal particle layer includes: copper, silver, or gold; The interface roughness of the metal particle layer ranges from 10 nanometers to 100 nanometers; The temperature at which one end of the wire bonded to the metal particle layer is less than 150 degrees Celsius. The tensile strength of the wire bonded to the metal particle layer is greater than 5 grams. The thickness of the metal particle layer ranges from 50 nanometers to 800 nanometers; The diameter of the metal particles in the metal particle layer ranges from 25 nanometers to 200 nanometers.

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