CMOS-mems integrated pressure sensor and its manufacturing process

Abstract

The application provides a CMOS-MEMS integrated pressure sensor and a preparation process thereof. The pressure sensor comprises a bonded MEMS wafer and a CMOS wafer; a bonding sealing area and a PAD vertical interconnection structure in the bonding sealing area are arranged between the MEMS wafer and the CMOS wafer; the bonding sealing structure is formed by eutectic bonding of a metallization layer and a metal solder ball formed in corresponding bonding areas of the two wafers, and the bonding sealing structure surrounds a sensitive element to form a sealed cavity; the PAD vertical interconnection structure comprises conductive bumps respectively formed on the two wafers, the two conductive bumps are aligned with each other and bonded, and electrical interconnection between the MEMS wafer and the CMOS wafer is realized. The electrical interconnection of the pressure sensor realizes monolithic integration, not only improves the problems of increased signal transmission loss, reduced detection precision caused by additional parasitic resistance, capacitance and inductance introduced by wire bonding, and external noise interference, but also improves the service life and reliability, and reduces the size of the chip.

Description

Technical Field

[0001] This invention belongs to the field of MEMS (Micro-Electro-Mechanical Systems) sensor technology, specifically relating to a CMOS-MEMS integrated pressure sensor and its fabrication process. Background Technology

[0002] MEMS pressure sensors have been widely used in consumer electronics, automotive electronics, medical and health, industrial control and other fields due to their advantages such as small size, light weight, low cost and ease of mass production. Traditional MEMS pressure sensors usually adopt a design that separates the MEMS sensing structure and signal processing circuit, that is, the MEMS chip and the CMOS signal processing chip are electrically connected by wire bonding and then packaged together.

[0003] This discrete structure has several drawbacks: First, wire bonding introduces additional parasitic resistance, capacitance, and inductance, leading to increased signal transmission loss in the sensor. This is especially true when processing weak electrical signals output from MEMS sensitive structures, making them susceptible to external noise interference and reducing detection accuracy. Second, packaging two independent chips requires more space, which is not conducive to the miniaturization design of the sensor and increases the complexity of the packaging process and manufacturing costs. In addition, the sensitive structure of traditional piezoresistive pressure sensors is exposed to the pressure environment under test, with only a passivation layer for protection, making it susceptible to external environmental influences that reduce its service life and reliability.

[0004] To address the aforementioned issues, existing technologies have developed monolithic integration solutions that integrate MEMS structures and CMOS circuits onto the same wafer. However, this approach suffers from poor compatibility between MEMS manufacturing processes and standard CMOS processes. MEMS structure fabrication often requires specialized processes such as deep etching and high-temperature annealing, which can damage the fabricated CMOS circuits, leading to performance degradation or even device failure. Therefore, achieving efficient integration of MEMS sensitive structures and CMOS circuits while ensuring the integrity of the CMOS circuit performance has become a pressing technical challenge in this field. Summary of the Invention

[0005] The present invention aims to solve the above-mentioned problems of the prior art and provide a pressure sensor based on CMOS-MEMS integration and its fabrication process.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: Firstly, it provides a CMOS-MEMS integrated pressure sensor, including: MEMS wafers and CMOS wafers bonded together; The MEMS wafer includes a piezoresistive sensing element, a MEMS metal trace electrically connected to the sensing element, and a first PAD metallization layer formed on the MEMS metal trace. The CMOS wafer includes multiple layers of metal wiring, interlayer dielectric layers, and a second PAD metallization layer; The MEMS wafer and the CMOS wafer are provided with an annular bonding and sealing structure and a PAD vertical interconnect structure located therein. The bonding sealing structure is formed by eutectic bonding of metallization layers formed on corresponding bonding regions of two wafers and metal solder balls located thereon. The bonding sealing structure surrounds the sensitive element to form a sealed cavity. The PAD vertical interconnect structure includes a first conductive bump and a second conductive bump formed on two wafers respectively. The first conductive bump and the second conductive bump are aligned with each other and bonded together to realize the electrical interconnection between the MEMS wafer and the CMOS wafer.

[0007] Secondly, it provides a fabrication process for CMOS-MEMS integrated pressure sensors, including: S1. Provide a MEMS wafer and a CMOS wafer; the MEMS wafer includes a piezoresistive sensing element, a MEMS metal trace electrically connected to the sensing element, and a first PAD metallization layer formed on the MEMS metal trace; the CMOS wafer includes multilayer metal wiring, an interlayer dielectric layer, and a second PAD metallization layer. S2. Metallization layers are formed in the bonding areas of the MEMS wafer and the CMOS wafer respectively, and metal solder balls are fabricated on the metal layers. A first conductive bump is formed on the first PAD metallization layer of the MEMS wafer, and a second conductive bump is formed on the second PAD metallization layer of the CMOS wafer. The positions of the first conductive bump and the second conductive bump correspond. S3. Align and bond the MEMS wafer and the CMOS wafer, so that the metallization layer and metal solder balls in the bonding area of ​​the two wafers form an annular sealing structure through eutectic bonding. The sealing structure surrounds the sensitive element to form a sealed cavity. At the same time, the first conductive bump and the second conductive bump are aligned with each other and bonded to form an electrical connection, forming a PAD vertical interconnect structure. S4. Identify the second PAD metal layer region on the CMOS wafer located outside the sealing structure, cut the corresponding part of the MEMS silicon strip, peel off and remove the cut MEMS silicon strip, expose part of the second PAD metal layer of the CMOS wafer, and obtain the package. S5. The package is diced to separate multiple independent integrated sensor chips.

[0008] Compared with the prior art, one or more of the above technical solutions can achieve at least one of the following beneficial effects: Existing technologies typically employ a separate design for the MEMS sensing structure and signal processing circuitry. This involves electrically connecting the MEMS chip and the CMOS signal processing chip via wire bonding and then packaging them together. This packaging structure suffers from several technical problems: large size, complex structure, high signal transmission loss, and insufficient detection accuracy. Furthermore, the sensitive element structure is often exposed to the pressure environment being measured, leading to poor product reliability. The CMOS-MEMS integrated pressure sensor provided by this invention achieves monolithic integration through electrical interconnection. This not only improves upon the problems introduced by existing technologies (wire bonding), such as increased signal transmission loss and susceptibility to external noise interference leading to reduced detection accuracy, but also seals the sensitive piezoresistive element within a vacuum environment, significantly improving lifespan and reliability, while simultaneously reducing chip size.

[0009] The fabrication process provided by this invention can effectively solve the problems of poor compatibility between MEMS manufacturing processes and CMOS standard processes. It can also achieve vacuum sealing through eutectic bonding without affecting the device. CMOS-MEMS electrical interconnection achieves monolithic integration and can seal sensitive piezoresistors in a vacuum environment, significantly improving service life, reducing the size of wafer-level bonded chips, and reducing the complexity of packaging processes and manufacturing costs.

[0010] The provided process uses precise Sn and Au ball implantation technology to ensure that the height difference between the balls is ≤3μm and the volume difference is <2%, so that the thickness of the Au-Sn phase and the Au-Sn compression amount after eutectic bonding fall within the 3σ window, which significantly improves the eutectic bonding quality. FEA simulations yielded a Sn ball diameter / sealing ring width ratio of 0.3~0.6, resulting in MEMS film stress <50 MPa after eutectic bonding. Optimization of the Au-Sn low-temperature eutectic bonding window reduced the MEMS-CMOS bonding temperature (conventional Ge-Al bonding processes are typically around 420℃), and improved the device vacuum level (from 1×10⁻⁶ in existing technologies). -5 Mbar decreased to 5×10 -6 (Level Mbar), vacuum level maintained for >5 years; low-temperature bonding reduces the impact of thermal stress during bonding process on MEMS chip performance, improving the thermal hysteresis performance of MEMS pressure sensor by more than 5%; The provided process optimizes the cutter wheel half-cutting parameters, limiting the cutting width to 60±2μm, the influence range to <5μm, and the depth accuracy to ±3μm, thereby improving the dicing yield to >99.9%, which is about 1% higher than the existing technology. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A flowchart illustrating the fabrication process of a CMOS-MEMS integrated pressure sensor.

[0013] Figures 2-9 A schematic diagram of the fabrication process for a CMOS-MEMS integrated pressure sensor.

[0014] Figure label: 1. Si substrate; 2. Metal interconnect; 3. Sensitive piezoresistive layer; 4. First metal film layer; 5. Metal solder ball; 6. First conductive bump; 7, 9. Metal traces of different layers; 8. Dielectric layer; 10. Second metal film layer; 11. Second conductive bump; 12. Metal solder ball; 13. Metal alloy layer; 14. Interconnect conductive layer metal. Detailed Implementation

[0015] To facilitate understanding of the present invention, the present invention will be described more fully and in detail below with reference to the accompanying drawings and preferred embodiments, but the scope of protection of the present invention is not limited to the following specific embodiments.

[0016] Unless otherwise defined, all technical terms used herein have the same meaning as commonly understood by those skilled in the art. The technical terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the scope of the invention.

[0017] Some embodiments of the present invention provide a CMOS-MEMS integrated pressure sensor, comprising: MEMS wafers and CMOS wafers bonded together; The MEMS wafer includes a piezoresistive sensing element, a MEMS metal trace electrically connected to the sensing element, and a first PAD metallization layer formed on the MEMS metal trace. The CMOS wafer includes multiple layers of metal wiring, interlayer dielectric layers, and a second PAD metallization layer; The MEMS wafer and the CMOS wafer are provided with an annular bonding and sealing structure and a PAD vertical interconnect structure located therein. The bonding sealing structure is formed by eutectic bonding of metallization layers formed on corresponding bonding regions of two wafers and metal solder balls located thereon. The bonding sealing structure surrounds the sensitive element to form a sealed cavity. The PAD vertical interconnect structure includes a first conductive bump and a second conductive bump formed on two wafers respectively. The first conductive bump and the second conductive bump are aligned with each other and bonded together to realize the electrical interconnection between the MEMS wafer and the CMOS wafer.

[0018] In some preferred embodiments, the metal solder ball is a Sn-based solder ball.

[0019] In some preferred embodiments, the first conductive bump and the second conductive bump are Au spheres.

[0020] In some preferred embodiments, the eutectic interface of the bonding sealing structure is an Au-Sn intermetallic compound layer.

[0021] In a preferred embodiment, the second PAD metallization layer of the CMOS wafer has an outgoing region located outside the bonding seal structure. The MEMS wafer is at least partially removed at a position corresponding to the outgoing region to expose the second PAD metallization layer in that region. The exposed second PAD metallization layer is used to realize the electrical connection between the pressure sensor and external circuitry.

[0022] Some embodiments of the present invention provide a fabrication process for a CMOS-MEMS integrated pressure sensor, including: S1. Provide a MEMS wafer and a CMOS wafer; the MEMS wafer includes a piezoresistive sensing element, a MEMS metal trace electrically connected to the sensing element, and a first PAD metallization layer formed on the MEMS metal trace; the CMOS wafer includes multilayer metal wiring, an interlayer dielectric layer, and a second PAD metallization layer. S2. Metallization layers are formed in the bonding areas of the MEMS wafer and the CMOS wafer respectively, and metal solder balls are fabricated on the metal layers. A first conductive bump is formed on the first PAD metallization layer of the MEMS wafer, and a second conductive bump is formed on the second PAD metallization layer of the CMOS wafer. The positions of the first conductive bump and the second conductive bump correspond. S3. Align and bond the MEMS wafer and the CMOS wafer, so that the metallization layer and metal solder balls in the bonding area of ​​the two wafers form an annular sealing structure through eutectic bonding. The sealing structure surrounds the sensitive element to form a sealed cavity. At the same time, the first conductive bump and the second conductive bump are aligned with each other and bonded to form an electrical connection, forming a PAD vertical interconnect structure. S4. Identify the second PAD metal layer region on the CMOS wafer located outside the sealing structure, cut the corresponding part of the MEMS silicon strip, peel off and remove the cut MEMS silicon strip, expose part of the second PAD metal layer of the CMOS wafer, and obtain the package. S5. The package is diced to separate multiple independent integrated sensor chips.

[0023] In some preferred embodiments, the metallization layer of the MEMS wafer bonding region is a Cr / Au stack structure; the Cr / Au stack structure includes a Cr layer disposed in the bonding region and an Au layer disposed on the Cr layer; the thickness of the Cr layer is 100~300Å, for example 100Å, 150Å, 200Å, 250Å, 300Å, etc.; the thickness of the Au layer is 3000~5000Å, for example 3000Å, 3200Å, 3500Å, 3800Å, 4000Å, 4200Å, 4500Å, 4800Å, 5000Å, etc.; the metallization layer of the MEMS wafer bonding region is formed using a lift-off process.

[0024] In some preferred embodiments, the metallization layer of the CMOS wafer bonding region is a Cr / Ni / Au stacked structure; the Cr / Ni / Au stacked structure includes a Cr layer disposed in the bonding region, a Ni layer disposed on the Cr layer, and an Au layer disposed on the Ni layer; the thickness of the Cr layer is 100~300 Å, for example 100 Å, 150 Å, 200 Å, 250 Å, 300 Å, etc.; the thickness of the Ni layer is 1~3 μm, for example 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, 3 μm, etc.; the thickness of the Au ...~300 Å, 100~300 Å, 100~300 Å, 100~300 Å, 100~300 Å, 100~300 Å, 100~300 Å, 100~300 Å, 100~300 Å, 100~300 Å, 100~300 Å, 100~300 Å, 100~300 Å, 100~30 The thickness of the layer is 500~1000Å, for example 500Å, 550Å, 600Å, 650Å, 700Å, 750Å, 800Å, 850Å, 900Å, 950Å, 1000Å, etc.; the metallization layer of the CMOS wafer bonding region is formed using a lift-off process.

[0025] In some preferred embodiments, the metal solder balls in the MEMS wafer bonding region are Sn balls; the diameter of the metal solder balls in the MEMS wafer bonding region is 30~80μm, for example, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, etc.; the ball spacing between adjacent metal solder balls is 60~200μm, for example, 60μm, 80μm, 100μm, 120μm, 140μm, 160μm, 180μm, 200μm, etc.; the height difference between the metal solder balls is ≤3μm; the volume difference between the metal solder balls is <2%.

[0026] In some preferred embodiments, the metal solder balls in the CMOS wafer bonding region are Sn balls; the diameter of the metal solder balls in the CMOS wafer bonding region is 40~70μm, for example, 40μm, 50μm, 60μm, 70μm, etc.; the ball spacing between adjacent metal solder balls is 80~150μm, for example, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, etc.; the height difference between the metal solder balls is ≤3μm; and the volume difference between the metal solder balls is <2%.

[0027] In some preferred embodiments, the metallization layer and metal solder balls of the MEMS wafer bonding region are bonded to the metallization layer and metal solder balls of the CMOS wafer bonding region to form a eutectic sealing connection structure, preferably an Au-Sn eutectic sealing connection structure.

[0028] In some preferred embodiments, the first conductive bump is an Au ball; the size of the first conductive bump is 30~80μm, for example 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, etc.; the height difference between the first conductive bumps is ≤3μm; the volume difference between the first conductive bumps is <2%; the Au ball is formed by a ball-planting process.

[0029] In some preferred embodiments, the second conductive bump is an Au ball; the size of the second conductive bump is 30~60μm, for example 30μm, 40μm, 50μm, 60μm, etc.; the distance between adjacent balls is >500μm between MEMS chip PADs; the height difference between the second conductive bumps is ≤3μm; the volume difference between the second conductive bumps is <2%; preferably, one conductive bump is provided in each PAD area; the Au ball is formed by a ball-planting process.

[0030] In some preferred embodiments, in step S3, the bonding temperature is 250~300℃; the bonding pressure is 5~15kN, for example 5kN, 6kN, 7kN, 8kN, 9kN, 10kN, 11kN, 12kN, 13kN, 14kN, 15kN, etc.; the bonding time is 10~20min, for example 10min, 12min, 15min, 18min, 20min, etc.; and the alignment accuracy of the bonding is <5μm.

[0031] In a preferred embodiment, in step S4, a blade wheel half-cutting process is used to cut the MEMS silicon strip, and the cut-off portion is removed to expose the CMOS PAD for testing and packaging wire bonding; preferably, the width of the cut is 60±2μm, the influence range is <5μm, and the depth accuracy is ±3μm; preferably, the thickness of the thinning is 150~300μm, exposing a second PAD metallization layer with a size of 60~100μm.

[0032] In some embodiments, step S1 includes: S11: Form alignment marks on the silicon substrate; S12: A varistor is formed on the silicon substrate by ion implantation; S13: High-concentration doping is performed on the contact area of ​​the varistor to form an ohmic contact area; S14: A dielectric layer is formed above the ohmic contact area, and contact holes exposing the ohmic contact area are etched in the dielectric layer; S15: Prepare metal interconnects on the dielectric layer. The metal interconnects form ohmic contacts with the varistor through the contact holes to constitute the MEMS metal traces. S16: After forming a passivation layer covering the metal interconnects and etching an interconnect window therein to expose a portion of the metal interconnects, the first PAD metallization layer is formed within the window. S17: Thin the back side of the silicon substrate and then etch the silicon substrate from the back side to form a back cavity and a pressure-sensitive film located below the varistor.

[0033] Example 1 The fabrication process flow diagram of the CMOS-MEMS integrated pressure sensor is as follows: Figure 1 As shown in the diagram, the preparation process is illustrated below. Figures 2-9 As shown, it includes: 1. First of all, as Figure 2 As shown, the wafer fabrication of a MEMS pressure sensor is completed using conventional MEMS processes (such as coating, photolithography, etching, and implantation). A typical process flow is as follows: 1) Fabrication of alignment marks: Alignment marks for subsequent layers are formed in Si substrate 1 by photolithography and etching processes, with a depth of 0.3 μm to 0.6 μm; 2) Fabrication of the sensing core—sensitive piezoresistive resistor: a sensitive piezoresistive resistor 3 is formed on a Si substrate 1 by photolithography and lightly doped ion implantation process; the width of the sensitive piezoresistive resistor 3 is 3μm to 8μm, and the sheet resistance of the sensitive piezoresistive resistor 3 is 200Ω / □ to 400Ω / □; 3) Fabrication of ohmic contact region: The contact region of the varistor 3 is heavily doped by photolithography and heavy doping ion implantation process to form an ohmic contact region, which can form an ohmic contact with the subsequent metal interconnects; the size of the ohmic contact region is larger than the size of the contact hole formed later, and the shape of the ohmic contact region can be square, with a sheet resistance of 10~20Ω / □. 4) Fabrication of contact holes: A silicon dioxide layer with a thickness of 0.3 μm to 0.5 μm is deposited above the ohmic contact area as a dielectric layer, and contact holes exposing the ohmic contact area are etched in the dielectric layer by photolithography and etching processes. The contact holes are square contact holes with a size of 2 μm to 4 μm. 5) Fabrication of metal interconnects: A composite metal layer consisting of a Ti layer and an Al layer is deposited sequentially on a dielectric layer. The thickness of the Ti layer is 100 Å to 300 Å, and the thickness of the Al layer is 0.5 μm to 1 μm. The Ti layer and the Al layer are then patterned using photolithography and etching processes to form metal interconnects 2. The metal interconnects 2 are electrically connected to the ohmic contact area through the contact holes to form the MEMS metal traces. 6) Fabrication of passivation layer and opening of pad window: A silicon nitride layer with a thickness of 0.3μm to 0.6μm is deposited on the metal interconnect 2 as a passivation layer, and a portion of the metal interconnect 2 is etched in the passivation layer by photolithography and etching process to expose the window of the metal interconnect 2 as a pad. The window is a square window with a size of 60μm to 80μm, and a PAD metallization layer is formed in the window. 7) Formation of back cavity and pressure-sensitive film: The back side of the wafer needs to be thinned first, for example from 725μm to 350~450μm, and then photolithography is used to etch a deep cavity with a large opening from the back side of the silicon wafer, while retaining a thin silicon film as a pressure-sensitive film. The opening size of the back cavity is 600μm to 1000μm, the etching depth is 300μm to 500μm, and the thickness of the pressure-sensitive film is 10μm to 30μm.

[0034] 2. Using a negative resist photolithography process, a negative resist thickness of 2~5μm is formed to create an inverted trapezoidal photoresist sidewall morphology with a sidewall angle of 60°~70°. Then, evaporation or deposition is performed to deposit the first metal film layer 4. The metal composition can be CrAu (i.e., Cr layer and Au layer are deposited sequentially), where the Cr layer thickness is 100~300Å and the Au layer thickness is 3000~5000Å. The wafer with the metal pattern is placed in a stripping and cleaning machine, where the negative resist is removed and cleaned using an organic solvent such as NMP at 70°C, ultimately achieving the patterning process of the first metal film layer 4 for bonding. 3. For example Figure 4As shown, using a ball-planting machine, metal solder balls 5, such as Sn balls, are implanted onto the first metal film layer 4 in the bonding ring region for bonding. The Sn balls have a diameter of 30~80μm, a ball spacing of 60~200μm, and a height difference between the metal solder balls ≤3μm; the volume difference between the metal solder balls is <2%. First conductive bumps 6, such as Au balls, for electrical connections are implanted into the PAD region. The Au balls have a size of 30~80μm, a height difference between the first conductive bumps ≤3μm, and a volume difference between the first conductive bumps is <2%. Only one ball is implanted on each PAD. 4. For example Figure 5 The diagram shows a CMOS wafer fabricated using conventional CMOS technology, comprising: forming a CMOS device layer on a silicon substrate, wherein the gate size of the transistors in the CMOS device layer is 90nm to 350nm; and forming a multilayer metal interconnect structure on the CMOS device layer, wherein the multilayer metal interconnect structure includes 3 to 5 metal layers 7 / 9 (e.g., W, Al, or Cu), with a SiO2 dielectric layer 8 used as an insulating dielectric between different metal layers, i.e., adjacent metal layers are electrically isolated through the SiO2 dielectric layer 8. Vias are provided between the CMOS device layer and the multilayer metal interconnect structure, as well as between the metal layers of the multilayer metal interconnect structure, to achieve interlayer electrical connection. The top metal layer of the multilayer metal interconnect structure is suitable for subsequent electrical connections, and a PAD metallization layer is formed on the top metal layer, corresponding to the PAD metallization layer on the MEMS wafer. 5. For example Figure 6 As shown, a negative resist photolithography process is used to form an inverted trapezoidal photoresist sidewall morphology with a negative resist thickness of 2-5 μm and a sidewall angle of 60°-70°. Then, evaporation is performed to deposit a second metal film layer 10. The metal composition can be CrNiAu (i.e., Cr layer, Ni layer, and Au layer are deposited sequentially), where the Cr layer thickness is 100-300 Å, the Ni layer thickness is 1-3 μm, and the Au layer thickness is 500-1000 Å. The wafer with the metal pattern is placed in a stripping and cleaning machine, where the negative resist is removed and cleaned using an organic solvent such as NMP at 70°C, ultimately achieving the patterning process for the bonding metal. 6. For example Figure 7 As shown, a ball-planting machine is used to implant metal solder balls 12, such as Sn balls, for bonding in the bonding ring area of ​​the CMOS wafer. The Sn balls have a diameter of 40~70μm, a ball spacing of 80~150μm, a height difference between balls ≤3μm, and a volume difference <2%.

[0035] Second conductive bumps 11, such as Au balls, for electrical connections are implanted on the PAD region (PAD metallization layer) of the CMOS wafer. The size of the Au balls is 30~60μm, the ball spacing is generally >500μm between MEMS chip PADs, the height difference between balls is ≤3μm, and the volume difference is <2%. Only one ball is implanted on each PAD. Through precise control of the Sn ball and Au ball implantation process, the thickness of the Au-Sn phase and the Au-Sn compression after eutectic bonding fall within the 3σ window at the same time, which significantly improves the quality of subsequent eutectic bonding. 7. For example Figure 8 As shown, a wafer bonding machine is used to perform eutectic bonding of CMOS and MEMS wafers. The alignment accuracy is controlled to be <5μm, the bonding temperature is 250~300℃, the bonding pressure is 5~15kN, and the duration is 10~20min. Finally, metal solder balls 5 and 12 are bonded to the first metal film layer 4 and the second metal film layer 10 in the bonding ring region to form a metal alloy layer 13, Au-Sn alloy. In the PAD region, the first conductive bump 6 and the second conductive bump 11 form an interconnect conductive layer metal 14, Au pillars, realizing the electrical connection between CMOS and MEMS. FEA simulation shows that the "Sn ball diameter / sealing ring width" ratio is 0.3~0.6, resulting in MEMS film stress <50MPa after eutectic bonding. Optimization of the Au-Sn low-temperature eutectic bonding window reduces the MEMS-CMOS bonding temperature (the conventional Ge-Al bonding process temperature is generally around 420℃), and improves the device vacuum level (from the general 1×10⁻⁶ of existing technologies). - 5 Mbar, reduced to 5×10 -6 (Level Mbar), vacuum level maintained for >5 years; low-temperature bonding reduces the impact of thermal stress during bonding process on MEMS chip performance, improving the thermal hysteresis performance of MEMS pressure sensor by more than 5%; 8. For example Figure 9 As shown, the metal layer of the PAD region on the CMOS wafer located outside the bonding and sealing structure is identified. A small portion of the MEMS silicon strip area above this region is processed using a dicing machine to create a half-depth groove, ensuring the cutting depth only penetrates the MEMS silicon strip without damaging the underlying CMOS wafer and PAD structure. The half-cut MEMS silicon strip is then peeled off from the bonding wafer surface, completely exposing the PAD metal layer area of ​​the underlying CMOS wafer. The exposed PAD metal layer can be directly used for subsequent testing and wire bonding. The half-cut silicon strip size is typically set to 150~300μm with a thickness of 300~500μm, and the wire bonding PAD size is 60~100μm. By limiting the dicing parameters, the cutting width is limited to 60±2μm, the influence range is <5μm, and the depth accuracy is ±3μm, improving the wafer yield to >99.9%, which is approximately 1% higher than existing technologies. 9. Use a dicing machine to cut the wafer-level packaged MEMS pressure sensor to finally form a CMOS-MEMS monolithic integrated pressure sensor chip, with a typical chip size of 1~3mm.

[0036] Example 2 The fabrication process flow diagram of the CMOS-MEMS integrated pressure sensor is as follows: Figure 1 As shown in the diagram, the preparation process is illustrated below. Figures 2-9 As shown, it includes: 1. Step 1 is the same as in Example 1.

[0037] 2. Using a negative resist photolithography process, a negative resist thickness of 3μm is formed to create an inverted trapezoidal photoresist sidewall morphology with a sidewall angle of 65°. Then, evaporation or deposition is performed to deposit the first metal film layer 4. The metal composition can be CrAu (i.e., Cr layer and Au layer are deposited sequentially), where the Cr layer is 200Å thick and the Au layer is 4000Å thick. The wafer with the metal pattern is placed in a stripping and cleaning machine, where the negative resist is removed and cleaned using an organic solvent such as NMP at 70°C, ultimately achieving the patterning process of the first metal film layer 4 for bonding. 3. Using a ball-planting machine, metal solder balls 5, such as Sn balls, are implanted onto the first metal film layer 4 in the bonding ring region for bonding. The Sn balls have a diameter of 50 μm and a ball spacing of 130 μm. The height difference between the metal solder balls is ≤3 μm, and the volume difference between the metal solder balls is <2%. First conductive bumps 6, such as Au balls, for electrical connections are implanted into the PAD region. The Au balls have a size of 50 μm, and the height difference between the first conductive bumps is ≤3 μm. The volume difference between the first conductive bumps is <2%, and only one ball is implanted on each PAD. 4. A CMOS wafer fabricated using conventional CMOS technology, comprising: forming a CMOS device layer on a silicon substrate, wherein the gate size of the transistors in the CMOS device layer is 220nm; and forming a multilayer metal interconnect structure on the CMOS device layer, wherein the multilayer metal interconnect structure comprises four metal layers 7 / 9 (e.g., W, Al, or Cu), with a SiO2 dielectric layer 8 used as an insulating dielectric between different metal layers, i.e., adjacent metal layers are electrically isolated through the SiO2 dielectric layer 8. Vias are provided between the CMOS device layer and the multilayer metal interconnect structure, and between the metal layers of the multilayer metal interconnect structure, to achieve interlayer electrical connection. The top metal layer of the multilayer metal interconnect structure is suitable for subsequent electrical connections, and a PAD metallization layer is formed on the top metal layer, corresponding to the PAD metallization layer on the MEMS wafer. 5. Using a negative resist photolithography process, a negative resist thickness of 4μm is formed to create an inverted trapezoidal photoresist sidewall morphology with a sidewall angle of 60°. Then, evaporation is performed to deposit a second metal film layer 10. The metal composition can be CrNiAu (i.e., Cr layer, Ni layer, and Au layer are deposited sequentially), where the Cr layer is 200Å thick, the Ni layer is 2μm thick, and the Au layer is 750Å thick. The wafer with the metal pattern is placed in a stripping and cleaning machine, where the negative resist is removed and cleaned using an organic solvent such as NMP at 70°C, ultimately achieving the patterning process for the bonding metal. 6. Using a ball-planting machine, implant metal solder balls 12, such as Sn balls, for bonding in the bonding ring area of ​​the CMOS wafer. The Sn balls have a diameter of 60μm, a ball spacing of 110μm, a height difference between balls ≤3μm, and a volume difference <2%.

[0038] Second conductive bumps 11, such as Au balls, for electrical connections are implanted on the PAD region (PAD metallization layer) of the CMOS wafer. The Au balls are 50 μm in size, the ball spacing is 800 μm between MEMS chip PADs, the height difference between balls is ≤3 μm, the volume difference is <2%, and only one ball is implanted on each PAD. Through precise control of the Sn ball and Au ball implantation process, the thickness of the Au-Sn phase and the Au-Sn compression after eutectic bonding fall within the 3σ window, which significantly improves the quality of subsequent eutectic bonding. 7. Using a wafer bonding machine, CMOS and MEMS wafers are eutectic bonded. Alignment accuracy is controlled to <5μm, bonding temperature is 280℃, bonding pressure is 10kN, and duration is 15min. Finally, metal solder balls 5 and 12 are bonded to the first metal film layer 4 and the second metal film layer 10 in the bonding ring region to form a metal alloy layer 13, Au-Sn alloy. In the PAD region, the first conductive bump 6 and the second conductive bump 11 form an interconnect conductive layer metal 14, Au pillars, realizing the electrical connection between CMOS and MEMS. FEA simulation shows a Sn ball diameter / sealing ring width ratio of 0.5, resulting in MEMS film stress <50MPa after eutectic bonding. Window optimization for Au-Sn low-temperature eutectic bonding reduces the MEMS-CMOS bonding temperature (conventional Ge-Al bonding temperatures are generally around 420℃), improving device vacuum (from the typical 1×10⁻⁶ of existing technologies). -5 Mbar, reduced to 5*10 -6 (Level Mbar), vacuum level maintained for >5 years; low-temperature bonding reduces the impact of thermal stress during bonding process on MEMS chip performance, improving the thermal hysteresis performance of MEMS pressure sensor by more than 5%; 8. Identify the PAD region metal layer on the CMOS wafer located outside the bonding and sealing structure. Use a dicing machine to perform a half-depth groove cut on the corresponding small portion of the MEMS silicon strip area above this region, ensuring the cutting depth only penetrates the MEMS silicon strip without damaging the underlying CMOS wafer and PAD structure. Remove the half-cut MEMS silicon strip from the bonding wafer surface, completely exposing the PAD metal layer area of ​​the underlying CMOS wafer. The exposed PAD metal layer can be directly used for subsequent testing and wire bonding. The half-cut silicon strip size is typically set to 200μm with a thickness of 4500μm, and the wire bonding PAD size is 80μm. By limiting the dicing parameters, the cutting width is limited to 60±2μm, the influence range is <5μm, and the depth accuracy is ±3μm, improving the wafer yield to >99.9%, approximately 1% higher than existing technologies. 9. Use a dicing machine to cut the wafer-level packaged MEMS pressure sensor to finally form a CMOS-MEMS monolithic integrated pressure sensor chip, with a typical chip size of 1~3mm.

[0039] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A CMOS-MEMS integrated pressure sensor, characterized in that, include: MEMS wafers and CMOS wafers bonded together; The MEMS wafer includes a piezoresistive sensing element, a MEMS metal trace electrically connected to the sensing element, and a first PAD metallization layer formed on the MEMS metal trace. The CMOS wafer includes multiple layers of metal wiring, interlayer dielectric layers, and a second PAD metallization layer; The MEMS wafer and the CMOS wafer are provided with an annular bonding and sealing structure and a PAD vertical interconnect structure located therein. The bonding sealing structure is formed by eutectic bonding of metallization layers formed on corresponding bonding regions of two wafers and metal solder balls located thereon. The bonding sealing structure surrounds the sensitive element to form a sealed cavity. The PAD vertical interconnect structure includes a first conductive bump and a second conductive bump formed on two wafers respectively. The first conductive bump and the second conductive bump are aligned with each other and bonded together to realize the electrical interconnection between the MEMS wafer and the CMOS wafer.

2. The CMOS-MEMS integrated pressure sensor as described in claim 1, characterized in that, The metal solder balls are Sn-based solder balls; the first conductive bump and the second conductive bump are Au balls; the eutectic interface of the bonding and sealing structure is an Au-Sn intermetallic compound layer.

3. The CMOS-MEMS integrated pressure sensor as described in claim 1, characterized in that, The second PAD metallization layer of the CMOS wafer has an outgoing region located outside the bonding and sealing structure. The MEMS wafer is partially removed at the position corresponding to the outgoing region to expose the second PAD metallization layer in that region. The exposed second PAD metallization layer is used to realize the electrical connection between the pressure sensor and the external circuit.

4. The fabrication process of a CMOS-MEMS integrated pressure sensor, characterized in that, include: S1. Provide a MEMS wafer and a CMOS wafer; the MEMS wafer includes a piezoresistive sensing element, a MEMS metal trace electrically connected to the sensing element, and a first PAD metallization layer formed on the MEMS metal trace; the CMOS wafer includes multilayer metal wiring, an interlayer dielectric layer, and a second PAD metallization layer. S2. Metallization layers are formed in the bonding areas of the MEMS wafer and the CMOS wafer respectively, and metal solder balls are fabricated on the metal layers. A first conductive bump is formed on the first PAD metallization layer of the MEMS wafer, and a second conductive bump is formed on the second PAD metallization layer of the CMOS wafer. The positions of the first conductive bump and the second conductive bump correspond. S3. Align and bond the MEMS wafer and the CMOS wafer, so that the metallization layer and metal solder balls in the bonding area of ​​the two wafers form an annular sealing structure through eutectic bonding. The sealing structure surrounds the sensitive element to form a sealed cavity. At the same time, the first conductive bump and the second conductive bump are aligned with each other and bonded to form an electrical connection, forming a PAD vertical interconnect structure. S4. Identify the second PAD metal layer region on the CMOS wafer located outside the sealing structure, cut the corresponding part of the MEMS silicon strip, peel off and remove the cut MEMS silicon strip, expose part of the second PAD metal layer of the CMOS wafer, and obtain the package. S5. The package is diced to separate multiple independent integrated sensor chips.

5. The fabrication process of the CMOS-MEMS integrated pressure sensor as described in claim 4, characterized in that, The metallization layer of the MEMS wafer bonding region is a Cr / Au stacked structure; the Cr / Au stacked structure includes a Cr layer disposed in the bonding region and an Au layer disposed on the Cr layer; the thickness of the Cr layer is 100~300 Å, and the thickness of the Au layer is 3000~5000 Å; the metallization layer of the MEMS wafer bonding region is formed using a lift-off process. The metallization layer of the CMOS wafer bonding region is a Cr / Ni / Au stacked structure; the Cr / Ni / Au stacked structure includes a Cr layer disposed in the bonding region, a Ni layer disposed on the Cr layer, and an Au layer disposed on the Ni layer; the thickness of the Cr layer is 100~300 Å, the thickness of the Ni layer is 1~3 μm, and the thickness of the Au layer is 500~1000 Å; the metallization layer of the CMOS wafer bonding region is formed using a lift-off process.

6. The fabrication process of the CMOS-MEMS integrated pressure sensor as described in claim 4, characterized in that, The metal solder balls in the MEMS wafer bonding region are Sn balls; the diameter of the metal solder balls in the MEMS wafer bonding region is 30~80μm; the ball spacing between adjacent metal solder balls is 60~200μm; the height difference between the metal solder balls is ≤3μm; and the volume difference between the metal solder balls is <2%. The metal solder balls in the CMOS wafer bonding region are Sn balls; the diameter of the metal solder balls in the CMOS wafer bonding region is 40~70μm; the ball spacing between adjacent metal solder balls is 80~150μm; the height difference between the metal solder balls is ≤3μm; and the volume difference between the metal solder balls is <2%.

7. The fabrication process of the CMOS-MEMS integrated pressure sensor as described in claim 4, characterized in that, The first conductive bump is an Au ball; the size of the first conductive bump is 30~80μm; the height difference between the first conductive bumps is ≤3μm; the volume difference between the first conductive bumps is <2%; the Au ball is formed by a ball-planting process; The second conductive bump is an Au ball; the size of the second conductive bump is 30~60μm; the height difference between the second conductive bumps is ≤3μm; the volume difference between the second conductive bumps is <2%; at least one conductive bump is provided in each PAD area; The Au spheres are formed through a sphere-planting process.

8. The fabrication process of the CMOS-MEMS integrated pressure sensor as described in claim 4, characterized in that, In step S3, the bonding temperature is 250~300℃; the bonding pressure is 5~15kN; the bonding time is 10~20min; and the alignment accuracy during bonding is <5μm.

9. The fabrication process of the CMOS-MEMS integrated pressure sensor as described in claim 4, characterized in that, In step S4, a cutting wheel half-cutting process is used to partially cut the MEMS silicon strip and remove the cut-off part to expose the CMOS PAD; the cutting width is 60±2μm, the influence range is <5μm, and the depth accuracy is ±3μm; the thinning thickness is 150~300μm, exposing a second PAD metallization layer with a size of 60~100μm.

10. The fabrication process of the CMOS-MEMS integrated pressure sensor as described in claim 4, characterized in that, Step S1 includes: S11: Form alignment marks on the silicon substrate; S12: A varistor is formed on the silicon substrate by ion implantation; S13: High-concentration doping is performed on the contact area of ​​the varistor to form an ohmic contact area; S14: A dielectric layer is formed above the ohmic contact area, and contact holes exposing the ohmic contact area are etched in the dielectric layer; S15: Prepare metal interconnects on the dielectric layer. The metal interconnects form ohmic contacts with the varistor through the contact holes to constitute the MEMS metal traces. S16: After forming a passivation layer covering the metal interconnects and etching an interconnect window therein to expose a portion of the metal interconnects, the first PAD metallization layer is formed within the window. S17: Thin the back side of the silicon substrate and then etch the silicon substrate from the back side to form a back cavity and a pressure-sensitive film located below the varistor.

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