Data processing method and device, computer device, and storage medium

Abstract

The present disclosure provides a data processing method and device, computer equipment and a storage medium, wherein the method comprises: determining a level of a first data block corresponding to a first processing block from a plurality of preset levels based on information of at least one processing block of a data processing operation, wherein the at least one processing block comprises the first processing block, and the information of the processing block comprises information of a data block corresponding to the processing block; determining a data caching mode of the first data block based on the level of the first data block. The present disclosure determines the corresponding data caching mode according to the level area of different data blocks, thereby being able to cache different data blocks, and being able to realize data caching according to the actual data access situation, improve the data reading efficiency, and improve the data processing efficiency.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of data processing, and in particular, to a data processing method and device, computer equipment and a storage medium. BACKGROUND

[0002] With the development of deep learning and artificial intelligence technology, the application field of deep learning technology is also becoming more and more extensive. Among them, the neural network has obvious effect in the application of image processing, video super-resolution, etc., and is widely used. The commonly used operator in neural network is convolution operation, which is a computationally intensive operator. The graphics processing unit (GPU) has natural advantages for computationally intensive operators. For large batch, large feature data scale and large input / output channel convolution operation, GPU can get very high performance.

[0003] However, with the development of neural networks, the types and operators of neural networks become more and more, such as small input / output channel neural networks, or the emergence of down-sampling layers, etc. which leads to small feature data scale of neural networks, etc. For these operators, the data processing efficiency of GPU is low. SUMMARY

[0004] The embodiments of the present disclosure at least provide a data processing scheme.

[0005] In a first aspect, the embodiments of the present disclosure provide a data processing method, comprising: determining a level of a first data block corresponding to a first processing block from a plurality of preset levels based on information of at least one processing block of a data processing operation, wherein the at least one processing block includes the first processing block, and the information of the processing block includes information of a data block corresponding to the processing block; determining a data caching mode of the first data block based on the level of the first data block.

[0006] In this way, based on the information of at least one processing block of a data processing operation, the level of a first data block corresponding to a first processing block included in the first processing block is determined from a plurality of preset levels, and then the data caching mode of the first data block is determined based on the level of the first data block, so that different data blocks are cached, and the data caching can be realized according to the actual data access situation, which is beneficial to improving the data reading efficiency and the data processing efficiency.

[0007] In a possible implementation, the higher the level of the first data block is, the more the number of caches used for caching the first data block in the corresponding data caching manner is; and / or, in a first data caching manner and a second data caching manner different from the first data caching manner, the first data block is cached in at least partially different cache layers; and / or, in a third data caching manner, the first data block is cached to a first specific cache layer, and in a fourth data caching manner different from the third data caching manner, the first data block is not cached to the first specific cache layer; and / or, in a fifth data caching manner and a sixth data caching manner different from the fifth data caching manner, the first data block has different replacement priorities in a same second specific cache layer.

[0008] In this way, by setting different levels and determining different data caching manners for different levels, the classified caching of different data can be implemented, and the utilization rate of cached data can be improved.

[0009] In a possible implementation, the determining of the level of the first data block corresponding to the first processing block from the plurality of preset levels comprises: determining sharing degree information of the first data block based on the information of the at least one processing block; and determining the level of the first data block based on the sharing degree information of the first data block, and a correspondence between the sharing degree information and the plurality of preset levels.

[0010] In this way, the level of the first data block can be determined based on the sharing degree information, and then the data with a high sharing degree can be cached to the cache that can be accessed by threads in all SMs, and the data with a low sharing degree can be cached to the cache that can be accessed by only a small number of SMs, so that the access rate of the data stored in the cache is improved, and the reading efficiency of the data in the data processing process is improved.

[0011] In a possible implementation, the sharing degree information of the first data block comprises: an access frequency of the first data block, and the access frequency of the first data block comprises a proportion of a number of processing blocks that need to access the first data block in a total number of the at least one processing block.

[0012] In a possible implementation, the information of the at least one processing block comprises: a starting storage address of all data blocks corresponding to the at least one processing block, and an offset of a storage address of a data block of each processing block relative to the starting storage address.

[0013] In this way, the data corresponding to the first processing block can be accurately determined based on the starting storage address and the offset.

[0014] In a possible implementation, the data processing method is executed by a central processing unit (CPU), and the method further includes: sending task processing instructions corresponding to the first processing block to a graphics processing unit (GPU), where the task processing instructions indicate a data caching manner of the first data block.

[0015] In a possible implementation, the data processing method is executed by a graphics processing unit (GPU), and the method further includes: in a process of executing a data processing task corresponding to the first processing block, caching the first data block according to the data caching manner corresponding to the first data block.

[0016] In a possible implementation, the method further includes: dividing a data processing task corresponding to the first processing block into a plurality of subtasks, each of which is executed by a thread; and determining a storage location of data corresponding to each thread based on a data dependency relationship between the plurality of subtasks, where the storage location of the data corresponding to the first thread includes a register of at least one second thread that has a data dependency relationship with the first thread.

[0017] In this way, each thread stores intermediate data or part of input data calculated by the thread into a corresponding register, and other threads that have a data dependency relationship can directly obtain the data by accessing the register, thereby accelerating the data access speed and improving the efficiency of the data processing task.

[0018] In a possible implementation, the data corresponding to the first thread includes part of a first data block corresponding to the first processing block and / or second intermediate data of the second thread, where the second intermediate data is used to obtain one value in result data of the first thread.

[0019] In a possible implementation, the first processing block is executed by a plurality of threads, and the method further includes: reading part of data in a sub data block corresponding to a third thread from the plurality of threads, processing the data read by the third thread to obtain at least one second intermediate data, and storing the at least one second intermediate data into a register of the third thread, where the at least one second intermediate data is used to determine one value in result data of the third thread.

[0020] In a possible implementation, the first processing block is executed by a plurality of threads, and the method further includes: for a first thread from the plurality of threads, reading first intermediate data obtained by at least one second thread from a register of the at least one second thread; and based on the read first intermediate data, obtaining one value in result data of the first thread.

[0021] In a possible implementation, the method further includes: determining a target chunking strategy of the data processing operation from a plurality of preset chunking strategies based on configuration information of the data processing operation; and performing chunking processing on the task processing operation based on the target chunking strategy to obtain information of each processing block in the at least one processing block.

[0022] In this way, the data processing operation can be more reasonably divided into a plurality of processing blocks, so as to improve the efficiency of the data processing operation.

[0023] In a possible implementation, the at least one processing block is obtained by performing chunking processing on at least one of result data, input data, and parameter data of the data processing operation.

[0024] In a second aspect, the embodiments of the present disclosure further provide another data processing method, which is applied to a graphics processing unit (GPU) and includes: reading a first data block corresponding to a first processing block, where the first processing block is included in at least one processing block of a data processing operation; caching the first data block in a target data caching mode, where the target data caching mode is determined based on a level of the first data block; and performing data processing corresponding to the first processing block on the cached first data block to obtain a processing result of the first data block.

[0025] In a possible implementation, the performing data processing corresponding to the first processing block on the cached first data block to obtain the processing result of the first data block includes: for a first thread in the plurality of threads, reading first intermediate data obtained by at least one second thread from a register of the at least one second thread; and based on the read first intermediate data, obtaining one value in result data of the first thread.

[0026] In a possible implementation, the performing data processing corresponding to the first processing block on the cached first data block to obtain the processing result of the first data block includes: reading a part of data in a sub-data block corresponding to a third thread in the plurality of threads, processing the data read by the third thread to obtain at least one second intermediate data, and storing the at least one second intermediate data into a register of the third thread, where the at least one second intermediate data is used to determine one value in result data of the third thread.

[0027] In a possible implementation, the level of the first data block is obtained based on information of the at least one processing block of the data processing operation, where the information of the processing block includes information of a data block corresponding to the processing block.

[0028] In a possible implementation, the higher the level of the first data block is, the more the number of caches used for caching the first data block in the corresponding data caching manner is; and / or, in a first data caching manner and a second data caching manner different from the first data caching manner, the first data block is cached in at least partially different cache layers; and / or, in a third data caching manner, the first data block is cached to a first specific cache layer, and in a fourth data caching manner different from the third data caching manner, the first data block is not cached to the first specific cache layer; and / or, in a fifth data caching manner and a sixth data caching manner different from the fifth data caching manner, the first data block has different replacement priorities in a same second specific cache layer.

[0029] In a possible implementation, the information of the data block corresponding to the processing block includes: a starting storage address of all data blocks corresponding to the at least one processing block, and an offset of the storage address of the data block of each processing block relative to the starting storage address.

[0030] In a possible implementation, the level corresponding to the first data block is determined based on sharing degree information of the first data block, and determined based on the sharing degree information of the first data block and a correspondence relationship between a plurality of preset levels.

[0031] In a possible implementation, the sharing degree information of the first data block includes: an access frequency of the first data block, the access frequency of the first data block including a proportion of a number of processing blocks that need to access the first data block in a total number of the at least one processing block.

[0032] In a third aspect, the embodiments of the present disclosure further provide a data processing apparatus, including: a first determining module configured to determine a level of a first data block corresponding to a first processing block from a plurality of preset levels based on information of at least one processing block of a data processing operation, wherein the at least one processing block includes the first processing block, and the information of the processing block includes information of a data block corresponding to the processing block; and a second determining module configured to determine a data caching manner of the first data block based on the level of the first data block.

[0033] In a possible implementation, the higher the level of the first data block is, the more the number of caches used to cache the first data block in the corresponding data caching manner is; and / or, in a first data caching manner and a second data caching manner different from the first data caching manner, the first data block is cached in at least partially different cache layers; and / or, in a third data caching manner, the first data block is cached to a first specific cache layer, and in a fourth data caching manner different from the third data caching manner, the first data block is not cached to the first specific cache layer; and / or, in a fifth data caching manner and a sixth data caching manner different from the fifth data caching manner, the first data block has different replacement priorities in a same second specific cache layer.

[0034] In a possible implementation, the first determining module, when determining the level of the first data block corresponding to the first processing block from a plurality of preset levels, is configured to: determine sharing degree information of the first data block based on the information of the at least one processing block; and determine the level of the first data block based on the sharing degree information of the first data block, and a correspondence between the sharing degree information and the plurality of preset levels.

[0035] In a possible implementation, the sharing degree information of the first data block includes: an access frequency of the first data block, the access frequency of the first data block including a proportion of a number of processing blocks that need to access the first data block in a total number of the at least one processing block.

[0036] In a possible implementation, the information of the at least one processing block includes: a starting storage address of all data blocks corresponding to the at least one processing block, and an offset of a storage address of a data block of each processing block relative to the starting storage address.

[0037] In a possible implementation, when the data processing apparatus is deployed in a central processing unit (CPU), the data processing apparatus further includes a sending module configured to send a task processing instruction corresponding to the first processing block to a graphics processing unit (GPU), the task processing instruction indicating a data caching manner of the first data block.

[0038] In a possible implementation, when the data processing apparatus is deployed in a graphics processing unit (GPU), the data processing apparatus further includes a first processing module configured to cache reading of the first data block according to a data caching manner corresponding to the first data block in a process of executing a data processing task corresponding to the first processing block.

[0039] In a possible implementation, the second processing module is further configured to: divide the data processing corresponding to the first processing block into a plurality of sub-tasks, each of which is executed by a thread; and determine a storage location of data corresponding to each thread based on a data dependency relationship between the plurality of sub-tasks; and wherein the storage location of the data corresponding to the first thread includes a register of at least one second thread having a data dependency relationship with the first thread.

[0040] In a possible implementation, the data corresponding to the first thread includes: a part of a first data block corresponding to the first processing block; and / or second intermediate data of the second thread, the second intermediate data being used to obtain one value in result data of the first thread.

[0041] In a possible implementation, the first processing block is executed by a plurality of threads, and the data processing apparatus further includes a third processing module configured to: read a part of data in a sub-data block corresponding to a third thread from the plurality of threads, process the data read by the third thread to obtain at least one second intermediate data, and store the at least one second intermediate data in a register of the third thread, wherein the at least one second intermediate data is used to determine one value in result data of the third thread.

[0042] In a possible implementation, the first processing block is executed by a plurality of threads, and the data processing apparatus further includes a fourth processing module configured to: for a first thread from the plurality of threads, read first intermediate data obtained by at least one second thread from a register of the at least one second thread.

[0043] based on the read first intermediate data, to obtain one value in result data of the first thread.

[0044] In a possible implementation, the data processing apparatus further includes a fifth processing module 58 configured to: determine, based on configuration information of the data processing operation, a target block strategy of the data processing operation from a plurality of preset block strategies; and perform block processing on the task processing operation based on the target block strategy, to obtain information of each processing block from the at least one processing block.

[0045] In a possible implementation, the at least one processing block is obtained by performing block processing on at least one of result data, input data, and parameter data of the data processing operation.

[0046] In a fourth aspect, the embodiments of the present disclosure further provide a data processing apparatus, applied to a graphics processing unit (GPU), the data processing apparatus comprising: a reading module configured to read a first data block corresponding to a first processing block, wherein the first processing block is included in at least one processing block of a data processing operation; a caching module configured to cache the first data block in a target data caching mode, wherein the target data caching mode is determined based on a level of the first data block; and a processing module configured to perform data processing corresponding to the first processing block on the cached first data block to obtain a processing result of the first data block.

[0047] In a possible implementation, when performing data processing corresponding to the first processing block on the cached first data block to obtain the processing result of the first data block, the processing module is configured to: for a first thread in the plurality of threads, read first intermediate data obtained by at least one second thread from a register of the at least one second thread.

[0048] Based on the read first intermediate data, obtain one value in result data of the first thread.

[0049] In a possible implementation, when performing data processing corresponding to the first processing block on the cached first data block to obtain the processing result of the first data block, the processing module is configured to: read a part of data in a sub-data block corresponding to a third thread in the plurality of threads, process the data read by the third thread to obtain at least one second intermediate data,

[0050] store the at least one second intermediate data into a register of the third thread, wherein the at least one second intermediate data is used to determine one value in result data of the third thread.

[0051] In a possible implementation, the level of the first data block is obtained based on information of the at least one processing block of the data processing operation; and the information of the processing block comprises information of a data block corresponding to the processing block.

[0052] In a possible implementation, the higher the level of the first data block is, the more the number of caches used for caching the first data block in the corresponding data caching manner is; and / or, in a first data caching manner and a second data caching manner different from the first data caching manner, the first data block is cached in at least partially different cache layers; and / or, in a third data caching manner, the first data block is cached to a first specific cache layer, and in a fourth data caching manner different from the third data caching manner, the first data block is not cached to the first specific cache layer; and / or, in a fifth data caching manner and a sixth data caching manner different from the fifth data caching manner, the first data block has different replacement priorities in a same second specific cache layer.

[0053] In a possible implementation, the information of the data block corresponding to the processing block includes: a starting storage address of all data blocks corresponding to the at least one processing block, and an offset of the storage address of the data block of each processing block relative to the starting storage address.

[0054] In a possible implementation, the level corresponding to the first data block is determined based on the sharing degree information of the first data block, and determined based on the sharing degree information of the first data block, the sharing degree information, and a preset level corresponding relationship.

[0055] In a possible implementation, the sharing degree information of the first data block includes: an access frequency of the first data block, the access frequency of the first data block including a proportion of the number of processing blocks that need to access the first data block in the total number of the at least one processing block.

[0056] In a fifth aspect, an electronic device is provided, including a processor and a memory, the memory storing machine readable instructions executable by the processor, the processor being configured to execute the machine readable instructions stored in the memory, and the machine readable instructions being configured to perform the steps of the first aspect or any possible implementation of the first aspect when executed by the processor.

[0057] or perform the steps of the second aspect or any possible implementation of the second aspect.

[0058] In a sixth aspect, a computer readable storage medium is provided, the computer readable storage medium storing a computer program, the computer program being configured to perform the steps of the first aspect or any possible implementation of the first aspect when executed.

[0059] or performing the steps of the second aspect described above, or any one of the possible implementation manners of the second aspect.

[0060] For the effects of the data processing apparatus, the computer device, and the computer readable storage medium described above, refer to the description of the data processing method described above, which will not be repeated here.

[0061] In order to make the above objectives, characteristics and advantages of the present disclosure more obvious and easy to understand, the following preferred embodiments are specifically described below, and the accompanying drawings are described in detail as follows. BRIEF DESCRIPTION OF DRAWINGS

[0062] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings needed to be used in the embodiments. The drawings incorporated into the specification and form a part of the specification, which show the embodiments consistent with the present disclosure, and are used to explain the technical solutions of the present disclosure together with the specification. It should be understood that the following drawings only show some embodiments of the present disclosure, and therefore should not be considered as a limitation to the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor.

[0063] Figure 1 A schematic diagram of a system framework in the related art when performing data processing is shown;

[0064] Figure 2 A flowchart of a data processing method provided by an embodiment of the present disclosure is shown;

[0065] Figure 3 A flowchart of a specific method for determining a level of a first data block corresponding to a first processing block from a plurality of preset levels provided by an embodiment of the present disclosure is shown;

[0066] Figure 4 A flowchart of another data processing method provided by an embodiment of the present disclosure is shown;

[0067] Figure 5 A flowchart of another data processing method provided by an embodiment of the present disclosure is shown;

[0068] Figure 6 A schematic diagram of a determination manner of an optimization scheme of data processing provided by an embodiment of the present disclosure is shown;

[0069] Figure 7 A schematic diagram of a data processing apparatus provided by an embodiment of the present disclosure is shown;

[0070] Figure 8 A schematic diagram of another data processing apparatus provided by an embodiment of the present disclosure is shown;

[0071] Figure 9 A schematic diagram of a computer device is shown. DETAILED DESCRIPTION

[0072] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part but not all of the embodiments of the present disclosure. The components of the embodiments of the present disclosure described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the claimed present disclosure, but merely represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0073] In Figure 1 In the exemplary system framework shown, when performing data processing on a computation-intensive operator, the computing task is divided into multiple task processing blocks, and different task processing blocks are allocated to multiple streaming multi-processors (SMs) in a GPU, each SM including at least one thread block; each thread block can run multiple processing threads, and the multiple processing threads can perform data processing on the computing task corresponding to the task processing block allocated to the SM, thereby speeding up the data processing. As the data sharing degree of the neural network decreases, the computation of the neural network gradually changes from computation-intensive to memory-intensive, causing each thread in the SM to frequently access the memory to obtain the data required in the data processing process.

[0074] In the system architecture, there are Global Memory, L2 cache shared by all SMs, L1 cache inside SM, shared memory readable by threads inside SM, and registers private to each thread. In a common data reading process, the SM first reads data from the Global Memory, through the L2 cache to the L1 cache inside the SM, and writes to the registers or shared memory inside the SM. In the above data reading process, the read data is sequentially cached in the L2 cache, the L1 cache and the shared memory of the SM; but in fact, the amount of data required for data processing is much larger than the capacity of the L2 cache and the L1 cache, and after the data stored in the L2 cache and the L1 cache reaches the upper limit of storage, the GPU will release the previously cached data according to a certain cache management strategy and cache the recently accessed data; when the released data is accessed again, it still needs to be read from the Global Memory, which reduces the efficiency of data reading and further affects the efficiency of data processing.

[0075] The present disclosure provides a data processing method, which divides data blocks corresponding to each processing block of a data processing operation into different levels, and then determines a data caching mode for each data block according to the level of the different data blocks, so as to cache different data blocks in a targeted manner, thereby enabling the caching of data according to the actual data access situation, which is beneficial to improving the data reading efficiency and the data processing efficiency.

[0076] The above-mentioned defects are the results of the inventors' practice and careful research, and therefore, the discovery process of the above-mentioned problems and the solutions proposed by the present disclosure to solve the above-mentioned problems should be the contributions of the inventors to the present disclosure.

[0077] It should be noted that similar reference numbers and letters represent similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0078] For the convenience of understanding the present embodiment, first, a data processing method disclosed by the present embodiment is introduced in detail, the execution subject of the data processing method provided by the present embodiment is generally a computer device containing one or more processors, which for example includes a terminal device or a server or other processing device, and the terminal device can be a user equipment (User Equipment, UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (Personal Digital Assistant, PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc.

[0079] In some possible implementation manners, the data processing method can be realized by the way that a central processing unit (Central Processing Unit, CPU), a graphics processing unit (Graphics Processing Unit, GPU) or other types of processors call computer readable instructions stored in a memory.

[0080] The data processing method provided by the present embodiment is described below.

[0081] Referring to Figure 2 The data processing method provided by the present embodiment is provided, and the method includes steps S201-S202, wherein:

[0082] S201: determining the level of a first data block corresponding to a first processing block from a plurality of preset levels based on the information of at least one processing block of a data processing operation, wherein the at least one processing block includes the first processing block, and the information of the processing block includes the information of the data block corresponding to the processing block;

[0083] S202: determining the data caching mode of the first data block based on the level of the first data block.

[0084] The present embodiment determines the level of a first data block corresponding to a first processing block included in the first processing block from a plurality of preset levels based on the information of at least one processing block of a data processing operation, and then determines the data caching mode of the first data block based on the level of the first data block, so as to cache different data blocks in a targeted manner, to realize data caching according to actual data access conditions, to improve data reading efficiency, and to improve data processing efficiency.

[0085] In a specific implementation, the data processing operation in the embodiments of the present disclosure is, for example, a convolution operation, a pooling operation, or the like. Taking the convolution operation as an example, when the convolution operation is performed on data, the data required for the convolution operation includes input data (such as a feature map) and convolution parameters (such as a convolution kernel and a convolution step) required for performing the convolution operation on the input data. In order to speed up the efficiency of the convolution operation, the convolution operation can be divided into a plurality of processing blocks; a data block corresponding to each processing block includes at least part of the convolution parameters and part of the input data; a data processing task corresponding to each processing block is to perform a convolution operation on part of the input data by using at least part of the convolution parameters; and the final result of the convolution operation on the input data can be obtained by combining the convolution operation results corresponding to all the processing blocks.

[0086] In an embodiment, the at least one processing block is obtained by performing block processing on at least one of the result data of the data processing operation, the input data, and the parameter data.

[0087] For example, the convolution operation can be divided into blocks in the following manner: the number of processing blocks is determined according to configuration information of the convolution processing, and the information of each processing block is determined according to the number of processing blocks.

[0088] In a specific implementation, the configuration information of the convolution processing includes, for example, a batch of input data corresponding to the convolution calculation, the number of input channels, the size of output data, the number K of output channels, the size of a convolution kernel, a convolution step, and the like.

[0089] When the convolution operation is divided into blocks based on the configuration information of the convolution processing, the at least one processing block can be formed, for example, based on at least one of the configuration information of the convolution processing.

[0090] For example, in the case of dividing blocks based on the size of output data and the number of output channels, assuming that the size of the output data is HxW and the number of output channels is N, the first block division is performed according to the size HxW of the output data, the size of the output data corresponding to each processing block is H’xW’, and the number of output channels corresponding to each processing block is N’, and then the number of data blocks formed is

[0091] In another possible embodiment, in order to determine the block division manner and the number of blocks of the processing blocks, a target block division strategy of the data processing operation can be determined from a plurality of preset block division strategies based on the configuration information of the data processing operation; and then the task processing operation is processed based on the target block division strategy to obtain the information of each processing block in the at least one processing block.

[0092] In a specific implementation, different chunking strategies in the plurality of chunking strategies are generated based on different reference configuration information.

[0093] Exemplarily, since there is a certain position mapping relationship between the input data of the convolution processing and the output data of the convolution processing, and there is a certain calculation mapping relationship between the input data of the convolution processing and the convolution kernel of the convolution processing; after determining the number of chunks corresponding to the processing chunk based on the target chunking strategy, the data chunks of each processing chunk can be determined based on the position mapping relationship, the calculation mapping relationship, and the number of processing chunks.

[0094] Here, for example, for each reference configuration information, a plurality of candidate chunking strategies corresponding to each reference configuration information can be determined; then for each candidate chunking strategy, simulation is performed to determine the processing time corresponding to each candidate chunking strategy, and then according to the length of the processing time, a chunking strategy is determined for each reference configuration information from the plurality of candidate chunking strategies.

[0095] When the target chunking strategy is determined from the plurality of predetermined chunking strategies based on the configuration information, for example, the plurality of reference configuration information and the configuration information can be respectively regarded as vectors, and then the vector similarity between each reference configuration information in the plurality of reference configuration information and the configuration information is determined; the target reference configuration information is determined from the plurality of reference configuration information based on the similarity or distance between each reference configuration information in the plurality of reference configuration information and the configuration information of the data processing; the chunking strategy corresponding to the target reference configuration information is determined as the target chunking strategy. Then, based on the target chunking strategy, the number of processing chunks and the data chunks corresponding to each processing chunk are determined.

[0096] In a possible implementation, since the data chunks corresponding to different processing chunks are first stored in the Global Memory when processing; the data chunks corresponding to the processing chunk are read to the specific data processing task execution subject when the data processing task corresponding to the processing chunk is executed, so the information of different processing chunks can be represented by the storage addresses of the data chunks. Exemplarily, the information of any processing chunk includes the starting storage address of all data chunks corresponding to the processing chunk, and the offset of the storage address of each data chunk of the processing chunk relative to the starting storage address.

[0097] After the plurality of processing chunks and the information of each processing chunk are determined, the level of the first data chunk corresponding to the first processing chunk in the plurality of processing chunks can be determined based on the information of the plurality of processing chunks.

[0098] Among the plurality of processing chunks, the first processing chunk is included.

[0099] In a possible implementation, among the plurality of preset levels, the higher the level of the first data block is, the more the number of caches used for caching the first data block in the corresponding data caching manner is.

[0100] For example, for the first data block A and the first data block B, if the level of the first data block A is higher than that of the first data block B, the first data block A is cached in the L1-cache and the L2-cache, and the first data block B is only cached in the L1-cache.

[0101] In a possible implementation, among the first data caching manner and the second data caching manner different from the first data caching manner, the first data block is cached in at least partially different cache layers.

[0102] For example, for the first data caching manner s1 and the second data caching manner s2, the first data block corresponding to the first data caching manner s1 is cached in the L1-cache and the L2-cache, and the first data block corresponding to the second data caching manner s2 is cached in the shared cache in the L1-cache.

[0103] In a possible implementation, in the third data caching manner, the first data block is cached to a first specific cache layer, and in the fourth data caching manner different from the third data caching manner, the first data block is not cached to the first specific cache layer.

[0104] For example, for the third data caching manner s3 and the fourth data caching manner s4, the first data block corresponding to the third data caching manner s3 is cached in the L1-cache and the L2-cache, and the first data block corresponding to the fourth data caching manner s4 is not cached in the L1-cache and the L2-cache.

[0105] In a possible implementation, among the fifth data caching manner and the sixth data caching manner different from the fifth data caching manner, the first data block has different replacement priorities in the same second specific cache layer.

[0106] For example, for the fifth data caching manner s5 and the sixth data caching manner s6, the first data block corresponding to the fifth data caching manner s5 and the sixth data caching manner s6 is cached in the L1-cache, and when the data stored in the L1-cache reaches the upper limit of storage, when new data is to be cached in the L1-cache, the first data block corresponding to the fifth data caching manner s5 is preferentially replaced.

[0107] In specific implementations, different levels can be determined according to actual data access conditions.

[0108] Exemplarily, the following four preset levels can be set: level one, level two, level three, and level four, wherein level one corresponds to the highest level, and then the levels gradually decrease.

[0109] The data caching manner corresponding to level one is to cache the data block to L1-cache and L2-cache.

[0110] The data caching manner corresponding to level two is to cache the data block to L1-cache and L2-cache, but the data block can be replaced preferentially.

[0111] The data caching manner corresponding to level three is to cache the data block to the cache other than L1-cache.

[0112] The data caching manner corresponding to level four is to cache the data block to the cache other than L2-cache.

[0113] Referring to Figure 3 The embodiment of the disclosure provides a specific method for determining the level of the first data block corresponding to the first processing block from a plurality of preset levels, comprising:

[0114] S301: Determine the sharing degree information of the first data block based on the information of the at least one processing block.

[0115] Here, the sharing degree information of the first data block, for example, includes the access frequency of the first data block, and the access frequency of the first data block includes the proportion of the number of processing blocks that need to access the first data block in the total number of the at least one processing block.

[0116] When determining the sharing degree information of the first data block, for example, the address offset of the data block corresponding to the processing block can be used to determine how many processing blocks the data in the first data block will correspond to, and then based on the number of processing blocks corresponding to the data in the first data block and the total number of processing blocks, the sharing degree information of the first data block is determined.

[0117] Exemplarily, the higher the access frequency of the first data block is, the more SMs it will be accessed by, and therefore, it is preferentially cached to L2-cache that can be accessed by all SMs; the lower the access frequency of the first data block is, the fewer SMs it will be accessed by, and therefore, it can be cached in L1-cache that can be accessed by only one SM.

[0118] Further, the SM can divide the data processing task corresponding to the data block into a plurality of sub-tasks when performing the data processing task corresponding to the data block based on the data block corresponding to the SM, and then perform the corresponding sub-tasks by using threads in the SM; the sharing degree information can further include that threads needing to access the same data in the data block account for a second proportion of all threads in the SM.

[0119] For example, the higher the second proportion is, the more threads access the data block, and thus the data block can be cached to the L1-cache; the lower the second proportion is, the fewer threads access the data block, and thus the data in the data block can not be cached to the L1-cache; in this case, if threads in a plurality of SMs need to access the data in the data block, the data block can be cached to the L2-cache, so that threads in each SM can directly read the data in the data block from the L2-cache; if only a small number of threads in the SM need to access the data in the data block, the data block can be cached to the shared memory in the SM, so that the data in the data block can only be accessed by the threads in the SM and does not occupy the storage space of the L1-cache.

[0120] S302: Determine the level of the first data block based on the sharing degree information of the first data block and the correspondence between the sharing degree information and the plurality of preset levels.

[0121] Here, for example, the correspondence between the sharing degree information and the plurality of preset levels can be determined in advance. After the sharing degree information of the first data block is determined, the corresponding level is determined from the plurality of preset levels based on the sharing degree information of the first data block, and the determined level is taken as the level of the first data block.

[0122] For example, assuming that the size of the input data of the convolution processing is (M, K), the size of the data block corresponding to each processing block is (B M, B K), and the number of SMs in the GPU is X. The number of processing blocks BLOCK required by the GPU to perform the convolution processing is M / B M*K / B K. Assuming that the input data in the data is (M0, M1, M2,...), and the data block of the weight value is (K0, K1, K2,...), the information of each BLOCK is also determined. The access probability P(Mi) of the data block Mi is defined as the number of BLOCKs accessing Mi divided by the total number of BLOCKs, the access frequency P(Ki) of Ki is defined as the number of BLOCKs accessing Ki divided by the total number of BLOCKs, and the frequency thresholds PH and PL are set. The data block with an access frequency greater than the threshold PH is a data block of level one, and the data block with an access frequency lower than the threshold PL is a data block of level two. The data between PH and PL can be analyzed by simulation. By using the block configuration and the number of SMs in the GPU, the data blocks corresponding to two BLOCKs that can be accessed by one SM are set to level three, and the remaining data blocks are set to level two. For the convolution calculation result, write back to the global memory only once, and set the data block of level four.

[0123] After determining the level of the first data block corresponding to the first processing block, the data caching manner of the first data block can be determined based on the level of the first data block.

[0124] In another embodiment of the present disclosure, when the data processing method provided by the embodiment of the present disclosure is executed by the CPU, the data processing method provided by the embodiment of the present disclosure further comprises:

[0125] The task processing instruction corresponding to the first processing block is sent to the GPU, and the task processing instruction indicates the data caching manner of the first data block.

[0126] Here, the task processing instruction corresponding to the first processing block, for example, is generated based on the data caching manner corresponding to the first data block, and can indicate the data caching manner of the first data block. The task processing instruction can be executed by the GPU, and when the task processing instruction is executed by the GPU, the corresponding data block can be cached according to the data caching manner corresponding to the task processing instruction.

[0127] In another embodiment of the present disclosure, when the data processing method provided by the embodiment of the present disclosure is executed by the GPU, the data processing method provided by the embodiment of the present disclosure further comprises:

[0128] In the process of executing the data processing task corresponding to the first processing block, the first data block is cached and read according to the data caching manner corresponding to the first data block.

[0129] For example, in the data cache mode, only the first data block is cached to the L2-cache. When the SM_1 executes the data processing task corresponding to the first data block, the L1-cache in the SM_1 is accessed first. If the first data block is not cached in the L1-cache, the L2-cache is accessed. If the first data block is not cached in the L2-cache, the Global Memory is accessed. After the first data block is read from the Global Memory, the first data block is cached to the L2-cache. Based on the read first data block, the data processing task is executed. When another SM_2 executes the data processing task corresponding to the same data block, the first data block can be read from the L2-cache.

[0130] Referring to Figure 4 The embodiment of the present disclosure also provides another data processing method, including:

[0131] S401: dividing the data processing corresponding to the first processing block into a plurality of sub-tasks, each sub-task being executed by a thread;

[0132] S402: determining a storage location of data corresponding to each thread based on a data dependency relationship between the plurality of sub-tasks;

[0133] The storage location of the data corresponding to the first thread includes a register of at least one second thread having a data dependency relationship with the first thread.

[0134] For example, in the plurality of threads, the first thread is included. The data corresponding to the first thread includes a part of a first data block corresponding to the first processing block, and / or a second intermediate data of the second thread, the second intermediate data being used to obtain one value in result data of the first thread.

[0135] In a possible implementation, the embodiment of the present disclosure also includes:

[0136] reading a part of data in a sub-data block corresponding to a third thread in the plurality of threads,

[0137] processing the data read by the third thread to obtain at least one second intermediate data,

[0138] storing the at least one second intermediate data into a register of the third thread, wherein the at least one second intermediate data is used to determine one value in result data of the third thread.

[0139] For example, when the SM is performing a data processing task corresponding to the first processing block, the SM reads the first data block according to the data caching mode determined according to the level corresponding to the first data block, and stores the read first data block in the shared memory inside the SM for access by each thread inside the SM.

[0140] When the first thread and the second thread have a data dependency relationship, at least part of the first sub-data block of the first thread and the second sub-data block of the second thread are the same. When the second thread performs the corresponding second sub-task, the second sub-data block is read from the shared memory inside the SM (and / or the register corresponding to other threads having a data dependency relationship therewith), the sub-task is performed based on the second sub-data block, and the data in the same part of the second sub-data block as in the first sub-data block is stored in the register of the second sub-data block.

[0141] When the first thread performs the first sub-task corresponding thereto, for data in the same part of the second data block, the data can be directly read from the register corresponding to the second thread using shuffle. For different parts, the data can be read from the shared memory inside the SM.

[0142] Since the speed of reading data in the register corresponding to the sub-thread is faster than the speed of reading data from the memory, and further, reading data from the register corresponding to other threads having a data dependency relationship has higher data reading efficiency, the execution speed of the data processing task is accelerated.

[0143] For example, the input data included in the first data block corresponding to the first processing block is:

[0144]

[0145] The data processing task corresponding to the first processing block is to perform convolution processing on it using a 3x3 convolution kernel with a step size of 1.

[0146] The data corresponding to the second thread L1 includes:

[0147] The data corresponding to the first thread L2 includes:

[0148] Part of the data D1 and D2 is the same, that is, the thread L1 and the thread L2 share part of the input data. After L1 reads D1 from the shared memory of the SM, the shared data of D1 and D2 is stored in the register corresponding to the thread L1, that is, the data is stored in the register corresponding to L1.

[0149] When L2 reads D2, reads and read from a register corresponding to the L1 to obtain D2.

[0150] In another possible implementation, the method further includes: for a first thread of the plurality of threads,

[0151] reading first intermediate data obtained by the at least one second thread from a register of the at least one second thread;

[0152] obtaining one value in result data of the first thread based on the read first intermediate data.

[0153] For example, the second thread is configured to read the second data block from the SM, perform a calculation task based on the second data block to obtain second intermediate data output by the second thread, and store the second intermediate data into a register corresponding to the second thread.

[0154] The first thread reads the second intermediate data from the register corresponding to the second thread, and obtains one value in result data of the first thread based on the second intermediate data.

[0155] For example, the input data included in the first data block corresponding to the first processing block includes:

[0156]

[0157] The data processing task corresponding to the first processing block is to perform convolution processing on the first data block by using a 3*3 convolution kernel with a step of 1.

[0158] The convolution parameter is:

[0159] The data corresponding to the thread L1 includes: and performs calculation:

[0160] and saves the intermediate data to a register corresponding to the L1.

[0161] The data corresponding to the thread L2 includes: and performs calculation:

[0162] and saves the intermediate data to a register corresponding to the L2.

[0163] The data corresponding to the thread L3 includes: and performs calculation:

[0164] and saves the intermediate data to a register corresponding to the L3.

[0165] The thread L1 has a data dependency relationship with the above L2 and L3, that is, L1 reads P42 from the corresponding register of L2 and reads P53 from the corresponding register of L3.

[0166] Then, the calculation P31+P42+P53 is performed, and the result is one of the values in the result data of the thread L1.

[0167] It should be noted that, since the example is only a simple example, there is only one value in the result data corresponding to each thread, and when the amount of data corresponding to each thread is more, the number of values in the obtained result data is also more.

[0168] Through the above process, each thread stores the intermediate data or part of the input data calculated into the corresponding register, and other threads having a data dependency relationship can directly obtain the data by accessing the register, thereby accelerating the data access speed and improving the efficiency of the data processing task.

[0169] Referring to Figure 5 The embodiment of the disclosure also provides a data processing method applied to a graphics processing unit (GPU), wherein the same or similar contents as the above will not be repeated, and the data processing method comprises the following steps:

[0170] S501: reading a first data block corresponding to a first processing block, wherein the first processing block is included in at least one processing block of a data processing operation;

[0171] S502: caching the first data block in a target data caching mode, wherein the target data caching mode is determined based on a level of the first data block;

[0172] S503: performing data processing corresponding to the first processing block on the cached first data block to obtain a processing result of the first data block.

[0173] After reading the first data block corresponding to the first processing block, the embodiment of the disclosure caches the first data block according to the target data caching mode corresponding to the first data block, and performs data processing corresponding to the first processing block on the cached first data block to obtain a processing result of the first data block. Since the target data caching mode corresponding to the first data block is determined based on the level of the first data block, different data blocks can be cached accordingly, so that the data caching can be realized according to the actual data access situation, the data reading efficiency is improved, and the data processing efficiency is improved.

[0174] In a possible implementation, the data processing corresponding to the first processing block is performed on the cached first data block to obtain a processing result of the first data block, including:

[0175] For a first thread in the plurality of threads,

[0176] reading first intermediate data obtained by at least one second thread from a register of the at least one second thread;

[0177] obtaining one value in result data of the first thread based on the read first intermediate data.

[0178] In a possible implementation, the data processing corresponding to the first processing block is performed on the cached first data block to obtain a processing result of the first data block, including:

[0179] reading a part of data in a sub data block corresponding to a third thread in the plurality of threads,

[0180] performing processing on the data read by the third thread to obtain at least one second intermediate data,

[0181] storing the at least one second intermediate data into a register of the third thread, where the at least one second intermediate data is used to determine one value in result data of the third thread.

[0182] In a possible implementation, the level of the first data block is obtained based on information of at least one processing block of a data processing operation; where the information of the processing block includes information of a data block corresponding to the processing block.

[0183] In a possible implementation, the information of the data block corresponding to the processing block includes:

[0184] a starting storage address of all data blocks corresponding to the at least one processing block, and an offset of a data block of each processing block relative to the starting storage address.

[0185] In a possible implementation, the level corresponding to the first data block is determined based on sharing degree information of the first data block, and determined based on the sharing degree information of the first data block and a preset correspondence relationship between the sharing degree information and a plurality of preset levels.

[0186] In a possible implementation, the sharing degree information of the first data block includes: an access frequency of the first data block, where the access frequency of the first data block includes a proportion of a number of processing blocks that need to access the first data block in a total number of the at least one processing block.

[0187] The specific implementation process of the above steps can be specifically seen from Figure 1 The corresponding embodiments are not described here.

[0188] Those skilled in the art can understand that in the above method of the specific implementation, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0189] Referring to Figure 6 As shown in the figure, the disclosure embodiment also provides a determination method of an optimization scheme of data processing, in which the optimization process can be divided into four parts:

[0190] Optimization process one, block optimization engine, divides the data processing task of at least one network layer of the neural network into blocks to obtain a plurality of processing blocks. For the given network layer configuration information, the network layer configuration information and the GPU configuration information are taken as inputs to obtain the optimized block configuration, and the block information corresponding to each processing block is output. This process quickly optimizes the block mode of the data processing task.

[0191] Optimization process two, cache optimization engine, divides the weight data and feature data corresponding to the data processing task according to the block information, the configuration information of the GPU, and the configuration information of the network layer, and uses different instructions to access and cache the data of different levels in combination with the address of the memory to generate the optimal data access mode. This process can implement the classification of irregular convolution data, and based on the classification of different data, the targeted cache optimization strategy uses different cache access mechanisms for different data.

[0192] Optimization process three, core calculation engine, determines the way and granularity of data sharing between threads, and generates the corresponding core calculation mode. The core calculation mode indicates that when each thread executes the data processing task, the intermediate data is shared through the register, and each thread reads the intermediate data of other threads to complete the data processing task. This process can improve the data acquisition efficiency by passing the intermediate data between threads.

[0193] Optimization process four: according to the block information obtained by the block optimization engine, the SM of the GPU is allocated, according to the priority order of the data obtained by the cache optimization engine, the data reading and writing mode is obtained, according to the data sharing mode and granularity determined by the core calculation engine, the core calculation code of data processing is generated, and the final data processing optimization scheme is obtained.

[0194] Through the above method, the specific processing process of data processing is determined. This process improves the data reading efficiency and improves the efficiency of data processing.

[0195] Based on the same inventive concept, the data processing apparatus corresponding to the data processing method is also provided in the embodiments of the present disclosure. Since the principle of solving problems of the apparatus in the embodiments of the present disclosure is similar to the data processing method described above, the implementation of the apparatus can refer to the implementation of the method, and the repeated parts will not be described here.

[0196] Referring to Figure 7 FIG. 1 shows a schematic diagram of a data processing apparatus provided by the embodiments of the present disclosure, and the apparatus comprises:

[0197] The first determining module 71 is configured to determine, based on information of at least one processing block of a data processing operation, a level of a first data block corresponding to a first processing block from a plurality of preset levels, wherein the at least one processing block comprises the first processing block, and the information of the processing block comprises information of a data block corresponding to the processing block.

[0198] The second determining module 72 is configured to determine, based on the level of the first data block, a data caching manner of the first data block.

[0199] In a possible implementation, the higher the level of the first data block is, the more the number of caches used for caching the first data block in the corresponding data caching manner is; and / or

[0200] In the first data caching manner and a second data caching manner different from the first data caching manner, the first data block is cached in at least partially different cache layers; and / or

[0201] In the third data caching manner, the first data block is cached to a first specific cache layer, and in a fourth data caching manner different from the third data caching manner, the first data block is not cached to the first specific cache layer.

[0202] And / or, in a fifth data caching manner and a sixth data caching manner different from the fifth data caching manner, the first data block has different replacement priorities in a same second specific cache layer.

[0203] In a possible implementation, when determining the level of the first data block corresponding to the first processing block from the plurality of preset levels, the first determining module 71 is configured to:

[0204] determine sharing degree information of the first data block based on the information of the at least one processing block;

[0205] determine the level of the first data block based on the sharing degree information of the first data block, and a correspondence between the sharing degree information and the plurality of preset levels.

[0206] In a possible implementation, the sharing degree information of the first data block includes: an access frequency of the first data block, where the access frequency of the first data block includes a proportion of a number of processing blocks that need to access the first data block in a total number of the at least one processing block.

[0207] In a possible implementation, the information of the at least one processing block includes:

[0208] a start storage address of all data blocks corresponding to the at least one processing block, and an offset of a data block of each processing block relative to the start storage address.

[0209] In a possible implementation, when the data processing apparatus is deployed in a central processing unit (CPU), the data processing apparatus further includes:

[0210] a sending module 73, configured to send a task processing instruction corresponding to the first processing block to a graphics processing unit (GPU), where the task processing instruction indicates a data caching manner of the first data block.

[0211] In a possible implementation, when the data processing apparatus is deployed in a graphics processing unit (GPU), the data processing apparatus further includes:

[0212] a first processing module 74, configured to cache the first data block in a data caching manner corresponding to the first data block during execution of a data processing task corresponding to the first processing block.

[0213] In a possible implementation, the data processing apparatus further includes a second processing module 75, configured to:

[0214] divide a data processing corresponding to the first processing block into a plurality of subtasks, each of which is executed by a thread;

[0215] determine a storage location of data corresponding to each thread based on a data dependency relationship between the plurality of subtasks;

[0216] wherein the storage location of data corresponding to the first thread includes a register of at least one second thread having a data dependency relationship with the first thread.

[0217] In a possible implementation, the data corresponding to the first thread includes:

[0218] a part of a first data block corresponding to the first processing block; and / or,

[0219] second intermediate data of the second thread, where the second intermediate data is used to obtain one value in result data of the first thread.

[0220] In a possible implementation, the first processing block is executed by a plurality of threads, and the data processing apparatus further includes a third processing module 76, configured to:

[0221] read a part of data in a sub-data block corresponding to a third thread in the plurality of threads,

[0222] process the data read by the third thread to obtain at least one second intermediate data,

[0223] store the at least one second intermediate data into a register of the third thread, wherein the at least one second intermediate data is used to determine one value in result data of the third thread.

[0224] In a possible implementation, the first processing block is executed by a plurality of threads, and the data processing apparatus further includes a fourth processing module 77, configured to:

[0225] for a first thread in the plurality of threads,

[0226] read first intermediate data obtained by at least one second thread from a register of the at least one second thread;

[0227] determine one value in result data of the first thread based on the read first intermediate data.

[0228] In a possible implementation, the data processing apparatus further includes a fifth processing module 78, configured to:

[0229] determine a target block strategy of the data processing operation from a plurality of preset block strategies based on configuration information of the data processing operation;

[0230] perform block processing on the task processing operation based on the target block strategy to obtain information of each processing block in the at least one processing block.

[0231] In a possible implementation, the at least one processing block is obtained by performing block processing on at least one of result data, input data, and parameter data of the data processing operation.

[0232] The description of the processing procedure of each module in the apparatus and the interaction procedure between the modules can refer to the related description in the method embodiments, and will not be repeated here.

[0233] Referring to FIG. 1, Figure 8 the embodiments of the present disclosure further provide another data processing apparatus, which is applied to a graphics processing unit (GPU), and the data processing apparatus includes:

[0234] The reading module 81 reads a first data block corresponding to a first processing block, wherein the first processing block is included in at least one processing block of a data processing operation;

[0235] The caching module 82 caches the first data block in a target data caching manner, wherein the target data caching manner is determined based on a level of the first data block;

[0236] The processing module 83 performs data processing corresponding to the first processing block on the cached first data block, to obtain a processing result of the first data block.

[0237] In a possible implementation, when the processing module 83 performs data processing corresponding to the first processing block on the cached first data block, to obtain a processing result of the first data block, the processing module 83 is configured to:

[0238] For a first thread in the plurality of threads,

[0239] read, from a register of at least one second thread, first intermediate data obtained by the at least one second thread;

[0240] obtain one value in result data of the first thread based on the read first intermediate data.

[0241] In a possible implementation, when the processing module 83 performs data processing corresponding to the first processing block on the cached first data block, to obtain a processing result of the first data block, the processing module 83 is configured to:

[0242] read a part of data in a sub-data block corresponding to a third thread in the plurality of threads,

[0243] perform processing on the data read by the third thread, to obtain at least one second intermediate data,

[0244] store the at least one second intermediate data into a register of the third thread, wherein the at least one second intermediate data is used to determine one value in result data of the third thread.

[0245] In a possible implementation, the level of the first data block is obtained based on information of at least one processing block of a data processing operation; wherein the information of the processing block includes information of a data block corresponding to the processing block.

[0246] In a possible implementation, the higher the level of the first data block is, the more the number of caches used to cache the first data block in the corresponding data caching manner is; and / or

[0247] In the first data caching mode and a second data caching mode different from the first data caching mode, the first data block is cached in at least partially different cache layers; and / or

[0248] In a third data caching mode, the first data block is cached to a first specific cache layer, and in a fourth data caching mode different from the third data caching mode, the first data block is not cached to the first specific cache layer.

[0249] and / or, in a fifth data caching mode and a sixth data caching mode different from the fifth data caching mode, the first data block has different replacement priorities in a same second specific cache layer.

[0250] In a possible implementation, the information of the data block corresponding to the processing block includes:

[0251] a starting storage address of all data blocks corresponding to the at least one processing block, and an offset of the storage address of the data block of each processing block relative to the starting storage address.

[0252] In a possible implementation, the level of the first data block is determined based on the information of the at least one processing block, the sharing degree information of the first data block, and a correspondence relationship between the sharing degree information and a plurality of preset levels.

[0253] In a possible implementation, the sharing degree information of the first data block includes: an access frequency of the first data block, the access frequency of the first data block including a proportion of a number of processing blocks that need to access the first data block in a total number of the at least one processing block.

[0254] The embodiments of the present disclosure further provide a computer device, as shown in the accompanying drawings, which includes: Figure 9 As shown in the accompanying drawings, the computer device provided by the embodiments of the present disclosure includes:

[0255] a processor 11 and a memory 12; the memory 12 stores machine readable instructions executable by the processor 11, when the computer device is running, the machine readable instructions are executed by the processor to implement the following steps:

[0256] determine, based on information of at least one processing block of a data processing operation, a level of a first data block corresponding to a first processing block from a plurality of preset levels, wherein the at least one processing block includes the first processing block, and the information of the processing block includes information of a data block corresponding to the processing block;

[0257] determine a data caching mode of the first data block based on the level of the first data block.

[0258] Alternatively, the machine readable instructions are executed by the processor to implement the following steps:

[0259] reading a first data block corresponding to a first processing block, wherein the first processing block is included in at least one processing block of a data processing operation;

[0260] caching the first data block in a target data caching mode, wherein the target data caching mode is determined based on a level of the first data block;

[0261] performing data processing corresponding to the first processing block on the cached first data block to obtain a processing result of the first data block.

[0262] The specific execution process of the above instructions can refer to the steps of the data processing method described in the embodiments of the present disclosure, which will not be described here.

[0263] The embodiments of the present disclosure also provide a computer readable storage medium, which stores a computer program. When the computer program is run by a processor, the steps of the data processing method described in the above method embodiments are executed. The storage medium can be a volatile or non-volatile computer readable storage medium.

[0264] The computer program product of the data processing method provided by the embodiments of the present disclosure includes a computer readable storage medium storing program codes. The instructions included in the program codes can be used to execute the steps of the data processing method described in the above method embodiments. For details, refer to the above method embodiments, which will not be described here.

[0265] The embodiments of the present disclosure also provide a computer program, which is executed by a processor to implement any one of the methods of the preceding embodiments. The computer program product can be specifically implemented by hardware, software or a combination thereof. In one optional embodiment, the computer program product is specifically embodied as a computer storage medium. In another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (Software Development Kit, SDK) and the like.

[0266] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system and device described above can refer to the corresponding process in the foregoing method embodiment, and will not be repeated here. In several embodiments provided in the present disclosure, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and another division can be made in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some communication interfaces, devices or units, and can be electrical, mechanical or other forms.

[0267] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0268] In addition, each functional unit in each embodiment of the present disclosure can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0269] If the functions are realized in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer readable storage medium executable by a processor. Based on this understanding, the technical solutions of the present disclosure essentially or the part of the prior art or the part of the technical solutions can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions for making a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present disclosure. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and various program code storage media.

[0270] Finally, it should be noted that the above-described embodiments are merely specific embodiments of the present disclosure, used to illustrate the technical solutions of the present disclosure, and are not intended to limit the present disclosure. The protection scope of the present disclosure is not limited thereto. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can make modifications or easy changes to the technical solutions described in the foregoing embodiments, or easily think of changes or equivalent replacements for some of the technical features; and these modifications, changes or replacements do not cause the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A data processing method, characterized by, The method comprises: determining sharing degree information of a first data block based on information of at least one processing block of a data processing operation; determining a level of the first data block based on the sharing degree information of the first data block and a correspondence between the sharing degree information and a plurality of preset levels, wherein the at least one processing block comprises a first processing block, the information of the processing block comprises a starting storage address of all data blocks corresponding to the processing block and an offset of a storage address of a data block of each processing block relative to the starting storage address, the sharing degree information of the first data block comprises an access frequency of the first data block, and the access frequency of the first data block comprises a proportion of a number of processing blocks that need to access the first data block in a total number of the at least one processing block; determining a data caching mode of the first data block based on the level of the first data block.

2. The data processing method of claim 1, wherein: the higher the level of the first data block is, the more the number of caches used to cache the first data block in the corresponding data caching mode is; and / or in a first data caching mode and a second data caching mode different from the first data caching mode, the first data block is cached in at least partially different cache layers; and / or in a third data caching mode, the first data block is cached to a first specific cache layer, and in a fourth data caching mode different from the third data caching mode, the first data block is not cached to the first specific cache layer; and / or in a fifth data caching mode and a sixth data caching mode different from the fifth data caching mode, the first data block has different replacement priorities in a same second specific cache layer.

3. The data processing method according to claim 1 or 2, characterized in that, The data processing method is executed by a central processing unit (CPU), and the method further comprises: sending task processing instructions corresponding to the first processing block to a graphics processing unit (GPU), wherein the task processing instructions indicate the data caching mode of the first data block; or The data processing method is executed by a graphics processing unit (GPU), and the method further comprises: in a process of executing a data processing task corresponding to the first processing block, caching and reading the first data block according to the data caching mode corresponding to the first data block.

4. The data processing method according to any one of claims 1-2, characterized in that, The method further comprises: dividing data processing corresponding to the first processing block into a plurality of subtasks, each subtask being executed by a thread; determining a storage location of data corresponding to each thread based on a data dependency relationship between the plurality of subtasks; wherein the storage location of data corresponding to a first thread comprises a register of at least one second thread having a data dependency relationship with the first thread.

5. The data processing method according to any one of claims 1-2, characterized in that, The first processing block is executed by a plurality of threads, and the method further comprises: reading a part of data in a sub-data block corresponding to a third thread from the plurality of threads, processing the data read by the third thread to obtain at least one second intermediate data, store the at least one second intermediate data into a register of the third thread, wherein the at least one second intermediate data is used to determine one value in result data of the third thread.

6. The data processing method according to any one of claims 1-2, characterized in that, The first processing block is executed by a plurality of threads, and the method further comprises: reading, for a first thread in the plurality of threads, first intermediate data obtained by at least one second thread from a register of the at least one second thread; obtaining, based on the read first intermediate data, one value in result data of the first thread.

7. A data processing method, characterized by, The data processing method is applied to a graphics processing unit (GPU), and the data processing method comprises: reading a first data block corresponding to a first processing block, wherein the first processing block is included in at least one processing block of a data processing operation; caching the first data block in a target data caching mode, wherein the target data caching mode is determined based on a level of the first data block; the level of the first data block is obtained based on information of the at least one processing block of the data processing operation; wherein the information of the processing block comprises a starting storage address of all data blocks corresponding to the processing block and an offset of a storage address of a data block of each processing block relative to the starting storage address; the level corresponding to the first data block is determined based on shared degree information of the first data block, and determined based on the shared degree information of the first data block and a correspondence relationship between the shared degree information and a plurality of preset levels; the shared degree information of the first data block comprises an access frequency of the first data block, and the access frequency of the first data block comprises a proportion of a number of processing blocks that need to access the first data block in a total number of the at least one processing block; performing data processing corresponding to the first processing block on the cached first data block to obtain a processing result of the first data block.

8. The data processing method according to claim 7, characterized in that, The performing data processing corresponding to the first processing block on the cached first data block to obtain a processing result of the first data block comprises: The first processing block is executed by a plurality of threads, and for a first thread in the plurality of threads, first intermediate data obtained by at least one second thread is read from a register of the at least one second thread; based on the read first intermediate data, one value in result data of the first thread is obtained.

9. The data processing method according to claim 7 or 8, characterized in that, The performing data processing corresponding to the first processing block on the cached first data block to obtain a processing result of the first data block comprises: The first processing block is executed by a plurality of threads, and a part of data in a sub-data block corresponding to a third thread in the plurality of threads is read; processing the data read by the third thread to obtain at least one second intermediate data; storing the at least one second intermediate data into a register of the third thread, wherein the at least one second intermediate data is used to determine one value in result data of the third thread.

10. The data processing method of claim 7, wherein, The higher the level of the first data block is, the more the number of caches used to cache the first data block in the corresponding data caching mode is; and / or, In the first data caching mode and a second data caching mode different from the first data caching mode, the first data block is cached in at least partially different cache layers; and / or, In a third data caching mode, the first data block is cached to a first specific cache layer, and in a fourth data caching mode different from the third data caching mode, the first data block is not cached to the first specific cache layer; and / or, in a fifth data caching mode and a sixth data caching mode different from the fifth data caching mode, the first data block has different replacement priorities in a same second specific cache layer.

11. A data processing apparatus, characterized by Comprising: A first determination module configured to determine sharing degree information of a first data block based on information of at least one processing block of a data processing operation; determine a level of the first data block based on the sharing degree information of the first data block and a correspondence relationship between the sharing degree information and a plurality of preset levels, wherein the at least one processing block includes a first processing block, the information of the processing block includes a starting storage address of all data blocks corresponding to the processing block and an offset of a storage address of a data block of each processing block relative to the starting storage address; the sharing degree information of the first data block includes an access frequency of the first data block, and the access frequency of the first data block includes a proportion of a number of processing blocks that need to access the first data block in a total number of the at least one processing block; A second determination module configured to determine a data caching mode of the first data block based on the level of the first data block.

12. A data processing apparatus, characterized by The data processing module is applied to a graphics processing unit (GPU), and comprises: A reading module configured to read a first data block corresponding to a first processing block, wherein the first processing block is included in at least one processing block of a data processing operation; A caching module configured to cache the first data block in a target data caching mode, wherein the target data caching mode is determined based on a level of the first data block; the level of the first data block is obtained based on information of at least one processing block of a data processing operation; wherein the information of the processing block includes a starting storage address of all data blocks corresponding to the processing block and an offset of a storage address of a data block of each processing block relative to the starting storage address; the level corresponding to the first data block is determined based on sharing degree information of the first data block, and is determined based on the sharing degree information of the first data block and a correspondence relationship between the sharing degree information and a plurality of preset levels; the sharing degree information of the first data block includes an access frequency of the first data block, and the access frequency of the first data block includes a proportion of a number of processing blocks that need to access the first data block in a total number of the at least one processing block; A processing module configured to perform data processing corresponding to the first processing block on the cached first data block to obtain a processing result of the first data block.

13. An electronic device, comprising: Comprising: A processor, a memory, the memory storing machine readable instructions executable by the processor, the processor being configured to execute the machine readable instructions stored in the memory, the machine readable instructions, when executed by the processor, causing the processor to perform the steps of the data processing method according to any one of claims 1 to 10.

14. A computer-readable storage medium, characterized in that, A computer program is stored in the computer readable storage medium, and when the computer program is run by an electronic device, the electronic device performs the steps of the data processing method according to any one of claims 1 to 10.

Images