Data transmission circuit

Abstract

This invention provides a data transmission circuit. The data transmission circuit includes a transmitter configured to transmit data signals, a receiver configured to receive data signals, a first transmission line connected between the transmitter and the receiver, and a second transmission line connected between the transmitter and the receiver. The data signals include a line start signal and a configuration signal. The data signals further include at least one of an inverted line start signal and an inverted configuration signal, wherein the inverted line start signal is an inverted version of the line start signal, and the inverted configuration signal is an inverted version of the configuration signal.

Description

Technical Field

[0001] This invention relates to a data transmission circuit and a display device. More specifically, embodiments of this invention relate to a data transmission circuit that inserts an inverted version of at least one of a row start signal and a configuration signal to stabilize an input common-mode voltage, and a display device including the data transmission circuit. Background Technology

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes multiple gate lines and multiple data lines. The display panel driver includes a gate driver, a data driver, and a drive controller. The gate driver outputs gate signals to the gate lines. The data driver outputs data voltages to the data lines. The drive controller controls the gate driver and the data driver.

[0003] The display panel driver may include data transmission circuitry for sending data. The data transmission circuitry may have a data transmission interface type. The data transmission circuitry may include a transmitter and a receiver. The transmitter and receiver may send and receive data signals based on the input common-mode voltage.

[0004] When the ratio of high-level data signals to low-level data signals is high, the input common-mode voltage may increase compared to the ideal value. Conversely, when the ratio of low-level data signals to high-level data signals is high, the input common-mode voltage may decrease compared to the ideal value.

[0005] When the input common-mode voltage increases compared to the ideal value, the receiver circuitry may be damaged. When the input common-mode voltage decreases compared to the ideal value, errors may occur in the signal received by the receiver, and the signal transmission quality may deteriorate. Summary of the Invention

[0006] Embodiments of the present invention provide a data transmission circuit capable of stabilizing the input common-mode voltage of the data transmission circuit.

[0007] An embodiment of the present invention provides a display device including the data transmission circuit.

[0008] In an embodiment of a data transmission circuit according to the present invention, the data transmission circuit includes a transmitter configured to transmit a data signal, a receiver configured to receive a data signal, a first transmission line connected between the transmitter and the receiver, and a second transmission line connected between the transmitter and the receiver. The data signal includes a line start signal and a configuration signal. The data signal further includes at least one of an inverted line start signal and an inverted configuration signal, wherein the inverted line start signal is an inverted version of the line start signal, and the inverted configuration signal is an inverted version of the configuration signal.

[0009] In this embodiment, the data signal further includes pixel signals and horizontal blanking signals.

[0010] In an embodiment, the data signal may sequentially include a row start signal, a configuration signal, a first inverted signal, an inverted row start signal, an inverted configuration signal, and a second inverted signal.

[0011] In an embodiment, the transmitter may be configured to further transmit an inverted detection signal to the receiver. The inverted detection signal may change from a first level to a second level overlapping with a first inverted signal, and change from a second level to a first level overlapping with a second inverted signal.

[0012] In an embodiment, the first inverted signal and the second inverted signal may include the same signal pattern as the horizontal blanking signal.

[0013] In this embodiment, the data signal may sequentially include a row start signal, a first inverted signal, an inverted row start signal, a second inverted signal, a configuration signal, a third inverted signal, an inverted configuration signal, and a fourth inverted signal.

[0014] In an embodiment, the transmitter may be configured to further transmit an inverted detection signal to the receiver. The inverted detection signal may change from a first level to a second level overlapping with a first inverted signal, change from a second level to a first level overlapping with a second inverted signal, change from a first level to a second level overlapping with a third inverted signal, and change from a second level to a first level overlapping with a fourth inverted signal.

[0015] In an embodiment, the first inverted signal, the second inverted signal, the third inverted signal, and the fourth inverted signal may include the same signal pattern as the horizontal blanking signal.

[0016] In an embodiment, the data signal may include one of an inverted row start signal and an inverted configuration signal, respectively, based on the data patterns of the row start signal and the configuration signal.

[0017] In an embodiment, when the ratio between the high and low levels of the row start signal is not 1:1, the data signal may include an inverted row start signal.

[0018] In an embodiment, when the ratio between the high and low levels of the configuration signal is not 1:1, the data signal may include an inverted configuration signal.

[0019] In this embodiment, the configuration signal may include a first configuration signal and a second configuration signal. The inverted configuration signal may include a first inverted configuration signal, which is an inverted version of the first configuration signal, and a second inverted configuration signal, which is an inverted version of the second configuration signal. The data signal may sequentially include a row start signal, a first inverted signal, an inverted row start signal, a second inverted signal, a first configuration signal, a third inverted signal, a first inverted configuration signal, a fourth inverted signal, a second configuration signal, a fifth inverted signal, a second inverted configuration signal, and a sixth inverted signal.

[0020] In an embodiment, the transmitter may be configured to further transmit an inverted detection signal to the receiver. The inverted detection signal may change from a first level to a second level overlapping with a first inverted signal, from a second level to a first level overlapping with a second inverted signal, from a first level to a second level overlapping with a third inverted signal, from a second level to a first level overlapping with a fourth inverted signal, from a first level to a second level overlapping with a fifth inverted signal, and from a second level to a first level overlapping with a sixth inverted signal.

[0021] In the embodiments, the first inverted signal, the second inverted signal, the third inverted signal, the fourth inverted signal, the fifth inverted signal, and the sixth inverted signal may include the same signal pattern as the horizontal blanking signal.

[0022] In this embodiment, the configuration signal may include a first configuration signal and a second configuration signal. The data signal may include, respectively, a first inverted configuration signal and a second inverted configuration signal, based on the data modes of the first configuration signal and the second configuration signal, where the first inverted configuration signal is an inverted version of the first configuration signal, and the second inverted configuration signal is an inverted version of the second configuration signal.

[0023] In an embodiment, when the ratio between the high and low levels of the first configuration signal is not 1:1, the data signal may sequentially include a row start signal, a first inverted signal, an inverted row start signal, a second inverted signal, a first configuration signal, a third inverted signal, a first inverted configuration signal, a fourth inverted signal, and a second configuration signal.

[0024] In an embodiment, when the ratio between the high and low levels of the second configuration signal is not 1:1, the data signal may sequentially include a row start signal, a first inverted signal, an inverted row start signal, a second inverted signal, a first configuration signal, a second configuration signal, a third inverted signal, a second inverted configuration signal, and a fourth inverted signal.

[0025] In an embodiment, the data transmission circuit may further include a first capacitor disposed between the transmitter and the first transmission line, a second capacitor disposed between the receiver and the first transmission line, a third capacitor disposed between the transmitter and the second transmission line, and a fourth capacitor disposed between the receiver and the second transmission line.

[0026] In an embodiment of a display device according to the present invention, the display device includes a display panel, a drive controller, a data driver, and a data transmission circuit. The display panel is configured to display an image based on a data signal. The drive controller is configured to generate a data signal based on input image data. The data driver is configured to convert the data signal into a data voltage and output the data voltage to the display panel. The data transmission circuit includes a transmitter configured to transmit a data signal, a receiver configured to receive a data signal, a first transmission line connected between the transmitter and the receiver, and a second transmission line connected between the transmitter and the receiver. The data signal includes a line start signal, a configuration signal, a pixel signal, and a horizontal blanking signal. The data signal further includes at least one of an inverted line start signal and an inverted configuration signal, wherein the inverted line start signal is an inverted version of the line start signal, and the inverted configuration signal is an inverted version of the configuration signal.

[0027] In an embodiment, the data signal may sequentially include a row start signal, a configuration signal, a first inverted signal, an inverted row start signal, an inverted configuration signal, and a second inverted signal.

[0028] In an embodiment, the transmitter may be configured to further transmit an inverted detection signal to the receiver. The inverted detection signal may change from a first level to a second level overlapping with a first inverted signal, and change from a second level to a first level overlapping with a second inverted signal.

[0029] According to the data transmission circuit and the display device, an inverted version of at least one of the row start signal and the configuration signal can be inserted, allowing active control over the ratio between the high and low levels of the data signal transmitted through the data transmission circuit. Therefore, the input common-mode voltage of the data transmission circuit can be maintained within a target range.

[0030] Because the input common-mode voltage is kept within the target range, the receiver circuitry does not need to be damaged, errors do not need to occur in the signal received by the receiver, and the signal transmission quality does not need to be degraded.

[0031] Therefore, the stability and reliability of data transmission circuits and display devices can be improved. Attached Figure Description

[0032] The above and other embodiments of the inventive concept will become more apparent from the detailed description of the inventive concept with reference to the accompanying drawings, in which:

[0033] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention;

[0034] Figure 2 It is shown Figure 1 Circuit diagram of the data transmission circuit of the display device;

[0035] Figure 3 It is shown that Figure 2 A conceptual diagram illustrating an example of how the input common-mode voltage of a data transmission circuit varies according to the data signal;

[0036] Figure 4 It is shown Figure 2 The circuit diagram of the data transmission circuit, including the transmitting voltage, receiving voltage, and input common-mode voltage;

[0037] Figure 5 It shows through Figure 2 A conceptual diagram of the first signal transmitted by the data transmission circuit;

[0038] Figure 6 It shows through Figure 2 A conceptual diagram of the second signal transmitted by the data transmission circuit;

[0039] Figure 7 It is shown Figure 6 A conceptual diagram illustrating examples of the row start signal and configuration signal of the second signal;

[0040] Figure 8 It is shown Figure 6 A conceptual diagram illustrating examples of the inverted row start signal and inverted configuration signal of the second signal;

[0041] Figure 9 This is a conceptual diagram illustrating a third signal transmitted by a data transmission circuit of a display device according to an embodiment of the present invention;

[0042] Figure 10 This is a conceptual diagram illustrating a fourth signal transmitted by a data transmission circuit of a display device according to an embodiment of the present invention; and

[0043] Figure 11 This is a conceptual diagram illustrating a fifth signal transmitted by a data transmission circuit of a display device according to an embodiment of the present invention. Detailed Implementation

[0044] The embodiments of the present invention will be explained in detail below with reference to the accompanying drawings.

[0045] Figure 1 This is a block diagram illustrating a display device 101 according to an embodiment of the concept of the present invention.

[0046] refer to Figure 1 The display device 101 includes a display panel 100 and a display panel driver. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500. One or more of the drive controller 200, the gate driver 300, the gamma reference voltage generator 400, and the data driver 500 may be integrally formed with and / or formed together with the display panel 100.

[0047] For example, the display panel 100 may include a gate driver 300. For example, a drive controller 200 and a data driver 500 may be integrally formed. For example, a drive controller 200, a gamma reference voltage generator 400, and a data driver 500 may be integrally formed. A drive module that includes at least the integrally formed drive controller 200 and data driver 500 may be referred to as a timing controller embedded data driver (TED).

[0048] The display panel 100 has a display area AA on which an image is displayed and a peripheral area PA adjacent to the display area AA.

[0049] The display panel 100 includes multiple gate lines GL, multiple data lines DL, and multiple pixels P connected to the gate lines GL and the data lines DL. The gate lines GL extend in a first direction D1, and the data lines DL extend in a second direction D2 intersecting the first direction D1.

[0050] The drive controller 200 receives input image data IMG and input control signal CONT from an external device. The input image data IMG may include red, green, and blue image data. The input image data IMG may also include white image data. The input image data IMG may also include magenta, yellow, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0051] The drive controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0052] The drive controller 200 generates a first control signal CONT1 based on the input control signal CONT for controlling the operation of the gate driver 300, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may further include a vertical start signal and a gate clock signal.

[0053] The drive controller 200 generates a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver 500, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0054] The drive controller 200 generates a data signal DATA based on the input image data IMG. The drive controller 200 outputs the data signal DATA to the data driver 500.

[0055] The drive controller 200 generates a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and outputs the third control signal CONT3 to the gamma reference voltage generator 400.

[0056] The gate driver 300 generates a gate signal for driving the gate line GL in response to a first control signal CONT1 received from the drive controller 200. The gate driver 300 outputs the gate signal to the gate line GL. For example, the gate driver 300 may sequentially output the gate signal to the gate line GL. For example, the gate driver 300 may be mounted on the peripheral area PA of the display panel 100. For example, the gate driver 300 may be integrated into the peripheral area PA of the display panel 100.

[0057] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA.

[0058] In an embodiment, the gamma reference voltage generator 400 may be located in the drive controller 200 or in the data driver 500.

[0059] The data driver 500 receives a second control signal CONT2 and a data signal DATA from the drive controller 200, and receives a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 uses the gamma reference voltage VGREF to convert the data signal DATA into a data voltage of analog type. The data driver 500 outputs the data voltage to the data line DL.

[0060] Figure 2 It is shown Figure 1 The circuit diagram of the data transmission circuit 102 of the display device 101.

[0061] refer to Figure 1 and Figure 2The display device 101 includes a data transmission circuit 102. The data transmission circuit 102 includes a transmitter (TX) 10 for transmitting data signal DATA and a receiver (RX) 20 for receiving data signal DATA.

[0062] For example, transmitter 10 may be included in drive controller 200. Receiver 20 may be included in data driver 500.

[0063] The data transmission circuit 102 includes a first transmission line TL1 connected between the transmitter 10 and the receiver 20, and a second transmission line TL2 connected between the transmitter 10 and the receiver 20. For example, the first transmission line TL1 and the second transmission line TL2 can transmit a data signal DATA in differential mode. The first transmission line TL1 can be a positive signal transmission line. The second transmission line TL2 can be a negative signal transmission line.

[0064] For example, the data transmission circuit 102 may further include a first capacitor C1 disposed between the transmitter 10 and the first transmission line TL1, a second capacitor C2 disposed between the receiver 20 and the first transmission line TL1, a third capacitor C3 disposed between the transmitter 10 and the second transmission line TL2, and a fourth capacitor C4 disposed between the receiver 20 and the second transmission line TL2.

[0065] The data transmission circuit 102 may include first to fourth capacitors C1, C2, C3, and C4 to induce AC coupling in the data signal DATA. When AC coupling is induced, the DC component of the data signal DATA is removed, thereby improving the transmission stability of the data signal DATA.

[0066] Figure 3 It is shown that Figure 2 A conceptual diagram of example 103 showing how the input common-mode voltage of the data transmission circuit 102 varies according to the data signal DATA. Figure 4 It is shown Figure 2 The circuit diagram of the data transmission circuit 102 and the circuit 104 having the transmission voltage VTX, the reception voltage VRX and the input common-mode voltage VICM.

[0067] exist Figure 3 In this context, the data signal DATA is a digital signal. The data signal DATA has either a high or low voltage level. Figure 3 For example, during a time period 1T, the data signal DATA may consist of only a high level, except for the header HD.

[0068] When the data signal DATA is as follows Figure 3The diagram shows that, when the voltage level is high, the input common-mode voltage VICM of the positive voltage VP transmitted through the first transmission line TL1 can gradually increase from the ideal first voltage level VICMP1 to a second voltage level VICMP2 that is greater than the first voltage level VICMP1.

[0069] When the data signal DATA is as follows Figure 3 The diagram shows that, when the voltage level is high, the input common-mode voltage VICM of the negative voltage VN transmitted via the second transmission line TL2 can be reduced from the ideal third voltage level VICMN1 to a fourth voltage level VICMN2, which is lower than the third voltage level VICMN1.

[0070] When the input common-mode voltage VICM exceeds the ideal level, the circuitry of receiver 20 may be damaged, or errors may occur in the signal received by receiver 20.

[0071] like Figure 4 As shown, when VTX is the transmit voltage of transmitter 10, VRX is the receive voltage of receiver 20, Z1 is the impedance of AC coupling capacitor, and Z2 is the impedance of terminating resistor, the input common-mode voltage VICM can be expressed as Equation 1 below.

[0072] [Equation 1]

[0073] VICM=(VTX-VRX)*(Z2 / Z1+Z2)

[0074] The impedance Z1 of the AC coupling capacitor varies according to the frequency and the ratio between the high and low levels of the data signal DATA. Additionally, the input common-mode voltage VICM varies according to the ratio between the high and low levels of the data signal DATA.

[0075] like Figure 3 As shown, when the ratio of high level to low level is not 1:1, the input common-mode voltage VICM can be increased or decreased from the ideal value.

[0076] In an embodiment, the display panel driver includes: a drive controller 200; a data driver 500; a data transmission circuit (102, 104) connected between the drive controller and the data driver; a transmitter 10 of the data transmission circuit disposed in the drive controller; a receiver 20 of the data transmission circuit disposed in the data driver; a first transmission line TL1 of the data transmission circuit disposed between the transmitter and the receiver; a second transmission line TL2 of the data transmission circuit disposed between the transmitter and the receiver; a first transmitter voltage (VTX) terminal of the first transmission line disposed in the transmitter; a first receiver voltage (VRX) terminal of the first transmission line disposed in the receiver; and a series connection to the... A first capacitor (Z1, C1) and a first resistor (Z2) are located between a transmitter voltage terminal and a first receiver voltage terminal; a first input common-mode voltage (VICM, VICMP1) terminal is located between the first capacitor and the first resistor; a second transmitter voltage (VTX) terminal is located in the transmitter of a second transmission line; a second receiver voltage (VRX) terminal is located in the receiver of a second transmission line; a second capacitor (Z1, C3) and a second resistor (Z2) are connected in series between the second transmitter voltage terminal and the second receiver voltage terminal; and a second input common-mode voltage (VICM, VICMP1) terminal is located between the second capacitor and the second resistor.

[0077] In an embodiment, the display panel driver further includes: a third capacitor (Z1, C2) connected between a first resistor and a first receiver voltage terminal; a third input common-mode voltage (VICM, VICMP2) terminal disposed between the first resistor and the third capacitor; a fourth capacitor (Z1, C4) connected between a second resistor and a second receiver voltage terminal; and a fourth input common-mode voltage (VICM, VICMP2) terminal disposed between the second resistor and the fourth capacitor.

[0078] In an embodiment, the display panel driver further includes: a third resistor (Z2) disposed between the third capacitor and the first receiver voltage terminal; and a fourth resistor (Z2) disposed between the fourth capacitor and the second receiver voltage terminal.

[0079] In an embodiment of the display panel driver, the drive controller 200 and the data driver 500 are integrated to form a timing controller embedded data driver (TED).

[0080] In an embodiment of the display panel driver, at least one of the first capacitor (Z1, C1), the second capacitor (Z1, C3), the first resistor (Z2), and the second resistor (Z2) has a variable impedance.

[0081] Figure 5 It shows through Figure 2 A conceptual diagram of the first signal 105 transmitted by the data transmission circuit 102.

[0082] refer to Figures 1 to 5 The data signal DATA transmitted by the data transmission circuit 102 includes a row start signal SOL, a configuration signal CONFIG, a pixel signal PIXEL DATA, and a horizontal blanking signal HBP. The row start signal SOL indicates the start of the horizontal row data of the display panel 100. The configuration signal CONFIG indicates the configuration value corresponding to the horizontal row. The pixel signal PIXEL DATA indicates the pixel data corresponding to the horizontal row. The horizontal blanking signal HBP indicates the blanking of the horizontal row.

[0083] By using scrambling, the ratio between high and low levels in the pixel signal PIXEL DATA can be 1:1. Additionally, the horizontal blanking signal HBP can have a data mode with a 1:1 ratio between high and low levels.

[0084] For reference Figure 3 As explained, when the ratio between the high and low levels of the line start signal SOL or the configuration signal CONFIG is not 1:1, and the line start signal SOL or the configuration signal CONFIG is transmitted through the data transmission circuit 102, the input common-mode voltage VICM can rise or fall from the ideal value, which may damage the receiver 20 or cause errors in the signal received by the receiver 20.

[0085] Figure 6 It shows through Figure 2 A conceptual diagram of the second signal 106 transmitted by the data transmission circuit 102. Figure 7 It is shown Figure 6 The second signal 106 is a conceptual diagram of the row start signal SOL and the configuration signal CONFIG, as shown in Example 107. Figure 8 It is shown Figure 6 A conceptual diagram of example 108 of the second signal 106, the inverted row start signal ISOL, and the inverted configuration signal ICONFIG.

[0086] refer to Figure 6 In this embodiment, the data signal DATA may include at least one of an inverted row start signal ISOL and an inverted configuration signal ICONFIG. The inverted row start signal ISOL is the inverted version of the row start signal SOL, and the inverted configuration signal ICONFIG is the inverted version of the configuration signal CONFIG. Although in Figure 6 The diagram shows both the inverted line start signal ISOL and the inverted configuration signal ICONFIG, but one of the inverted line start signal ISOL and the inverted configuration signal ICONFIG is selectively included in the data signal DATA.

[0087] For example, in Figure 7 In this context, the high-level ratio of the row start signal SOL and the configuration signal CONFIG can be much greater than the low-level ratio of the row start signal SOL and the configuration signal CONFIG. When... Figure 7 When the high-level ratio of the start signal SOL and the configuration signal CONFIG shown in the diagram is much greater than the low-level ratio, the positive voltage VP of the input common-mode voltage VICM can rise to a level much higher than the ideal level, and the negative voltage VN of the input common-mode voltage VICM can drop to a level much lower than the ideal level, as shown in the reference. Figure 3 The explanation given.

[0088] Figure 8 The diagram shows the inverted version of the line start signal SOL, the inverted line start signal ISOL, and the inverted version of the configuration signal CONFIG, the inverted configuration signal ICONFIG. Figure 8 The inverted horizontal start signal ISOL and the inverted configuration signal ICONFIG are respectively Figure 7 The inverted versions of the row start signal SOL and configuration signal CONFIG in the inverted version allow the low-level ratio of the inverted row start signal IOL and the inverted configuration signal ICONFIG to be significantly greater than the high-level ratio of the inverted row start signal IOL and the inverted configuration signal ICONFIG.

[0089] exist Figure 6 In this context, the data signal DATA can sequentially include a row start signal SOL, a configuration signal CONFIG, a first inverted signal I1 indicating the transition from a non-inverted signal to an inverted signal, an inverted row start signal ISOL, an inverted configuration signal ICONIG, and a second inverted signal I2 indicating the transition from an inverted signal to a non-inverted signal.

[0090] The data signal DATA includes all of the row start signal SOL, configuration signal CONFIG, inverted row start signal ISOL, and inverted configuration signal ICONFIG, such that the ratio of high level to low level relative to all of the row start signal SOL, configuration signal CONFIG, inverted row start signal ISOL, and inverted configuration signal ICONFIG can be 1:1.

[0091] As a result, when the data signal DATA is transmitted through the data transmission circuit 102, the input common-mode voltage VICM does not need to rise or fall from the ideal value, so that the receiver 20 is not damaged and no errors occur in the signal received by the receiver 20.

[0092] The first inverted signal I1 and the second inverted signal I2 are inserted before and after the inverted horizontal start signal ISOL and the inverted configuration signal ICONFIG, respectively, so that the positions of the inverted horizontal start signal ISOL and the inverted configuration signal ICONFIG can be provided to the receiver 20. The inverted horizontal start signal ISOL and the inverted configuration signal ICONFIG are signals used only to adjust the ratio between the high and low levels of the data signal DATA. The inverted horizontal start signal ISOL and the inverted configuration signal ICONFIG do not contain information necessary for the receiver 20, so that the inverted horizontal start signal ISOL and the inverted configuration signal ICONFIG can be dummy signals.

[0093] Additionally, transmitter 10 can further transmit an inverted detection signal DDS to receiver 20. The inverted detection signal DDS can change from a first level (e.g., low level) to a second level (e.g., high level) overlapping with the first inverted signal I1, and can change from the second level to the first level overlapping with the second inverted signal I2.

[0094] Receiver 20 can detect changes in the level of the inverted detection signal DDS within the signal pattern of the first inverted signal I1, enabling receiver 20 to identify the start of a spurious signal. Additionally, receiver 20 can detect changes in the level of the inverted detection signal DDS within the signal pattern of the second inverted signal I2, enabling receiver 20 to identify the end of a spurious signal.

[0095] For example, the first inverted signal I1 and the second inverted signal I2 may include signal patterns substantially the same as the signal pattern of the horizontal blanking signal HBP. When the level of the inverted detection signal DDS does not change within the signal pattern of the horizontal blanking signal HBP, the receiver 20 can identify the horizontal blanking signal HBP. Conversely, as explained above, when the level of the inverted detection signal DDS changes within the signal pattern of the horizontal blanking signal HBP, the receiver 20 can identify the start and end of the spurious signal.

[0096] Although Figure 6 The data signal DATA includes both the inverted row start signal ISOL and the inverted configuration signal ICONFIG, but the concept of this invention is not limited to these.

[0097] The data signal DATA can selectively include either the inverted row start signal ISOL or the inverted configuration signal ICONFIG, depending on the data pattern of the row start signal SOL and the configuration signal CONFIG.

[0098] For example, when the ratio between the high and low levels of the row start signal SOL is not 1:1, the data signal DATA can include an inverted row start signal ISOL, so that the input common-mode voltage VICM can be compensated for the change in the row start signal SOL.

[0099] For example, when the ratio between the high and low levels of the configuration signal CONFIG is not 1:1, the data signal DATA can include an inverted configuration signal ICONFIG, so that the input common-mode voltage VICM can be compensated for due to the change in the configuration signal CONFIG.

[0100] According to this embodiment, an inverted version of at least one of the row start signal SOL and the configuration signal CONFIG can be inserted, allowing active control over the ratio between the high and low levels of the data signal DATA transmitted through the data transmission circuit 102. Therefore, the input common-mode voltage VICM of the data transmission circuit 102 can be maintained within a target range.

[0101] Since the input common-mode voltage VICM is kept within the target range, the circuitry of receiver 20 does not need to be damaged, and no errors need to occur in the signal received by receiver 20, so that the signal transmission quality does not need to be degraded.

[0102] Therefore, the stability and reliability of data transmission circuits and display devices can be improved.

[0103] Figure 9 This is a conceptual diagram showing a third signal 109 transmitted by a data transmission circuit 102 of a display device 101 according to an embodiment of the present invention.

[0104] Apart from the structure of the data signal, the data transmission circuit and display device according to this embodiment are similar to the reference. Figures 1 to 8 The data transmission circuit and display device explained in the previous embodiment are substantially the same. Therefore, the same reference numerals will be used to refer to the data transmission circuit and display device in the previous embodiment. Figures 1 to 8 The components described in the previous embodiments are the same or similar to those components, and any repeated explanations of the above-mentioned elements may be omitted.

[0105] refer to Figures 1 to 5 and Figures 7 to 9 The display device 101 includes a data transmission circuit 102. The data transmission circuit 102 includes a transmitter (TX) 10 for transmitting data signal DATA and a receiver (RX) 20 for receiving data signal DATA.

[0106] For example, transmitter 10 may be included in drive controller 200. Receiver 20 may be included in data driver 500.

[0107] The data transmission circuit 102 includes a first transmission line TL1 connected between the transmitter 10 and the receiver 20, and a second transmission line TL2 connected between the transmitter 10 and the receiver 20. For example, the first transmission line TL1 and the second transmission line TL2 can transmit a data signal DATA in differential mode. The first transmission line TL1 can be a positive signal transmission line. The second transmission line TL2 can be a negative signal transmission line.

[0108] The data signal DATA in this embodiment may include at least one of the inverted row start signal ISOL and the inverted configuration signal ICONFIG. The inverted row start signal ISOL is the inverted version of the row start signal SOL, and the inverted configuration signal ICONFIG is the inverted version of the configuration signal CONFIG.

[0109] exist Figure 9 In this context, the data signal DATA may sequentially include a row start signal SOL, a first inverted signal I1 indicating the transition from a non-inverted signal to an inverted signal, an inverted row start signal ISOL, a second inverted signal I2 indicating the transition from an inverted signal to a non-inverted signal, a configuration signal CONFIG, a third inverted signal I3 indicating the transition from a non-inverted signal to an inverted signal, an inverted configuration signal ICONIG, and a fourth inverted signal I4 indicating the transition from an inverted signal to a non-inverted signal.

[0110] The data signal DATA includes all of the row start signal SOL, configuration signal CONFIG, inverted row start signal ISOL, and inverted configuration signal ICONFIG, such that the ratio of high level to low level relative to all of the row start signal SOL, configuration signal CONFIG, inverted row start signal ISOL, and inverted configuration signal ICONFIG can be 1:1.

[0111] In this embodiment, the inverted horizontal start signal ISOL is set after the horizontal start signal SOL, and the inverted configuration signal ICONFIG is set after the configuration signal CONFIG. Therefore, when the input common-mode voltage VICM changes due to the horizontal start signal SOL, the change in the input common-mode voltage VICM can be immediately compensated by the inverted horizontal start signal ISOL. Furthermore, when the input common-mode voltage VICM changes due to the configuration signal CONFIG, the change in the input common-mode voltage VICM can be immediately compensated by the inverted configuration signal ICONFIG. Therefore, compared with... Figure 6 Compared to the previous embodiment, changes in the input common-mode voltage (VICM) can be compensated for more effectively.

[0112] The first inverted signal I1 and the second inverted signal I2 are inserted before and after the inverted line start signal ISOL, respectively, so that the position of the inverted line start signal ISOL can be provided to the receiver 20. Additionally, the third inverted signal I3 and the fourth inverted signal I4 are inserted before and after the inverted configuration signal ICONFIG, respectively, so that the position of the inverted configuration signal ICONFIG can be provided to the receiver 20.

[0113] In addition, transmitter 10 can further transmit the inverted detection signal DDS to receiver 20. The inverted detection signal DDS can change from a first level to a second level overlapping with the first inverted signal I1, can change from a second level to a first level overlapping with the second inverted signal I2, can change from a first level to a second level overlapping with the third inverted signal I3, and can change from a second level to a first level overlapping with the fourth inverted signal I4.

[0114] Receiver 20 can use the first to fourth inverted signals I1 to I4 and the inverted detection signal DDS to identify spurious signals (such as the inverted line start signal ISOL and the inverted configuration signal ICONFIG). For example, the first to fourth inverted signals I1 to I4 may include signal patterns that are substantially the same as the signal pattern of the horizontal blanking signal HBP.

[0115] According to this embodiment, an inverted version of at least one of the row start signal SOL and the configuration signal CONFIG can be inserted, allowing active control over the ratio between the high and low levels of the data signal DATA transmitted through the data transmission circuit 102. Therefore, the input common-mode voltage VICM of the data transmission circuit 102 can be maintained within a target range.

[0116] Since the input common-mode voltage VICM is kept within the target range, the circuitry of receiver 20 does not need to be damaged, errors do not need to occur in the signal received by receiver 20, and the signal transmission quality does not need to be degraded.

[0117] Therefore, the stability and reliability of data transmission circuits and display devices can be improved.

[0118] Figure 10 This is a conceptual diagram illustrating a fourth signal 110 transmitted by a data transmission circuit 102 of a display device 101 according to an embodiment of the present invention.

[0119] Apart from the structure of the data signal, the data transmission circuit and display device according to this embodiment are similar to the reference. Figures 1 to 8 The data transmission circuit and display device explained in the previous embodiment are substantially the same. Therefore, the same reference numerals will be used to refer to the data transmission circuit and display device in the previous embodiment. Figures 1 to 8The components described in the previous embodiments are the same or similar to those components, and any repeated explanations of the above-mentioned elements may be omitted.

[0120] refer to Figures 1 to 5 , Figure 7 , Figure 8 and Figure 10 The display device 101 includes a data transmission circuit 102. The data transmission circuit 102 includes a transmitter (TX) 10 for transmitting data signal DATA and a receiver (RX) 20 for receiving data signal DATA.

[0121] For example, transmitter 10 may be included in drive controller 200. Receiver 20 may be included in data driver 500.

[0122] The data transmission circuit 102 includes a first transmission line TL1 connected between the transmitter 10 and the receiver 20, and a second transmission line TL2 connected between the transmitter 10 and the receiver 20. For example, the first transmission line TL1 and the second transmission line TL2 can transmit a data signal DATA in differential mode. The first transmission line TL1 can be a positive signal transmission line. The second transmission line TL2 can be a negative signal transmission line.

[0123] The data signal DATA in this embodiment may include at least one of an inverted row start signal ISOL and an inverted configuration signal. The inverted row start signal ISOL is an inverted version of the row start signal SOL, and the inverted configuration signal is an inverted version of the configuration signal.

[0124] exist Figure 10 In this configuration signal, the configuration signal may include a first configuration signal CONFIG1 and a second configuration signal CONFIG2, and the inverted configuration signal may include a first inverted configuration signal ICONFIG1, which is an inverted version of the first configuration signal CONFIG1, and a second inverted configuration signal ICONFIG2, which is an inverted version of the second configuration signal CONFIG2.

[0125] The data signal DATA may sequentially include a row start signal SOL, a first inverted signal I1 indicating the transition from a non-inverted signal to an inverted signal, an inverted row start signal ISOL, a second inverted signal I2 indicating the transition from an inverted signal to a non-inverted signal, a first configuration signal CONFIG1, a third inverted signal I3 indicating the transition from a non-inverted signal to an inverted signal, a first inverted configuration signal ICONIG1, a fourth inverted signal I4 indicating the transition from an inverted signal to a non-inverted signal, a second configuration signal CONFIG2, a fifth inverted signal I5 indicating the transition from a non-inverted signal to an inverted signal, a second inverted configuration signal ICONIG2, and a sixth inverted signal I6 indicating the transition from an inverted signal to a non-inverted signal.

[0126] The data signal DATA includes all of the following: row start signal SOL, first configuration signal CONFIG1 and second configuration signal CONFIG2, inverted row start signal ISOL, and first inverted configuration signal ICONIG1 and second inverted configuration signal ICONIG2, such that the ratio of high level to low level is 1:1 relative to all of the following: row start signal SOL, first configuration signal CONFIG1 and second configuration signal CONFIG2, inverted row start signal ISOL, and first inverted configuration signal ICONIG1 and second inverted configuration signal ICONIG2.

[0127] In this embodiment, the inverted horizontal start signal ISOL is set after the horizontal start signal SOL, the first inverted configuration signal ICONFIG1 is set after the first configuration signal CONFIG1, and the second inverted configuration signal ICONFIG2 is set after the second configuration signal CONFIG2. Therefore, when the input common-mode voltage VICM changes due to the horizontal start signal SOL, the change in the input common-mode voltage VICM can be immediately compensated by the inverted horizontal start signal ISOL. Furthermore, when the input common-mode voltage VICM changes due to the first configuration signal CONFIG1, the change in the input common-mode voltage VICM can be immediately compensated by the first inverted configuration signal ICONFIG1. ​​Additionally, when the input common-mode voltage VICM changes due to the second configuration signal CONFIG2, the change in the input common-mode voltage VICM can be immediately compensated by the second inverted configuration signal ICONFIG2. Therefore, with... Figure 6 and Figure 9 Compared to the previous embodiment, changes in the input common-mode voltage (VICM) can be compensated for more effectively.

[0128] The first inverted signal I1 and the second inverted signal I2 are inserted before and after the inverted horizontal start signal ISOL, respectively, so that the position of the inverted horizontal start signal ISOL can be provided to the receiver 20. Additionally, the third inverted signal I3 and the fourth inverted signal I4 are inserted before and after the first inverted configuration signal ICONFIG1, respectively, so that the position of the first inverted configuration signal ICONFIG1 can be provided to the receiver 20. Furthermore, the fifth inverted signal I5 and the sixth inverted signal I6 are inserted before and after the second inverted configuration signal ICONFIG2, respectively, so that the position of the second inverted configuration signal ICONFIG2 can be provided to the receiver 20.

[0129] Furthermore, the transmitter 10 can further transmit the inverted detection signal DDS to the receiver 20. The inverted detection signal DDS can change from a first level to a second level overlapping with the first inverted signal I1, can change from a second level to a first level overlapping with the second inverted signal I2, can change from a first level to a second level overlapping with the third inverted signal I3, can change from a second level to a first level overlapping with the fourth inverted signal I4, can change from a first level to a second level overlapping with the fifth inverted signal I5, and can change from a second level to a first level overlapping with the sixth inverted signal I6.

[0130] Receiver 20 can use the first to sixth inverted signals I1 to I6 and the inverted detection signal DDS to identify spurious signals (inverted line start signal ISOL, first inverted configuration signal ICONFIG1, and second inverted configuration signal ICONFIG2). For example, the first to sixth inverted signals I1 to I6 may include signal patterns that are substantially the same as the signal pattern of the horizontal blanking signal HBP.

[0131] According to this embodiment, an inverted version of at least one of the row start signal SOL and the first configuration signal CONFIG1 and the second configuration signal CONFIG2 can be inserted, allowing active control over the ratio between the high and low levels of the data signal DATA transmitted through the data transmission circuit 102. Therefore, the input common-mode voltage VICM of the data transmission circuit 102 can be maintained within a target range.

[0132] Since the input common-mode voltage VICM is kept within the target range, the circuitry of receiver 20 does not need to be damaged, errors do not need to occur in the signal received by receiver 20, and the signal transmission quality does not need to be degraded.

[0133] Therefore, the stability and reliability of data transmission circuits and display devices can be improved.

[0134] Figure 11 This is a conceptual diagram showing a fifth signal 111 transmitted by a data transmission circuit 102 of a display device 101 according to an embodiment of the present invention.

[0135] exist Figure 11 In this process, the first inverted configuration signal ICONIG1 and the second inverted configuration signal ICONIG2 can be selectively inserted.

[0136] refer to Figure 10 and Figure 11The configuration signal may include a first configuration signal CONFIG1 and a second configuration signal CONFIG2. The data signal DATA may optionally include one of a first inverted configuration signal ICONFIG1 and a second inverted configuration signal ICONFIG2, wherein the first inverted configuration signal ICONFIG1 is an inverted version of the first configuration signal CONFIG1, and the second inverted configuration signal ICONFIG2 is an inverted version of the second configuration signal CONFIG2.

[0137] For example, when the ratio between the high and low levels of the first configuration signal CONFIG1 is not 1:1, the data signal DATA may sequentially include the row start signal SOL, the first inverted signal I1, the inverted row start signal ISOL, the second inverted signal I2, the first configuration signal CONFIG1, the third inverted signal I3, the first inverted configuration signal ICONFIG1, the fourth inverted signal I4, and the second configuration signal CONFIG2. In this paper, when the ratio between the high and low levels of the second configuration signal CONFIG2 is 1:1, the data signal DATA need not include the second inverted configuration signal ICONFIG2.

[0138] For example, when the ratio between the high and low levels of the second configuration signal CONFIG2 is not 1:1, the data signal DATA can sequentially include the row start signal SOL, the first inverted signal I1, the inverted row start signal ISOL, the second inverted signal I2, the first configuration signal CONFIG1, the second configuration signal CONFIG2, and the third inverted signal (…). Figure 10 The inverted configuration signal ICONFIG2 and the fourth inverted signal (in I5), the second inverted configuration signal ICONFIG2 and the fourth inverted signal ( Figure 10 (I6 in the text). In this paper, when the ratio between the high and low levels of the first configuration signal CONFIG1 is 1:1, the data signal DATA need not include the first inverted configuration signal ICONFIG1.

[0139] According to this embodiment, an inverted version of at least one of the row start signal SOL and the first configuration signal CONFIG1 and the second configuration signal CONFIG2 can be inserted, allowing active control over the ratio between the high and low levels of the data signal DATA transmitted through the data transmission circuit 102. Therefore, the input common-mode voltage VICM of the data transmission circuit 102 can be maintained within a target range.

[0140] Since the input common-mode voltage VICM is kept within the target range, the circuitry of receiver 20 does not need to be damaged, errors do not need to occur in the signal received by receiver 20, and the signal transmission quality does not need to be degraded.

[0141] Therefore, the stability and reliability of data transmission circuits and display devices can be improved.

[0142] According to this embodiment, an inverted version of at least one of the row start signal and the configuration signal can be inserted into the data signal to stabilize the input common-mode voltage.

[0143] The foregoing is illustrative of the inventive concept and should not be construed as limiting it. While embodiments of the inventive concept have been described, those skilled in the art will readily understand that many modifications can be made to the embodiments without substantially departing from the teachings of this disclosure. Therefore, it is intended that all such modifications be included within the scope of the inventive concept as defined in the claims. In the claims, functionally limiting clauses are intended to cover not only structural equivalents but also equivalent structures as described herein. Therefore, it should be understood that the foregoing is illustrative of the inventive concept and should not be construed as limiting the specific embodiments disclosed, and is intended to include modifications to the disclosed embodiments and other embodiments within the scope of the appended claims. The inventive concept is defined by the appended claims, which include equivalents.

Claims

1. A data transmission circuit, comprising: The transmitter is configured to send data signals; The receiver is configured to receive the data signal; A first transmitting line is connected between the transmitter and the receiver; as well as A second transmission line is connected between the transmitter and the receiver. The data signals mentioned above include a row start signal and a configuration signal. The data signal further includes at least one of an inverted row start signal and an inverted configuration signal, wherein the inverted row start signal is an inverted version of the row start signal, and the inverted configuration signal is an inverted version of the configuration signal. The data signals therein sequentially include the row start signal, the configuration signal, the first inverted signal, the inverted row start signal, the inverted configuration signal, and the second inverted signal, and The data signal further includes pixel signals and horizontal blanking signals.

2. The data transmission circuit according to claim 1, The transmitter is configured to further transmit an inverted detection signal to the receiver, and The inverting detection signal changes from a first level to a second level overlapping with the first inverting signal, and changes from the second level to the first level overlapping with the second inverting signal.

3. The data transmission circuit according to claim 1, The first inverted signal and the second inverted signal include the same signal pattern as the horizontal blanking signal.

4. A data transmission circuit, comprising: The transmitter is configured to send data signals; The receiver is configured to receive the data signal; A first transmitting line is connected between the transmitter and the receiver; as well as A second transmission line is connected between the transmitter and the receiver. The data signals mentioned above include a row start signal and a configuration signal. The data signal further includes at least one of an inverted row start signal and an inverted configuration signal, wherein the inverted row start signal is an inverted version of the row start signal, and the inverted configuration signal is an inverted version of the configuration signal. The data signals therein sequentially include the row start signal, the first inverted signal, the inverted row start signal, the second inverted signal, the configuration signal, the third inverted signal, the inverted configuration signal, and the fourth inverted signal. The data signal further includes pixel signals and horizontal blanking signals.

5. The data transmission circuit according to claim 4, The transmitter is configured to further transmit an inverted detection signal to the receiver, and The inverting detection signal changes from a first level to a second level overlapping with the first inverting signal, changes from a second level to a first level overlapping with the second inverting signal, changes from a first level to a second level overlapping with the third inverting signal, and changes from a second level to a first level overlapping with the fourth inverting signal.

6. The data transmission circuit according to claim 4, The first inverted signal, the second inverted signal, the third inverted signal, and the fourth inverted signal include signal patterns that are the same as the signal patterns of the horizontal blanking signal.

7. The data transmission circuit according to claim 1 or 4, wherein the data signal includes the inverted row start signal and the inverted configuration signal respectively according to the data modes of the row start signal and the configuration signal.

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