Display device

Abstract

The present invention discloses a display device, which may include: a display panel including a first image unit and a second image unit; a data driving unit for applying a data voltage to the display panel; a first scan driving unit for applying a write scan signal to the display panel; a second scan driving unit for applying a compensation scan signal and an initialization scan signal to the display panel; and a shielding unit connected to the second scan driving unit and selectively applying the initialization scan signal to the second image unit.

Description

Technical Field

[0001] This invention relates to display devices. Background Technology

[0002] Typically, electronic devices that provide images to users, such as smartphones, digital cameras, laptops, navigation devices, and smart TVs, include display devices for displaying images. The display device generates the image and provides it to the user through a display screen.

[0003] The display device includes a display panel having a plurality of pixels for generating images and a driving unit for driving the pixels. Each pixel includes a light-emitting element, a plurality of transistors connected to the light-emitting element, and at least one capacitor connected to the transistors.

[0004] The display panel may include a motion picture unit that displays moving images when driven at a driving frequency, and a still image unit that displays still images. The motion picture unit may continuously receive updated images during the driving frequency period. The still image unit may retain the initially provided image data during the driving frequency period, and thereafter, it may not receive image signals. Summary of the Invention

[0005] The object of the present invention is to provide a display device in which the pixels of the moving image section adjacent to the static image section can be properly compensated.

[0006] A display device according to an embodiment of the present invention may include: a display panel including a first image portion and a second image portion; a data driving portion for applying a data voltage to the display panel; a first scan driving portion for applying a write scan signal to the display panel; a second scan driving portion for applying a compensation scan signal and an initialization scan signal to the display panel; and a shielding portion connected to the second scan driving portion and selectively applying the initialization scan signal to the second image portion.

[0007] A display device according to an embodiment of the present invention may include: a display panel including a first image portion having pixels in first to (i-1)th rows and a second image portion having pixels in i to mth rows; a data driving unit applying a data voltage to the display panel; a first scan driving unit applying a write scan signal to the display panel; a second scan driving unit applying a compensation scan signal and an initialization scan signal to the display panel; and a shielding unit connected to the second scan driving unit. The second scan driving unit may include m+c compensation-initialization stages that output the compensation scan signal and the initialization scan signal. The shielding unit may include a plurality of shielding circuits connected to the i-th to (i+c-1)-th compensation-initialization stages and selectively outputting the i-th to (i+c-1)-th initialization scan signals output from the i-th to (i+c-1)-th compensation-initialization stages.

[0008] (Invention Effects)

[0009] According to an embodiment of the present invention, a compensation scan signal is applied to the pixels of the moving image portion adjacent to the static image portion, thereby enabling the compensation operation for the pixels of the moving image portion adjacent to the static image portion to be performed normally. Attached Figure Description

[0010] Figure 1 This is a block diagram of a display device according to an embodiment of the present invention.

[0011] Figure 2 It is shown Figure 1 The diagram shows the equivalent circuit of any pixel.

[0012] Figure 3 It is used for driving Figure 2 The timing diagram of the pixel signal is shown in the figure.

[0013] Figure 4 This is a diagram showing the timing of the signals and data voltages applied to the pixels during the k-frame period.

[0014] Figure 5 It is shown Figure 1 The diagram shows the structure of the first scan drive unit of the scan drive unit.

[0015] Figure 6 From Figure 5 The timing diagram of the write scan signal output of the write stage is shown in the figure.

[0016] Figure 7 , Figure 8 as well as Figure 9 It is shown Figure 1 The diagram shows the structure of the second scan drive unit of the scan drive unit.

[0017] Figure 10 It is shown Figure 8 as well as Figure 9 A diagram showing the structure of any of the shielding circuits in the shielding circuit is shown.

[0018] Figure 11 It is used to explain in the first frame Figures 7 to 9 The timing diagram showing the operation of the second scan drive unit and the shielding unit is shown in the figure.

[0019] Figure 12 It is used to illustrate based on Figure 11 The diagram shows the operation of the shielding circuits for the first and second control signals.

[0020] Figure 13 It is used to describe the respective frames from the second to the kth. Figures 7 to 9 The timing diagram showing the operation of the second scan drive unit and the shielding unit is shown in the figure.

[0021] Figure 14 It is used to illustrate based on Figure 13 The diagram shows the operation of the shielding circuits for the first and second control signals.

[0022] Figure 15 It shows based on Figure 13 The diagram shows the output states of the shielding circuits for the first and second control signals.

[0023] Figure 16 This is a diagram showing the structure of the shielding portion according to another embodiment of the present invention.

[0024] Figure 17 This is a diagram illustrating the timing of the first control signal and the second control signal according to another embodiment of the present invention.

[0025] (Explanation of reference numerals in the attached diagram)

[0026] DD: Display device

[0027] SDV: Scan Driver Unit

[0028] SDV1: First Scan Driver Unit

[0029] SDV2: Second Scan Driver

[0030] MP: Shielding section

[0031] MC: Shielding circuit

[0032] SW1: First switching element

[0033] SW2: Second switching element

[0034] GWS1~GWSm: Write scan signal

[0035] GIS1~GISm: Initialize scan signals

[0036] GCS1~GCSm: Compensation scan signal

[0037] S_W1~S_Wm: Write level

[0038] S_CI1~S_CI(m+c): Compensation-Initialization Level Detailed Implementation

[0039] In this specification, when a constituent element (or region, layer, part, etc.) is referred to as being "on", "connected to", or "integrated with" other constituent elements, it means that the constituent element can be directly configured / connected / integrated with other constituent elements, or that a third constituent element can be configured between them.

[0040] The same reference numerals refer to the same constituent elements. Furthermore, in the drawings, the thickness, scale, and dimensions of the constituent elements are enlarged for illustrative purposes.

[0041] "and / or" includes all combinations that can be defined by the relevant composition.

[0042] The terms "first," "second," etc., can be used to describe various constituent elements, but the constituent elements are not limited by the terms. The terms are used only to distinguish one constituent element from others. For example, without departing from the scope of the invention, a first constituent element may be named a second constituent element, and similarly, a second constituent element may be named a first constituent element. Singular expressions include plural expressions unless explicitly stated otherwise in the context.

[0043] In addition, terms such as "lower," "lower side," "upper," and "upper side" are used to describe the relational relationships of the structures shown in the accompanying drawings. These terms are relative concepts and are explained based on the directions indicated in the accompanying drawings.

[0044] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, terms such as those defined in commonly used dictionaries shall be interpreted as having the same meaning in the context of the relevant art, provided they are not interpreted as having an ideal or overly figurative meaning, and are expressly defined herein.

[0045] Terms such as “including” or “having” should be understood as indicating the presence of features, numbers, steps, operations, constituent elements, components, or combinations thereof as described in the specification, and do not preclude the existence or additional possibilities of one or more other features, numbers, steps, operations, constituent elements, components, or combinations thereof.

[0046] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0047] Figure 1 This is a block diagram of a display device according to an embodiment of the present invention.

[0048] Reference Figure 1 The display device DD may include a display panel DP, a scan driver SDV, a data driver DDV, an emission driver EDV, and a timing controller T-CON. The display panel DP may include multiple pixels PX, multiple scan lines SL1 to SLm, multiple data lines DL1 to DLn, and multiple emission lines EL1 to ELm. m and n are natural numbers.

[0049] Each of the scan lines SL1 to SLm may include a write scan line, a compensation scan line, and an initialization scan line. The write scan line, compensation scan line, and initialization scan line are shown below. Figure 2 .

[0050] According to an embodiment of the present invention, the display panel DP can be a light-emitting display panel. For example, the display panel DP can be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel can contain organic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel can contain quantum dots and quantum rods, etc. In the embodiments of the present invention, the display panel DP is described as an organic light-emitting display panel.

[0051] The display panel DP may include a dynamic image unit D-IM for displaying dynamic images and a static image unit S-IM for displaying static images. Multiple pixels PX may be provided in each of the dynamic image unit D-IM and the static image unit S-IM. Alternatively, the dynamic image unit D-IM may be defined as a first image unit, and the static image unit S-IM may be defined as a second image unit.

[0052] Pixel PX can be arranged with m rows R1 to Rm and n columns C1 to Cn. Alternatively, the m rows R1 to Rm can correspond to the second direction DR2, and the n columns C1 to Cn can correspond to the first direction DR1.

[0053] The dynamic image unit D-IM may include pixels PX arranged in the first row R1 to the (i-1)th row R(i-1). The static image unit S-IM may include pixels PX arranged in the i-th row Ri to the m-th row Rm. i can be a natural number of 2 or more. Hereinafter, pixels PX arranged in rows R1 to Rm are referred to as pixels PX in rows R1 to Rm.

[0054] Scan lines SL1 to SLm can extend in the second direction DR2 and connect to pixel PX and scan drive unit SDV. Data lines DL1 to DLn can extend in the first direction DR1 and connect to pixel PX and data drive unit DDV. Light emission lines EL1 to ELm can extend in the second direction DR2 and connect to pixel PX and light emission drive unit EDV.

[0055] A first voltage ELVDD and a second voltage ELVSS having a lower level than the first voltage ELVDD can be applied to the display panel DP. The first voltage ELVDD and the second voltage ELVSS can be applied to the pixel PX. Although not shown, the display device DD may also include a voltage generation unit for generating the first voltage ELVDD and the second voltage ELVSS.

[0056] A first initialization voltage Vint1 and a second initialization voltage Vint2 can be applied to the display panel DP. The first initialization voltage Vint1 and the second initialization voltage Vint2 can be applied to the pixel PX. The first initialization voltage Vint1 and the second initialization voltage Vint2 can be generated in the voltage generation unit.

[0057] The timing controller T-CON can receive image signals (RGB) from an external source (e.g., a system board). The timing controller T-CON can convert the RGB data format to match the interface specifications of the data driver unit (DDV) to generate image data (DATA). The timing controller T-CON can then provide the converted image data (DATA) to the data driver unit (DDV).

[0058] The timing controller T-CON can receive control signals CS from an external source (e.g., a system board). The timing controller T-CON can generate and output a first control signal CS1, a second control signal CS2, and a third control signal CS3 in response to the control signal CS.

[0059] Alternatively, the first control signal CS1 can be defined as a scan control signal, the second control signal CS2 as a data control signal, and the third control signal CS3 as a light emission control signal. Alternatively, the first control signal CS1 can be provided to the scan driver unit SDV, the second control signal CS2 to the data driver unit DDV, and the third control signal CS3 to the light emission driver unit EDV.

[0060] The scan drive unit SDV can generate multiple scan signals for supplying to the display panel DP in response to the first control signal CS1. The scan signals can be applied to pixels PX via scan lines SL1 to SLm. The scan signals can be sequentially applied row by row to pixels PX in rows R1 to Rm from the first to the mth row.

[0061] The data driving unit DDV can generate multiple data voltages corresponding to the image data DATA in response to the second control signal CS2. These data voltages can be supplied to the display panel DP. The data voltages can be applied to the pixels PX via data lines DL1 to DLn.

[0062] The light-emitting drive unit EDV can generate multiple light-emitting signals for supplying to the display panel DP in response to the third control signal CS3. The light-emitting signals can be applied to the pixel PX through the light-emitting lines EL1 to ELm.

[0063] A pixel (PX) can receive a data voltage in response to a scan signal. A pixel (PX) can emit light of a brightness corresponding to the data voltage in response to a light emission signal, thereby displaying an image. The emission time of a pixel (PX) can be controlled by the light emission signal.

[0064] Figure 2 It is shown Figure 1 The diagram shows the equivalent circuit of any pixel. Figure 3 It is used for driving Figure 2 The timing diagram of the pixel signal is shown in the figure.

[0065] Illustratively, in Figure 2 The image illustrates, for example, the pixel PXij connected to the i-th scan line SLi, the i-th emission line ELi, and the j-th data line DLj. j is a natural number.

[0066] Reference Figure 2 Pixel PXij may include an OLED light-emitting element, multiple transistors T1 to T7, and a capacitor CAP. The transistors T1 to T7 and the capacitor CAP can control the amount of current flowing in the OLED light-emitting element in response to the data voltage. The OLED light-emitting element can generate light with a predetermined brightness in response to the provided current.

[0067] The i-th scan line SLi may include the i-th write scan line GWi, the i-th compensation scan line GCI, and the i-th initialization scan line GIi. Specifically, the i-th write scan line GWi may receive the i-th write scan signal GWSi, the i-th compensation scan line GCI may receive the i-th compensation scan signal GCSi, and the i-th initialization scan line GIi may receive the i-th initialization scan signal GISi.

[0068] Transistors T1 through T7 may each include a source electrode, a drain electrode, and a gate electrode. Hereinafter, for convenience, either the source electrode or the drain electrode will refer to the first electrode, and the other will be defined as the second electrode. Furthermore, the gate electrode will be defined as the control electrode.

[0069] Transistors T1 to T7 may include the first to the seventh transistors T1 to T7. The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include PMOS transistors. The third transistor T3 and the fourth transistor T4 may include NMOS transistors.

[0070] The first transistor T1 can be defined as a driving transistor, the second transistor T2 can be defined as a switching transistor, and the third transistor T3 can be defined as a compensation transistor.

[0071] The fourth transistor T4 and the seventh transistor T7 can be defined as initialization transistors. The fifth transistor T5 can be defined as a working control transistor, and the sixth transistor T6 can be defined as a light-emitting control transistor.

[0072] An OLED (Organic Light Emitting Device) can be defined as an organic light-emitting element. An OLED can include an anode (AE) and a cathode (CE). The anode (AE) can receive a first voltage (ELVDD) through a sixth transistor (T6), a first transistor (T1), and a fifth transistor (T5). The cathode (CE) can receive a second voltage (ELVSS).

[0073] The first transistor T1 is connected between the fifth transistor T5 and the sixth transistor T6. The first transistor T1 may include a first electrode that receives the first voltage ELVDD through the fifth transistor T5, a second electrode that is connected to the anode AE ​​through the sixth transistor T6, and a control electrode that is connected to the node ND.

[0074] Alternatively, the first electrode of the first transistor T1 can be connected to the fifth transistor T5, and the second electrode of the first transistor T1 can be connected to the sixth transistor T6. The first transistor T1 can control the amount of current flowing in the light-emitting element OLED according to the voltage applied to the control electrode of the first transistor T1.

[0075] The second transistor T2 can be connected between the data line DLj and the first electrode of the first transistor T1. The second transistor T2 may include a first electrode connected to the data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th write scan line GWi.

[0076] The second transistor T2 can be turned on under the i-th write scan signal GWSi applied through the i-th write scan line GWi, thereby electrically connecting the data line DLj and the first electrode of the first transistor T1. The second transistor T2 can perform switching operation to supply the data voltage Vd applied through the data line DLj to the first electrode of the first transistor T1.

[0077] The third transistor T3 can be connected between the second electrode of the first transistor T1 and node ND. The third transistor T3 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to node ND, and a control electrode connected to the i-th compensation scan line GCI.

[0078] The third transistor T3 can be turned on by the i-th compensation scan signal GCSi applied through the i-th compensation scan line GCI, thereby electrically connecting the second electrode and the control electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 and the third transistor T3 can be switched on in diode form.

[0079] The fourth transistor T4 can be connected to node ND. The fourth transistor T4 may include a first electrode connected to node ND, a second electrode to which a first initialization voltage Vint1 is applied, and a control electrode connected to the i-th initialization scan line GIi. The fourth transistor T4 can be turned on by the i-th initialization scan signal GISi applied through the i-th initialization scan line GIi to provide the first initialization voltage Vint1 to node ND.

[0080] The fifth transistor T5 may include a first electrode that receives the first voltage ELVDD, a second electrode that is connected to the first electrode of the first transistor T1, and a control electrode that is connected to the i-th light-emitting line ELi.

[0081] The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode AE, and a control electrode connected to the i-th light-emitting line ELi.

[0082] The fifth transistor T5 and the sixth transistor T6 can be turned on under the application of the i-th emission signal ESi through the i-th emission line ELi. Through the turned-on fifth transistor T5 and sixth transistor T6, the first voltage ELVDD is provided to the light-emitting element OLED, allowing a driving current to flow within the OLED. Therefore, the light-emitting element OLED can emit light.

[0083] The seventh transistor T7 may include a first electrode connected to the anode AE, a second electrode receiving the second initialization voltage Vint2, and a control electrode connected to the (i-1)th write scan line GWi-1. The (i-1)th write scan line GWi-1 can be defined as the write scan line preceding the i-th write scan line GWi.

[0084] The seventh transistor T7 can be turned on by the i-1 write scan signal GWSi-1 applied through the i-1 write scan line GWi-1, thereby providing the second initialization voltage Vint2 to the anode AE ​​of the light-emitting element OLED.

[0085] In another embodiment of the present invention, the seventh transistor T7 may be omitted. In an embodiment of the present invention, the second initialization voltage Vint2 may have the same level as the first initialization voltage Vint1, but is not limited thereto, and may have a different level than the first initialization voltage Vint1.

[0086] The capacitor CAP may include a first electrode that receives a first voltage ELVDD and a second electrode that is connected to node ND. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing in the first transistor T1 can be determined based on the voltage stored in the capacitor CAP.

[0087] The following is for reference Figure 3 The timing diagram illustrates the operation of pixel PXij in more detail.

[0088] Reference Figure 2 as well as Figure 3 The i-th emission signal ESi can have a high level during the non-emission period and a low level during the emission period.

[0089] The activation range of the i-th write scan signal GWSi can be defined as the low level of the i-th write scan signal GWSi. The activation ranges of the i-th compensation scan signal GCSi and the i-th initialization scan signal GISi can be defined as the high level of the i-th compensation scan signal GCSi and the i-th initialization scan signal GISi, respectively.

[0090] For example, the activation interval 4H of the i-th initial scan signal GISi and the activation interval 4H of the i-th compensation scan signal GCSi can be 4 times the activation interval 1H of the i-th write scan signal GWSi.

[0091] After the i-th initialization scan signal GISi is activated, the i-th write scan signal GWSi and the i-th compensation scan signal GCSi can be activated. During the non-light emission period, the i-th initialization scan signal GISi, the i-th write scan signal GWSi, and the i-th compensation scan signal GCSi, which are activated respectively, can be applied to pixel PXij.

[0092] The following descriptions of the operation of each signal applied to the corresponding transistor can represent the operation of the activated signal applied to the transistor.

[0093] The i-th initialization scan signal GISi is applied to the fourth transistor T4, which then turns on. The first initialization voltage Vint1 can be provided to node ND through the fourth transistor T4. Therefore, the first initialization voltage Vint1 is applied to the control electrode of the first transistor T1, and the first transistor T1 can be initialized through the first initialization voltage Vint1.

[0094] Although Figure 3 As not shown in the timing diagram, the (i-1)th write scan signal GWSi-1, which is activated before the i-th write scan signal GWSi, is applied to the seventh transistor T7, and the seventh transistor T7 can be turned on. The second initialization voltage Vint2 is provided to the anode AE ​​through the seventh transistor T7, and the anode AE ​​can be initialized with the second initialization voltage Vint2.

[0095] Subsequently, the i-th write scan signal GWSi is applied to the second transistor T2, which can then be turned on. Additionally, the i-th compensation scan signal GCSi is applied to the third transistor T3, which can then be turned on.

[0096] Therefore, the first transistor T1 and the third transistor T3 can be connected to each other as diodes. In this case, a compensation voltage Vd-Vth, which reduces the threshold voltage Vth of the first transistor T1 from the data voltage Vd supplied through the data line DLj, can be applied to the control electrode of the first transistor T1.

[0097] A first voltage ELVDD and a compensation voltage Vd-Vth can be applied to the first and second electrodes of capacitor CAP, respectively. The capacitor CAP can store a charge corresponding to the difference between the voltage at the first and second electrodes.

[0098] Subsequently, during the light-emitting period, the i-th light-emitting signal ESi is applied to the fifth transistor T5 and the sixth transistor T6 through the i-th light-emitting line ELi, allowing the fifth transistor T5 and the sixth transistor T6 to be turned on. In this case, a drive current Id corresponding to the voltage difference between the voltage of the control electrode of the first transistor T1 and the first voltage ELVDD can be generated. The drive current Id is provided to the light-emitting element OLED through the sixth transistor T6, thereby enabling the light-emitting element OLED to emit light.

[0099] During the light-emitting period, through capacitor CAP, the gate-source voltage Vgs of the first transistor T1 can be defined as the voltage difference between the first voltage ELVDD and the compensation voltage Vd-Vth, as shown in Equation 1 below.

[0100] [Mathematical Expression 1]

[0101] Vg s =ELVDD-(Vd-Vth)

[0102] The current-voltage relationship of the first transistor T1 is the same as that in Equation 2 below. Equation 2 is the current-voltage relationship for a typical transistor.

[0103] [Mathematical Expression 2]

[0104] Id=(1 / 2)μCox(W / L)(Vgs-Vth) 2

[0105] When Equation 1 is substituted into Equation 2, the threshold voltage Vth is eliminated, and the drive current Id can be proportional to the square of the value of the difference between the first voltage ELVDD and the data voltage Vd (ELVDD-Vd)². Therefore, the drive current Id can be determined independently of the threshold voltage Vth of the first transistor T1. This operation can be defined as threshold voltage compensation operation.

[0106] Figure 4 This is a diagram showing the timing of the signals and data voltages applied to the pixels during the k-frame period.

[0107] Reference Figure 4 The vertical start signal Vsync is essentially a signal corresponding to a frame. Synchronously with the vertical start signal Vsync, the write scan signal GWS (1~m), the initial scan signal GIS (1~m), the compensation scan signal GCS (1~m), and the data voltage Vd can be applied to the pixel PX.

[0108] Illustratively, in Figure 4 In the diagram, the written scan signal GWS (1~m), the initialization scan signal GIS (1~m), and the compensation scan signal GCS (1~m) are not shown as follows. Figure 3 Such activation intervals are only shown as the timing applied to rows R1 to Rm from the first to the mth.

[0109] The write scan signal GWS(1~m) may include the first write scan signal GWS1 to the m-th write scan signal GWSm. The initialization scan signal GIS(1~m) may include the first initialization scan signal GIS1 to the m-th initialization scan signal GISm. The compensation scan signal GCS(1~m) may include the first compensation scan signal GCS1 to the m-th compensation scan signal GCSm.

[0110] The pixels PX of the display panel DP can be driven in k frames. In the first frame F1, the write scan signal GWS (1~m), the initialization scan signal GIS (1~m), and the compensation scan signal GCS (1~m) can be applied to the pixels PX of the dynamic image unit D-IM and the static image unit S-IM. In the first frame F1, the data voltage Vd can be applied to the pixels PX of the dynamic image unit D-IM and the static image unit S-IM.

[0111] The write scan signal GWS (1-m) can be applied row by row to the pixels PX in rows R1-Rm from the first to the mth. The initialization scan signal GIS (1-m) can be applied row by row to the pixels PX in rows R1-Rm from the first to the mth. The compensation scan signal GCS (1-m) can be applied row by row to the pixels PX in rows R1-Rm from the first to the mth.

[0112] During the time period F2 to Fk of the second to kth frames, the write scan signal GWS(1 to m) can be applied to the pixels PX of the first to mth rows R1 to Rm. During the time period F2 to Fk of the second to kth frames, the data voltage Vd can be applied to the pixels PX of the motion picture unit D-IM. For example, during the time period F2 to Fk of the second to kth frames, the data voltage Vd can be applied to the pixels PX of the first to (i-1)th rows R1 to R(i-1).

[0113] During the second to kth frames, from F2 to Fk, the data voltage Vd may not be applied to the pixels PX of the still image unit S-IM. For example, during the second to kth frames, from F2 to Fk, the data voltage Vd may not be applied to the pixels PX of rows i to m, Ri to Rm. During the second to kth frames, from F2 to Fk, a reference voltage Vref having a predetermined DC level may be applied to the pixels PX of the still image unit S-IM. Example, the reference voltage Vref may be a voltage corresponding to black brightness.

[0114] During the time period F2 to Fk of the second to kth frames, the initialization scan signal GIS(1 to m) and the compensation scan signal GCS(1 to m) can be applied to the pixel PX of the dynamic image unit D-IM but not to the pixel PX of the static image unit S-IM. For example, during the time period F2 to Fk of the second to kth frames, the initialization scan signal GIS(1 to m) and the compensation scan signal GCS(1 to m) can be applied to the pixel PX of the first to (i-1)th rows R1 to R(i-1) but not to the pixel PX of the i to mth rows Ri to Rm.

[0115] The third transistor T3 and the fourth transistor T4 may include NMOS transistors. NMOS transistors can have smaller power-down leakage current than PMOS transistors.

[0116] When a still image is displayed in the still image unit S-IM, during the period F2 to Fk of the second to kth frames, the third transistor T3 and the fourth transistor T4 can be turned off. The power-off leakage current of the third transistor T3 and the fourth transistor T4 is small, thus reducing the discharge amount of capacitor CAP and making it easier to maintain the charged state of capacitor CAP. Therefore, during the period F2 to Fk of the second to kth frames, the charge in capacitor CAP is more easily maintained, allowing pixel PX to display the still image normally.

[0117] Transistors can exhibit hysteresis characteristics. Based on the hysteresis characteristics of the first transistor T1, the current flowing through the first transistor T1 can vary.

[0118] The hysteresis characteristic can change when the data voltage applied to the source electrode (first electrode) of the first transistor T1 changes between the current frame and the previous frame. When the hysteresis characteristic changes, the gate-source voltage versus source-drain current curve changes; therefore, changes in the hysteresis characteristic may affect brightness.

[0119] In order for the static image unit S-IM to display a static image, the hysteresis characteristics of the first transistor T1 of the pixel PX configured in the static image unit S-IM need to be maintained constant.

[0120] In an embodiment of the present invention, a reference voltage Vref is applied to the source electrode of the first transistor T1 disposed in the still image section S-IM, thereby allowing the first transistor T1 to be in a biased state. In this case, the variation of the hysteresis characteristics of the first transistor T1 used to display the still image is reduced, and the hysteresis characteristics of the first transistor T1 can be maintained more consistently.

[0121] Figure 5 It is shown Figure 1 The diagram shows the structure of the first scan drive unit of the scan drive unit. Figure 6 From Figure 5 The timing diagram of the write scan signal output of the write stage is shown in the figure.

[0122] In the following figures, pixels PX arranged in any row are illustrated as a block and described as pixel PX_R.

[0123] Reference Figure 5 as well as Figure 6 The scan drive unit SDV may include a first scan drive unit SDV1 for generating multiple write scan signals GWS1 to GWSm and applying them to the display panel DP.

[0124] The first scan driver unit SDV1 may include multiple write stages S_W1 to S_Wm and at least one dummy stage D_S. The write stages S_W1 to S_Wm can output multiple write scan signals GWS1 to GWSm. The write scan signals GWS1 to GWSm can be... Figure 4 The write scan signal GWS(1~m) is described in the document. The dummy stage D_S can output the dummy write scan signal GWS0.

[0125] The pixel PX_R in row h can receive the h-th write scan signal output from the h-th write stage and the (h-1)-th write scan signal output from the (h-1)-th write stage. h is a natural number. Alternatively, the h-th write scan signal can be the write scan signal applied to the aforementioned second transistor T2, and the (h-1)-th write scan signal can be the write scan signal applied to the aforementioned seventh transistor T7.

[0126] For example, when h is 3, the pixel PX_R of the third row R3 can receive the application of the third write scan signal GWS3 output from the third write stage S_W3 and the second write scan signal GWS2 output from the second write stage S_W2. Specifically, the third write scan signal GWS3 can be applied to the second transistor T2 of each pixel PX_R in the third row R3, and the second write scan signal GWS2 can be applied to the seventh transistor T7 of each pixel PX_R in the third row R3.

[0127] The h-th write stage can be driven by receiving the h-1 write scan signal output from the (h-1)-th write stage. In this case, the h-1-th write scan signal can be defined as a carry signal. For example, when h is 3, the third write stage S_W3 can be driven by receiving the second write scan signal GWS2 and output the third write scan signal GWS3. Therefore, as Figure 6 As shown, the write scan signals GWS1 to GWSm can be output sequentially.

[0128] The dummy stage D_S can be used to apply a preceding write scan signal to the pixels PX_R of the first row R1. For example, the dummy stage D_S can output a dummy write scan signal GWS0, which is applied to the seventh transistor T7 of each pixel PX_R in the first row R1. The first write stage S_W1 can be driven by receiving the application of the dummy write scan signal GWS0 as a carry signal. The dummy stage D_S can be driven by receiving the application of the start signal STV.

[0129] Figure 7 , Figure 8 as well as Figure 9 It is shown Figure 1 The diagram shows the structure of the second scan drive unit of the scan drive unit.

[0130] Illustratively, Figure 7 The initial section of the second scan drive unit SDV2 is shown. Figure 8 The middle portion of the second scan drive unit SDV2, which is adjacent to the boundary between the dynamic image unit D-IM and the static image unit S-IM, is shown. Figure 9 The end portion of the second scan drive unit SDV2 is shown.

[0131] Reference Figure 7 , Figure 8 as well as Figure 9 The scan drive unit SDV may include a second scan drive unit SDV2 and a shielding unit MP. The second scan drive unit SDV2 can generate compensation scan signals GCS1 to GCSm and initialization scan signals GIS1 to GISm and apply them to the display panel DP.

[0132] The compensation scan signals GCS1 to GCSm can be in Figure 4 The compensated scan signals GCS(1~m) are described in the document. The initial scan signals GIS1~GISm can be in Figure 4 The initial scan signal GIS (1-m) is described in the document.

[0133] The shielding unit MP can be connected to the second scan drive unit SDV2, and selectively apply initialization scan signals GIS1 to GISm to the still image unit S-IM. This operation will be described in detail below.

[0134] The second scan driver unit SDV2 may include m+c compensation-initialization stages S_CI1 to S_CI(m+c) that generate and output compensated scan signals GCS1 to GCSm and initialized scan signals GIS1 to GISm. c is a natural number greater than 2. Hereinafter, the structure of the second scan driver unit SDV2 will be described by setting c to 5 as an example.

[0135] It is possible that the pixels PX_R are arranged in m rows R1~Rm, and the number of compensation-initialization levels S_CI1~S_CI(m+c) is c more than the number of m rows R1~Rm. The reasoning for this is as follows... Figure 11 Timing Figure 1 This is an explanation.

[0136] The first to m initialization scan signals GIS1 to GISm output from the first to m-th compensation-initialization stages S_CI1 to S_CIm can be applied to pixels PX_R in the first to m-th rows R1 to Rm. The first to m compensation scan signals GCS1 to GCSm output from the (1+c) to (m+c)-th compensation-initialization stages S_CI(1+c) to S_CI(m+c) can be applied to pixels PX_R in the first to m-th rows R1 to Rm.

[0137] In essence, the compensation scan signals output by each of the first to m+c compensation-initialization stages S_CI1 to S_CI(m+c) can be used as initialization scan signals. The structure of the compensation scan signal used as the initialization scan signal is described in detail below.

[0138] Reference Figure 7 The compensation scan signals GCSx output from the first to the cth compensation-initialization levels S_CI1 to S_CIc may not be applied to the pixel PX_R. The first to the cth compensation-initialization levels S_CI1 to S_CIc that output unused compensation scan signals GCSx can be defined as dummy levels.

[0139] The compensation scan signal GCSx output from the first compensation-initialization stage S_CI1 can be applied as the first initialization scan signal GIS1 to the pixel PX_R of the first row R1. The compensation scan signal GCSx output from the second compensation-initialization stage S_CI2 can be applied as the second initialization scan signal GIS2 to the pixel PX_R of the second row R2.

[0140] The compensation scan signal GCSx output from the third compensation-initialization stage S_CI3 can be applied as the third initialization scan signal GIS3 to the pixel PX_R of the third row R3. The compensation scan signal GCSx output from the fourth to c-th compensation-initialization stages S_CI4 to S_CIc can be used as the fourth to c-th initialization scan signals GIS4 to GISc.

[0141] The first compensation scan signal GCS1, output from the 1+c compensation-initialization level S_CI(1+c), can be applied to the pixel PX_R of the first row R1. The first compensation scan signal GCS1 can be used as the 1+c initialization scan signal GIS(1+c).

[0142] The second compensation scan signal GCS2, output from the 2+c compensation-initialization stage S_CI(2+c), can be applied to the pixel PX_R of the second row R2. The second compensation scan signal GCS2 can be used as the 2+c initialization scan signal GIS(2+c).

[0143] The third compensation scan signal GCS3, output from the 3+c compensation-initialization level S_CI(3+c), can be applied to the pixel PX_R of the third row R3. The third compensation scan signal GCS3 can be used as the 3+c initialization scan signal GIS(3+c). For example... Figures 7 to 9 As shown, such work can be repeated up to the m+c level S_CI(m+c).

[0144] exist Figure 7 In this process, the first compensation-initialization stage S_CI1 can be driven by receiving the start signal FLM. Additionally, the current compensation-initialization stage can be driven by receiving the compensation scan signal output from the previous compensation-initialization stage.

[0145] For example, the 1+c compensation-initialization stage S_CI(1+c) can be driven by receiving the compensation scan signal GCSx output from the c-th compensation-initialization stage (S_CIc). The 2+c compensation-initialization stage S_CI(2+c) can be driven by receiving the first compensation scan signal GCS1 output from the 1+c compensation-initialization stage S_CI(1+c). The compensation scan signal output from the previous compensation-initialization stage can be defined as a carry signal.

[0146] The following is an explanation. Figure 8 as well as Figure 9 The structure of the second scan drive unit SDV2 and the shielding unit MP shown in the figure is as follows: Figure 8 as well as Figure 9 The accompanying figures are shown only illustratively for a portion of the signals required for explanation.

[0147] Reference Figure 8 as well as Figure 9 The shielding part MP may include multiple shielding circuits MC that are respectively connected to the i-th to m+c-th compensation-initialization stages S_CIi to S_CI(m+c) and selectively output initialization scan signals GISi to GISm.

[0148] The compensation scan signals GCS(ic) to GCSm and the initialization scan signals GISi to GISm output from the compensation-initialization stages S_CIi to S_CI(m+c) from i to m+c can be applied to pixel PX_R through the shielding circuit MC. Additionally, the initialization scan signals GISi to GISm output from the compensation-initialization stages S_CIi to S_CI(m+c) from i to m+c can be selectively applied to pixel PX_R through the shielding circuit MC. The following describes this operation in conjunction with... Figure 11 as well as Figure 13 Timing Figure 1 This is an explanation.

[0149] Reference Figure 8 The i-th compensation scan signal GCS(ic) output from the i-th compensation-initialization level S_CIi can be applied to the pixel PX_R in the i-th row R(ic). The i-th compensation scan signal GCS(ic) can be applied as the i-th initialization scan signal GISi to the pixel PX_R in the i-th row Ri.

[0150] The ic-th compensation scan signal GCS(ic) and the i-th initialization scan signal GISi can be applied to the pixel PX_R of the ic-th row R(ic) and the pixel PX_R of the i-th row Ri respectively through the corresponding shielding circuit MC in the shielding circuit MC.

[0151] The (i+c)th compensation-initialization level S_CI(i+c) can output the i-th compensation scan signal GCSi. The i-th compensation scan signal GCSi can be applied to the pixel PX_R in the i-th row Ri.

[0152] Reference Figure 9 The mc-th compensation scan signal GCS(mc) output from the m-th compensation-initialization level S_CIm can be applied to the pixel PX_R in the mc-th row R(mc). The mc-th compensation scan signal GCS(mc) can be applied as the m-th initialization scan signal GISm to the pixel PX_R in the m-th row Rm.

[0153] The mc-th compensation scan signal GCS(mc) and the m-th initialization scan signal GISm can be applied to the pixel PX_R of the mc-th row R(mc) and the pixel PX_R of the m-th row Rm respectively through the corresponding shielding circuit MC in the shielding circuit MC.

[0154] The m-th compensation scan signal GCSm output from the m+c-th compensation-initialization level S_CI(m+c) can be applied to the pixel PX_R of the m-th row Rm through the corresponding shielding circuit MC in the shielding circuit MC.

[0155] The initialization scan signal GISx output from the compensation-initialization levels S_CI(m+1) to S_CI(m+c) from m+1 to m+c can be omitted from pixel PX_R.

[0156] Reference Figure 8 The (i+c)th compensation-initialization stage S_CI(i+c) can be driven by receiving the (i+c-1)th initialization scan signal GIS(i+c-1) output from the (i+c-1)th compensation-initialization stage S_CI(i+c-1). That is, the (i+c)th compensation-initialization stage S_CI(i+c) receives the (i+c-1)th initialization scan signal GIS(i+c-1) instead of the (i-1)th compensation scan signal GCS(i-1) output from the previous stage, i.e., the (i+c-1)th compensation-initialization stage S_CI(i+c-1).

[0157] In the remaining compensation-initialization levels other than the (i+c)th compensation-initialization level S_CI(i+c), such as in Figure 7 As explained in the document, the current compensation-initialization stage can be driven by receiving the compensation scan signal output from the previous compensation-initialization stage.

[0158] Figure 10 It is shown Figure 8 as well as Figure 9 A diagram showing the structure of any of the shielding circuits in the shielding circuit is shown.

[0159] Illustratively, in Figure 10 The shielding circuit MC connected to the i-th compensation-initialization stage S_CIi is shown in the figure.

[0160] Reference Figure 10 The shielding circuit MC may include a first switching element SW1 connected to the i-th compensation-initialization stage S_CIi and a second switching element SW2 connected to the first switching element SW1. The first switching element SW1 and the second switching element SW2 may include PMOS transistors, but are not limited thereto, and may also include NMOS transistors.

[0161] The first switching element SW1 can respond to the first control signal CTS1 by outputting the i-th compensation scan signal GCS(ic) from the i-th compensation-initialization stage S_CIi as the i-th initialization scan signal GISi. The second switching element SW2 can respond to the second control signal CTS2 by deactivating the i-th initialization scan signal GISi output from the first switching element SW1.

[0162] This can be achieved by having the activated i-th initialization scan signal GISi be at a high level, and the deactivated i-th initialization scan signal GISi be at a low level. The second switching element SW2 can receive a voltage VGL having a low level for deactivating the i-th initialization scan signal GISi.

[0163] The i-th compensation-initialization stage S_CIi can be connected to the first output terminal OT1 for outputting the ic-th compensation scan signal GCS(ic) and the second output terminal OT2 for outputting the i-th initialization scan signal GISi.

[0164] The first switching element SW1 may include an input electrode (or source electrode) connected to the first output terminal OT1, a control electrode (or gate electrode) receiving the first control signal CTS1, and an output electrode (or drain electrode) connected to the second output terminal OT2. The second switching element SW2 may include an input electrode (or source electrode) connected to the second output terminal OT2, a control electrode (or gate electrode) receiving the second control signal CTS2, and an output electrode (or drain electrode) receiving voltage VGL.

[0165] The first control signal CTS1 and the second control signal CTS2 can have different voltage levels. When the first control signal CTS1 is high, the second control signal CTS2 can be low. Conversely, when the first control signal CTS1 is low, the second control signal CTS2 can be high.

[0166] Figure 11 It is used to explain in the first frame Figures 7 to 9 The timing diagram showing the operation of the second scan drive unit and the shielding unit is shown in the figure. Figure 12 It is used to illustrate based on Figure 11 The diagram shows the operation of the shielding circuits for the first and second control signals.

[0167] The following sections will be explained together as needed. Figures 7 to 9 The second scan drive unit SDV2 and the shielding unit MP are shown in the figure.

[0168] Reference Figures 7 to 9 as well as Figure 11 In the first frame F1, the first to m initialization scan signals GIS1 to GISm output from the first to m compensation-initialization levels S_CI1 to S_CIm can be applied sequentially to the pixels PX_R of the first to m rows R1 to Rm in row unit.

[0169] In the first frame F1, the first to m-th compensation scan signals GCS1 to GCSm output from the compensation-initialization levels S_CI(1+c) to S_CI(m+c) can be applied sequentially to the pixels PX_R of the first to m-th rows R1 to Rm in row units.

[0170] The compensation scan signals and initialization scan signals applied to the same row can be non-overlapping. For example, the first to m-th initialization scan signals GIS1 to GISm can each have an activation interval of 4H. The first to m-th compensation scan signals GCS1 to GCSm can each have an activation interval of 4H.

[0171] In this case, for pixel PX_R to function, it may be required to have m compensation-initialization levels corresponding to m rows R1 to Rm, and 5 additional compensation-initialization levels. For example, c can be set to a value that is 1 added to 4 corresponding to the active interval 4H of 4H. However, it is not limited to this; c can be set to various values ​​according to the active intervals of the compensation scan signals GCS1 to GCSm and the initialization scan signals GIS1 to GISm.

[0172] For example, the first initialization scan signal GIS1 and the first compensation scan signal GCS1 can be obtained from... Figure 7 The first compensation-initialization stage S_CI1 shown outputs a first initialization scan signal GIS1 with an activation interval of 4H of 4H. Afterwards, four compensation-initialization stages can be skipped, from... Figure 7 The output of the 1+c compensation-initialization stage S_CI(1+c) shown in the figure has a first compensation scan signal GCS1 with an activation interval of 4H of 4H.

[0173] In this case, the first compensation scan signal GCS1 can be output by delaying the first initialization scan signal GIS1 by 5 times by 1H. Therefore, the first compensation scan signal GCS1 can be separated from the first initialization scan signal GIS1 by 1H and do not overlap with the first initialization scan signal GIS1. When the compensation scan signal and the initialization scan signal applied to the same row do not overlap with each other, the initialization and compensation operations of pixel PX_R described above can be performed normally.

[0174] The first to m-th initialization scan signals GIS1~GISm can be output sequentially with a 1H delay interval. The first to m-th compensation scan signals GCS1~GCSm can be output sequentially with a 1H delay interval.

[0175] Reference Figure 11 as well as Figure 12In the first frame F1, the first control signal CTS1 may have a low level VL (or a low voltage level), and the second control signal CTS2 may have a high level VH (or a high voltage level). Alternatively, the first control signal CTS1 with a low level VL may be defined as the active state, and the second control signal CTS2 with a high level VH may be defined as the deactivated state.

[0176] During the first frame F1 period, the first switching element SW1 can be turned on in response to the activated first control signal CTS1. During the first frame F1 period, the second switching element SW2 can be turned off in response to the deactivated second control signal CTS2.

[0177] exist Figure 12 In this case, the i-th compensation scan signal GCS(ic) can be output through the first output terminal OT1, and the i-th initialization scan signal GISi can be output through the first switching element SW1 and the second output terminal OT2. In this scenario, Figure 8 as well as Figure 9 In the process, the compensation scan signal and the initialization scan signal output from the i-th to the m+c-th compensation-scan level S_CIi~S_CI(m+c) can be output through the shielding circuit MC.

[0178] Figure 13 It is used to describe the respective frames from the second to the kth. Figures 7 to 9 The timing diagram showing the operation of the second scan drive unit and the shielding unit is shown in the figure. Figure 14 It is used to illustrate based on Figure 13 The diagram shows the operation of the shielding circuits for the first and second control signals. Figure 15 It shows based on Figure 13 The diagram shows the output states of the shielding circuits for the first and second control signals.

[0179] The following sections will be explained together as needed. Figures 7 to 9 The second scan drive unit SDV2 and the shielding unit MP are shown in the figure.

[0180] Reference Figures 7 to 9 as well as Figure 13 In each of the second to the kth frames F2 to Fk, the first to the (i-1)th initialization scan signals GIS1 to GIS(i-1) can be applied to the pixels PX_R in the first to the (i-1)th rows R1 to R(i-1) of the displayed dynamic image. In each of the second to the kth frames F2 to Fk, the first to the (i-1)th compensation scan signals GCS1 to GCS(i-1) can be applied to the pixels PX_R in the first to the (i-1)th rows R1 to R(i-1) of the displayed dynamic image.

[0181] In the second to the kth frames F2 to Fk, the initial scan signals GISi to GISm and the compensation scan signals GCSi to GCSm of the i to mth rows can be omitted from the pixel PX_R of the i to mth rows Ri to Rm of the static image.

[0182] After outputting the (i-1)th initialization scan signal GIS(i-1), the first control signal CTS1 can be deactivated with a high level VH, and the second control signal CTS2 can be activated with a low level VL. For example, at the timing of the activation of the i-th initialization scan signal GISi, the first control signal CTS1 is deactivated, and the second control signal CTS2 is activated.

[0183] However, it is not limited to this, it can also be like this Figure 13 As shown by the dashed lines for the first control signal CTS1 and the second control signal CTS2, before the timing of the activation of the i-th initialization scan signal GISi, the first control signal CTS1 is deactivated and the second control signal CTS2 is activated.

[0184] Reference Figure 8 , Figure 9 , Figure 13 as well as Figure 14 In the second to the kth frames F2 to Fk, the shielding part MP can intercept the i-th to m+c initialization scan signals GISi to GISm and GISx output by the i-th to m+c compensation-initialization levels S_CIi to S_CI(m+c).

[0185] For example, such as Figure 14 As shown, during the second to kth frames F2 to Fk period, the first switching element SW1 can be turned off in response to the deactivation first control signal CTS1. During the second to kth frames F2 to Fk period, the second switching element SW2 can be turned on in response to the activation second control signal CTS2.

[0186] The conducting second switching element SW2 can pull down the i-th initialization scan signal GISi to a low-level voltage VGL. The shielding circuit MC can pull down the i-th to m+c-th initialization scan signals GISi~GISm, GISx to a low-level voltage VGL.

[0187] Therefore, during the time period F2 to Fk of the second to kth frames, the initialization scan signals GISi to GISm of the i to mth frames are deactivated, so the initialization scan signals GISi to GISm of the i to mth frames can be omitted from the static image unit S-IM.

[0188] Reference Figure 8 , Figure 13 as well as Figure 14The shielding part MP can apply the compensation scan signals GCS(ic) to GCS(i-1) output from the compensation-initialization levels S_CIi to S_CI(i+c-1) from the i to the i+c-1th to the pixels PX_R of the rows R(ic) to R(i-1).

[0189] The shielding circuit MC connected to the compensation-initialization levels S_CIi to S_CI(i+c-1) from i to i+c-1 can apply the compensation scan signals GCS(ic) to GCS(i-1) from ic to i-1 to the pixels PX_R in rows R(ic) to R(i-1).

[0190] When the shielding part MP is not used, in order to prevent the i-th to m-th initialization scan signals GISi to GISm from being applied to the pixel PX_R, the i-th to m+c-th compensation-initialization levels S_CIi to S_CI(m+c) can be forcibly turned off. In this case, since the i-th to i+c-1-th compensation-initialization levels S_CIi to S_CI(i+c-1) are turned off, the ic-th to i-1-th compensation scan signals GCS(ic) to GCS(i-1) can be deactivated and not output.

[0191] Since the compensation scan signals GCS(ic) to GCS(i-1) from the icth to the (i-1th)th row are not applied to the pixels PX_R in the R(ic) to R(i-1)th row from the icth to the (i-1th)th row, the compensation work for the pixels PX_R in the R(ic) to R(i-1)th row from the icth to the (i-1th)th row may not be performed.

[0192] However, in the embodiments of the present invention, since the compensation scan signals GCS(ic) to GCS(i-1) from the icth to the (i-1th)th row R(ic) to R(i-1) are applied to the pixels PX_R, compensation work can be performed for the pixels PX_R from the icth to the (i-1th)th row R(ic) to R(i-1).

[0193] As a result, in embodiments of the present invention, a compensation scan signal can be applied to the pixel PX_R of the dynamic image unit D-IM adjacent to the static image unit S-IM, and the compensation operation for the pixel PX_R of the dynamic image unit D-IM adjacent to the static image unit S-IM can be performed normally.

[0194] Reference Figure 13 , Figure 14 as well as Figure 15The OFF flag indicates that the signal is deactivated. The i+c-1th initialization scan signal GIS(i+c-1) output from the i+c-1th compensation-initialization stage S_CI(i+c-1) can be deactivated and turned off by being low.

[0195] The (i+c)th compensation-initialization stage S_CI(i+c) can receive the (i+c-1)th initialization scan signal GIS(i+c-1) output from the (i+c-1)th compensation-initialization stage S_CI(i+c-1). In frames F2 to Fk from the second to the kth, the (i+c)th compensation-initialization stage S_CI(i+c) that receives the deactivated (i+c-1)th initialization scan signal GIS(i+c-1) can be deactivated and cease operation. That is, the (i+c)th compensation scan signal GCSi output from the (i+c)th compensation-initialization stage S_CI(i+c) can be deactivated and cut off.

[0196] The compensation-initialization stages S_CI(i+c) to S_CI(m+c) following the (i+c)th compensation-initialization stage S_CI(i+c+1) each receive the application of the deactivated compensation scan signal from the previous end, and therefore can still be deactivated. Therefore, in the second to the kth frames F2 to Fk, the (i)th to the mth compensation scan signals GCSi to GCSm may not be applied to the still image section S-IM.

[0197] Figure 16 This is a diagram showing the structure of the shielding portion according to another embodiment of the present invention.

[0198] Illustratively, Figure 16 The second scan driver unit SDV2 is shown as being with Figure 8 The corresponding second scan driver unit SDV2. Besides the number of shielding circuits MC used, Figure 16 The structure shown can be substantially the same as Figure 8 The structure shown is the same.

[0199] Reference Figure 16 The shielding section MP may include multiple shielding circuits MC connected to the compensation-initialization levels S_CIi to S_CI(i+c-1) from the i to the i+c-1th. In the second to the kth frames F2 to Fk, the shielding circuit MC can apply the compensation scan signals GCS(ic) to GCS(i-1) from the ic to the i-1th rows R(ic) to R(i-1) to the pixels PX_R.

[0200] In frames F2 to Fk from the second to the kth, the shielding circuit MC can deactivate the initialization scan signals GISi to GIS(i+c-1) output from the compensation-initialization stages S_CIi to S_CI(i+c-1) from the i-th to the i+c-1-th. Therefore, the initialization scan signals GISi to GIS(i+c-1) from the i-th to the i+c-1-th are not applied to the still image unit S-IM.

[0201] As mentioned earlier, the (i+c)th compensation-initialization stage S_CI(i+c) can receive the deactivated (i+c-1)th initialization scan signal GIS(i+c-1). Therefore, the i-th compensation scan signal GCSi output from the (i+c)th compensation-initialization stage S_CI(i+c) can be deactivated and cut off. Furthermore, the (i+c)th initialization scan signal GIS(i+c), output as the i-th compensation scan signal GCSi, can also be deactivated and cut off.

[0202] The (i+c+1)th compensation-initialization stage S_CI(i+c+1) can receive the deactivated i-th compensation scan signal GCSi. Therefore, the (i+1)th compensation scan signal GCS(i+1) and the (i+c+1)th initialization scan signal GIS(i+c+1) output from the (i+c+1)th compensation-initialization stage S_CI(i+c) can also be deactivated and cut off. This process can continue until the final (m+c)th compensation-initialization stage S_CI(m+c).

[0203] Therefore, in the second to the kth frames F2 to Fk, the i to mth initialization scan signals GISi to GISm and the i to mth compensation scan signals GCSi to GCSm may not be applied to the static image section S-IM.

[0204] Figure 17 This is a diagram illustrating the timing of the first control signal and the second control signal according to another embodiment of the present invention.

[0205] Illustratively, Figure 17 and Figure 13 Similarly, the timing of the signal in the second frame is shown.

[0206] Reference Figure 17 The first control signal CTS1 and the second control signal CTS2 can be deactivated and activated after the first frame F1 and before the second frame F2, which displays the static image. For example, the first control signal CTS1 can be deactivated and the second control signal CTS2 can be activated during the blanking interval BNK between the first frame F1 and the second frame F2.

[0207] The shielding circuit MC has the function of cutting off the initialization scan signals GISi to GISm and the compensation scan signals GCSi to GCSm applied to the still image section S-IM from the second frame F2. Therefore, it is acceptable for the levels of the first control signal CTS1 and the second control signal CTS2 to be changed before the start of the second frame F2. The operation of the shielding circuit MC when the first control signal CTS1 is deactivated and the second control signal CTS2 is activated has been described in detail above, so the description is omitted.

[0208] The above description refers to embodiments; however, those skilled in the art will understand that various modifications and alterations can be made to the present invention without departing from the concept and scope of the invention as set forth in the appended claims. Furthermore, the embodiments disclosed herein are not intended to limit the technical concept of the invention, and should be understood as including all technical concepts within the scope of the appended claims and their equivalents within the scope of the present invention.

Claims

1. A display device comprising: a display panel including a first image portion and a second image portion; a data drive portion applying a data voltage to the display panel; a first scan drive portion applying a write scan signal to the display panel; a second scan drive portion applying a compensation scan signal and an initialization scan signal to the display panel; and a shield portion connected to the second scan drive portion and selectively applying the initialization scan signal to the second image portion, the first image portion displaying a dynamic image and the second image portion displaying a static image, the first image portion including first to i-1th rows of pixels and the second image portion including i to mth rows of pixels, m being a natural number and i being a natural number of 2 or more, the second scan drive portion including m+c compensation-initialization stages outputting the compensation scan signal and the initialization scan signal, c being a natural number of 2 or more, the shield portion including a plurality of shield circuits selectively outputting the initialization scan signal connected to i to m+c compensation-initialization stages, respectively.

2. The display device according to claim 1, wherein the pixels of the first image portion and the second image portion are driven in k frames, and in a first frame period, the pixels receive application of the write scan signal, the compensation scan signal, the initialization scan signal, and the data voltage, k being a natural number of 2 or more.

3. The display device according to claim 2, wherein in second to kth frame periods, the write scan signal is applied to the pixels of the first image portion and the second image portion, in the second to kth frame periods, the data voltage is applied to the pixels of the first image portion and a reference voltage is applied to the pixels of the second image portion, in the second to kth frame periods, the compensation scan signal and the initialization scan signal are applied to the pixels of the first image portion and are not applied to the pixels of the second image portion.

4. The display device according to claim 2, wherein the first scan drive portion includes a plurality of write stages outputting the write scan signal in sequence, pixels of an hth row receive application of an hth write scan signal output from an hth write stage and an h-1th write scan signal output from an h-1th write stage, h being a natural number.

5. The display device according to claim 1, wherein in the first frame, first to mth initialization scan signals output from first to mth compensation-initialization stages are applied to pixels of first to mth rows in sequence in row units, and first to mth compensation scan signals output from 1+c to m+c compensation-initialization stages are applied to the pixels of the first to mth rows in sequence in row units.

6. The display device according to claim 1, wherein an i+c compensation-initialization stage applying an i th compensation scan signal to pixels of an i th row is driven by receiving an i+c-1th initialization scan signal output from an i+c-1th compensation-initialization stage. ​ In the compensation-initialization stages other than the i+c-th compensation-initialization stage, the current-stage compensation-initialization stage receives the compensation scan signal output from the previous-stage compensation-initialization stage and is driven.

7. The display device according to claim 1, wherein In the second to k-th frames, the shielding section cuts off the initialization scan signal output from the i-th to m+c-th compensation-initialization stages.

8. The display device according to claim 1, wherein In the second to k-th frames, the shielding section applies the compensation scan signal output from the i-th to i+c-l-th compensation-initialization stages to the i-c-th to i-l-th rows of pixels.

9. The display device according to claim 1, wherein The shielding circuits each include: a first switching element that, in response to a first control signal, outputs, as an initialization scan signal, the compensation scan signal output from the corresponding one of the compensation-initialization stages; and a second switching element that, in response to a second control signal, deactivates the initialization scan signal output from the first switching element.

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