Organic light emitting display device

Abstract

Disclosed is an organic light emitting display device. The organic light emitting display device includes a display panel including a plurality of pixels, and a panel driving portion driving the display panel. Each of the plurality of pixels includes a driving transistor, a switching transistor, a compensation transistor including first and second compensation sub-transistors connected in series between a gate node and a drain of the driving transistor, a storage capacitor, and an organic light emitting diode. The panel driving portion calculates an average representative gray scale of input image data for a plurality of frame intervals, determines a voltage level of a node control voltage based on the average representative gray scale, and supplies the node control voltage to each of the plurality of pixels to control a voltage of a node between the first and second compensation sub-transistors.

Description

Technical Field

[0001] This invention relates to a display device, and more specifically to an organic light-emitting display device. Background Technology

[0002] Each pixel of an organic light-emitting display device can store a data voltage at the gate node using a storage capacitor, and can display an image with a brightness corresponding to the stored data voltage. However, due to leakage current leaking from or into the gate node, the data voltage stored at the gate node may be distorted, and the pixel may not emit light at the desired brightness. In particular, when the organic light-emitting display device is driven at a low frequency (below the normal driving frequency) to drive the display panel, the distortion of the stored data voltage due to the leakage current may be amplified, and the image quality of the organic light-emitting display device may be degraded. Summary of the Invention

[0003] One object of the present invention is to provide an organic light-emitting display device that can reduce the leakage current of pixels.

[0004] However, the problems to be solved by the present invention are not limited to those mentioned above, and various extensions can be realized without departing from the spirit and concept of the present invention.

[0005] To achieve an objective of the present invention, an organic light-emitting display device according to an embodiment of the present invention includes: a display panel including a plurality of pixels; and a panel driving unit for driving the display panel. Each of the plurality of pixels includes: a driving transistor having a gate electrode connected to a gate node; a switching transistor for transmitting a data voltage to the source of the driving transistor; a compensation transistor including a first compensation sub-transistor and a second compensation sub-transistor connected in series between the gate node and the drain of the driving transistor, connecting the diode of the driving transistor; a storage capacitor for storing the data voltage transmitted by the driving transistor connected by the switching transistor and the diode; and an organic light-emitting diode for emitting light based on a driving current generated by the driving transistor. The panel driving unit calculates the average representative grayscale of input image data in a plurality of frame intervals, determines the voltage level of a node control voltage based on the average representative grayscale, and provides the node control voltage to each of the plurality of pixels to control the voltage of the node between the first compensation sub-transistor and the second compensation sub-transistor.

[0006] In one embodiment, at least one of the first compensator transistor and the second compensator transistor may include a lower electrode, and the node control voltage may be a lower electrode voltage applied to the lower electrode.

[0007] In one embodiment, each of the plurality of pixels may further include: a reference transistor that applies a reference voltage to the node between the first compensating sub-transistor and the second compensating sub-transistor, wherein the node control voltage may be the reference voltage.

[0008] In one embodiment, the average representative gray level may be the average of multiple representative gray levels of the input image data in the plurality of frame intervals, and each of the plurality of representative gray levels may be the average gray level of the gray level represented by the input image data in the corresponding frame interval in the plurality of frame intervals.

[0009] In one embodiment, the average representative gray level can be the average of multiple representative gray levels of the input image data in the multiple frame intervals, and each of the multiple representative gray levels can be the median gray level, maximum gray level, or minimum gray level of the gray level represented by the input image data in the corresponding frame interval in the multiple frame intervals.

[0010] In one embodiment, the plurality of frame intervals may include at least one previous frame interval and a current frame interval. The panel driving unit may store the previous frame representative grayscale of the at least one previous frame interval. The panel driving unit may calculate the current frame representative grayscale based on the input image data of the current frame interval, calculate the average representative grayscale by averaging the previous frame representative grayscale and the current frame representative grayscale, and determine the voltage level of the node control voltage in accordance with the average representative grayscale.

[0011] In one embodiment, the panel driving unit may include: a data driver providing the data voltage to each of the plurality of pixels; a gate driver providing a gate signal to each of the plurality of pixels; a power management circuit providing the node control voltage to each of the plurality of pixels; and a controller controlling the data driver, the gate driver, and the power management circuit. The controller may include: a previous grayscale storage block storing a previous frame representative grayscale of at least one previous frame interval; a current grayscale calculation block calculating the current frame representative grayscale based on input image data of the current frame interval; an average grayscale calculation block calculating the average representative grayscale by averaging the previous frame representative grayscale and the current frame representative grayscale; and a voltage level determination block determining the voltage level of the node control voltage to correspond to the average representative grayscale.

[0012] In one embodiment, each of the plurality of pixels may further include: a gate initialization transistor, including a first gate initialization sub-transistor and a second gate initialization sub-transistor connected in series between the gate node and the line of the initialization voltage, in response to a gate initialization signal to apply an initialization voltage to the gate node. At least one of the first and second compensation sub-transistors may include a first lower electrode, and at least one of the first and second gate initialization sub-transistors may include a second lower electrode. The node control voltage may be a lower electrode voltage applied to the first and second lower electrodes.

[0013] In one embodiment, each of the plurality of pixels may further include: a gate initialization transistor that applies an initialization voltage to the drain of the driving transistor in response to a gate initialization signal.

[0014] In one embodiment, each of the plurality of pixels may further include: a gate initialization transistor, including a first gate initialization sub-transistor and a second gate initialization sub-transistor connected in series between the gate node and the line of the initialization voltage, which apply an initialization voltage to the gate node in response to a gate initialization signal; a first reference transistor, which applies the reference voltage to the node between the first compensation sub-transistor and the second compensation transistor; and a second reference transistor, which applies the reference voltage to the node between the first gate initialization sub-transistor and the second gate initialization transistor. The node control voltage may be the reference voltage.

[0015] In one embodiment, the panel driving unit may include: a still image detector, which determines whether the input image data represents a moving image or a still image; if the input image data represents a moving image, it determines the driving mode for the display panel as a moving image mode; and if the input image data represents a still image, it determines the driving mode for the display panel as a still image mode; and a driving frequency determiner, which determines the driving frequency for the display panel as a normal driving frequency in the moving image mode, and determines the driving frequency for the display panel as a low frequency lower than the normal driving frequency in the still image mode.

[0016] In one embodiment, the panel driving unit may provide the node control voltage to each of the plurality of pixels in the still image mode, and the panel driving unit may not provide the node control voltage to each of the plurality of pixels in the moving image mode.

[0017] In one embodiment, the panel driving unit can provide the node control voltage to each of the plurality of pixels in the still image mode and during the transition interval between the still image mode and the moving image mode, and not provide the node control voltage to each of the plurality of pixels in the moving image mode after the transition interval.

[0018] In one embodiment, each of the plurality of pixels may further include: a first light-emitting transistor that connects a power supply voltage line to the source of the driving transistor in response to a light-emitting signal; and a second light-emitting transistor that connects the drain of the driving transistor to the organic light-emitting diode in response to the light-emitting signal.

[0019] In one embodiment, each of the plurality of pixels further includes: a first light-emitting transistor that connects a power supply voltage line to the source of the driving transistor in response to a light-emitting signal; a second light-emitting transistor that connects the drain of the driving transistor to the organic light-emitting diode in response to the light-emitting signal; and an anode initialization transistor that applies the initialization voltage to the organic light-emitting diode in response to a gate bypass signal.

[0020] In the organic light-emitting display device according to the present invention, each pixel may include a first compensating sub-transistor and a second compensating sub-transistor connected in series between the gate node and the drain of the driving transistor. The panel driving section of the organic light-emitting display device can determine the voltage level of the node control voltage based on the average representative grayscale across multiple frame intervals, and can provide the node control voltage to each pixel to control the voltage of the node between the first compensating sub-transistor and the second compensating sub-transistor. Therefore, leakage current to the gate node can be reduced. Furthermore, as the image displayed in the organic light-emitting display device changes, the voltage level of the node control voltage can be gradually changed. Accordingly, the display quality of the organic light-emitting display device can be improved.

[0021] However, the effects of the present invention are not limited to those described above, and various extensions can be achieved without departing from the spirit and concept of the present invention. Attached Figure Description

[0022] Figure 1 This is a block diagram illustrating an organic light-emitting display device according to an embodiment of the present invention.

[0023] Figure 2 This is a diagram illustrating an example of calculating an average representative grayscale and determining the voltage level of a node control voltage based on the average representative grayscale in an organic light-emitting display device according to an embodiment of the present invention.

[0024] Figure 3This is a circuit diagram illustrating the pixels of an organic light-emitting display device according to an embodiment of the present invention.

[0025] Figure 4 This is a cross-sectional view showing an example of a compensation transistor or gate initialization transistor included in a pixel of an organic light-emitting display device according to an embodiment of the present invention.

[0026] Figure 5 This is a timing diagram illustrating an example of the operation of pixels in an organic light-emitting display device according to an embodiment of the present invention.

[0027] Figure 6 This is a circuit diagram illustrating the pixels of an organic light-emitting display device according to another embodiment of the present invention.

[0028] Figure 7 This is a timing diagram illustrating an example of the operation of pixels in an organic light-emitting display device according to another embodiment of the present invention.

[0029] Figure 8 This is a circuit diagram illustrating the pixels of an organic light-emitting display device according to yet another embodiment of the present invention.

[0030] Figure 9 This is a circuit diagram illustrating the pixels of an organic light-emitting display device according to yet another embodiment of the present invention.

[0031] Figure 10 This is a block diagram illustrating an organic light-emitting display device according to another embodiment of the present invention.

[0032] Figure 11 This is a timing diagram illustrating an example of the operation of an organic light-emitting display device according to another embodiment of the present invention.

[0033] Figure 12 This is a diagram illustrating an example of calculating an average representative grayscale and determining the voltage level of a node control voltage based on the average representative grayscale in an organic light-emitting display device according to another embodiment of the present invention.

[0034] Figure 13 This is a block diagram illustrating an electronic device including an organic light-emitting display device according to an embodiment of the present invention.

[0035] Explanation of symbols in the attached drawings:

[0036] 100, 700: Organic light-emitting display devices

[0037] 110, 710: Display panel

[0038] 120, 720: Data drives

[0039] 130, 730: Gate drivers

[0040] 140, 740: Light-emitting drivers

[0041] 150, 750: Power management circuit

[0042] 160, 760: Controller

[0043] 172, 772: Previous grayscale storage blocks

[0044] 174, 774: Current grayscale calculation block

[0045] 176, 776: Average grayscale calculation blocks

[0046] 178, 778: Voltage level determination block

[0047] 780: Still Image Detector

[0048] 790: Drive Frequency Determiner

[0049] 300, 400, 500, 600, PX: pixels

[0050] T1 to T9: Transistors

[0051] CST: Storage Capacitor

[0052] EL: Organic Light Emitting Diode Detailed Implementation

[0053] Preferred embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings, and repeated descriptions of the same constituent elements are omitted.

[0054] Figure 1 This is a block diagram illustrating an organic light-emitting display device according to an embodiment of the present invention. Figure 2 This is a diagram illustrating an example of calculating an average representative grayscale and determining the voltage level of a node control voltage based on the average representative grayscale in an organic light-emitting display device according to an embodiment of the present invention.

[0055] Reference Figure 1An organic light-emitting display device 100 according to an embodiment of the present invention may include a display panel 110 comprising a plurality of pixels PX and a panel driving unit for driving the display panel 110. In one embodiment, the panel driving unit may include: a data driver 120 for providing a data voltage DV to the plurality of pixels PX; a gate driver 130 for providing a gate signal GS to the plurality of pixels PX; a light-emitting driver 140 for providing a light-emitting signal EM to the plurality of pixels PX; a power management circuit 150 for providing a node control voltage VNC to the plurality of pixels PX; and a controller 160 for controlling the data driver 120, the gate driver 130, the light-emitting driver 140, and the power management circuit 150.

[0056] The display panel 110 may include a plurality of pixels PX. In one embodiment, each pixel PX may include: a driving transistor having a gate electrode connected to a gate node; a switching transistor for transmitting a data voltage DV to the source of the driving transistor; a compensation transistor for diode-connecting the driving transistor; a storage capacitor for storing the data voltage DV transmitted from the gate node through the switching transistor and the diode-connected driving transistor; and an organic light-emitting diode for emitting light based on the data voltage DV stored in the gate node and based on the driving current generated by the driving transistor.

[0057] However, in each pixel PX, the data voltage DV stored at the gate node may be distorted due to leakage current leaking from or to the gate node, and the organic light-emitting diode may not emit light at the desired brightness. That is, the leakage current leaking from or to the gate node flows through the compensation transistor connected to the gate node at its source / drain, and the data voltage DV is distorted due to the leakage current of such a compensation transistor. In particular, when the organic light-emitting display device 100 performs low-frequency driving of the display panel 110 at a low frequency lower than the normal driving frequency, the leakage current may deepen the distortion of the data voltage DV stored at the gate node, and the image quality of the organic light-emitting display device 100 may be reduced. However, in each pixel PX of the organic light-emitting display device 100 according to an embodiment of the present invention, the compensation transistor connected to the gate node at its source / drain can be implemented as a dual-transistor or a dual-gate transistor. That is, the compensation transistor may include a first compensation sub-transistor and a second compensation sub-transistor connected in series between the gate node and the drain of the driving transistor. Accordingly, the leakage current from the drain of the driving transistor to the gate node of the compensation transistor can be reduced, and the display quality of the organic light-emitting display device 100 can be improved.

[0058] Data driver 120 can generate a data voltage DV based on the output image data ODAT and data control signal DCTRL received from controller 160, and provide the data voltage DV to multiple pixels PX. In one embodiment, the data control signal DCTRL may include an output data enable signal, a level start signal, and a load signal, but is not limited thereto. In one embodiment, data driver 120 and controller 160 can be implemented as a single integrated circuit, and such integrated circuit may be referred to as a timing controller embedded data driver (TED). In another embodiment, data driver 120 and controller 160 can be implemented as a separate integrated circuit.

[0059] The gate driver 130 can generate a gate signal GS based on a gate control signal GCTRL received from the controller 160, and can sequentially provide the gate signal GS to a plurality of pixels PX on a row-by-row basis. In one embodiment, the gate control signal GCTRL may include a gate start signal and a gate clock signal, but is not limited thereto. Furthermore, according to an embodiment, the gate signal GS can be as follows: Figure 3 , Figure 5 and Figure 8 The diagram shows the gate initialization signal GI, the gate bypass signal GB, and the gate write signal GW, or it can be as follows: Figure 6 , Figure 7 and Figure 9 The signal shown includes a gate initialization signal GI, a gate compensation signal GC, and a gate write signal GW, but is not limited to these. Furthermore, in one embodiment, the gate driver 130 may be integrated or formed in the periphery of the display panel 110. In another embodiment, the gate driver 130 may be implemented as one or more integrated circuits.

[0060] The light-emitting driver 140 can generate a light-emitting signal EM based on a light-emitting control signal EMCTRL received from the controller 160, and can provide the light-emitting signal EM to multiple pixels PX. In one embodiment, the light-emitting signal EM can be provided sequentially to multiple pixels PX in pixel row units. In another embodiment, the light-emitting signal EM can be a global signal provided substantially simultaneously to multiple pixels PX. Furthermore, in one embodiment, the light-emitting driver 140 can be integrated or formed in the periphery of the display panel 110. In another embodiment, the light-emitting driver 140 can be implemented as one or more integrated circuits.

[0061] The power management circuit 150 can be controlled in response to a power control signal PCTRL received from the controller 160, and can generate a first power supply voltage ELVDD, a second power supply voltage ELVSS, an initialization voltage VINT, and / or a node control voltage VNC provided to the display panel 110. In one embodiment, the power control signal PCTRL may include a signal representing a voltage level of the node control voltage VNC, and the power management circuit 150 can generate a node control voltage VNC having the voltage level represented by the signal. In one embodiment, the power management circuit 150 may be implemented as an integrated circuit (e.g., a power management integrated circuit (PMIC)), but is not limited thereto. In another embodiment, the power management circuit 150 may be included in the controller 160 or the data driver 120.

[0062] The controller 160 (e.g., a timing controller (T-CON)) can receive input image data IDAT and control signals CTRL from an external host (e.g., a graphics processing unit (GPU) or a graphics card). In one embodiment, the control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc., but is not limited thereto. The controller 160 can generate output image data ODAT, a data control signal DCTRL, a gate control signal GCTRL, an emission control signal EMCTRL, and a power control signal PCTRL based on the input image data IDAT and the control signal CTRL. It can provide the output image data ODAT and the data control signal DCTRL to the data driver 120 to control the operation of the data driver 120, provide the gate control signal GCTRL to the gate driver 130 to control the gate driver 130, provide the emission control signal EMCTRL to the emission driver 140 to control the emission driver 140, and provide the power control signal PCTRL to the power management circuit 150 to control the power management circuit 150.

[0063] Furthermore, as described above, since the compensation transistor is implemented as both the first and second compensation sub-transistors, the leakage current from the drain of the driving transistor to the compensation transistor at the gate node can be reduced. However, even if the compensation transistor is implemented as both the first and second compensation sub-transistors, the node between the first and second compensation sub-transistors and the signal applied to the first and second compensation sub-transistors (e.g., Figure 3and Figure 8 The gate write signal GW shown is Figure 6 and Figure 9 Parasitic capacitors can also be formed between the lines of the gate compensation signal (GC) shown, and leakage current can flow from the node between the first and second compensating transistors to the gate node. To prevent leakage current caused by such parasitic capacitors, the panel driving section of the organic light-emitting display device 100 according to an embodiment of the present invention can provide a node control voltage VNC to each pixel PX. The node control voltage VNC can control the voltage of the node between the first and second compensating transistors to reduce leakage current caused by the parasitic capacitors. In one embodiment, at least one of the first and second compensating transistors may include a bottom metal layer, and the node control voltage VNC may be a bottom electrode voltage VBML applied to the bottom electrode. In another embodiment, each pixel PX may also include a reference transistor that applies a reference voltage VREF to the node between the first and second compensating transistors, and the node control voltage VNC may be the reference voltage VREF.

[0064] Furthermore, in the organic light-emitting display device 100 according to an embodiment of the present invention, the panel driving unit can minimize the leakage current by determining the voltage level of the node control voltage VNC based on the input image data IDAT. However, in this case, when the image displayed on the display panel 110 changes, that is, when the input image data IDAT of adjacent frame intervals changes, the voltage level of the node control voltage VNC may change drastically, and the display quality of the organic light-emitting display device 100 may decrease. However, in the organic light-emitting display device 100 according to an embodiment of the present invention, the panel driving unit can calculate the average representative grayscale ARG of the input image data IDAT of multiple frame intervals, determine the voltage level of the node control voltage VNC based on the average representative grayscale ARG, and provide the node control voltage VNC having the determined voltage level to each of the multiple pixels PX to control the voltage of the node between the first compensating sub-transistor and the second compensating sub-transistor. Here, the average representative grayscale ARG may be the average of multiple representative grayscales of the input image data IDAT of the multiple frame intervals, and may be referred to as the average on-pixel ratio (OPR), but is not limited thereto. In one embodiment, each of the plurality of representative gray levels may be the average gray level of the gray level represented by the input image data IDAT in the corresponding frame interval of the plurality of frame intervals. In another embodiment, each of the plurality of representative gray levels may be the median gray level, the maximum gray level, or the minimum gray level of the gray level represented by the input image data IDAT in the corresponding frame interval of the plurality of frame intervals, but is not limited thereto.

[0065] In one embodiment, the plurality of frame intervals may include at least one previous frame interval and a current frame interval. The panel driving unit may store the previous frame representative grayscale PFRG of the at least one previous frame interval, calculate the current frame representative grayscale CFRG based on the input image data IDAT of the current frame interval, calculate the average representative grayscale ARG by averaging the previous frame representative grayscale PFRG and the current frame representative grayscale CFRG, determine the voltage level of the node control voltage VNC corresponding to the average representative grayscale ARG, and provide each pixel PX with the determined voltage level of the node control voltage VNC. Accordingly, when the image displayed on the display panel 110 changes, the voltage level of the node control voltage VNC can be gradually changed, and the display quality of the organic light-emitting display device 100 can be improved. In one embodiment, the controller 160 may include a previous grayscale storage block 172, a current grayscale calculation block 174, an average grayscale calculation block 176, and a voltage level determination block 178 to perform such operations.

[0066] The previous grayscale storage block 172 can store one or more previous frame representative grayscale PFRGs for one or more previous frame intervals. The previous frame representative grayscale PFRG for each previous frame interval can be a representative grayscale (e.g., average grayscale, median grayscale, maximum grayscale, minimum grayscale, etc.) of the input image data IDAT of the previous frame interval.

[0067] The current grayscale calculation block 174 can calculate the representative grayscale CFRG of the current frame based on the input image data IDAT of the current frame interval. For example, the current grayscale calculation block 174 can calculate the average grayscale, the median grayscale, the maximum grayscale, or the minimum grayscale represented by the input image data IDAT of the current frame interval to calculate the representative grayscale CFRG of the current frame.

[0068] The average grayscale calculation block 176 can calculate the average representative grayscale ARG by averaging the representative grayscale PFRG of the previous frame and the representative grayscale CFRG of the current frame. For example, the average grayscale calculation block 176 can calculate the average representative grayscale ARG by averaging the four representative grayscale PFRGs of the previous frame intervals and the representative grayscale CFRG of the current frame interval (i.e., the average of five representative grayscales). In one embodiment, the average grayscale calculation block 176 can calculate the average representative grayscale ARG by calculating a weighted average of the representative grayscale PFRGs of the previous frame and the representative grayscale CFRG of the current frame with a relatively high weighting value and the representative grayscale PFRGs of the previous frame with a relatively low weighting value, but it is not limited to this.

[0069] The voltage level determination block 178 can determine the voltage level of the node control voltage VNC to correspond to the average representative grayscale ARG. The controller 160 can generate a power control signal PCTRL representing the determined voltage level of the node control voltage VNC, and the power management circuit 150 can provide each pixel PX with the node control voltage VNC having the determined voltage level in response to the power control signal PCTRL. For example, the node control voltage VNC can be the lower electrode voltage VBML, and when the average representative grayscale ARG represents 0 grayscale, the voltage level determination block 178 can determine the voltage level of the lower electrode voltage VBML to be approximately -7V; when the average representative grayscale ARG represents 255 grayscale, the voltage level determination block 178 can determine the voltage level of the lower electrode voltage VBML to be approximately -9V, and can determine the voltage level of the lower electrode voltage VBML from approximately -9V to approximately -7V, but is not limited to these settings. In another example, the node control voltage VNC can be a reference voltage VREF, and when the average representative grayscale ARG represents 0 grayscale, the voltage level determination block 178 can determine the voltage level of the reference voltage VREF to be about 4V. When the average representative grayscale ARG represents 255 grayscale levels, the voltage level determination block 178 can determine the voltage level of the reference voltage VREF to be about 0V (or about 1V), and determine the voltage level of the reference voltage VREF to be in the range of about 0V to about 4V, but is not limited to this.

[0070] exist Figure 2 An example is shown where the image 200 displayed on the display panel 110 changes from image "A" to image "B". Figure 2 In the example, the input image data IDAT corresponding to image "A" can have approximately 150 representative gray levels RG, and the input image data IDAT corresponding to image "B" can have approximately 100 representative gray levels RG. For example... Figure 2As shown, in the third frame interval FP3, the average grayscale calculation block 176 can calculate the average representative grayscale ARG of approximately 150 by averaging the average of the grayscale PFRG of approximately 150 in the first frame interval FP1, the grayscale CFRG of approximately 150 in the second frame interval FP2, and the grayscale CFRG of approximately 150 in the current frame of the third frame interval FP3. The voltage level determination block 178 can determine the voltage level of the node control voltage VNC as a first voltage level VL1 corresponding to the average representative grayscale ARG of approximately 150. Furthermore, in the fifth frame interval FP5, the average grayscale calculation block 176 can calculate an average representative grayscale ARG of approximately 145 by averaging the two previous frame representative grayscale PFRGs of approximately 150 in the third frame interval FP3 and approximately 150 in the fourth frame interval FP4, and the current frame representative grayscale CFRG of approximately 136 in the fifth frame interval FP5. The voltage level determination block 178 can then determine the voltage level of the node control voltage VNC as a second voltage level VL2 corresponding to the average representative grayscale ARG of approximately 145. In this way, the voltage level determination block 178 can determine the voltage level of the node control voltage VNC as a third voltage level VL3 corresponding to the average representative grayscale ARG of approximately 128 in the sixth frame interval FP6, and can determine the voltage level of the node control voltage VNC as a fourth voltage level VL4 corresponding to the average representative grayscale ARG of approximately 112 in the seventh frame interval FP7, and can determine the voltage level of the node control voltage VNC as a fifth voltage level VL5 corresponding to the average representative grayscale ARG of approximately 100 in the eighth frame interval FP8. Accordingly, even if the image 200 displayed on the display panel 110 changes from image "A" to image "B", the voltage level of the node control voltage VNC can be gradually changed from the first voltage level VL1 to the fifth voltage level VL5, thereby improving the display quality of the organic light-emitting display device 100.

[0071] As described above, in the organic light-emitting display device 100 according to an embodiment of the present invention, each pixel PX may include a first compensating sub-transistor and a second compensating sub-transistor connected in series between the gate node and the drain of the driving transistor. Furthermore, the panel driving unit can determine the voltage level of the node control voltage VNC based on the average representative grayscale ARG of the plurality of frame intervals, and can provide the node control voltage VNC to each pixel PX to control the voltage of the node between the first compensating sub-transistor and the second compensating sub-transistor. Therefore, leakage current to the gate node can be reduced. Furthermore, when the image displayed in the organic light-emitting display device 100 changes, the voltage level of the node control voltage VNC can be gradually changed. Accordingly, the display quality of the organic light-emitting display device 100 can be improved.

[0072] Figure 3 This is a circuit diagram illustrating the pixels of an organic light-emitting display device according to an embodiment of the present invention. Figure 4 This is a cross-sectional view showing an example of a compensation transistor or gate initialization transistor included in a pixel of an organic light-emitting display device according to an embodiment of the present invention. Figure 5 This is a timing diagram illustrating an example of the operation of pixels in an organic light-emitting display device according to an embodiment of the present invention.

[0073] Reference Figure 3 According to an embodiment of the present invention, the pixel 300 of the organic light-emitting display device may include a storage capacitor CST, a driving transistor T1, a switching transistor T2, a compensation transistor T3, a gate initialization transistor T4, a first light-emitting transistor T5, a second light-emitting transistor T6, an anode initialization transistor T7, and an organic light-emitting diode EL.

[0074] The storage capacitor CST can store the data voltage DV transmitted through the switching transistor T2 and the (diode-connected) driving transistor T1. In one embodiment, the storage capacitor CST may have a first electrode connected to a line of a first power supply voltage ELVDD and a second electrode connected to the gate node NG.

[0075] The driving transistor T1 can generate a driving current based on the data voltage DV stored in the storage capacitor CST (i.e., the voltage of the gate node NG). In one embodiment, the driving transistor T1 may have a gate electrode connected to the second electrode of the storage capacitor CST (i.e., the gate node NG), a source connected to the second source / drain of the first light-emitting transistor T5, and a drain connected to the first source / drain of the second light-emitting transistor T6.

[0076] Switching transistor T2 can deliver a data voltage DV to the source of driving transistor T1 in response to a gate write signal GW. Switching transistor T2 can be referred to as a scan transistor. In one embodiment, switching transistor T2 may have a gate electrode for receiving the gate write signal GW, a first source / drain for receiving the data voltage DV, and a second source / drain connected to the source of driving transistor T1.

[0077] The compensation transistor T3 can diode-connect the driving transistor T1 in response to the gate write signal GW. In one embodiment, the compensation transistor T3 may have a gate electrode for receiving the gate write signal GW, a first source / drain (or the second source / drain of the second compensation sub-transistor T3-2) connected to the drain of the driving transistor T1, and a second source / drain (or the first source / drain of the first compensation sub-transistor T3-1) connected to the gate electrode (i.e., gate node NG) of the driving transistor T1. During the application of the gate write signal GW, the data voltage DV transmitted by the switching transistor T2 can be stored in the storage capacitor CST via the driving transistor T1 diode-connected by the compensation transistor T3. Accordingly, the data voltage DV compensated for the threshold voltage of the driving transistor T1 can be stored in the storage capacitor CST.

[0078] The gate initialization transistor T4 can transmit an initialization voltage VINT to the gate node NG in response to the gate initialization signal GI. In one embodiment, the gate initialization transistor T4 may have a gate electrode that receives the gate initialization signal GI, a first source / drain connected to the gate node NG (or the first source / drain of the first gate initialization sub-transistor T4-1), and a second source / drain connected to the line of the initialization voltage VINT (or the second source / drain of the second gate initialization sub-transistor T4-2). During the application of the gate initialization signal GI, the gate initialization transistor T4 can initialize the gate node NG (i.e., the storage capacitor CST and the gate electrode of the drive transistor T1) using the initialization voltage VINT.

[0079] The first light-emitting transistor T5 can connect the line of the first power supply voltage ELVDD to the source of the driving transistor T1 in response to the light-emitting signal EM. In one embodiment, the first light-emitting transistor T5 may include a gate electrode for receiving the light-emitting signal EM, a first source / drain electrode connected to the line of the first power supply voltage ELVDD, and a second source / drain electrode connected to the source of the driving transistor T1.

[0080] The second light-emitting transistor T6 can connect the drain of the driving transistor T1 to the anode of the organic light-emitting diode EL in response to the light-emitting signal EM. In one embodiment, the second light-emitting transistor T6 may include a gate electrode for receiving the light-emitting signal EM, a first source / drain connected to the drain of the driving transistor T1, and a second source / drain connected to the anode of the organic light-emitting diode EL. During the application of the light-emitting signal EM, the first light-emitting transistor T5 and the second light-emitting transistor T6 can be turned on, and a path for the driving current can be formed from the line of the first power supply voltage ELVDD to the line of the second power supply voltage ELVSS.

[0081] An anode initialization transistor T7 can deliver an initialization voltage VINT to the anode of an organic light-emitting diode (OLED) EL in response to a gate bypass signal GB. In one embodiment, the anode initialization transistor T7 may include a gate electrode receiving the gate bypass signal GB, a first source / drain connected to the anode of the OLED EL, and a second source / drain connected to the line of the initialization voltage VINT. During the application of the gate bypass signal GB, the anode initialization transistor T7 can initialize the OLED EL using the initialization voltage VINT.

[0082] An organic light-emitting diode (OLED) EL can emit light based on the drive current generated by a driving transistor T1. In one embodiment, the OLED EL may have an anode connected to the second source / drain of a second light-emitting transistor T6 and a cathode connected to a line of a second power supply voltage ELVSS. During the application of a light-emitting signal EM, the drive current generated by the driving transistor T1 can be provided to the OLED EL, and the OLED EL can emit light based on the drive current.

[0083] Pixel 300 can emit light during the light-emitting period based on the data voltage DV stored at the gate node NG via the storage capacitor CST. However, during the light-emitting period, leakage current from the compensation transistor T3 and the gate initialization transistor T4 may flow to the gate node NG, and the data voltage DV stored at the gate node NG may be distorted. In one embodiment, to reduce the leakage current, each of the compensation transistor T3 and the gate initialization transistor T4, whose source / drain is directly connected to the storage capacitor CST (i.e., the gate node NG), can be implemented as a dual-transistor or a dual-gate transistor. For example, as Figure 3 As shown, the compensation transistor T3 may include a first compensation sub-transistor T3-1 and a second compensation sub-transistor T3-2 connected in series between the gate node NG and the drain of the driving transistor T1, and the gate initialization transistor T4 may include a first gate initialization sub-transistor T4-1 and a second gate initialization sub-transistor T4-2 connected in series between the gate node NG and the line of the initialization voltage VINT. When the compensation transistor T3 includes the first compensation sub-transistor T3-1 and the second compensation sub-transistor T3-2, the leakage current of the compensation transistor T3 between the drain of the driving transistor T1 and the gate node NG can be reduced. Furthermore, when the gate initialization transistor T4 includes the first gate initialization sub-transistor T4-1 and the second gate initialization sub-transistor T4-2, the leakage current of the gate initialization transistor T4 between the line of the initialization voltage VINT and the gate node NG can be reduced.

[0084] However, even if the compensation transistor T3 includes a first compensation sub-transistor T3-1 and a second compensation sub-transistor T3-2, a parasitic capacitance may form between node NT3 between the first compensation sub-transistor T3-1 and the second compensation sub-transistor T3-2 and the line of pixel 300 (e.g., the line of gate write signal GW), and leakage current from node NT3 between the first compensation sub-transistor T3-1 and the second compensation sub-transistor T3-2 to gate node NG may occur. Furthermore, even if the gate initialization transistor T4 includes a first gate initialization sub-transistor T4-1 and a second gate initialization sub-transistor T4-2, a parasitic capacitance may form between node NT4 between the first gate initialization sub-transistor T4-1 and the second gate initialization sub-transistor T4-2 and the line of pixel 300 (e.g., the line of gate initialization signal GI), and leakage current from node NT4 between the first gate initialization sub-transistor T4-1 and the second gate initialization sub-transistor T4-2 to gate node NG may occur. Accordingly, the voltage of the gate node NG may increase, the drive current of the driving transistor T1 may decrease, and the brightness of the organic light-emitting diode EL may decrease.

[0085] In a pixel 300 of an organic light-emitting display device according to an embodiment of the present invention, at least one of the first compensating sub-transistor T3-1 and the second compensating sub-transistor T3-2 may include a first lower electrode BML1, and at least one of the first gate initialization sub-transistor T4-1 and the second gate initialization sub-transistor T4-2 may include a second lower electrode BML2 to reduce voltage distortion at the gate node NG caused by leakage current from the first compensating sub-transistor T3-1 and the first gate initialization sub-transistor T4-1. In one embodiment, each of the first lower electrode BML1 and the second lower electrode BML2 may be referred to as a bottom metal layer (BML). The lower electrode voltage VBML can be applied to the first lower electrode BML1 and the second lower electrode BML2. The lower electrode voltage VBML applied to the first lower electrode BML1 can indirectly control the voltage of node NT3 between the first compensating sub-transistor T3-1 and the second compensating sub-transistor T3-2. The lower electrode voltage VBML applied to the second lower electrode BML2 can indirectly control the voltage of node NT4 between the first gate initialization sub-transistor T4-1 and the second gate initialization sub-transistor T4-2.

[0086] In one embodiment, such as Figure 4As shown, each of the compensation transistor T3 and the gate initialization transistor T4 may include a first source / drain SD1 of the first sub-transistor T3-1 / T4-1, a first gate electrode GAT1 of the first sub-transistor T3-1 / T4-1, a node NT that functions as a second source / drain of the first sub-transistor T3-1 / T4-1 and a first source / drain of the second sub-transistor T3-2 / T4-2, a second gate electrode GAT2 of the second sub-transistor T3-2 / T4-2, a second source / drain SD2 of the second sub-transistor T3-2 / T4-2, and a lower electrode BML disposed below the first gate electrode GAT1 of the first sub-transistor T3-1 / T4-1. For example, the lower electrode BML may be formed on a substrate SUB, such as an organic substrate or a polyimide (PI) substrate, in a manner overlapping the first gate electrode GAT1. In one embodiment, the lower electrode BML may include molybdenum (Mo), but is not limited thereto. In another embodiment, the lower electrode BML may include a low-resistivity, opaque conductive material such as aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), platinum (Pt), tantalum (Ta), etc. A buffer layer BUF for preventing impurities from the substrate SUB can be formed on the lower electrode BML. A first source / drain SD1, a first active region ACT1, a node NT, a second active region ACT2, and a second source / drain SD2 can be formed on the buffer layer BUF. A first gate insulating layer GI1 and a second gate insulating layer GI2 can be formed on the first active region ACT1 and the second active region ACT2. A first gate electrode GAT1 and a second gate electrode GAT2 can be formed on the first gate insulating layer GI1 and the second gate insulating layer GI2. The first gate electrode GAT1 can be formed to overlap with the lower electrode BML. An interlayer insulating layer ILD can be formed on the buffer layer BUF.

[0087] In addition, although Figure 3 The illustration shows an example of a 7T1C structure for pixel 300, which includes seven transistors T1 to T7 and a storage capacitor CST. However, the structure of pixel 300 according to embodiments of the present invention is not limited to this. Figure 3 For example. In one embodiment, such as Figure 3 As shown, the transistors T1 to T7 of pixel 300 can be implemented as PMOS transistors, but are not limited to this. For example, at least one transistor of pixel 300 (e.g., compensation transistor T3 and / or gate initialization transistor T4) can be implemented as an NMOS transistor.

[0088] The following is for reference Figure 3 and Figure 5 An example of the operation of pixel 300 according to an embodiment of the present invention will be described.

[0089] Reference Figure 3 and Figure 5 For each 300-pixel frame interval FP, it can include initialization interval PINT, data writing interval PDW, and light emission interval PEM.

[0090] During the initialization interval PINT, the gate initialization signal GI and the gate bypass signal GB can be applied to pixel 300. Gate initialization transistor T4 is turned on in response to the gate initialization signal GI, and the turned-on gate initialization transistor T4 can initialize the gate node NG (i.e., the gate electrode of the storage capacitor CST and the driving transistor T1) using the initialization voltage VINT. Furthermore, anode initialization transistor T7 is turned on in response to the gate bypass signal GB, and the turned-on anode initialization transistor T7 can initialize the organic light-emitting diode EL using the initialization voltage VINT.

[0091] In the data write interval PDW, a gate write signal GW can be applied to pixel 300. Switching transistor T2 and compensation transistor T3 can be turned on in response to the gate write signal GW. The turned-on switching transistor T2 can transfer the data voltage DV to the source of driving transistor T1, and the turned-on compensation transistor T3 can diode-connect driving transistor T1. Accordingly, the data voltage DV can be transferred to the storage capacitor CST (i.e., gate node NG) through switching transistor T2 and diode-connected driving transistor T1, and the storage capacitor CST can store the data voltage DV compensated for the threshold voltage of driving transistor T1.

[0092] In the light-emitting region PEM, a light-emitting signal EM can be applied to pixel 300. A first light-emitting transistor T5 and a second light-emitting transistor T6 can be turned on in response to the light-emitting signal EM. The turned-on first light-emitting transistor T5 and second light-emitting transistor T6 can form a path for the drive current generated by the drive transistor T1, from the line of the first power supply voltage ELVDD to the line of the second power supply voltage ELVSS. Accordingly, the drive current generated based on the data voltage DV stored in the storage capacitor CST (i.e., the gate node NG) can be provided to the organic light-emitting diode EL, and the organic light-emitting diode EL can emit light based on the drive current.

[0093] Furthermore, during the light-emitting period (PEM), the data voltage DV may be distorted due to leakage current leaking into the storage capacitor CST (i.e., the gate node NG). However, in the pixel 300 according to an embodiment of the present invention, since the compensation transistor T3 is implemented as a first compensation sub-transistor T3-1 and a second compensation sub-transistor T3-2, and the gate initialization transistor T4 is implemented as a first gate initialization sub-transistor T4-1 and a second gate initialization sub-transistor T4-2, the leakage current leaking into the gate node NG can be reduced. Furthermore, in pixel 300 according to an embodiment of the present invention, since the first compensating sub-transistor T3-1 includes a first lower electrode BML1, the first gate initialization sub-transistor T4-1 includes a second lower electrode BML2, and a lower electrode voltage VBML is applied to the first lower electrode BML1 and the second lower electrode BML2, the voltage of node NT3 between the first compensating sub-transistor T3-1 and the second compensating sub-transistor T3-2 and the voltage of node NT4 between the first gate initialization sub-transistor T4-1 and the second gate initialization sub-transistor T4-2 can be controlled, and leakage current to gate node NG can be further reduced. Moreover, the lower electrode voltage VBML applied to the first lower electrode BML1 and the second lower electrode BML2 can have a voltage level corresponding to the average representative grayscale of multiple frame intervals. Accordingly, when the image displayed in the organic light-emitting display device changes, the voltage level of the lower electrode voltage VBML can be gradually changed, and the display quality of the organic light-emitting display device can be improved.

[0094] In addition, although Figure 5 The illustration shows an example of signals EM, GI, GB, and GW applied to pixel 300; however, the signals EM, GI, GB, and GW applied to pixel 300 according to embodiments of the present invention are not limited to those shown in the illustration. Figure 5 Example.

[0095] Figure 6 This is a circuit diagram illustrating pixels of an organic light-emitting display device according to another embodiment of the present invention. Figure 7 This is a timing diagram illustrating an example of the operation of pixels in an organic light-emitting display device according to another embodiment of the present invention.

[0096] Reference Figure 6According to another embodiment of the organic light-emitting display device, the pixel 400 may include a storage capacitor CST, a driving transistor T1, a switching transistor T2, a compensation transistor T3', a gate initialization transistor T4', a first light-emitting transistor T5, a second light-emitting transistor T6, and an organic light-emitting diode EL. Except that the pixel 400 may not include an anode initialization transistor T7, the compensation transistor T3' may receive a gate compensation signal GC, and the first source / drain of the gate initialization transistor T4' is connected outside the drain of the driving transistor T1, replacing the gate node NG. Figure 6 The 400 pixels can have the same Figure 3 The 300 pixels have similar composition and similar operation.

[0097] The compensation transistor T3' can connect the driving transistor T1 diode in response to the gate compensation signal GC. The gate electrode of the compensation transistor T3' can receive the gate compensation signal GC. In one embodiment, the compensation transistor T3' may include a first compensation sub-transistor T3-1' and a second compensation sub-transistor T3-2' connected in series between the gate node NG and the drain of the driving transistor T1. Accordingly, leakage current to the gate node NG can be reduced. Furthermore, in one embodiment, the gate compensation signal GC applied to the gate electrode of the first compensation sub-transistor T3-1' and the gate compensation signal GC applied to the gate electrode of the second compensation sub-transistor T3-2' may have different voltage levels than each other, but is not limited thereto.

[0098] In one embodiment, at least one of the first compensator transistor T3-1' and the second compensator transistor T3-2' may include a first lower electrode BML1. For example, as Figure 6 As shown, the first compensator transistor T3-1' may include a first lower electrode BML1 arranged to overlap with the gate electrode of the first compensator transistor T3-1'. A lower electrode voltage VBML may be applied to the first lower electrode BML1, and the voltage of the node NT3 between the first compensator transistor T3-1' and the second compensator transistor T3-2' may be indirectly controlled by the lower electrode voltage VBML applied to the first lower electrode BML1, thereby further reducing the leakage current to the gate node NG. Furthermore, the lower electrode voltage VBML applied to the first lower electrode BML1 may have a voltage level corresponding to the average representative grayscale of multiple frame intervals. Accordingly, when the image displayed in the organic light-emitting display device changes, the voltage level of the lower electrode voltage VBML may gradually change, thereby improving the display quality of the organic light-emitting display device.

[0099] The gate initialization transistor T4' can deliver an initialization voltage VINT to the drain of the driving transistor T1 in response to the gate initialization signal GI. In one embodiment, the gate initialization transistor T4' may have a gate electrode that receives the gate initialization signal GI, a first source / drain connected to the drain of the driving transistor T1, and a second source / drain connected to the line of the initialization voltage VINT. Additionally, in Figure 6 In pixel 400, since the gate initialization transistor T4' is not directly connected to the gate node NG (i.e., the storage capacitor CST), the gate initialization transistor T4' does not need to be implemented as a dual transistor. The gate initialization transistor T4' applies an initialization voltage VINT to the gate node NG through the compensation transistor T3', thereby initializing the storage capacitor CST and the gate electrode of the driving transistor T1. In one embodiment, the gate initialization transistor T4' can further apply the initialization voltage VINT to the organic light-emitting diode EL through the second light-emitting transistor T6, thereby initializing the organic light-emitting diode EL.

[0100] The following is for reference Figure 6 and Figure 7 An example of the operation of pixel 400 according to an embodiment of the present invention will be described.

[0101] Reference Figure 6 and Figure 7 For each 400-pixel frame interval FP, it can include the initialization interval PINT, the data writing interval PDW, and the light emission interval PEM.

[0102] During the initialization interval PINT, the gate initialization signal GI and the gate compensation signal GC can be applied to pixel 400. The compensation transistor T3' can be turned on in response to the gate compensation signal GC, and the gate initialization transistor T4' can be turned on in response to the gate initialization signal GI. The turned-on compensation transistor T3' and the turned-on gate initialization transistor T4' can initialize the gate node NG (i.e., the storage capacitor CST and the gate electrode of the driving transistor T1) using the initialization voltage VINT. In one embodiment, before the initialization interval PINT, a black data voltage can be applied to the storage capacitor CST, and afterwards, the gate initialization signal GI and the light emission signal EM can be applied to pixel 400. During the application of the gate initialization signal GI and the light emission signal EM, the gate initialization transistor T4' and the second light emission transistor T6 can be turned on, and the turned-on gate initialization transistor T4' and the turned-on second light emission transistor T6 can initialize the organic light-emitting diode EL using the initialization voltage VINT.

[0103] During the data write interval PDW, the gate write signal GW and the gate compensation signal GC can be applied to pixel 400. Switching transistor T2 can be turned on in response to the gate write signal GW, and compensation transistor T3' can be turned on in response to the gate compensation signal GC. The turned-on switching transistor T2 transmits the data voltage DV to the source of driving transistor T1, and the turned-on compensation transistor T3' enables the driving transistor T1 to be diode-connected. Accordingly, the data voltage DV can be transmitted to the storage capacitor CST (i.e., the gate node NG) through switching transistor T2 and the diode-connected driving transistor T1, and the storage capacitor CST can store the data voltage DV compensated for the threshold voltage of driving transistor T1.

[0104] In the light-emitting region PEM, a light-emitting signal EM can be applied to pixel 400. The first light-emitting transistor T5 and the second light-emitting transistor T6 can be turned on in response to the light-emitting signal EM. The turned-on first light-emitting transistor T5 and second light-emitting transistor T6 can form a path for a drive current generated by a drive transistor T1, from a line of the first power supply voltage ELVDD to a line of the second power supply voltage ELVSS. Accordingly, the drive current generated based on the data voltage DV stored in the storage capacitor CST (i.e., the gate node NG) can be provided to the organic light-emitting diode EL, and the organic light-emitting diode EL can emit light based on the drive current.

[0105] As described above, in pixel 400 according to another embodiment of the present invention, compensation transistor T3' may include a first compensation sub-transistor T3-1' and a second compensation sub-transistor T3-2', thereby reducing leakage current to the gate node NG. Furthermore, the first compensation sub-transistor T3-1' may include a first lower electrode BML1, and a lower electrode voltage VBML may be applied to the first lower electrode BML1, thereby further reducing leakage current to the gate node NG. In addition, the lower electrode voltage VBML applied to the first lower electrode BML1 may have a voltage level corresponding to the average representative grayscale of multiple frame intervals. Accordingly, when the image displayed in the organic light-emitting display device changes, the voltage level of the lower electrode voltage VBML may gradually change, thereby improving the display quality of the organic light-emitting display device.

[0106] Figure 8 This is a circuit diagram illustrating the pixels of an organic light-emitting display device according to yet another embodiment of the present invention.

[0107] Reference Figure 8According to another embodiment of the present invention, the pixel 500 of the organic light-emitting display device may include a storage capacitor CST, a driving transistor T1, a switching transistor T2, a compensation transistor T3, a gate initialization transistor T4, a first light-emitting transistor T5, a second light-emitting transistor T6, an anode initialization transistor T7, a first reference transistor T8, a second reference transistor T9, and an organic light-emitting diode EL. Except that the first compensation sub-transistor T3-1 and the first gate initialization sub-transistor T4-1 do not include the first lower electrode BML1 and the second lower electrode BML2, and the pixel 500 includes the first reference transistor T8 and the second reference transistor T9, in... Figure 8 The 500 pixels can have the same Figure 3 The 300 pixels have similar composition and similar operation.

[0108] The compensation transistor T3 may include a first compensation sub-transistor T3-1 and a second compensation sub-transistor T3-2 connected in series between the gate node NG and the drain of the driving transistor T1, and the gate initialization transistor T4 may include a first gate initialization sub-transistor T4-1 and a second gate initialization sub-transistor T4-2 connected in series between the gate node NG and the line of the initialization voltage VINT. Accordingly, leakage current to the gate node NG can be reduced.

[0109] The first reference transistor T8 can apply a reference voltage VREF to node NT3 between the first compensator transistor T3-1 and the second compensator transistor T3-2 in response to a light-emitting signal EM. In one embodiment, the first reference transistor T8 may include a gate electrode for receiving the light-emitting signal EM, a first source / drain electrode connected to the reference voltage VREF, and a second source / drain electrode connected to node NT3 between the first compensator transistor T3-1 and the second compensator transistor T3-2. By applying the reference voltage VREF to node NT3 between the first compensator transistor T3-1 and the second compensator transistor T3-2, the voltage at node NT3 between the first compensator transistor T3-1 and the second compensator transistor T3-2 can be controlled. Accordingly, the leakage current leaking to the gate node NG can be further reduced.

[0110] The second reference transistor T9 can apply a reference voltage VREF to node NT4 between the first gate initialization sub-transistor T4-1 and the second gate initialization sub-transistor T4-2 in response to the emitted light signal EM. In one embodiment, the second reference transistor T9 may include a gate electrode for receiving the emitted light signal EM, a first source / drain electrode connected to the reference voltage VREF, and a second source / drain electrode connected to node NT4 between the first gate initialization sub-transistor T4-1 and the second gate initialization sub-transistor T4-2. By applying the reference voltage VREF to node NT4 between the first gate initialization sub-transistor T4-1 and the second gate initialization sub-transistor T4-2, the voltage at node NT4 between the first gate initialization sub-transistor T4-1 and the second gate initialization sub-transistor T4-2 can be controlled. Accordingly, leakage current to gate node NG can be further reduced.

[0111] In one embodiment, the reference voltage VREF may have a voltage level corresponding to the average representative grayscale of multiple frame intervals. Accordingly, as the image displayed on the organic light-emitting display device changes, the voltage level of the reference voltage VREF can be gradually changed, thereby improving the display quality of the organic light-emitting display device.

[0112] Figure 9 This is a circuit diagram illustrating the pixels of an organic light-emitting display device according to yet another embodiment of the present invention.

[0113] Reference Figure 9 According to another embodiment of the organic light-emitting display device of the present invention, the pixel 600 may include a storage capacitor CST, a driving transistor T1, a switching transistor T2, a compensation transistor T3', a gate initialization transistor T4', a first light-emitting transistor T5, a second light-emitting transistor T6, a first reference transistor T8, and an organic light-emitting diode EL. Except that the pixel 600 does not include an anode initialization transistor T7 and a second reference transistor T9, the compensation transistor T3' receives a gate compensation signal GC, and the first source / drain of the gate initialization transistor T4' is connected outside the drain of the driving transistor T1 instead of the gate node NG. Figure 9 The 600 pixels can have the same Figure 8 The 500 pixels have similar composition and similar operation.

[0114] In pixel 600 according to another embodiment of the present invention, compensation transistor T3' may include a first compensation sub-transistor T3-1' and a second compensation sub-transistor T3-2', thereby reducing leakage current to gate node NG. Furthermore, a first reference transistor T8 may apply a reference voltage VREF to node NT3 between the first compensation sub-transistor T3-1' and the second compensation sub-transistor T3-2', thereby further reducing leakage current to gate node NG. In addition, the reference voltage VREF may have a voltage level corresponding to the average representative grayscale of multiple frame intervals. Accordingly, when the image displayed in the organic light-emitting display device changes, the voltage level of the reference voltage VREF can be gradually changed, thereby improving the display quality of the organic light-emitting display device.

[0115] Figure 10 This is a block diagram illustrating an organic light-emitting display device according to another embodiment of the present invention. Figure 11 This is a timing diagram illustrating an example of the operation of an organic light-emitting display device according to another embodiment of the present invention. Figure 12 This is a diagram illustrating an example of calculating an average representative grayscale and determining the voltage level of a node control voltage based on the average representative grayscale in an organic light-emitting display device according to another embodiment of the present invention.

[0116] Reference Figure 10 An organic light-emitting display device 700 according to another embodiment of the present invention may include a display panel 710 comprising a plurality of pixels PX and a panel driving unit for driving the display panel 710. In one embodiment, the panel driving unit may include a data driver 720, a gate driver 730, a light-emitting driver 740, a power management circuit 750, and a controller 760. The controller 760 may include a previous grayscale storage block 772, a current grayscale calculation block 774, an average grayscale calculation block 776, a voltage level determination block 778, a still image detector 780, and a driving frequency determiner 790. In addition to the panel driving unit or the controller 760, the device may also include a still image detector 780 and a driving frequency determiner 790, which selectively apply a node control voltage VNC to the plurality of pixels PX depending on whether the driving mode for the display panel 710 is a moving image mode or a still image mode. Figure 10 The organic light-emitting display device 700 can have the same characteristics as... Figure 1 It has a similar structure and similar operation to the organic light-emitting display device 100.

[0117] The still image detector 780 can determine whether the input image data IDAT represents a moving image or a still image. If the input image data IDAT represents a moving image, the still image detector 780 can determine the driving mode for the display panel 710 as a moving image mode; if the input image data IDAT represents a still image, the still image detector 780 can determine the driving mode for the display panel 710 as a still image mode. In one embodiment, the still image detector 780 can compare the input image data IDAT of a previous frame interval with the input image data IDAT of the current frame interval to determine whether the input image data IDAT represents a moving image or a still image.

[0118] The drive frequency determiner 790 can determine the drive frequency DF for the display panel 710 as a general drive frequency in the moving image mode, and determine the drive frequency DF for the display panel 710 as a low frequency lower than the general drive frequency in the still image mode. In one embodiment, in the still image mode, the drive frequency determiner 790 can use a flicker lookup table storing flicker values ​​based on multiple grayscale flicker values ​​to determine a flicker value (e.g., representing the degree of flicker perceived by the user) based on the grayscale (or brightness) of the input image data IDAT, and can determine the drive frequency DF for the display panel 710 based on the flicker value. According to an embodiment, the determination of the flicker value can be performed by pixel, by segment, or by portion of the panel area.

[0119] Therefore, in the still image mode, even if the controller 760 receives input image data IDAT at a fixed input frame frequency IFF (e.g., about 120 Hz), the controller 760 can also provide output image data ODAT to the data driver 720 at a drive frequency DF over a wider range of drive frequencies (e.g., about 1 Hz to about 120 Hz). For example, as Figure 11As shown, where the input image data IDAT represents the first frame interval FP1 and the second frame interval FP2 of the moving image, the controller 760 can receive frame data FDAT as input image data IDAT at an input frame frequency IFF of approximately 120 Hz, and can determine the driving mode for the display panel 710 as a moving image mode MIMODE, and can provide the frame data FDAT as output image data ODAT to the data driver 720 at a driving frequency DF of approximately 120 Hz, the same as the input frame frequency IFF. Accordingly, the display panel 710 can be driven at a driving frequency DF of approximately 120 Hz. Alternatively, if the still image is detected, the controller 760 can determine the driving mode for the display panel 710 as a still image mode SIMODE, and can determine the driving frequency DF of the display panel 710 as a low frequency (e.g., approximately 40 Hz) lower than the input frame frequency IFF of approximately 120 Hz. That is, in still image mode SIMODE, the controller 760 can provide frame data FDAT to the data driver 720 in the third frame interval FP3 and the sixth frame interval FP6, and can not provide frame data FDAT to the data driver 720 in the fourth frame interval FP4, the fifth frame interval FP5, the seventh frame interval FP7, and the eighth frame interval FP8. Accordingly, in the third frame interval FP3 to the eighth frame interval FP8, the controller 760 can provide frame data FDAT to the data driver 720 at a drive frequency DF of approximately 40Hz, which is about one-third of the input frame frequency IFF of approximately 120Hz, and the data driver 720 can drive the display panel 710 at a drive frequency DF of approximately 40Hz. In addition, although in Figure 11 An example is shown in which the display panel 710 is driven at a driving frequency DF of about 120 Hz or about 40 Hz. However, in one embodiment, the display panel 710 may be driven at a driving frequency DF of a wider range of driving frequencies from about 1 Hz to about 120 Hz.

[0120] And, although Figure 11 An example is shown where the controller 760 receives input image data IDAT at a fixed input frame frequency (IFF) of approximately 120 Hz. However, in another embodiment, the controller 760 may receive the input image data IDAT at a variable input frame frequency (IFF) of approximately 1 Hz to approximately 120 Hz. In this case, the controller 760 may drive the display panel 710 at a variable drive frequency (DF) corresponding to the variable input frame frequency (IFF).

[0121] In one embodiment, the panel driving unit can provide a node control voltage VNC to each of the plurality of pixels PX in still image mode (SIMODE) and can not provide a node control voltage VNC to each of the plurality of pixels PX in moving image mode (MIMODE). Here, not providing a node control voltage VNC to each pixel PX may include a power management circuit 750 causing the node control voltage VNC to float, or the power management circuit 750 providing a base voltage (e.g., ground voltage) as the node control voltage VNC. Furthermore, since the display panel 710 is driven at the normal driving frequency in moving image mode (MIMODE) and at a lower frequency than the normal driving frequency in still image mode (SIMODE), the time the data voltage DV is maintained at the gate node of each pixel PX in still image mode (SIMODE) can be longer than the time the data voltage DV is maintained at the gate node of each pixel PX in moving image mode (MIMODE). Therefore, the distortion of the data voltage DV in still image mode SIMODE may be more severe than that in moving image mode MIMODE. Accordingly, although the panel driving unit does not provide node control voltage VNC to each pixel PX in moving image mode MIMODE, it can provide node control voltage VNC to each pixel PX in still image mode SIMODE to reduce or prevent the distortion of the data voltage DV.

[0122] Furthermore, when a node control voltage VNC is provided to each pixel PX in still image mode SIMODE and not provided to each pixel PX in moving image mode MIMODE, brightness changes due to the node control voltage VNC may be detected during the transition between still image mode SIMODE and moving image mode MIMODE, potentially degrading the display quality of the organic light-emitting display device 700. To prevent such a degradation in display quality, in one embodiment, the panel driving unit may provide the node control voltage VNC to each of the plurality of pixels PC in the transition between still image mode SIMODE and moving image mode MIMODE, and may not provide the node control voltage VNC to each of the plurality of pixels PX in moving image mode MIMODE after the transition.

[0123] For example, such as Figure 12As shown, when the input image data IDAT represents the moving image in the first frame interval FP1 and the second frame interval FP2, the panel driving unit can determine the driving mode for the display panel 710 as a moving image mode (MIMODE). In MIMODE, the panel driving unit may not calculate the representative grayscale RG and the average representative grayscale ARG in each frame interval FP1 and FP2, and may treat the representative grayscale RG and the average representative grayscale ARG as having a basic grayscale DEF (e.g., 0 grayscale). Furthermore, in MIMODE, the panel driving unit may not provide the node control voltage VNC to the multiple pixels PX. For example, the panel driving unit may allow the node control voltage VNC to float, or may provide a basic voltage (e.g., ground voltage) as the node control voltage VNC.

[0124] Subsequently, when the input image data IDAT represents the still image in the third frame interval FP3 to the sixth frame interval FP6, the panel driving unit can determine the driving mode for the display panel 710 as still image mode SIMODE. In still image mode SIMODE, the panel driving unit can calculate the representative grayscale RG and the average representative grayscale ARG in each frame interval FP3 to FP6, and can determine the voltage level of the node control voltage VNC to correspond to the average representative grayscale ARG. Furthermore, during the transition interval TP1 from motion picture mode (MIMODE) to still picture mode (SIMODE), specifically during the third frame interval FP3 and the fourth frame interval FP4, the panel driving unit can calculate the average representative gray level ARG by averaging the representative gray level RG (i.e., the basic gray level DEF) of at least one frame interval (e.g., FP2 and / or FP1) in motion picture mode and the representative gray level RG calculated in at least one frame interval (e.g., FP3 and / or FP4) in still picture mode, and can determine the voltage level of the node control voltage VNC to correspond to the average representative gray level ARG. Accordingly, during the transition interval TP1 from motion picture mode (MIMODE) to still picture mode (SIMODE) and the frame interval FP5 immediately following the transition interval TP1, the voltage level of the node control voltage VNC can be sequentially (i.e., gradually) changed to a first voltage level VL1, a second voltage level VL2, and a third voltage level VL3. Subsequently, with the representative grayscale RG of the input image data IDAT remaining constant in the still image mode SIMODE, the voltage level of the node control voltage VNC can be maintained at the third voltage level VL3.

[0125] Subsequently, when the input image data IDAT represents the moving image in the seventh frame interval FP7 to the ninth frame interval FP9, the panel driving unit can determine the driving mode for the display panel 710 as the moving image mode MIMODE. In the moving image mode MIMODE, the panel driving unit may not calculate the representative grayscale RG in each frame interval FP7, FP8, and FP9, and may consider the representative grayscale RG as having a basic grayscale DEF (e.g., 0 grayscale). However, in the transition interval TP2 from the still image mode SIMODE to the moving image mode MIMODE, i.e., in the seventh frame interval FP7 and the eighth frame interval FP8 where the transition occurs, the panel driving unit may calculate the average representative grayscale ARG by averaging the representative grayscale RG calculated in at least one frame interval (e.g., FP6) of the still image mode SIMODE and the basic grayscale DEF in the moving image mode MIMODE, and may determine the voltage level of the node control voltage VNC to correspond to the average representative grayscale ARG. Accordingly, in the frame interval FP6 immediately preceding the transition interval TP2 and in the transition interval TP2 from still image mode SIMODE to moving image mode MIMODE, the voltage level of the node control voltage VNC can be sequentially (i.e., gradually) changed to the third voltage level VL3, the second voltage level VL2, and the first voltage level VL1. Therefore, the brightness change of the node control voltage VNC can be ignored, and the display quality of the organic light-emitting display device 700 can be further improved. Subsequently, in the moving image mode MIMODE after the transition interval TP2 (i.e., the ninth frame interval FP9), the panel driving unit can cause the node control voltage VNC line to float, or provide a basic voltage (e.g., ground voltage) as the node control voltage VNC.

[0126] Figure 13 This is a block diagram illustrating an electronic device including an organic light-emitting display device according to an embodiment of the present invention.

[0127] Reference Figure 13 Electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output device 1140, a power supply 1150, and an organic light-emitting display device 1160. Electronic device 1000 may also include various ports capable of communicating with graphics cards, sound cards, memory cards, USB devices, etc., or capable of communicating with other systems.

[0128] Processor 1110 can perform specific calculations or tasks. According to embodiments, processor 1110 can be a microprocessor, central processing unit (CPU), etc. Processor 1110 can be connected to other components via address bus, control bus, and data bus. According to embodiments, processor 1110 can also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus.

[0129] The memory device 1120 can store data required for the operation of the electronic device 1100. For example, memory device 1120 may include non-volatile memory devices such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, phase change random access memory (PRAM), resistance random access memory (RRAM), nano floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), and / or volatile memory devices such as dynamic random access memory (DRAM), static random access memory (SRAM), mobile DRAM, etc.

[0130] Storage device 1130 may include solid-state drive (SSD), hard disk drive (HDD), CD-ROM, etc. Input / output device 1140 may include input means such as keyboard, keypad, touchpad, touch screen, mouse, etc., and output means such as speakers, printers, etc. Power supply 1150 provides the power required for the operation of electronic device 1100. Organic light-emitting display device 1160 can be connected to other components via the bus or other communication links.

[0131] In the organic light-emitting display device 1160, each pixel may include a first compensator transistor and a second compensator transistor connected in series between the gate node and the drain of the driving transistor. Furthermore, the panel driving unit of the organic light-emitting display device 1160 can determine the voltage level of the node control voltage based on the average representative grayscale of multiple frame intervals, and can provide the node control voltage to each pixel to control the voltage of the node between the first and second compensator transistors. Therefore, leakage current to the gate node can be reduced. Moreover, when the image displayed in the organic light-emitting display device 1160 changes, the voltage level of the node control voltage can be gradually changed. Accordingly, the display quality of the organic light-emitting display device 1160 can be improved.

[0132] According to an embodiment, the electronic device 1100 may be any electronic device including the organic light-emitting display device 1160, such as a mobile phone, smartphone, tablet computer, laptop computer, personal computer (PC), digital television, 3D TV, home electronic device, personal digital assistant (PDA), portable multimedia player (PMP), digital camera, music player, portable game console, navigation device, etc.

[0133] Industrial availability

[0134] This invention can be applied to any organic light-emitting display device and electronic devices including thereof. For example, this invention can be applied to portable telephones, smartphones, tablet computers, laptop computers, PCs, TVs, digital TVs, 3D TVs, home electronic devices, PDAs, PMPs, digital cameras, music players, portable game consoles, navigators, etc.

[0135] Although the invention has been described above with reference to exemplary embodiments thereof, those skilled in the art will understand that various modifications and alterations can be made to the invention without departing from the spirit and technical scope of the invention as set forth in the claims.

Claims

1. An organic light-emitting display device, characterized in that, include: The display panel includes multiple pixels; as well as The panel driver unit drives the display panel. Each of the plurality of pixels includes: A driving transistor having a gate electrode connected to a gate node; A switching transistor is used to transfer the data voltage to the source of the driving transistor; The compensation transistor includes a first compensation sub-transistor and a second compensation sub-transistor that connect the driving transistor diode and are connected in series between the gate node and the drain of the driving transistor. A storage capacitor stores the data voltage transmitted by a drive transistor connected via the switching transistor and the diode; and An organic light-emitting diode (OLED) emits light based on a drive current generated by the driving transistor. Specifically, the panel driving unit calculates the average representative grayscale of input image data across multiple frame intervals, determines the voltage level of the node control voltage based on the average representative grayscale, and provides the node control voltage to each of the multiple pixels to control the voltage of the node between the first compensating sub-transistor and the second compensating sub-transistor. Wherein, the average representative gray level is the average of multiple representative gray levels of the input image data across the multiple frame intervals.

2. The organic light-emitting display device as described in claim 1, characterized in that, At least one of the first compensator transistor and the second compensator transistor includes a lower electrode. The node control voltage is the lower electrode voltage applied to the lower electrode.

3. The organic light-emitting display device as described in claim 1, characterized in that, Each of the plurality of pixels also includes: A reference transistor applies a reference voltage to the node between the first compensating sub-transistor and the second compensating sub-transistor. The node control voltage is the reference voltage.

4. The organic light-emitting display device as described in claim 1, characterized in that, Each of the plurality of grayscale representations is the average grayscale value of the input image data represented by the corresponding frame interval in the plurality of frame intervals.

5. The organic light-emitting display device as described in claim 1, characterized in that, Each of the plurality of grayscale values ​​is the middle, maximum, or minimum grayscale value of the input image data represented by the corresponding frame interval in the plurality of frame intervals.

6. The organic light-emitting display device as described in claim 1, characterized in that, The plurality of frame intervals includes at least one previous frame interval and the current frame interval. The panel driving unit: The previous frame representing the grayscale value is stored in the at least one previous frame interval. The grayscale value representing the current frame is calculated based on the input image data of the current frame interval. The average representative gray level is calculated by averaging the gray levels represented by the previous frame and the gray levels represented by the current frame. The voltage level of the node control voltage is determined to correspond to the average representative gray level.

7. The organic light-emitting display device as described in claim 1, characterized in that, The panel driving unit includes: A data driver provides the data voltage to each of the plurality of pixels; A gate driver provides a gate signal to each of the plurality of pixels; The power management circuit provides the node control voltage to each of the plurality of pixels; The controller controls the data driver, the gate driver, and the power management circuit. The controller includes: Previous grayscale storage block, storing at least one previous frame range representing grayscale; The current grayscale calculation block calculates the grayscale value representing the current frame based on the input image data of the current frame range; An average grayscale calculation block calculates the average representative grayscale by averaging the representative grayscale of the previous frame and the representative grayscale of the current frame; and The voltage level determination block determines the voltage level of the node control voltage to correspond to the average representative gray level.

8. The organic light-emitting display device as claimed in claim 1, characterized in that, Each of the plurality of pixels also includes: A gate initialization transistor includes a first gate initialization sub-transistor and a second gate initialization sub-transistor connected in series between the gate node and the line of the initialization voltage, which apply an initialization voltage to the gate node in response to a gate initialization signal. Wherein, at least one of the first compensating transistor and the second compensating transistor includes a first lower electrode. At least one of the first gate initialization sub-transistor and the second gate initialization sub-transistor includes a second lower electrode. The node control voltage is the lower electrode voltage applied to the first lower electrode and the second lower electrode.

9. The organic light-emitting display device as described in claim 2 or 3, characterized in that, Each of the plurality of pixels also includes: A gate initialization transistor applies an initialization voltage to the drain of the driving transistor in response to a gate initialization signal.

10. The organic light-emitting display device as claimed in claim 1, characterized in that, Each of the plurality of pixels also includes: A gate initialization transistor includes a first gate initialization sub-transistor and a second gate initialization sub-transistor that apply an initialization voltage to the gate node in response to a gate initialization signal, and are connected in series between the gate node and the line of the initialization voltage. A first reference transistor applies a reference voltage to the node between the first compensating sub-transistor and the second compensating transistor; and The second reference transistor applies the reference voltage to the node between the first gate initialization sub-transistor and the second gate initialization transistor. The node control voltage is the reference voltage.

11. The organic light-emitting display device as claimed in claim 1, characterized in that, The panel driving unit includes: A still image detector determines whether the input image data represents a moving image or a still image. If the input image data represents a moving image, the driving mode for the display panel is determined to be a moving image mode; if the input image data represents a still image, the driving mode for the display panel is determined to be a still image mode. A drive frequency determiner determines the drive frequency for the display panel as a normal drive frequency in the moving image mode and determines the drive frequency for the display panel as a low frequency lower than the normal drive frequency in the still image mode.

12. The organic light-emitting display device as claimed in claim 11, characterized in that, The panel driving unit provides the node control voltage to each of the plurality of pixels in the still image mode. The panel driving unit does not provide the node control voltage to each of the plurality of pixels in the motion picture mode.

13. The organic light-emitting display device as claimed in claim 11, characterized in that, The panel driving unit provides the node control voltage to each of the plurality of pixels in the still image mode and in the transition interval between the still image mode and the moving image mode. The panel driving unit does not provide the node control voltage to each of the plurality of pixels in the motion picture mode after the transition interval.

14. The organic light-emitting display device as claimed in claim 9, characterized in that, Each of the plurality of pixels also includes: A first light-emitting transistor, in response to a light-emitting signal, connects a power supply voltage line to the source of the driving transistor; and The second light-emitting transistor connects the drain of the driving transistor to the organic light-emitting diode in response to the light-emitting signal.

15. The organic light-emitting display device as described in claim 8 or 10, characterized in that, Each of the plurality of pixels also includes: The first light-emitting transistor connects a power supply voltage line to the source of the driving transistor in response to a light-emitting signal. A second light-emitting transistor, in response to the light-emitting signal, connects the drain of the driving transistor to the organic light-emitting diode; and An anode initialization transistor applies the initialization voltage to the organic light-emitting diode in response to a gate bypass signal.

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