Display device

Abstract

A display apparatus includes a pixel portion in which a plurality of pixels are arranged, the plurality of pixels being connected to a scan line and a data line; a source output line to which a data signal is transmitted; a data driver configured to transmit a data signal to the source output line; a data distributor configured to selectively connect the source output line to the data line; and a latch portion arranged between the data distributor and the pixel portion, wherein the latch portion includes a plurality of latches connected to at least one of the data lines other than the data line connected to the source output line through the data distributor at a time when a scan signal is transmitted to the scan line.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0096944, filed on August 3, 2020, which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] Exemplary embodiments and implementations of the present invention generally relate to a display device and a driving method thereof. Background Technology

[0004] Display devices include multiple scan lines, multiple data lines, and multiple pixels arranged at their intersections. In order to apply data signals to each of the multiple data lines, the data driver needs to include the same number of output lines as the number of data lines, and requires multiple integrated circuits, thus increasing manufacturing costs.

[0005] The information disclosed in this background section is only for understanding the background of the inventive concept, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0006] One or more embodiments include a display device and a driving method for the display device, wherein the display device has a reduced number of output lines of a data driver. One or more embodiments include a display device and a driving method for the display device that can reduce image quality degradation caused by external noise introduced into the data lines. However, such technical problems are exemplary, and this disclosure is not limited thereto.

[0007] Other aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing the embodiments proposed in this disclosure.

[0008] According to one or more embodiments, a display device includes: a pixel portion, in which a plurality of pixels are arranged, the plurality of pixels being connected to a scan line and a data line; a source output line to which a data signal is transmitted; a data driver configured to transmit a data signal to the source output line; a data distributor configured to selectively connect the source output line to the data line; and a latch portion disposed between the data distributor and the pixel portion, wherein the latch portion includes a plurality of latches connected to at least one of the data lines, excluding the data line connected to the source output line via the data distributor at the time the scan signal is transmitted to the scan line.

[0009] Each of the plurality of latches may include: an amplifier including a first input terminal connected to the source output line and an output terminal connected to a corresponding data line among the data lines; and a capacitor connected between the first input terminal and the power supply section.

[0010] The power supply section can apply a first power supply voltage and a second power supply voltage to each of the plurality of pixels.

[0011] The amplifier may further include a second input terminal connected to the output terminal.

[0012] The latch may further include a first resistor between the second input terminal of the amplifier and the power supply section, and a second resistor between the second input terminal and the output terminal.

[0013] The latch section may further include a first transistor connected between the first input terminal and the output terminal of the amplifier.

[0014] The first transistor can be turned on when the corresponding data line is connected to the source output line.

[0015] The latch section may further include a second transistor connected between the first input terminal of the amplifier and the source output line.

[0016] The first transistor can be turned on when the corresponding data line is connected to the source output line, and the second transistor can be turned on when the scan signal is transmitted to the scan line.

[0017] The pixels may include red pixels, blue pixels, and green pixels. The red pixels are connected to a first data line in a first column, the blue pixels are connected to a second data line in a second column, and the green pixels are connected to a third data line in a third column. The latch portion may include a first latch and a second latch. The first latch is connected to the first data line, and the second latch is connected to the second data line.

[0018] The pixel may include a red pixel, a blue pixel, and a green pixel. The red pixel is connected to a first data line on a first column, the blue pixel is connected to a second data line on a second column, and the green pixel is connected to a third data line on a third column. The latch portion may include a latch connected to the first data line.

[0019] The data distributor may include a plurality of switches, and each of the plurality of switches may be connected between a corresponding data line in the data lines and the source output line.

[0020] According to one or more embodiments, a display device includes: a plurality of pixels connected to a scan line and a data line; a source output line to which a data signal is transmitted; a demultiplexer including a plurality of switches connected to the source output line and the data line; and a plurality of latches connected between a switch among the plurality of switches that is disconnected when a scan signal is transmitted to the scan line and the data line.

[0021] Each of the plurality of latches may include: an amplifier including a first input terminal connected to the source output line and an output terminal connected to a corresponding data line among the data lines; and a capacitor connected between the first input terminal and a power supply section, wherein the power supply section can apply a first power supply voltage and a second power supply voltage to each of the plurality of pixels.

[0022] The amplifier may further include a second input terminal connected to the output terminal.

[0023] The latch may further include a first resistor between the second input terminal of the amplifier and the power supply section, and a second resistor between the second input terminal and the output terminal.

[0024] The latch section may further include a first transistor connected between the input terminal and the output terminal of the amplifier.

[0025] The first transistor can be turned on when the corresponding data line is connected to the source output line.

[0026] The latch section may further include a second transistor connected between the first input terminal of the amplifier and the source output line.

[0027] The first transistor can be turned on when the corresponding data line is connected to the source output line, and the second transistor can be turned on when the scan signal is transmitted to the scan line.

[0028] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0029] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 This is a perspective view showing a display device according to an embodiment;

[0031] Figure 2 This is a cross-sectional view of a display device according to an embodiment;

[0032] Figure 3 This is a plan view showing a display panel according to an embodiment;

[0033] Figure 4A and Figure 4B This shows an equivalent circuit diagram of a pixel according to an embodiment;

[0034] Figure 5 This is a view showing a portion of the display panel according to an embodiment;

[0035] Figure 6 It is shown that, according to an embodiment Figure 5 The timing diagram of the demultiplexer operation is shown below;

[0036] Figure 7 This is a view illustrating the operation of the demultiplexer according to an embodiment;

[0037] Figure 8 It is used for explanation Figure 7 The timing diagram of the demultiplexer operation is shown below;

[0038] Figure 9 This is a view showing the operation of the demultiplexer in a comparative example;

[0039] Figure 10 It shows Figure 9 The timing diagram of the demultiplexer operation is shown below;

[0040] Figure 11 and Figure 12 This is a view showing the demultiplexer of the display panel and a portion of its surroundings according to an embodiment; and

[0041] Figure 13A , Figure 13B , Figure 13C and Figure 13D This is a circuit diagram showing the sub-latch portion according to an embodiment. Detailed Implementation

[0042] In the following description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, “embodiment” and “implementation” are interchangeable terms, referring to non-limiting examples of apparatus or methods employing one or more inventive concepts disclosed herein. However, it will be apparent that various exemplary embodiments may be implemented without these specific details or using one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, a particular shape, construction, and characteristic of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0043] Unless otherwise stated, the exemplary embodiments shown are to be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions and / or aspects of various embodiments (hereinafter individually or collectively referred to as “elements”) may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0044] Crosshairs and / or shading are typically used in accompanying drawings to clarify the boundaries between adjacent elements. Therefore, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, size, scale, commonalities between illustrated elements, or any other characteristics, properties, etc. Furthermore, in the drawings, the size and relative size of elements may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a particular process sequence may be performed differently than the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Moreover, the same reference numerals denote the same elements.

[0045] When an element or layer is referred to as being "on" another element or layer, "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or an intermediary element or layer may be present. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to," or "directly coupled to" another element or layer, an intermediary element or layer is not present. For this purpose, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection, with or without an intermediary element. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0046] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., in a “sidewall”) may be used herein to describe the relationship between one element (or multiple elements) and another element (or multiple elements) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device during use, operation, and / or manufacture. For example, if the device in the figures is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” other elements or features. Thus, the exemplary term “below” can cover both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative terms used herein should be interpreted accordingly.

[0047] It should also be noted that, as used herein, the terms “substantially,” “approximately,” and other similar terms are used as approximate terms rather than terms of degree, and thus to explain the inherent biases in measurements, calculations, and / or provided values ​​that will be recognized by one of ordinary skill in the art.

[0048] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Unless expressly defined herein, terms such as those defined in a general dictionary shall be interpreted as having a meaning consistent with the meaning of the term in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense.

[0049] Reference will now be made in detail to embodiments illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements throughout the text. In this respect, embodiments may take different forms and should not be construed as being limited to the description set forth herein. Therefore, the following description, by reference to the accompanying drawings, aims only at illustrating aspects of the description. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, a and b, a and c, b and c, all of a, b, and c, or variations thereof.

[0050] Because this description allows for various variations and numerous embodiments, certain embodiments will be shown in the accompanying drawings and described in the written description. The effects and features of one or more embodiments, as well as methods of implementing them, will become apparent from the following detailed description of one or more embodiments taken in conjunction with the accompanying drawings. However, these embodiments may take different forms and should not be construed as being limited to the description set forth herein.

[0051] Although terms such as "first" and "second" can be used to describe various components, such components are not limited to these terms. The terms are used to distinguish one component from another.

[0052] Unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” used herein are intended to also include the plural forms.

[0053] It will be understood that the terms “comprise,” “comprising,” “include,” and / or “including” as used herein specify the presence of the said feature or element, but do not preclude the addition of one or more other features or elements.

[0054] It will be further understood that when a layer, region, or element is referred to as being "on" another layer, region, or element, it can be directly or indirectly on the other layer, region, or element. That is, for example, there can be intermediate layers, regions, or elements.

[0055] For ease of illustration, the dimensions of the elements in the accompanying drawings may be enlarged or reduced. In other words, because the dimensions and thicknesses of the elements in the accompanying drawings are arbitrarily shown for ease of illustration, the following embodiments are not limited thereto.

[0056] In this disclosure, "A and / or B" may include "A", "B", or "A and B". Additionally, in the inventive concept, "at least one of A and B" may include "A", "B", or "A and B".

[0057] As used herein, when wiring is referred to as “extending in a first direction or a second direction”, it means that wiring may extend in a straight line, or in a zigzag or curved shape in the first or second direction.

[0058] In the following disclosure, a "plan view" means a portion of the target object seen from above, and a "section view" means a portion of the target object is cut vertically and the section is viewed from the side. As used herein, when referring to the first element "overlapping" with the second element, the first element is positioned above or below the second element.

[0059] As used herein, when referring to an X and Y connection, it can include cases where X and Y are electrically connected, cases where X and Y are functionally connected, and cases where X and Y are directly connected. Here, X and Y can include objects (e.g., devices, apparatuses, circuits, wiring, electrodes, terminals, conductive layers, layers, etc.). Therefore, the connection is not limited to predetermined connection relationships, such as those shown in the accompanying drawings or detailed description, and can include other connection relationships not shown in the accompanying drawings or detailed description.

[0060] The case of an electrical connection between X and Y can include, for example, at least one device (e.g., a switch, transistor, capacitor, inductor, resistor, diode, etc.) capable of enabling the electrical connection between X and Y is connected between X and Y.

[0061] As used herein, "ON" in association with a component state indicates the active state of the component, while "OFF" indicates the inactive state. "ON" in association with a signal received by the component indicates a signal used to activate the component, while "OFF" indicates a signal used to deactivate the component. A component can be activated by either a high or low voltage level. For example, a P-channel transistor is activated by a low voltage level, while an N-channel transistor is activated by a high voltage level. Therefore, it should be understood that the "ON" voltages for P-channel and N-channel transistors are opposite (high vs. low) voltage levels.

[0062] Figure 1 This is a perspective view showing a display device 1 according to an embodiment. Figure 2 It shows along Figure 1 A cross-sectional view of the display device 1 according to the embodiment, taken by line I-I'.

[0063] The display device 1 according to the embodiment can be implemented as an electronic device including a smartphone, mobile phone, smartwatch, navigation device, game console, television (TV), automotive head unit, laptop computer, tablet computer, personal media player (PMP), and personal digital assistant (PDA). Additionally, the electronic device may include a flexible device.

[0064] Display device 1 may include a display area DA and a peripheral area PA, wherein an image is displayed in the display area DA and the peripheral area PA is located outside the display area DA. Display device 1 can display the image by using light emitted from a plurality of pixels arranged in the display area DA.

[0065] Display device 1 can be fabricated in various shapes and, for example, as a rectangular plate with two pairs of parallel sides. When the display device is fabricated as a rectangular plate, one pair of sides may be longer than the other pair. In this embodiment, for ease of description, the description refers to the case where the display device has a rectangular shape with one pair of long sides and one pair of short sides. The direction of extension of the short sides is represented by a first direction (x-direction), the direction of extension of the long sides is represented by a second direction (y-direction), and the direction perpendicular to the directions of extension of the long and short sides is represented by a third direction (z-direction). In another embodiment, display device 1 may have a non-quadrilateral shape. Non-quadrilateral shapes may include, for example, circles, ellipses, polygons whose portions are circles, and polygons that do not include quadrilaterals.

[0066] In a plan view, the display area DA can have, for example... Figure 1 The rectangular shape shown is illustrated. In another embodiment, the display area DA can have polygonal shapes such as triangles, pentagons, and hexagons, circular shapes, elliptical shapes, or irregular shapes.

[0067] The peripheral area PA is the area outside the display area DA and can be a non-display area where no pixels are arranged. The display area DA can be completely surrounded by the peripheral area PA. Various wirings or pads can be arranged in the peripheral area PA. The wirings are used to transmit electrical signals to be applied to the display area DA, and the printed circuit board and driver integrated circuit (IC) chip are attached to the pads.

[0068] In the following description, although the organic light-emitting display device is used as an example to describe display device 1 according to an embodiment, the embodiment is not limited thereto. In another embodiment, display device 1 according to the embodiment may include an inorganic light-emitting display and a quantum dot light-emitting display.

[0069] refer to Figure 2The display device 1 may include a display panel 10, an input sensing layer 40, and an optical functional layer 50, with the input sensing layer 40 on the display panel 10. These components may be covered by a window 60.

[0070] Display panel 10 can display images. Display panel 10 includes pixels arranged in display area DA. Each pixel can include a display element. The display element can be connected to pixel circuitry. The display element can include an organic light-emitting diode or a quantum dot organic light-emitting diode.

[0071] The input sensing layer 40 obtains coordinate information corresponding to external inputs (e.g., touch events). The input sensing layer 40 may include sensing electrodes (or touch electrodes) and traces connected to the sensing electrodes. The input sensing layer 40 may be disposed on the display panel 10. The input sensing layer 40 can sense external inputs using mutual capacitance and / or self-capacitance methods.

[0072] The input sensing layer 40 can be formed directly on the display panel 10 or coupled to the display panel 10 via an adhesive layer such as an optically clear adhesive. As an example, the input sensing layer 40 can be formed sequentially after the process of forming the display panel 10. In this case, the input sensing layer 40 can be part of the display panel 10, and no adhesive layer may be disposed between the input sensing layer 40 and the display panel 10. Although in Figure 2 The diagram shows an input sensing layer 40 disposed between the display panel 10 and the optical functional layer 50, but in another embodiment, the input sensing layer 40 may be disposed on the optical functional layer 50.

[0073] The optical functional layer 50 may include an anti-reflective layer. The anti-reflective layer reduces the reflectivity of light (external light) incident from the outside through the window 60 toward the display panel 10. The anti-reflective layer may include a retarder and a polarizer. The retarder may be a film-type or a liquid crystal-coated type and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also be a film-type or a liquid crystal-coated type. The film-type may include a stretched synthetic resin film, and the liquid crystal-coated type may include liquid crystals arranged in a specific configuration. The retarder and polarizer may each further include a protective film. The retarder and polarizer themselves, or the protective film of the retarder and polarizer, may be defined as the substrate layer of the anti-reflective layer.

[0074] In another embodiment, the anti-reflective layer may include a black matrix and color filters. The color filters can be arranged taking into account the colors of light emitted from the pixels of the display panel 10. In another embodiment, the anti-reflective layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers. The first reflected light and the second reflected light reflected by the first reflective layer and the second reflective layer, respectively, will produce destructive interference, and thus can reduce the reflectivity of external light.

[0075] The optical functional layer 50 may include a lens layer. The lens layer can improve the emission efficiency of light emitted from the display panel 10 or reduce color deviation. The lens layer may include a layer having a concave lens shape or a convex lens shape and / or include multiple layers with different refractive indices. The optical functional layer 50 may include both an anti-reflective layer and a lens layer, or one of these layers.

[0076] In this embodiment, the optical functional layer 50 can be formed sequentially after the processes for forming the display panel 10 and / or the input sensing layer 40. In this case, an adhesive layer may not be required between the optical functional layer 50 and the display panel 10 and / or the input sensing layer 40.

[0077] Figure 3 This is a plan view showing the display panel 10 according to an embodiment.

[0078] refer to Figures 1-3 Various components constituting the display panel 10 are arranged on a substrate. That is, the substrate may include the display area DA corresponding to the display area DA and the peripheral area PA of the display panel 10, as well as the peripheral area PA surrounding the display area DA.

[0079] A pixel portion 110, which has multiple pixels P, can be arranged in the display area DA. A scan driver 120, a data driver 130, a data distributor 140, and a controller 150 can be arranged in the peripheral area PA.

[0080] Each of the plurality of pixels P can be connected to a corresponding scan line among a plurality of scan lines GL1, GL2, ..., GLn (including scan line GL3) and a corresponding data line among a plurality of data lines DL1, DL2, ..., DLm (including data lines DLi, DLi+1, DLi+2, DL2i, ..., DLm-i+1, DLm-i+2, etc.). The plurality of scan lines GL1, GL2, ..., GLn are arranged in rows and separated from each other at constant intervals to transmit corresponding scan signals. The plurality of data lines DL1, DL2, ..., DLm are arranged in columns and separated from each other at constant intervals to transmit corresponding data signals. The plurality of scan lines GL1, GL2, ..., GLn and the plurality of data lines DL1, DL2, ..., DLm are arranged in a matrix configuration. In this case, pixel P can be formed at the intersection of a scan line (e.g., scan line GLn) and a data line (e.g., data line DLm). The driving voltage ELVDD, which serves as the first power supply voltage, and the common voltage ELVSS, which serves as the second power supply voltage, can be transmitted from the power supply section to the pixel P of the pixel section 110. The power supply section can be provided in the peripheral area PA.

[0081] Scan driver 120 is connected to multiple scan lines GL1, GL2, ..., GLn, and generates corresponding scan signals based on scan drive control signals SCS input from controller 150, and supplies the generated scan signals to the multiple scan lines GL1, GL2, ..., GLn. In an embodiment, scan driver 120 may include multi-stage circuitry and sequentially supplies scan signals to the multiple scan lines GL1, GL2, ..., GLn. When scan signals are sequentially supplied to the multiple scan lines GL1, GL2, ..., GLn, pixels P can be selected on a row-by-row basis.

[0082] Data driver 130 is connected to multiple source output lines SL1, SL2, ..., and SLm / i, which are connected to multiple data lines DL1, DL2, ..., and DLm via data distributor 140. Data driver 130 converts the image signal DATA' into a voltage or current data signal based on the data drive control signal DCS input from controller 150. Data driver 130 supplies the corresponding data signal to data distributor 140 via source output lines SL1, SL2, ..., and SLm / i.

[0083] One side of the data distributor 140 is connected to a plurality of source output lines SL1, SL2, ..., and SLm / i, while the other side is connected to a plurality of data lines DL1, DL2, ..., and DLm. The data distributor 140 may include m / i demultiplexers 142 (where i is a natural number equal to or greater than 2), each comprising a plurality of switching elements. The data distributor 140 includes the same number of demultiplexers 142 as the number of source output lines SL1, SL2, ..., and SLm / i. One end of each demultiplexer 142 is connected to a corresponding source output line among the plurality of source output lines SL1, SL2, ..., and SLm / i. Additionally, the other end of each demultiplexer 142 is connected to i data lines. The demultiplexer 142 supplies a data signal from one source output line to the i data lines. When demultiplexer 142 is used, the number of source output lines SL1, SL2, ..., SLm / i is less than the number of data lines DL1, DL2, ..., DLm. Therefore, the number of source output lines SL1, SL2, ..., SLm / i connected to data driver 130 is reduced, and thus manufacturing costs can be lowered. Demultiplexer 142 may include multiple switches connected to each of the respective source output lines and the i data lines.

[0084] A latch section 180' may be arranged between the data distributor 140 and the pixel section 110. The latch section 180' may include a plurality of sub-latch sections, each corresponding to a demultiplexer 142. That is, the number of demultiplexers 142 may be the same as the number of sub-latch sections. Each sub-latch section may include a plurality of latches connected to data lines among the data lines connected to the corresponding demultiplexer 142, excluding the data lines connected to the corresponding source output line when a scan signal is applied via a scan line. It is possible that the demultiplexer 142 selectively connects to i data lines relative to a single source output line. Therefore, a sub-latch section may be connected to at least one data line among the i data lines, excluding the data lines connected to the source output line when a scan signal is applied via a scan line. As an example, a sub-latch section may include at least one to (i-1) latches.

[0085] Controller 150 generates a data drive control signal DCS and a scan drive control signal SCS based on an externally supplied synchronization signal. Controller 150 outputs the data drive control signal DCS to data driver 130 and the scan drive control signal SCS to scan driver 120. Controller 150 can output a demultiplexing control signal CSx to data distributor 140, which can selectively connect source output lines SL1, SL2, ..., SLm / i to data lines DL1, DL2, ..., DLm based on the demultiplexing control signal CSx. Controller 150 can output i demultiplexing control signals CSx to demultiplexer 142 to supply i data signals supplied to one source output line to i data lines through time division. The i control signals can be output sequentially to prevent overlap.

[0086] The scan driver 120, data distributor 140, and controller 150 can be formed directly on the substrate. The data driver 130 can be disposed on a flexible printed circuit board (FPCB) electrically connected to pads located on one side of the substrate. In another embodiment, the data driver 130 can be disposed directly on the substrate using a chip-on-glass method or a chip-on-plastic method.

[0087] Figure 4A and Figure 4B This illustrates an equivalent circuit diagram of a pixel according to an embodiment.

[0088] refer to Figure 4A The pixel circuit PC can be connected to a light-emitting element to enable pixel P to emit light. The light-emitting element may include an organic light-emitting diode (OLED). The pixel circuit PC includes a driving transistor (first transistor) T1, a switching transistor (second transistor) T2, and a capacitor Cst. The switching transistor T2 is connected to the scan line GL and the data line DL and transmits the data signal DATA input through the data line DL to the driving transistor T1 according to the scan signal Gn input through the scan line GL.

[0089] Capacitor Cst is connected to switching transistor T2 and drive voltage line PL, and stores a voltage corresponding to the difference between the voltage transmitted from switching transistor T2 and the drive voltage ELVDD supplied to drive voltage line PL.

[0090] The driving transistor T1 is connected to the driving voltage line PL and the capacitor Cst, and the driving current flowing from the driving voltage line PL to the organic light-emitting diode (OLED) can be controlled according to the voltage stored in the capacitor Cst. The OLED can then emit light with a specific brightness based on the driving current.

[0091] AlthoughFigure 4A The illustration shows a pixel circuit PC comprising two thin-film transistors and a capacitor, but the embodiments are not limited to this.

[0092] refer to Figure 4B The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The first terminal of each of these transistors may be either a source terminal or a drain terminal, and the second terminal may be a different terminal from the first terminal, depending on the type of transistor (P-type or N-type) and / or the operating conditions. As an example, if the first terminal is a source terminal, the second terminal may be a drain terminal.

[0093] The pixel circuit PC can be connected to the first scan line GL, the second scan line GL-1, the third scan line GL+1, the transmit control line EL, the data line DL, the drive voltage line PL, and the initialization voltage line VL. The first scan line GL transmits the first scan signal Gn, the second scan line GL-1 transmits the second scan signal Gn-1, the third scan line GL+1 transmits the third scan signal Gn+1, the transmit control line EL transmits the transmit control signal En, the data line DL transmits the data signal DATA, the drive voltage line PL transmits the drive voltage ELVDD, and the initialization voltage line VL transmits the initialization voltage Vint.

[0094] The first transistor T1 includes a gate terminal, a first terminal, and a second terminal. The gate terminal is connected to a second node N2, the first terminal is connected to a first node N1, and the second terminal is connected to a third node N3. The first transistor T1 functions as a driving transistor, receiving a data signal DATA according to the switching operation of the second transistor T2, and supplying driving current to a light-emitting element. The light-emitting element may include an organic light-emitting diode (OLED).

[0095] The second transistor T2 (switching transistor) includes a gate terminal, a first terminal, and a second terminal. The gate terminal is connected to the first scan line GL, the first terminal is connected to the data line DL, and the second terminal is connected to the first node N1 (or the first terminal of the first transistor T1). The second transistor T2 can be turned on according to the first scan signal Gn transmitted through the first scan line GL and can perform a switching operation to transmit the data signal DATA transmitted through the data line DL to the first node N1.

[0096] The third transistor T3 (compensation transistor) includes a gate terminal, a first terminal, and a second terminal. The gate terminal is connected to a first scan line GL, the first terminal is connected to a second node N2 (or the gate terminal of the first transistor T1), and the second terminal is connected to a third node N3 (or the second terminal of the first transistor T1). The third transistor T3 can be turned on according to a first scan signal Gn transmitted through the first scan line GL, thus connecting the first transistor T1 in a diode configuration and compensating for the threshold voltage of the first transistor T1. The third transistor T3 may have a structure in which two or more transistors are connected in series.

[0097] The fourth transistor T4 (the first initialization transistor) includes a gate terminal, a first terminal, and a second terminal. The gate terminal is connected to a second scan line GL-1, the first terminal is connected to an initialization voltage line VL, and the second terminal is connected to a second node N2. The fourth transistor T4 can be turned on according to a second scan signal Gn-1 transmitted through the second scan line GL-1 to initialize the gate voltage of the first transistor T1 by transmitting the initialization voltage Vint to the gate terminal of the first transistor T1. The fourth transistor T4 may have a structure in which two or more transistors are connected in series.

[0098] The fifth transistor T5 (first emitter control transistor) includes a gate terminal, a first terminal, and a second terminal. The gate terminal is connected to the emitter control line EL, the first terminal is connected to the drive voltage line PL, and the second terminal is connected to the first node N1. The sixth transistor T6 (second emitter control transistor) includes a gate terminal, a first terminal, and a second terminal. The gate terminal is connected to the emitter control line EL, the first terminal is connected to the third node N3, and the second terminal is connected to the pixel electrode of the organic light-emitting diode (OLED). The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the emitter control signal En transmitted through the emitter control line EL, and current flows through the OLED.

[0099] The seventh transistor T7 (second initialization transistor) includes a gate terminal, a first terminal, and a second terminal. The gate terminal is connected to the third scan line GL+1, the first terminal is connected to the second terminal of the sixth transistor T6 and the pixel electrode of the OLED, and the second terminal is connected to the initialization voltage line VL. The seventh transistor T7 can be turned on according to the third scan signal Gn+1 transmitted through the third scan line GL+1, and the voltage of the pixel electrode of the OLED can be initialized by transmitting the initialization voltage Vint to the pixel electrode of the OLED. The seventh transistor T7 can be omitted.

[0100] The capacitor Cst includes a first electrode and a second electrode, the first electrode being connected to a second node N2 and the second electrode being connected to a drive voltage line PL.

[0101] An organic light-emitting diode (OLED) may include pixel electrodes and a common electrode facing the pixel electrodes. The common electrode may receive a common voltage ELVSS. An OLED can display an image by receiving a drive current from a first transistor T1 and emitting light with a preset color. The common electrode may be provided publicly, i.e., it may be provided as a single entity to multiple sub-pixels.

[0102] Although Figure 4B The illustration shows the fourth transistor T4 and the seventh transistor T7 connected to the second scan line GL-1 and the third scan line GL+1, respectively, but the embodiment is not limited to this. In another embodiment, both the fourth transistor T4 and the seventh transistor T7 can be connected to the second scan line GL-1 and driven according to the second scan signal Gn-1.

[0103] Despite Figure 4A and Figure 4B The diagram shows that the transistors in the pixel circuit PC are P-type transistors, but the embodiments are not limited to this. As an example, the transistors in the pixel circuit PC can be N-type transistors, or some transistors can be P-type transistors and others can be N-type transistors. Various embodiments are possible.

[0104] Figure 4A and Figure 4B The pixel circuit is provided as an example, and the pixel circuit of pixel P according to the embodiment can be one of the various types of pixel circuits known.

[0105] Figure 5 This is a view showing a portion of the display panel according to an embodiment. Figure 6 It shows Figure 5 The timing diagram of the operation of the demultiplexer 142 shown is shown.

[0106] Figure 5 Pixel P is shown connected to scan line GLn-1 on row (n-1) and scan line GLn on row n. The i data lines ranging from the first data line DLk1 to the i-th data line DLki can be connected to the k-th source output line SLk. Demultiplexer 142 can be arranged between the k-th source output line SLk and the first data lines DLk1 to DLki. Demultiplexer 142 may include first switches SW1 to SW1i.

[0107] A first switch SW1 is disposed between the k-th source output line SLk and the first data line DLk1. The first switch SW1 may include a gate terminal, a first terminal, and a second terminal. The gate terminal is connected to a first control line CL1, the first terminal is connected to the k-th source output line SLk, and the second terminal is connected to the first data line DLk1. The first switch SW1 can be turned on according to a first control signal CS1 applied from the first control line CL1, and can apply the data signal DATA applied to the k-th source output line SLk to the first data line DLk1.

[0108] The second switch SW2 can be arranged between the k-th source output line SLk and the second data line DLk2. The second switch SW2 may include a gate terminal, a first terminal, and a second terminal. The gate terminal is connected to the second control line CL2, the first terminal is connected to the k-th source output line SLk, and the second terminal is connected to the second data line DLk2. The second switch SW2 can be turned on according to a second control signal CS2 applied from the second control line CL2, and can apply the data signal DATA applied to the k-th source output line SLk to the second data line DLk2.

[0109] The third switch SW3 can be arranged between the k-th source output line SLk and the third data line DLk3. The third switch SW3 may include a gate terminal, a first terminal, and a second terminal. The gate terminal is connected to the third control line CL3, the first terminal is connected to the k-th source output line SLk, and the second terminal is connected to the third data line DLk3. The third switch SW3 can be turned on according to a third control signal CS3 applied from the third control line CL3, and can apply the data signal DATA applied to the k-th source output line SLk to the third data line DLk3.

[0110] The data signal applied to each data line can be stored in a parasitic capacitor equivalent to that formed by the data line. The data signal stored in the parasitic capacitor of the data line can be supplied to pixel P according to the scan signal.

[0111] Since the connection and operation of the fourth switch SW4 (not shown), ..., the (i-1)th switch SWi-1 and the i-th switch SWi are the same as the connection and operation of the first switch SW1, the second switch SW2 and the third switch SW3, their description is omitted.

[0112] A sub-latch section 180 may be provided between a plurality of pixels P and demultiplexer 142. The sub-latch section 180 may include a plurality of latches 1801 to 180i-1. The number of switches within the demultiplexer 142 may be greater than the number of latches within the sub-latch section 180. The sub-latch section 180 may include a plurality of first latches 1801 to (i-1)th latches 180i-1, which are connected to the first data lines DLk1 to DLki-1 connected to the demultiplexer 142, excluding the DLki-1 first data line DLk1 to DLki-1 connected to the source output line SLk at the time the scan signal is applied via scan lines GL1 to GLn. As an example, the sub-latch section 180 may include a plurality of latches connected between the first data lines DLk1 to (i-1)th data lines DLki-1 corresponding to the first switches SW1 to i-th switches SWi, which are disconnected when a scan signal is applied through scan lines GL1 to GLn within the demultiplexer 142.

[0113] The sub-latch section 180 may include first latches 1801 to (i-1)th latches 180i-1, respectively, corresponding to the first data line DLk1 to the (i-1)th data line DLki-1. The input terminal IN of each of the first latches 1801 to the (i-1)th latches 180i-1 can be connected to the source output line SLk by a corresponding switch of the demultiplexer 142, and the output terminal OUT can be connected to the corresponding data line.

[0114] refer to Figure 6 Data drive 130 (see Figure 3 During the first time period t1, a data signal DATA corresponding to pixel P in the (n-1)th row is supplied, and during the second time period t2, a data signal DATA corresponding to pixel P in the nth row is supplied. Additionally, controller 150 (see...) Figure 3 The first control signal CS1, ..., the (i-1)th control signal CSi-1 to the i-th control signal CSi are sequentially supplied with the switch conduction voltage through the first control line CL1, ..., the (i-1)th control line CLi-1 and the i-th control line CLi.

[0115] During the first time period t1, a scan signal Gn-1 can be applied to pixel P in the (n-1)th row, and a data signal DATA stored in the first data line DLk1 to the i-th data line DLki can be applied to pixel P in the (n-1)th row. The scan signal Gn-1 follows the i-th control signal CSi, but the application duration of the scan signal Gn-1 can partially overlap with the application duration of the i-th control signal CSi.

[0116] During the second time period t2, a scan signal Gn can be applied to pixel P in the nth row, and a data signal DATA stored in the first data line DLk1 to the i-th data line DLki can be applied to pixel P in the nth row. The scan signal Gn follows the i-th control signal CSi, but the duration of the scan signal Gn can partially overlap with the duration of the i-th control signal CSi.

[0117] Each of the first data lines DLk1 to the i-th data line DLki may float when a data signal is applied to the other data lines among the first data lines DLk1 to the i-th data lines DLki. An embodiment may include a latch configured to maintain a constant voltage (e.g., the stored data signal) on each of the data lines connected to a source output line, except for the data lines biased at the moment a scan signal is applied to write the data signal to the pixel (i.e., each data line that floats at the moment a scan signal is applied to write the data signal to the pixel). While the data signal is applied to the other data lines, the latch may cause each data line to be biased without floating.

[0118] Figure 7 This is a view illustrating the operation of the demultiplexer according to an embodiment. Figure 8 It shows Figure 7 The timing diagram for the operation of the demultiplexer is shown. Figure 9 This is a view showing the operation of the demultiplexer according to the comparison example. Figure 10 It shows Figure 9 The timing diagram for the operation of the demultiplexer is shown. Figure 9 The comparative example shown is an example of a display panel where no latch is provided between the demultiplexer 142 and the data lines DLk1 and DLk2.

[0119] For ease of description, please refer to the following text. Figure 3 , Figure 5 as well as Figures 7-10 The demultiplexer 142 and the sub-latch section 180 connected to the k-th source output line SLk, the first data line DLk1, and the second data line DLk2 are described as an example when i=2.

[0120] Pixel P may include a first pixel Pr, a second pixel Pb, and a third pixel Pg that emit different colors of light. In an embodiment, a structure may be provided in which the first pixel Pr and the second pixel Pb are alternately arranged in the same column, and the third pixel Pg may be aligned with the column where the first pixel Pr and the second pixel Pb are arranged. The first pixel Pr may be a red pixel that emits red light, the second pixel Pb may be a blue pixel that emits blue light, and the third pixel Pg may be a green pixel that emits green light.

[0121] The first control signal CS1 and the second control signal CS2 can be applied alternately at different times to avoid overlapping. The data signal DATA may include a first data signal R applied to the first pixel Pr, a second data signal B applied to the second pixel Pb, and a third data signal G applied to the third pixel Pg.

[0122] During the first time period t1, the data driver 130 supplies the data signal DATA corresponding to the pixel P in the (n-1)th row. Additionally, the controller 150 sequentially supplies a first control signal CS1 and a second control signal CS2 for the switch on-state voltage.

[0123] When a low-level first control signal CS1 is applied, the first switch SW1 is turned on and the second switch SW2 is turned off. The k-th source output line SLk can be connected to the first data line DLk1, and the first data signal R applied to the first data line DLk1 can be stored in the first data line DLk1.

[0124] Next, when a low-level second control signal CS2 is applied, the second switch SW2 is turned on and the first switch SW1 is turned off. The k-th source output line SLk can be connected to the second data line DLk2, and the third data signal G applied to the second data line DLk2 can be stored in the second data line DLk2.

[0125] Following the second control signal CS2, a scan signal Gn-1 can be applied to pixel P in the (n-1)th row, a first data signal R pre-charged in the first data line DLk1 can be applied to the first pixel Pr, and a third data signal G applied to the second data line DLk2 can be applied to the third pixel Pg. The scan signal Gn-1 follows the second control signal CS2, but the application duration of the scan signal Gn-1 can partially overlap with the application duration of the second control signal CS2.

[0126] like Figure 9 and Figure 10As shown in the comparative example, while the scan signal Gn-1 is applied, the second data line DLk2 is biased because the third data signal G is applied to it, but the first data line DLk1 floats. Therefore, in the case of introduced external noise, the first data signal R of the floating first data line DLk1 may be affected by external noise (e.g., due to...). Figure 2 The image may be distorted due to noise (such as noise caused by the input sensing layer 40). Therefore, when the scan signal Gn-1 is applied, the distorted first data signal R may be applied to the first pixel Pr, and the image quality may be degraded.

[0127] Conversely, as in Figure 7 and Figure 8 As shown in the embodiment, when a low-level first control signal CS1 is applied from the controller 150, the k-th source output line SLk can be connected to the first data line DLk1, and the first data signal R can be applied to the sub-latch section 180 (due to...). Figure 7 and Figure 12 There is only one latch (hereinafter referred to as latch 180) with input terminal IN, and output terminal OUT of latch 180 can hold the first data signal R. Therefore, the first data line DLk1 can store the first data signal R. Simultaneously with the application of scan signal Gn-1, because the third data signal G is applied to the second data line DLk2, the second data line DLk2 is biased, and the first data line DLk1 can be biased through latch 180. Therefore, even if external noise is introduced, the influence of noise on the first data signal R of the first data line DLk1 can be reduced, and thus, distortion of the first data signal R can be reduced or prevented.

[0128] Similarly, during the second time period t2, the data driver 130 supplies the data signal DATA corresponding to the pixel P on the nth row. Additionally, the controller 150 sequentially supplies a first control signal CS1 and a second control signal CS2 for the switch on-state voltage.

[0129] When a low-level first control signal CS1 is applied, the first switch SW1 is turned on and the second switch SW2 is turned off. The k-th source output line SLk can be connected to the first data line DLk1, and the second data signal B applied to the first data line DLk1 can be stored in the first data line DLk1.

[0130] Next, when a low-level second control signal CS2 is applied, the second switch SW2 is turned on and the first switch SW1 is turned off. The k-th source output line SLk can be connected to the second data line DLk2, and the third data signal G applied to the second data line DLk2 can be stored in the second data line DLk2.

[0131] Following the second control signal CS2, a scan signal Gn can be applied to pixel P in the nth row, a second data signal B pre-charged in the first data line DLk1 can be applied to the second pixel Pb, and a third data signal G applied to the second data line DLk2 can be applied to the third pixel Pg. The scan signal Gn follows the second control signal CS2, but the application duration of the scan signal Gn can partially overlap with the application duration of the second control signal CS2.

[0132] like Figure 9 and Figure 10 As shown in the comparative example, while the scan signal Gn is applied, the third data signal G is applied to the second data line DLk2, and thus the second data line DLk2 is biased, but the first data line DLk1 floats. Therefore, in the case of introduced external noise, the second data signal B of the floating first data line DLk1 may be distorted due to the influence of external noise. Therefore, when the scan signal Gn is applied, the distorted second data signal B may be applied to the second pixel Pb, and thus, the image quality may be degraded.

[0133] Conversely, as in Figure 7 and Figure 8 As shown in the embodiment, when a low-level first control signal CS1 is applied from the controller 150, the k-th source output line SLk can be connected to the first data line DLk1, the second data signal B is applied to the input terminal IN of the latch 180, and the output terminal OUT of the latch 180 can hold the second data signal B. Therefore, the first data line DLk1 can store the second data signal B. Simultaneously with the application of the scan signal Gn, a third data signal G is applied to the second data line DLk2, and thus, the second data line DLk2 can be biased, and the first data line DLk1 can be biased by the latch 180. Therefore, even if external noise is introduced, the impact of noise on the second data signal B of the first data line DLk1 can be reduced, and thus, distortion of the second data signal B can be reduced or prevented.

[0134] Figure 11 and Figure 12 This is a view showing the demultiplexer of the display panel and a portion of its surroundings according to an embodiment.

[0135] Figure 11 The embodiment illustrates a demultiplexer 142 and a sub-latch section 180 connected to the k-th source output line SLk and the first data line DLk1, the second data line DLk2, and the third data line DLk3 when i=3. The demultiplexer 142 includes a first switch SW1, a second switch SW2, and a third switch SW3.

[0136] In the display area DA (seeFigure 1 In this configuration, the first pixel Pr can be arranged in the first column, the second pixel Pb can be arranged in the second column, and the third pixel Pg can be arranged in the third column. According to an embodiment, the columns in which the first pixel Pr, the second pixel Pb, and the third pixel Pg are arranged can be changed.

[0137] The first control signal CS1, the second control signal CS2, and the third control signal CS3 can be applied alternately at different times to avoid overlapping. As an example, the first control signal CS1, the second control signal CS2, and the third control signal CS3 can be applied sequentially. The first data signal R can be applied to the first pixel Pr, the second data signal B can be applied to the second pixel Pb, and the third data signal G can be applied to the third pixel Pg.

[0138] The first switch SW1 can be arranged between the k-th source output line SLk and the first data line DLk1, and is turned on according to the first control signal CS1 applied from the first control line CL1, and can apply the first data signal R applied through the k-th source output line SLk to the first data line DLk1.

[0139] The second switch SW2 can be arranged between the k-th source output line SLk and the second data line DLk2, and is turned on according to the second control signal CS2 applied from the second control line CL2, and can apply the second data signal B applied through the k-th source output line SLk to the second data line DLk2.

[0140] The third switch SW3 can be arranged between the k-th source output line SLk and the third data line DLk3. It is turned on according to the third control signal CS3 applied from the third control line CL3, and the third data signal G applied through the k-th source output line SLk can be applied to the third data line DLk3.

[0141] When scan signals Gn-1 and Gn are applied, the third data signal G is applied to the third data line DLk3, and the first data signal R and the second data signal B can be applied to the first data line DLk1 and the second data line DLk2 respectively through latches 1801 and 1802.

[0142] The above embodiment includes latches (e.g., latches 1801 and 1802) corresponding to (i-1) data lines (e.g., three data lines DLk1, DLk2 and DLk3) that are connected to a source output line (e.g., the k-th source output line SLk) and float at the moment when a scan signal is applied to write a data signal (e.g., data signal R, B or G) to a pixel (e.g., pixel Pr, Pb or Pg).

[0143] In another embodiment, as Figure 12 shown, pixels with low visibility of brightness change (e.g., the second data line DLk2 of the column on which the second pixel Pb is arranged) may not be connected to the latch. In this case, since the latch 180 is only connected to the first data line DLk1 of the column on which the first pixel Pr is arranged, the circuit complexity can be reduced without deteriorating the image quality.

[0144] Figure 13A , Figure 13B , Figure 13C and Figure 13D are circuit diagrams of latches showing the sub-latch part according to an embodiment.

[0145] Referring to Figure 13A , each latch of the sub-latch part 180a may include a capacitor Cs and an operational amplifier OP. The first terminal ((-) terminal or first input terminal) of the operational amplifier OP may be connected to the output terminal of the operational amplifier OP, and the second terminal ((+) terminal or second input terminal) may be connected to the source output line by connecting to the input terminal IN of the latch. The output terminal of the operational amplifier OP may be the output terminal OUT of the latch. The input terminal IN may be connected to the source output line by connecting to one terminal of a switch connected to the source output line. The output terminal OUT may be connected to the data line. The capacitor Cs may be connected between the input terminal IN (the second terminal of the operational amplifier OP) and the power supply part. The power supply part may supply a driving voltage ELVDD or a common voltage ELVSS. Figure 13A The latch of

[0146] As Figure 13B shown, each latch of the sub-latch part 180b may include an operational amplifier OP whose gain is not 1. A resistor R1 and a resistor R2 may be respectively connected between the first terminal ((-) terminal) of the operational amplifier OP and the power supply part and between the first terminal ((-) terminal) of the operational amplifier OP and the output terminal of the operational amplifier OP (the output terminal OUT of the latch). The power supply part connected to the first terminal ((-) terminal) may supply the common voltage ELVSS.

[0147] The embodiment is not limited to the above-mentioned sub-latch parts 180a and 180b and various circuits that can be used as analog latches may be used.

[0148] Figure 13C and Figure 13DThe diagram illustrates, as an example, a demultiplexer connected to the k-th source output line SLk and the first data line DLk1 and the second data line DLk2 when i=2, along with sub-latch sections 180c and 180d connected to the demultiplexer. The demultiplexer may include a first switch SW1 and a second switch SW2, where the first switch SW1 is connected to the k-th source output line SLk and the first data line DLk1, and the second switch SW2 is also connected to the k-th source output line SLk and the second data line DLk2. The second switch SW2 can be turned on at the moment a scan signal is applied to write the data signal DATA to the pixel, thus connecting the k-th source output line SLk to the second data line DLk2. In this case, a latch may be connected between the first data line DLk1 and the first switch SW1. That is, a latch may be connected between the k-th source output line SLk and the first data line DLk1.

[0149] refer to Figure 13C Each latch in the sub-latch section 180c can be connected to a first data line DLk1 and a first switch SW1, and may include a capacitor Cs and an operational amplifier OP. The first terminal ((-) terminal or first input terminal) of the operational amplifier OP can be connected to the output terminal of the operational amplifier OP, and the second terminal ((+) terminal or second input terminal) can be connected to the k-th source output line SLk via the input terminal IN of the latch. The output terminal of the operational amplifier OP can be the output terminal OUT of the latch. The input terminal IN can be connected to the k-th source output line SLk via a terminal of the first switch SW1 connected to the k-th source output line SLk. The output terminal OUT can be connected to the first data line DLk1. The capacitor Cs can be connected between the input terminal IN (the second terminal of the operational amplifier OP) and the power supply section. The power supply section can supply a drive voltage ELVDD or a common voltage ELVSS (see...). Figure 13A ).

[0150] The sub-latch section 180c may further include a first latching transistor TL1. The first latching transistor TL1 may be connected between the input terminal IN (the second terminal of the operational amplifier OP) and the output terminal OUT (the output terminal of the operational amplifier OP) of the latch. The gate terminal of the first latching transistor TL1 may be connected to a first control line CL1 connected to the gate terminal of the first switch SW1, and may be turned on according to a first control signal CS1. The data signal DATA may be directly applied to the first data line DLk1 through the first latching transistor TL1. The sub-latch section 180c may reduce the duration required to charge the capacitor of the first data line DLk1 by using the capacitor Cs, the operational amplifier OP, and the first latching transistor TL1 to charge the capacitor of the first data line DLk1. In another embodiment, the gate terminal of the first latching transistor TL1 may be connected to a control line configured to apply a separate control signal.

[0151] refer to Figure 13D ,and Figure 13C Compared to the sub-latch section 180c shown, the sub-latch section 180d may further include a second latch transistor TL2. The second latch transistor TL2 may be connected between the second terminal of the operational amplifier OP and the k-th source output line SLk (or the input terminal IN of the latch). The gate terminal of the second latch transistor TL2 may be connected to the second control line CL2, which is connected to the gate terminal of the second switch SW2, and is turned on according to the second control signal CS2. That is, the second latch transistor TL2 can be turned on when a scan signal is applied through the scan line.

[0152] When the first latching transistor TL1 applies the data signal DATA to the first data line DLk1, the second latching transistor TL2 is turned off, and therefore, the operation of the operational amplifier OP can be prevented. Thus, the capacitor of the first data line DLk1 can be charged only by the first latching transistor TL1. The second latching transistor TL2 can be turned on while the capacitor of the second data line DLk2 is being charged, and can operate the operational amplifier OP, thereby applying a bias voltage to the first data line DLk1. Figure 13C Compared to the sub-latch section 180c shown, Figure 13D The sub-latch portion 180d shown can reduce the power consumption of the display panel. In another embodiment, the gate terminal of the second latch transistor TL2 can be connected to a control line configured to apply a separate control signal.

[0153] Figure 13C and 13D It shows including Figure 13A An example of a latch is shown. In another embodiment, such as... Figure 13CThe diagram may further provide a first latching transistor TL1, or as shown Figure 13D The diagram shows that can be directed to Figure 13B The latch shown further provides a first latch transistor TL1 and a second latch transistor TL2.

[0154] The embodiment includes a latch that floats in the data line at the moment a scan signal writing data signals to the pixels is applied, and thus the data line can be biased in a display device including an (n:1) demultiplexer, wherein the switches of the demultiplexer are sequentially turned on to sequentially apply data signals. Therefore, voltage corresponding to the data signals charged in the data lines can be prevented from being distorted by external noise. That is, according to the embodiment, there is no floating data line when data signals are sequentially applied to the data lines connected to the demultiplexer, and therefore, the influence of external noise on the data signals can be reduced.

[0155] According to the embodiments, the number of output lines of the data driver is reduced, and therefore, the manufacturing cost of the display device can be reduced. Additionally, according to the embodiments, image quality degradation of the display device caused by external noise introduced through the data lines can be reduced. However, this disclosure is not limited to these effects.

[0156] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention.

Claims

1. A display device, wherein, The display device includes: The pixel portion comprises a plurality of pixels arranged therein, each of the plurality of pixels being connected to a scan line and a data line; The source output line is where the data signal is transmitted; A data driver configured to convert an image signal into a data signal and transmit the data signal to the source output line; A data distributor configured to selectively connect the source output line to n data lines, where n is a positive integer greater than or equal to 2; and A latch section is disposed between the data distributor and the pixel section. The latch section includes n-1 latches, which are connected to n-1 of the n data lines. Specifically, the n-1 data lines receive data signals from the n-1 latches at the moment the scan signal is transmitted to the scan line. These data signals are input from the source output line to the n-1 latches via the data distributor before the moment the scan signal is transmitted to the scan line. Of the n data lines, all except the n-1 data lines receive data signals from the source output line via the data distributor at the moment when the scan signal is transmitted to the scan line.

2. The display device according to claim 1, wherein, Each of the n-1 latches includes: An amplifier, the amplifier including a first input terminal connected to the source output line and an output terminal connected to a corresponding data line among the n-1 data lines; and A capacitor is connected between the first input terminal and the power supply section.

3. The display device according to claim 2, wherein, The power supply section applies a first power supply voltage and a second power supply voltage to each of the plurality of pixels.

4. The display device according to claim 2, wherein, The amplifier further includes a second input terminal connected to the output terminal.

5. The display device according to claim 4, wherein, The latch further includes: A first resistor between the second input terminal of the amplifier and the power supply section; and a second resistor between the second input terminal and the output terminal.

6. The display device according to claim 4, wherein, The latch further includes a first transistor connected between the first input terminal and the output terminal of the amplifier.

7. The display device according to claim 6, wherein, The first transistor is turned on when the corresponding data line is connected to the source output line.

8. The display device according to claim 6, wherein, The latch further includes a second transistor connected between the first input terminal of the amplifier and the source output line.

9. The display device according to claim 8, wherein, The first transistor turns on when the corresponding data line is connected to the source output line, and The second transistor is turned on at the moment the scan signal is transmitted to the scan line.

10. The display device according to claim 1, wherein, The pixels include red pixels, blue pixels, and green pixels. The red pixels are connected to a first data line in a first column, the blue pixels are connected to a second data line in a second column, and the green pixels are connected to a third data line in a third column. The latch section includes a first latch and a second latch, the first latch being connected to the first data line and the second latch being connected to the second data line.

11. The display device according to claim 1, wherein, The pixels include red pixels, blue pixels, and green pixels. The red pixels are connected to a first data line in a first column, the blue pixels are connected to a second data line in a second column, and the green pixels are connected to a third data line in a third column. The latch section includes a latch connected to the first data line.

12. The display device according to claim 1, wherein, The data distributor includes multiple switches, and Each of the plurality of switches is connected between the corresponding data line among the n data lines and the source output line.

13. A display device, wherein, The display device includes: Multiple pixels, each of which is connected to a scan line and a data line; The source output line is where the data signal is transmitted; A demultiplexer, comprising multiple switches connected to the source output line and n data lines, where n is a positive integer greater than or equal to 2; and n-1 latches are arranged between the demultiplexer and n-1 of the n data lines. Specifically, the n-1 data lines receive data signals from the n-1 latches at the moment the scan signal is transmitted to the scan line. Prior to the moment the scan signal is transmitted to the scan line, the data signals are input from the source output line to the n-1 latches via corresponding switches among the plurality of switches. The data lines other than the n-1 data lines among the n data lines receive data signals from the source output line through the corresponding switches among the plurality of switches at the moment when the scan signal is transmitted to the scan line.

14. The display device according to claim 13, wherein, Each of the n-1 latches includes: An amplifier, the amplifier including a first input terminal connected to the source output line and an output terminal connected to a corresponding data line among the n data lines; and A capacitor, the capacitor being connected between the first input terminal and the power supply section, and The power supply section applies a first power supply voltage and a second power supply voltage to each of the plurality of pixels.

15. The display device according to claim 14, wherein, The amplifier further includes a second input terminal connected to the output terminal.

16. The display device according to claim 15, wherein, The latch further includes a first resistor between the second input terminal of the amplifier and the power supply section, and a second resistor between the second input terminal and the output terminal.

17. The display device according to claim 15, wherein, The latch further includes a first transistor connected between the input terminal and the output terminal of the amplifier.

18. The display device according to claim 17, wherein, The first transistor is turned on when the corresponding data line is connected to the source output line.

19. The display device according to claim 17, wherein, The latch further includes a second transistor connected between the first input terminal of the amplifier and the source output line.

20. The display device according to claim 19, wherein, The first transistor turns on when the corresponding data line is connected to the source output line, and The second transistor is turned on when the scan signal is transmitted to the scan line.

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