Display panel, driving method thereof, driving circuit and display device

Abstract

This invention proposes a display panel and its driving method, driving circuit, and display device. The display panel includes multiple scan lines, multiple data lines, and pixel circuits arranged in an array. The pixel circuit includes a light-emitting unit, a light-emitting driving unit, a storage capacitor, a data switch, a logic circuit, a switching circuit, and a first reset switch. The logic circuit performs an AND operation on the input row scan signal and data signal, and outputs a corresponding first level signal or second level signal to the switching circuit and the first reset switch, thereby controlling the first reset switch to reset and turn the driving transistor on or off during the sampling period to write the data signal of the next frame or maintain the data signal of the previous frame. During the light-emitting period, the driving transistor is triggered by the light emission signal to output a current signal to drive the light-emitting unit to emit light. It can control the corresponding pixel circuit to maintain the current screen and switch the display screen, and can realize independent control of a single pixel circuit to meet the display requirements of different refresh rates.

Description

Technical Field

[0001] This invention belongs to the field of display panel technology, and particularly relates to a display panel and its driving method, driving circuit and display device. Background Technology

[0002] Compared to traditional LCD devices, OLED (Organic Light-Emitting Diode) display panels have advantages in thinness, brightness, contrast, and color that are difficult to surpass through process design improvements. They are widely used in electronic terminals such as mobile phones and tablets. However, these terminals often use energy storage devices such as batteries and are quite sensitive to power consumption. In order to pursue higher display effects, they usually use higher refresh rates, which conflicts with the need for low power consumption.

[0003] Based on this, modern display technology has developed a partitioned refresh scheme on top of full-screen high refresh rate. The usual approach is to adjust the timing of multiple GOA (Gate Driver On Array) units of the gate driver circuit, and divide the refresh rate blocks in the refresh direction on a row-by-row basis.

[0004] To achieve this, the timing controller must precisely adjust the switching time of the GOA unit, which increases power consumption to some extent. In addition, there are obvious limitations. In the gate drive circuit, the GOA unit controls the screen in units of at least one line. However, the local adjustment of the refresh rate based on changes in screen content is complex. For example, it is not possible to achieve different refresh rates when different positions of the same line appear on the screen. Summary of the Invention

[0005] The purpose of this invention is to provide a display panel that solves the problem that the driving architecture in traditional display devices cannot meet the different refresh rate requirements of different locations.

[0006] A first aspect of this invention provides a display panel including multiple scan lines, multiple data lines, and an array of pixel circuits, wherein the pixel circuits include: A light-emitting driving unit is connected in series with the light-emitting unit between the anode voltage terminal and the cathode voltage terminal. The light-emitting driving unit includes a first light-emitting switch, a driving tube, and a second light-emitting switch connected in series. The first light-emitting switch and the second light-emitting switch are triggered to conduct by the light emission signal during the light emission period. Storage capacitor; A data switch is connected to the input terminals of the data line, the scan line, and the driving transistor, respectively. The data switch is triggered to turn on by a row open signal and transmits the data signal on the data line to the input terminal of the driving transistor, and is triggered to turn off by a row close signal. A logic circuit, connected to the data line and the scan line respectively, is used to trigger the output of a first level signal when the row enable signal and the data signal are received simultaneously, and otherwise output a second level signal. The first reset switch is connected to the first reset terminal, the output terminal of the logic circuit, and the control terminal of the driving transistor, respectively. The first reset switch is triggered to turn on by the first level signal and transmits the first reset signal to control the driving transistor to turn on, and is triggered to turn off by the second level signal. A switching circuit is connected to the anode voltage terminal, the first and second terminals of the storage capacitor, and the control and output terminals of the driving transistor, respectively. The switching circuit is triggered by the first level signal to form a first path and triggered by the row-off signal to form a second path. The first path consists of the anode voltage terminal, the second terminal of the storage capacitor, the first terminal of the storage capacitor, and the output terminal of the driving transistor. The second path consists of the anode voltage terminal, the first terminal of the storage capacitor, the second terminal of the storage capacitor, and the control terminal of the driving transistor.

[0007] Optionally, the switching circuit includes: The first switching circuit is connected to the first terminal of the storage capacitor, the second terminal of the storage capacitor, the anode voltage terminal, the scan line and the logic circuit respectively. The first switching circuit is used to connect the anode voltage terminal and the first terminal of the storage capacitor when a row close signal is received, or to connect the anode voltage terminal and the second terminal of the storage capacitor when the first level signal is received, or to turn off when the row open signal and the second level signal are received. The second switching circuit is connected to the first terminal of the storage capacitor, the second terminal of the storage capacitor, the control terminal of the driving transistor, the output terminal of the driving transistor, the scan line, and the logic circuit, respectively. The second switching circuit is used to connect the output terminal of the driving transistor and the first terminal of the storage capacitor when the first level signal is received, or to connect the second terminal of the storage capacitor and the control terminal of the driving transistor when the row close signal is received, or to turn off when the second level signal and the row open signal are received.

[0008] Optionally, the first switching circuit includes a first transistor and a second transistor; The first terminal of the first transistor, the first terminal of the second transistor, and the anode voltage terminal are connected. The second terminal of the first transistor is connected to the first terminal of the storage capacitor. The second terminal of the second transistor is connected to the second terminal of the storage capacitor. The control terminal of the first transistor is connected to the scan line. The control terminal of the second transistor is connected to the output terminal of the logic circuit. The second switching circuit includes a third transistor and a fourth transistor; The first terminal of the third transistor is connected to the first terminal of the storage capacitor, the first terminal of the fourth transistor is connected to the second terminal of the storage capacitor, the second terminal of the third transistor is connected to the output terminal of the driving transistor, the second terminal of the fourth transistor is connected to the control terminal of the driving transistor, the control terminal of the third transistor is connected to the output terminal of the logic circuit, and the control terminal of the fourth transistor is connected to the scan line.

[0009] Optionally, the logic circuit includes a NOR gate and an OR gate, the first input terminal of the NOR gate is connected to the data line, the second input terminal of the NOR gate, the first input terminal of the OR gate and the scan line are connected, the output terminal of the NOR gate is connected to the second input terminal of the OR gate, and the output terminal of the OR gate constitutes the output terminal of the logic circuit.

[0010] Optionally, the pixel circuit further includes: The second reset switch has a first terminal for inputting a second reset signal, a second terminal connected to the light-emitting unit, and a control terminal connected to the scan line. The second reset switch is triggered to turn on by the row enable signal and triggered to turn off by the row disable signal.

[0011] A second aspect of this invention provides a driving method for a display panel, used to drive the display panel as described above, the driving method comprising: Determine whether the content of the next frame of the target partial image on the display panel has changed; When the content of the next frame of the target partial image remains unchanged, switch to the maintenance mode, and when the next frame is scanned, output the corresponding row enable signal and do not output data signal to the target pixel circuit corresponding to the target partial image, and control the control terminal of the driving transistor of the target pixel circuit to maintain the data signal of the previous frame. When the content of the next frame of the target partial image changes, the system switches to the working mode. During the scanning drive of the next frame, the system outputs the corresponding data signal and the line opening signal to the target pixel circuit corresponding to the target partial image, and controls the control terminal of the driving transistor of the target pixel circuit to input the data signal of the current frame.

[0012] Optionally, the step of switching to a maintenance mode when the content of the next frame of the target partial image remains unchanged, and outputting a corresponding row enable signal and not outputting a data signal to the target pixel circuit corresponding to the target partial image during the next frame scan drive, includes: During the sampling period of the sustain mode, a row enable signal is output to the scan line, and no data signal is output to the data line; During the light emission period of the maintenance mode, a row turn-off signal is output to the scan line, and a data signal corresponding to the next row pixel circuit is output to the data line or no data signal is output to the data line.

[0013] Optionally, when the content of the next frame of the target partial image changes, switching to the working mode, and outputting the corresponding data signal and the line opening signal to the target pixel circuit corresponding to the target partial image during the scanning drive of the next frame, includes: During the sampling period of the operating mode, a row enable signal is output to the scan line and a data signal is output to the data line; During the light emission period of the operating mode, no row activation signal is output to the scan line, and no data signal is output to the data line corresponding to the next row pixel circuit.

[0014] A third aspect of the present invention provides a driving circuit for a display panel, including a source driving circuit, a gate driving circuit, and a timing controller. The source driving circuit is connected to multiple data lines of the display panel, and the gate driving circuit is connected to multiple scan lines of the display panel. The timing controller is connected to the source driving circuit and the gate driving circuit respectively. The timing controller is used to output control signals to the source driving circuit and the gate driving circuit to realize the display panel driving method described above.

[0015] A fourth aspect of the present invention provides a display device, including a display panel as described above and a driving circuit for the display panel as described above, wherein the driving circuit for the display panel is connected to the display panel.

[0016] The beneficial effects of the present invention embodiments compared with the prior art are as follows: The above-mentioned display panel includes multiple scan lines, multiple data lines, and pixel circuits arranged in an array. The pixel circuit includes a light-emitting unit, a light-emitting driving unit, a storage capacitor, a data switch, a logic circuit, a switching circuit, and a first reset switch. The logic circuit performs an AND operation on the input row scan signal and data signal, and outputs a corresponding first level signal or a second level signal to the switching circuit and the first reset switch, thereby controlling the first reset switch to reset and turn on or off the driving transistor during the sampling period to write the data signal of the next frame or control the storage capacitor and the driving transistor to maintain the data signal of the previous frame. During the light-emitting period, the light emission signal triggers the driving transistor to output a current signal to drive the light-emitting unit to emit light. By selecting whether to input data signals and row scan signals to the data lines and scan lines, the corresponding pixel circuit can be controlled to maintain the current screen and switch the display screen. Independent control of a single pixel circuit can be realized to meet the display requirements of different refresh rates. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a first structure of a display panel provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of a second structure of the display panel provided in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of a first type of pixel circuit provided in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the first signal timing of the pixel circuit provided in Embodiment 1 of the present invention; Figure 5 This is a second signal timing diagram of the pixel circuit provided in Embodiment 1 of the present invention; Figure 6 This is a schematic diagram of the third signal timing of the pixel circuit provided in Embodiment 1 of the present invention; Figure 7 This is a second circuit diagram of the pixel circuit provided in Embodiment 1 of the present invention; Figure 8 This is a schematic diagram of a third type of pixel circuit provided in Embodiment 1 of the present invention; Figure 9 This is a circuit diagram of the pixel circuit provided in Embodiment 2 of the present invention; Figure 10 This is a flowchart illustrating the driving method for the display panel provided in Embodiment 3 of the present invention; Figure 11 for Figure 10 The flowchart of step S20 of the driving method for the display panel is shown. Figure 12 for Figure 10 The flowchart of step S30 of the driving method for the display panel is shown. Figure 13 The diagram shows the structure of the driving circuit and display device of the display panel provided in Embodiments 4 and 5 of the present invention.

[0018] The figures in the diagram are labeled as follows: 100. Display panel; 200. Driving circuit for display panel; 210. Source driving circuit; 220. Gate driving circuit; 230. Timing controller; 10. Pixel circuit; 20. Light-emitting unit; 11. Light-emitting driving unit; 101. First light-emitting switch; 102. Second light-emitting switch; 12. Data switch; 13. Logic circuit; 14. First reset switch; 15. Switching circuit; 16. Second reset switch; SD, driver transistor; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; Cst, storage capacitor; OLED, light-emitting diode; S1, first data line; S2, second data line; S3, third data line; S4, fourth data line; G1, first scan line; G2, second scan line; G3, third scan line; G4, fourth scan line; G5, fifth scan line; G6, sixth scan line; U1, NOR gate; U2, OR gate; VDD, Anode voltage; VSS, Cathode voltage; Da, Data signal; Sc, Horizontal scan signal; Sc1, First horizontal scan signal; Sc2, Second horizontal scan signal; Sc3, Third horizontal scan signal; Da1, First data signal; Da2, Second data signal; Da3, Third data signal; Vint, First reset signal; VI, Second reset signal; EM, Light emission signal; VGH, Horizontal enable signal; VGL, Horizontal disable signal; EN, Output level of logic circuit; Q, Voltage at the control terminal of the driver transistor; t11, sampling period of the first frame; t12, emission period of the first frame; t21, sampling period of the second frame; t22, emission period of the second frame. Detailed Implementation

[0019] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0021] Example 1 A first aspect of the present invention provides a display panel 100, such as... Figure 1 and Figure 2 As shown, it includes multiple scan lines, multiple data lines, and an array of pixel circuits 10, for example... Figure 1 As shown, the multiple scan lines include a first scan line G1, a second scan line G2, a third scan line G3, a fourth scan line G4, a fifth scan line G5, and a sixth scan line G6, and the multiple data lines include a first data line S1, a second data line S2, a third data line S3, and a fourth data line S4. The pixel circuit 10 is connected to one scan line and one data line respectively, for example... Figure 2 As shown, the pixel circuit 10 in the first row and first column is connected to the first scan line G1 and the first data line S1 and inputs the first row scan signal Sc1 and the first data signal Da1. The pixel circuit 10 in the second row and second column is connected to the second scan line G2 and the second data line S2 and inputs the second row scan signal Sc2 and the second data signal Da2. The pixel circuit 10 in the third row and third column is connected to the third scan line G3 and the third data line S3 and inputs the third row scan signal Sc3 and the third data signal Da3. The pixel circuit 10 is used to generate a current signal to the light-emitting unit 20 inside the pixel circuit 10 according to the received row scan signal Sc and data signal Da, and the light-emitting unit 20 lights up accordingly.

[0022] In order to achieve independent control of each pixel circuit 10 or the target pixel circuit of the target local image, and to meet the requirements of different refresh rates, such as Figure 3 As shown, in this embodiment, the pixel circuit 10 includes: The light-emitting driving unit 11 is connected in series with the light-emitting unit 20 between the anode voltage terminal and the cathode voltage terminal. The light-emitting driving unit 11 includes a first light-emitting switch 101, a driving tube SD and a second light-emitting switch 102 connected in series. The first light-emitting switch 101 and the second light-emitting switch 102 are triggered to conduct by the light emission signal EM during the light emission period. Storage capacitor Cst; Data switch 12 is connected to the input terminals of the data line, the scan line and the drive transistor SD respectively. Data switch 12 is triggered to turn on by the horizontal turn-on signal VGH and transmits the data signal Da on the data line to the input terminal of the drive transistor SD, and is triggered to turn off by the horizontal turn-off signal VGL. Logic circuit 13 is connected to the data line and the scan line respectively, and is used to trigger the output of a first level signal when the row enable signal VGH and the data signal Da are received simultaneously; otherwise, it outputs a second level signal. The first reset switch 14 is connected to the first reset terminal, the output terminal of the logic circuit 13 and the control terminal of the drive transistor SD respectively. The first reset switch 14 is triggered to turn on by the first level signal and transmits the first reset signal Vint to control the drive transistor SD to turn on, and is triggered to turn off by the second level signal. The switching circuit 15 is connected to the anode voltage terminal, the first and second terminals of the storage capacitor Cst, and the control and output terminals of the driving transistor SD. The switching circuit 15 is triggered by a first level signal to form a first path and triggered by a row turn-off signal VGL to form a second path. The first path is the anode voltage terminal, the second terminal of the storage capacitor Cst, the first terminal of the storage capacitor Cst, and the output terminal of the driving transistor SD. The second path is the anode voltage terminal, the first terminal of the storage capacitor Cst, the second terminal of the storage capacitor Cst, and the control terminal of the driving transistor SD.

[0023] In this embodiment, the anode voltage terminal is used to input the anode voltage VDD, and the cathode voltage terminal is used to input the cathode voltage VSS. The anode voltage VDD is greater than the cathode voltage VSS. The anode voltage terminal, the light-emitting driving unit 11, the light-emitting unit 20 and the cathode voltage terminal are connected in sequence.

[0024] The driving transistor SD can be a P-channel thin-film transistor or an N-channel thin-film transistor. The line scan signal Sc consists of a line enable signal VGH and a line disable signal VGL. In each frame, each pixel circuit 10 can work sequentially in the sampling period and the emission period. When the current frame is scanned to the pixel circuit 10 of the corresponding line, during the sampling period, the line enable signal VGH is input to the scan line connected to the corresponding pixel circuit 10, and the data line connected to the corresponding pixel circuit 10 inputs the data signal Da or does not input the data signal Da. During the emission period, the line disable signal VGL is input to the corresponding scan line. At the same time, the pixel circuit 10 receives the light emission signal EM and generates a current signal to the light-emitting unit 20, and drives the light-emitting unit 20 to light up.

[0025] The pixel circuit 10 can switch between working mode and holding mode according to the received data signal Da and line scan signal Sc. The working mode can refresh the input data signal Da, and the holding mode can retain the data signal Da of the previous frame.

[0026] In progressive scan, when scanning to a number of pixel circuits 10 of a target local image, the number of target pixel circuits may include one or more.

[0027] refer to Figure 4As shown, Q represents the voltage at the control terminal of the driving transistor SD, and EN represents the output level of logic circuit 13. In the working mode, during the sampling period of pixel circuit 10, such as the sampling period t11 of the first frame, when scanning to the row where pixel circuit 10 is located, the scan line connected to pixel circuit 10 inputs the row enable signal VGH, and the data line connected to pixel circuit 10 inputs the data signal Da. Logic circuit 13 outputs a first level signal to switch circuit 15 and first reset switch 14. First reset switch 14 is turned on, and the first reset signal Vint is transmitted to the control terminal of driving transistor SD through first reset switch 14. The voltage of the first reset signal Vint is less than the data voltage, so driving transistor SD is reset and turned on. At the same time, switch circuit 15 receives the first level signal and forms the first... One path is formed by connecting the anode voltage terminal, the second terminal of the storage capacitor Cst, the first terminal of the storage capacitor Cst, and the output terminal of the driving transistor SD. That is, the anode voltage terminal and the second terminal of the storage capacitor Cst are connected, and the first terminal of the storage capacitor Cst is connected to the output terminal of the driving transistor SD. When the data switch 12 receives the row enable signal VGH, it is triggered to conduct. The data signal Da is written to the storage capacitor Cst through the driving transistor SD and the switching circuit 15. According to Kirchhoff's law, the potential difference of the storage capacitor Cst is Vdata + Vth - VDD, where Vth is the threshold voltage of the driving transistor SD and Vdata is the data voltage of the data signal Da. The pixel circuit 10 completes the data writing of the data signal Da and the sampling of the driving transistor SD.

[0028] Then, during the light emission period, such as the light emission period t12 of the first frame, when the scanning of this line ends and no data signal Da is input to other lines, the scan line connected to pixel circuit 10 inputs the line close signal VGL, the data line connected to pixel circuit 10 does not input the data signal Da, logic circuit 13 outputs the second level signal, the first reset switch 14 is turned off, and when the switch circuit 15 receives the line close signal VGL, a second path is formed. The second path is the anode voltage terminal, the first terminal of storage capacitor Cst, the second terminal of storage capacitor Cst, and the control terminal of driving transistor SD. That is, the anode voltage terminal is connected to the first terminal of storage capacitor Cst, and the second terminal of storage capacitor Cst is connected to the control terminal of driving transistor SD. At this time, the potential of the control terminal of driving transistor SD is the sum of the potential difference written during the sampling period and the anode voltage VDD, that is, the potential of the control terminal of driving transistor SD is Vdata + Vth - VDD + VDD = Vdata + Vth. When the input light emission signal EM is received, the first light emission switch 101 and the second light emission switch 102 are turned on. The voltage at the control terminal of the driving transistor SD and the gate-source voltage at the input terminal are Vdata + Vth - VDD, where the data voltage is less than the anode voltage VDD. Correspondingly, the gate-source voltage is less than the threshold voltage of the driving transistor SD, so the driving transistor SD can be turned on normally. The driving transistor SD enters the saturation region and converts the data voltage into a current signal, I = (1 / 2) * K * (Vdata - VDD)², where K is the proportional coefficient and I represents the current signal. There is no variable of threshold voltage in the current signal, thus eliminating the influence of threshold voltage. The anode voltage terminal, the first light emission switch 101, the driving transistor SD and the second light emission switch 102 form a current path. The driving transistor SD generates a current signal and outputs it to the light-emitting unit 20 through the second light emission switch 102. The light-emitting unit 20 displays the grayscale data of the sampling stage and emits light normally, achieving a high refresh rate.

[0029] Alternatively, during the light emission period, when scanning downlink, the data line switches to input data signal Da due to the downlink data signal Da. At this time, the scan line connected to pixel circuit 10 inputs row turn-off signal VGL, and logic circuit 13 still outputs the second level signal normally. The anode voltage terminal is connected to the first terminal of storage capacitor Cst, and the second terminal of storage capacitor Cst is connected to the control terminal of driving transistor SD. At this time, the input light emission signal EM is activated, and the first light emission switch 101 and the second light emission switch 102 are turned on. The anode voltage terminal, the first light emission switch 101, the driving transistor SD, and the second light emission switch 102 form a current path. The driving transistor SD generates a current signal and outputs it to the light emission unit 20 through the second light emission switch 102. The light emission unit 20 displays the grayscale data of the sampling stage and emits light normally, achieving a high refresh rate.

[0030] When switching to the next frame's sustain mode, such as Figure 5As shown, during the sampling period of pixel circuit 10, such as the sampling period t21 of the second frame, when scanning to the row where pixel circuit 10 is located, the scan line connected to pixel circuit 10 inputs the row enable signal VGH, and the data line connected to pixel circuit 10 does not input the data signal Da. At this time, the data line is in a low-level state, the logic circuit 13 outputs the second-level signal, the first reset switch 14 is turned off, and the driving transistor SD is turned off. At this time, the switch circuit 15 disconnects the output terminal of the driving transistor SD and the first terminal of the storage capacitor Cst. At the same time, when the switch circuit 15 receives the row enable signal VGH, it disconnects the first terminal of the storage capacitor Cst and the anode voltage terminal. When the switch circuit 15 receives the second-level signal, it disconnects the anode voltage terminal and the second terminal of the storage capacitor Cst. When the switch circuit 15 receives the row enable signal VGH, it disconnects the second terminal of the storage capacitor Cst and the control terminal of the driving transistor SD. That is, the switch circuit 15 remains in the off state, and the storage capacitor Cst will maintain the storage voltage of the previous frame.

[0031] Then, during the light emission period, such as the light emission period t22 of the second frame, when the scanning of this line ends and no data signal Da is input to other lines, at this time, the scan line connected to the pixel circuit 10 inputs the line close signal VGL, the data line connected to the pixel circuit 10 does not input the data signal Da, the logic circuit 13 outputs the second level signal, the switch circuit 15 connects the second end of the storage capacitor Cst and the control end of the driving transistor SD, the storage voltage of the storage capacitor Cst, which is the storage voltage of the previous frame, is output to the driving transistor SD. At this time, the input light emission signal EM, the first light emission switch 101 and the second light emission switch 102 are turned on, the anode voltage end, the first light emission switch 101, the driving transistor SD and the second light emission switch 102 form a current path, the driving transistor SD generates a current signal and outputs it to the light emission unit 20 through the second light emission switch 102, the light emission unit 20 displays the grayscale data of the sampling stage and emits light normally, realizing a low refresh rate of the local screen.

[0032] Alternatively, during the illumination period, when other rows are scanned, such as... Figure 5As shown, when the data line switches the input data signal Da due to the data signal Da of other rows, at this time, the scan line input row closing signal VGL connected to the pixel circuit 10 is turned on, the logic circuit 13 still outputs the second level signal normally, the switch circuit 15 connects the second terminal of the storage capacitor Cst and the control terminal of the driving transistor SD, the storage voltage of the previous frame is output to the driving transistor SD, at this time, the input light emission signal EM is turned on, the first light emission switch 101 and the second light emission switch 102 are turned on, the anode voltage terminal, the first light emission switch 101, the driving transistor SD and the second light emission switch 102 form a current path, the driving transistor SD generates a current signal and outputs it to the light-emitting unit 20 through the second light emission switch 102, the light-emitting unit 20 displays the grayscale data of the previous frame and emits light normally. The pixel circuit 10 displays the same display information based on the same data signal Da in the two frames before and after, realizing a low refresh rate of the local screen.

[0033] The data signal Da serves as both the data voltage for display and the control signal for the logic circuit 13. When the pixel circuit 10 of the target local image needs to be in a low refresh rate, the output data signal Da to the data line connected to the pixel circuit 10 can be cut off when scanning to the row where the pixel circuit 10 is located. This will switch the pixel circuit 10 to the sustain mode, thus achieving a low refresh rate.

[0034] Therefore, the pixel circuit 10 can refresh or maintain the data signal Da under the control of the dual signals of the data signal Da and the input row scan signal Sc, so as to realize the control of the refresh rate of the target pixel circuit.

[0035] The switching circuit 15 can employ a corresponding transistor, a switching switch, etc., in an optional embodiment, such as... Figure 7 As shown, the switching circuit 15 includes: The first switching circuit 151 is connected to the first terminal, the second terminal and the anode voltage terminal of the storage capacitor Cst, respectively. The first switching circuit 151 is used to trigger the connection between the anode voltage terminal and the second terminal of the storage capacitor Cst when receiving the row enable signal VGH and the first level signal, or to turn off when receiving the row enable signal VGH and the second level signal, or to trigger the connection between the anode voltage terminal and the first terminal of the storage capacitor Cst when receiving the row disable signal VGL and the second level signal. The second switching circuit 152 is connected to the first terminal of the storage capacitor Cst, the second terminal of the storage capacitor Cst, the control terminal of the driving transistor SD, and the output terminal of the driving transistor SD, respectively. The second switching circuit 152 is used to trigger the connection between the output terminal of the driving transistor SD and the first terminal of the storage capacitor Cst when the row open signal VGH is received, or to trigger the connection between the second terminal of the storage capacitor Cst and the control terminal of the driving transistor SD when the row close signal VGL is received.

[0036] In this embodiment, Figure 4 As shown, in the working mode, during the sampling period of pixel circuit 10, such as the sampling period t11 of the first frame, when scanning to the row where pixel circuit 10 is located, the scan line connected to pixel circuit 10 inputs the row enable signal VGH, the data line connected to pixel circuit 10 inputs the data signal Da, and the logic circuit 13 outputs the first level signal to the switch circuit 15 and the first reset switch 14. The first reset switch 14 is turned on, and the first reset signal Vint is transmitted to the control terminal of the driving transistor SD through the first reset switch 14. The voltage of the first reset signal Vint is less than the data voltage, and the driving transistor SD is reset and turned on. At the same time, the first switch circuit 151 receives the first level signal and connects the anode voltage terminal and the second terminal of the storage capacitor Cst, and the second switch circuit 152 connects the first terminal of the storage capacitor Cst and the output terminal of the driving transistor SD. The data switch 12 is turned on, and the data signal Da is written to the storage capacitor Cst through the driving transistor SD and the second switch circuit 152. The pixel circuit 10 completes the data writing work of the data signal Da and the sampling work of the driving transistor SD.

[0037] Then, during the light emission period, such as the light emission period t12 of the first frame, when the scanning of this line ends and no data signal Da is input to other lines, the scan line connected to pixel circuit 10 inputs the line close signal VGL, the data line connected to pixel circuit 10 does not input the data signal Da, logic circuit 13 outputs the second level signal, the first reset switch 14 is turned off, the first switch circuit 151 connects the anode voltage terminal to the first terminal of the storage capacitor Cst, and the second switch circuit 152 connects the second terminal of the storage capacitor Cst to the control terminal of the driving transistor SD. At this time, the potential of the control terminal of the driving transistor SD is... The sum of the potential difference and anode voltage VDD written during the sampling period is used to input the light emission signal EM. The first light emission switch 101 and the second light emission switch 102 are turned on, and the driving transistor SD can be turned on normally. The driving transistor SD enters the saturation region and converts the data voltage into a current signal. The anode voltage terminal, the first light emission switch 101, the driving transistor SD and the second light emission switch 102 form a current path. The driving transistor SD generates a current signal and outputs it to the light-emitting unit 20 through the second light emission switch 102. The light-emitting unit 20 displays the grayscale data of the sampling period and emits light normally, realizing a high refresh rate.

[0038] Alternatively, during the light emission period, when scanning downlink, the data line switches to input data signal Da due to the downlink data signal Da. At this time, the scan line connected to pixel circuit 10 inputs row off signal VGL, and logic circuit 13 still outputs the second level signal normally. The first switch circuit 151 connects the anode voltage terminal to the first terminal of storage capacitor Cst, and the second switch circuit 152 connects the second terminal of storage capacitor Cst to the control terminal of driving transistor SD. At this time, the input light emission signal EM is activated, and the first light emission switch 101 and the second light emission switch 102 are turned on. The anode voltage terminal, the first light emission switch 101, the driving transistor SD, and the second light emission switch 102 form a current path. The driving transistor SD generates a current signal and outputs it to the light emission unit 20 through the second light emission switch 102. The light emission unit 20 displays the grayscale data of the sampling stage and emits light normally, achieving a high refresh rate.

[0039] When switching to the next frame's sustain mode, such as Figure 5 As shown, during the sampling period of pixel circuit 10, such as the sampling period t21 of the second frame, when scanning to the row where pixel circuit 10 is located, the scan line connected to pixel circuit 10 inputs the row enable signal VGH, and the data line connected to pixel circuit 10 does not input the data signal Da. At this time, the data line is in a low-level state, the logic circuit 13 outputs the second-level signal, the first reset switch 14 is turned off, and the driving transistor SD is turned off. At this time, the second switch circuit 152 disconnects the output terminal of the driving transistor SD and the first terminal of the storage capacitor Cst. At the same time, when the first switch circuit 151 receives the row enable signal VGH, it disconnects the first terminal of the storage capacitor Cst and the anode voltage terminal. When the first switch circuit 151 receives the second-level signal, it disconnects the anode voltage terminal and the second terminal of the storage capacitor Cst. When the second switch circuit 152 receives the row enable signal VGH, it disconnects the second terminal of the storage capacitor Cst and the control terminal of the driving transistor SD. That is, the first switch circuit 151 and the second switch circuit 152 remain in the off state, and the storage capacitor Cst will maintain the storage voltage of the previous frame.

[0040] Then, during the light emission period, such as the light emission period t22 of the second frame, when the scanning of this line ends and no data signal Da is input to other lines, at this time, the scan line connected to the pixel circuit 10 inputs the line close signal VGL, the data line connected to the pixel circuit 10 does not input the data signal Da, the logic circuit 13 outputs the second level signal, the second switch circuit 152 connects the second end of the storage capacitor Cst and the control end of the driving transistor SD, the storage voltage of the storage capacitor Cst, which is the storage voltage of the previous frame, is output to the driving transistor SD. At this time, the input light emission signal EM, the first light emission switch 101 and the second light emission switch 102 are turned on, the anode voltage end, the first light emission switch 101, the driving transistor SD and the second light emission switch 102 form a current path, the driving transistor SD generates a current signal and outputs it to the light emission unit 20 through the second light emission switch 102, the light emission unit 20 displays the grayscale data of the sampling stage and emits light normally, realizing a low refresh rate of the local screen.

[0041] Alternatively, during the illumination period, when other rows are scanned, such as... Figure 5 As shown, when the data line switches the input data signal Da due to the data signal Da of other rows, at this time, the scan line input row closing signal VGL connected to the pixel circuit 10 is turned on, the logic circuit 13 still outputs the second level signal normally, the second switch circuit 152 connects the second terminal of the storage capacitor Cst and the control terminal of the driving transistor SD, the storage voltage of the previous frame is output to the driving transistor SD, at this time, the input light emission signal EM is turned on, the first light emission switch 101 and the second light emission switch 102 are turned on, the anode voltage terminal, the first light emission switch 101, the driving transistor SD and the second light emission switch 102 form a current path, the driving transistor SD generates a current signal and outputs it to the light-emitting unit 20 through the second light emission switch 102, the light-emitting unit 20 displays the grayscale data of the previous frame and emits light normally. The pixel circuit 10 displays the same display information based on the same data signal Da in the two frames before and after, realizing a low refresh rate of the local screen.

[0042] Furthermore, since the light-emitting unit 20 may store the charge of the previous frame in each frame, there may be charge accumulation during frame scanning, which may cause abnormal grayscale display of the light-emitting unit 20.

[0043] Therefore, in one alternative embodiment, such as Figure 8 As shown, the pixel circuit 10 also includes: The second reset switch 16 has a first terminal for inputting a second reset signal VI, a second terminal for connecting to the light-emitting unit 20, and a control terminal for connecting to the scan line. The second reset switch 16 is triggered to turn on by a row enable signal VGH and to turn off by a row disable signal VGL.

[0044] In a conventional pixel circuit, the 10 operates sequentially during the reset period, the sampling period, and the emission period to complete the reset, sampling, and emission operations in sequence. However, in this embodiment, the second reset switch 16 is connected to the scan line, so it only needs to operate sequentially during the sampling period and the emission period to complete the reset, sampling, and emission operations.

[0045] During the sampling period of the working mode, the scan line input row enable signal VGH is activated, the second reset switch 16 is turned on, and the grayscale data of the previous frame received by the light-emitting unit 20 is reset and cleared to zero. At the same time, the switch circuit 15 refreshes the data signal Da of the next frame and completes sampling. During the sampling period of the working mode, the reset and sampling work are completed simultaneously.

[0046] Then, during the light emission period in the working mode, the scan line input row turn-off signal VGL is activated, the second reset switch 16 is turned off, and no reset operation is performed.

[0047] During the sampling period in the sustain mode, the scan line input row enable signal VGH is activated, the second reset switch 16 is turned on, and the residual charge of the light-emitting unit 20 is reset to zero.

[0048] Similarly, during the illumination period in the sustain mode, the scan line input row off signal VGL is turned off, the second reset switch 16 is turned off, and no reset operation is performed, so that the current signal corresponding to the grayscale data of the previous frame of the pixel circuit 10 is lit up.

[0049] The first optical emitting switch 101, the second optical emitting switch 102, the switching circuit 15, the data switch 12, the logic circuit 13, the first reset switch 14, and the second reset switch 16 can be composed of corresponding thin-film transistors, and the specific structure is not limited.

[0050] The light-emitting unit 20 is a light-emitting diode (OLED).

[0051] Example 2 In an alternative embodiment, such as Figure 9 As shown, the first switching circuit 151 includes a first transistor T1 and a second transistor T2; The first terminal of the first transistor T1 and the first terminal of the second transistor T2 are connected to the anode voltage terminal. The second terminal of the first transistor T1 is connected to the first terminal of the storage capacitor Cst. The second terminal of the second transistor T2 is connected to the second terminal of the storage capacitor Cst. The control terminal of the first transistor T1 is connected to the scan line. The control terminal of the second transistor T2 is connected to the output terminal of the logic circuit 13. The second switching circuit 152 includes a third transistor T3 and a fourth transistor T4; The first terminal of the third transistor T3 is connected to the first terminal of the storage capacitor Cst, the first terminal of the fourth transistor T4 is connected to the second terminal of the storage capacitor Cst, the second terminal of the third transistor T3 is connected to the output terminal of the driving transistor SD, the second terminal of the fourth transistor T4 is connected to the control terminal of the driving transistor SD, the control terminal of the third transistor T3 is connected to the output terminal of the logic circuit 13, and the control terminal of the fourth transistor T4 is connected to the scan line.

[0052] The logic circuit 13 includes a NOR gate U1 and an OR gate U2. The first input terminal of the NOR gate U1 is connected to the data line, the second input terminal of the NOR gate U1 and the first input terminal of the OR gate U2 are connected to the scan line, the output terminal of the NOR gate U1 is connected to the second input terminal of the OR gate U2, and the output terminal of the OR gate U2 constitutes the output terminal of the logic circuit 13.

[0053] The data switch 12 includes a fifth transistor T5. The input terminal of the fifth transistor T5 is connected to the data line, the output terminal of the fifth transistor T5 is connected to the input terminal of the drive transistor SD, and the control terminal of the fifth transistor T5 is connected to the scan line.

[0054] The first reset switch 14 includes a sixth transistor T6. The input terminal of the sixth transistor T6 is connected to the first reset terminal, the output terminal of the sixth transistor T6 is connected to the control terminal of the drive transistor SD, and the control terminal of the sixth transistor T6 is connected to the output terminal of the logic circuit 13.

[0055] The first optical emission switch 101 includes a seventh transistor T7. The second terminal of the seventh transistor T7 is connected to the input terminal of the driving transistor SD. The control terminal of the seventh transistor T7 is used to input the optical emission signal EM. The output terminal of the seventh transistor T7 is connected to the input terminal of the driving transistor SD.

[0056] The second light emitting switch 102 includes an eighth transistor T8. The first terminal of the eighth transistor T8 is connected to the output terminal of the driving transistor SD. The control terminal of the eighth transistor T8 is connected to the control terminal of the seventh transistor T7. The output terminal of the eighth transistor T8 is connected to the light-emitting unit 20.

[0057] The second reset switch 16 includes a ninth transistor T9. The input terminal of the ninth transistor T9 is connected to the second reset terminal, the output terminal of the ninth transistor T9 is connected to the light-emitting unit 20, and the control terminal of the ninth transistor T9 is connected to the scan line.

[0058] In this embodiment, during the sampling period of the pixel circuit 10, such as the sampling period t11 of the first frame, when scanning to the row where the pixel circuit 10 is located, the scan line connected to the pixel circuit 10 inputs the row enable signal VGH, the ninth transistor T9 is turned on and inputs the second reset signal VI, and the second reset signal VI resets and clears the residual charge of the light-emitting unit 20.

[0059] The pixel circuit 10 is connected to the data line to input the data signal Da. The OR gate U2 outputs a first level signal to the second transistor T2 and the sixth transistor T6. The second transistor T2, the third transistor T3, and the sixth transistor T6 are turned on. The first reset signal Vint is transmitted to the control terminal of the driving transistor SD through the sixth transistor T6. The voltage of the first reset signal Vint is less than the data voltage, so the driving transistor SD is reset and turned on. At the same time, the second transistor T2 connects the anode voltage terminal and the second terminal of the storage capacitor Cst, and the third transistor T3 connects the first terminal of the storage capacitor Cst and the output terminal of the driving transistor SD. The fifth transistor T5 is turned on and writes the data signal Da to the storage capacitor Cst through the driving transistor SD and the third transistor T3. The pixel circuit 10 completes the data writing operation of the data signal Da and the sampling operation of the driving transistor SD.

[0060] Then, during the light emission period, such as the light emission period t12 of the first frame, when the scanning of this line ends and no data signal Da is input to other lines, the scan line connected to pixel circuit 10 inputs the line turn-off signal VGL, the data line connected to pixel circuit 10 does not input the data signal Da, the OR gate U2 outputs the second level signal, the sixth transistor T6 is turned off, the first transistor T1 is turned on and connects the anode voltage terminal to the first terminal of the storage capacitor Cst, the fourth transistor T4 is turned on and connects the second terminal of the storage capacitor Cst to the control terminal of the driving transistor SD. At this time, the potential of the control terminal of the driving transistor SD is the sum of the potential difference written during the sampling period and the anode voltage VDD. The light emission signal EM is input, the seventh transistor T7 and the eighth transistor T8 are turned on, the driving transistor SD can be turned on normally, the driving transistor SD enters the saturation region and converts the data voltage into a current signal. The anode voltage terminal, the seventh transistor T7, the driving transistor SD and the eighth transistor T8 form a current path. The driving transistor SD generates a current signal and outputs it to the light emission unit 20 through the eighth transistor T8. The light emission unit 20 displays the grayscale data of the sampling stage and emits light normally, realizing a high refresh rate.

[0061] Alternatively, during the light emission period, when scanning downlink, the data line switches to input data signal Da due to the downlink data signal Da. At this time, the scan line input row off signal VGL connected to pixel circuit 10, and OR gate U2 still outputs the second level signal normally. The first transistor T1 is turned on, connecting the anode voltage terminal to the first terminal of storage capacitor Cst. The fourth transistor T4 is turned on, connecting the second terminal of storage capacitor Cst to the control terminal of driving transistor SD. At this time, the input light emission signal EM is activated, the seventh transistor T7 and the eighth transistor T8 are turned on, and the anode voltage terminal, the seventh transistor T7, the driving transistor SD and the eighth transistor T8 form a current path. The driving transistor SD generates a current signal and outputs it to the light emission unit 20 through the eighth transistor T8. The light emission unit 20 displays the grayscale data of the sampling stage and emits light normally, achieving a high refresh rate.

[0062] When switching to the next frame's sustain mode, such as Figure 5 As shown, during the sampling period of pixel circuit 10, such as the sampling period t21 of the second frame, when scanning to the row where pixel circuit 10 is located, the scan line connected to pixel circuit 10 inputs the row enable signal VGH, and the data line connected to pixel circuit 10 does not input the data signal Da. At this time, the data line is in a low-level state, and the OR gate U2 outputs the second-level signal. The sixth transistor T6 is turned off, and the driving transistor SD is turned off. At this time, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned off, and the first switch circuit 151 and the second switch circuit 152 remain in the off state. The storage capacitor Cst will maintain the storage voltage of the previous frame.

[0063] Then, during the light emission period, such as the light emission period t22 of the second frame, when the scanning of this line ends and no data signal Da is input to other lines, the scan line connected to pixel circuit 10 inputs the line close signal VGL, the data line connected to pixel circuit 10 does not input the data signal Da, the OR gate U2 outputs the second level signal, the fourth transistor T4 connects the second terminal of the storage capacitor Cst and the control terminal of the driving transistor SD, the storage voltage of the storage capacitor Cst, which is the storage voltage of the previous frame, is output to the driving transistor SD. At this time, the light emission signal EM is input, the seventh transistor T7 and the eighth transistor T8 are turned on, the anode voltage terminal, the seventh transistor T7, the driving transistor SD and the eighth transistor T8 form a current path, the driving transistor SD generates a current signal and outputs it to the light emission unit 20 through the eighth transistor T8, the light emission unit 20 displays the grayscale data of the sampling stage and emits light normally, realizing a low refresh rate of the local screen.

[0064] Alternatively, during the illumination period, when other rows are scanned, such as... Figure 5 As shown, when the data line switches the input data signal Da due to the data signal Da of other rows, at this time, the scan line input row closing signal VGL connected to the pixel circuit 10, the OR gate U2 still outputs the second level signal normally, the fourth transistor T4 connects the second terminal of the storage capacitor Cst and the control terminal of the driving transistor SD, the storage voltage of the previous frame is output to the driving transistor SD, at this time, the input light emission signal EM, the seventh transistor T7 and the eighth transistor T8 are turned on, the anode voltage terminal, the seventh transistor T7, the driving transistor SD and the eighth transistor T8 form a current path, the driving transistor SD generates a current signal and outputs it to the light-emitting unit 20 through the eighth transistor T8, the light-emitting unit 20 displays the grayscale data of the previous frame and emits light normally. The pixel circuit 10 displays the same display information based on the same data signal Da in the two frames before and after, realizing a low refresh rate of the local screen.

[0065] Corresponding to the above signal types and the on / off modes of each transistor, in an optional embodiment, the first transistor T1 and the fourth transistor T4 are N-channel thin-film transistors, and the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are P-channel thin-film transistors.

[0066] Example 3 A second aspect of this invention provides a driving method for a display panel, used to drive the aforementioned display panel. The driving method for the display panel includes: S10. Determine whether the content of the next frame of the target partial image on the display panel has changed; S20. When the content of the next frame of the target local image remains unchanged, switch to the maintenance mode, and when the next frame is scanned, output the corresponding row enable signal VGH and do not output the data signal Da to the target pixel circuit corresponding to the target local image, and control the control terminal of the drive transistor SD of the target pixel circuit to maintain the data signal Da of the previous frame. S30. When the content of the next frame of the target local image changes, switch to the working mode. When scanning the next frame, output the corresponding data signal Da and the line open signal VGH to the target pixel circuit corresponding to the target local image, and control the control terminal of the driver transistor SD of the target pixel circuit to input the data signal Da of the current frame.

[0067] In this embodiment, when a static image is displayed in the target local image, the feature values ​​of the subsequent images can be analyzed to determine whether the target local image has changed. When it is determined that the display content of the target local image remains unchanged, the target local image has a low refresh rate. At this time, the image is switched to the sustain mode. During line-by-line scanning, the image can be switched to the sustain mode, i.e., the low refresh rate is achieved.

[0068] When it is determined that the target local image changes in the next frame, the target local image is at a high refresh rate. At this time, the working mode is switched. During progressive scanning, the output data signal Da can be selected to the pixel circuit 10 of the corresponding target local image, which can complete the switching of the pixel circuit 10 of the target local image to the working mode, that is, to achieve a high refresh rate.

[0069] The pixel circuit 10 can refresh or maintain the data signal Da under the control of the dual signals of the data signal Da and the input row scan signal Sc, so as to realize the control of the refresh rate of the target pixel circuit.

[0070] For example, when it is necessary to achieve localized low refresh rates and localized high refresh rates along the column direction of the display panel 100, such as Figure 2As shown, if the pixel circuit 10 of the second column needs to be at a low refresh rate, during progressive scanning, the first data line S1 and the third data line S3 can normally input the first data signal Da1 and the third data signal Da3 line by line, while the second data line S2 selects not to input the second data signal Da2 and is correspondingly pulled low. In this way, during progressive scanning, the pixel circuit 10 of the second column maintains the grayscale data of the previous frame and emits light, realizing a low refresh rate in the column direction, while the pixel circuit 10 of the first column and the pixel circuit 10 of the third column refresh the input of the grayscale data of the next frame and emit light, realizing a high refresh rate in the column direction, thereby realizing different refresh rates in the column direction of the display panel 100.

[0071] When a localized low refresh rate is required in the row direction of the display panel 100, such as Figure 2 and Figure 6 As shown, if the pixel circuit 10 of the second row needs to be at a low refresh rate, during line-by-line scanning, when scanning to the pixel circuit 10 of the first row and the pixel circuit 10 of the third row, each data line can normally input data signal Da. Each pixel circuit 10 of the first row and each pixel circuit 10 of the third row refreshes the input grayscale data of the next frame and emits light, achieving a high refresh rate in the row direction. However, when scanning to the pixel circuit 10 of the second row, each data line does not input data signal Da and is pulled low. The pixel circuit 10 of the second row maintains the grayscale data of the previous frame and emits light, achieving a low refresh rate in the row direction, thereby achieving different refresh rates in the row direction of the display panel 100.

[0072] When scanning to each pixel circuit 10 in the second row, the first data line S1 and the third data line S3 normally input the first data signal Da1 and the third data signal Da3. The two pixel circuits 10 in the first column of the second row and the third column of the second row refresh the input of the grayscale data of the next frame and emit light to achieve a high refresh rate. The second data line S2 does not input the second data signal Da2 and is pulled low. The pixel circuit 10 in the second column of the second row maintains the grayscale data of the previous frame and emits light to achieve a low refresh rate, thereby achieving a low refresh rate for individual pixel circuits 10.

[0073] When scanning to the pixel circuits 10 in the third row, the first data line S1 and the second data line S2 normally input the first data signal Da1 and the second data signal Da2. The two pixel circuits 10 in the first column of the third row and the second column of the third row refresh the input of the grayscale data of the next frame and emit light to achieve a high refresh rate. The third data line S3 does not input the third data signal Da3 and is pulled low. The pixel circuit 10 in the third column of the third row maintains the grayscale data of the previous frame and emits light to achieve a low refresh rate, thereby achieving a low refresh rate for individual pixel circuits 10.

[0074] In an alternative embodiment, such as Figure 11 As shown, S20 includes: S21. During the sampling period of the sustain mode, output the row enable signal VGH to the scan line and do not output the data signal Da to the data line.

[0075] During the sampling period of pixel circuit 10, when scanning to the row where pixel circuit 10 is located, the scan line connected to pixel circuit 10 inputs the row enable signal VGH, and the data line connected to pixel circuit 10 does not input the data signal Da. At this time, the data line is in a low-level state, the logic circuit 13 of pixel circuit 10 outputs the second-level signal, and the switching circuit 15 of pixel circuit 10 disconnects the second terminal of storage capacitor Cst from the control terminal of driving transistor SD. At this time, pixel circuit 10 does not input the light emission signal EM, and storage capacitor Cst will maintain the storage voltage of the previous frame.

[0076] S22. During the light emission period in the maintenance mode, output the row off signal VGL to the scan line, and output the data signal Da corresponding to the next row pixel circuit 10 to the data line or do not output the data signal Da to the data line.

[0077] During the light emission period, when the scanning of the current line ends and no data signal Da is input to other lines, or when the input data signal Da is switched due to the data signal Da of other lines, the scan line connected to the pixel circuit 10 inputs the line closing signal VGL, the logic circuit 13 of the pixel circuit 10 outputs the second level signal, the switch circuit 15 connects the second terminal of the storage capacitor Cst and the control terminal of the driving transistor SD, the storage voltage of the storage capacitor Cst, which is the storage voltage of the previous frame, is output to the driving transistor SD. At this time, the input light emission signal EM is generated, the driving transistor SD generates a current signal and outputs it to the light emission unit 20 through the second light emission switch 102, the light emission unit 20 displays the grayscale data of the sampling stage and emits light normally, realizing a low refresh rate of the local screen.

[0078] In an alternative embodiment, such as Figure 12 As shown, S30 includes: S31. During the sampling period of the working mode, output the row enable signal VGH to the scan line and output the data signal Da to the data line; S32. During the light-emitting period of the working mode, the row enable signal VGH is not output to the scan line, and the data signal Da corresponding to the next row pixel circuit 10 is output to the data line or the data signal Da is not output to the data line.

[0079] In the working mode, during the sampling period of pixel circuit 10, such as the sampling period of the first frame, when scanning to the row where pixel circuit 10 is located, the scan line connected to pixel circuit 10 inputs the row enable signal VGH, the data line connected to pixel circuit 10 inputs the data signal Da, the logic circuit 13 of pixel circuit 10 outputs the first level signal, and the switching circuit 15 of pixel circuit 10 connects the anode voltage terminal and the control terminal of the driving transistor SD, as well as the second terminal of the storage capacitor Cst and the output terminal of the driving transistor SD. At this time, no light emission signal EM is input, the potential difference of the storage capacitor Cst is Vdata + Vth - VDD, and pixel circuit 10 completes the sampling of data signal Da.

[0080] Then, during the light emission period, when the scanning of this line ends and no data signal Da is input to other lines, the scan line connected to the pixel circuit 10 inputs the line close signal VGL, the data line connected to the pixel circuit 10 does not input the data signal Da or the data line switches to input the data signal Da due to the data signal Da of other lines, the logic circuit 13 outputs the second level signal, the switch circuit 15 connects the second end of the storage capacitor Cst and the control end of the driving transistor SD, the storage voltage of the storage capacitor Cst is output to the driving transistor SD, at this time, the input light emission signal EM, the first light emission switch 101 and the second light emission switch 102 are turned on, the anode voltage end, the first light emission switch 101, the driving transistor SD and the second light emission switch 102 form a current loop, the driving transistor SD generates a current signal and outputs it to the light emission unit 20 through the second light emission switch 102, the light emission unit 20 displays the grayscale data of the sampling stage and emits light normally, realizing a high refresh rate.

[0081] Alternatively, during the light emission period, when other rows are scanned, the data line switches its input data signal Da due to the data signal Da of other rows. At this time, the scan line connected to the pixel circuit 10 inputs the row closing signal VGL, the logic circuit 13 still outputs the second level signal normally, the switch circuit 15 connects the second terminal of the storage capacitor Cst and the control terminal of the driving transistor SD, the storage voltage of the storage capacitor Cst is output to the driving transistor SD, at this time, the input light emission signal EM, the driving transistor SD generates a current signal and outputs it to the light emission unit 20 through the second light emission switch 102, the light emission unit 20 displays the grayscale data of the sampling stage and emits light normally, realizing a high refresh rate.

[0082] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0083] Example 4 like Figure 13As shown, a third aspect of the present invention provides a driving circuit 200 for a display panel, including a source driving circuit 210, a gate driving circuit 220 and a timing controller 230. The source driving circuit 210 is connected to multiple data lines of the display panel 100, and the gate driving circuit 220 is connected to multiple scan lines of the display panel 100. The timing controller 230 is connected to the source drive circuit 210 and the gate drive circuit 220 respectively. The timing controller 230 is used to output control signals to the source drive circuit 210 and the gate drive circuit 220 to realize the driving method of the display panel 100 as described above.

[0084] In this embodiment, the source drive circuit 210 is used to output the data signal Da under control or not output the data signal Da, and the gate drive circuit 220 is used to output the row enable signal VGH and the row disable signal VGL under control row by row.

[0085] When the target local screen displays a static image, the timing controller 230 analyzes the feature values ​​of the subsequent images to determine whether the target local screen has changed. When it is determined that the display content of the target local screen remains unchanged, the target local screen has a low refresh rate. At this time, it switches to the sustain mode. The timing controller 230 controls the source drive circuit 210 not to output the data signal Da to the target pixel circuit of the target local screen during the sampling period, thereby controlling the target pixel circuit to maintain the data signal Da and the display image of the previous frame, thus achieving a low refresh rate.

[0086] When it is determined that the target local image will change in the next frame, the target local image will have a high refresh rate. At this time, the working mode is switched, and the timing controller 230 controls the source drive circuit 210 to output the data signal Da to the target pixel circuit of the target local image during the sampling period, thereby controlling the target pixel circuit to switch to the data signal Da of the next frame and the display image to achieve a high refresh rate.

[0087] Example 5 A fourth aspect of the present invention provides a display device, such as... Figure 13 As shown, the display device includes a display panel 100 and a driving circuit 200 for the display panel. The specific structure of the display panel 100 and the driving circuit 200 is as described in the above embodiments. Since this display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here. The driving circuit 200 for the display panel is connected to the display panel 100.

[0088] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

[0089] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A display panel, characterized in that, It includes multiple scan lines, multiple data lines, and an array of pixel circuits, wherein the pixel circuits include: A light-emitting driving unit is connected in series with the light-emitting unit between the anode voltage terminal and the cathode voltage terminal. The light-emitting driving unit includes a first light-emitting switch, a driving tube, and a second light-emitting switch connected in series. The first light-emitting switch and the second light-emitting switch are triggered to conduct by the light emission signal during the light emission period. Storage capacitor; A data switch is connected to the input terminals of the data line, the scan line, and the driving transistor, respectively. The data switch is triggered to turn on by a row open signal and transmits the data signal on the data line to the input terminal of the driving transistor, and is triggered to turn off by a row close signal. A logic circuit, connected to the data line and the scan line respectively, is used to trigger the output of a first level signal when the row enable signal and the data signal are received simultaneously, and otherwise output a second level signal. The first reset switch is connected to the first reset terminal, the output terminal of the logic circuit, and the control terminal of the driving transistor, respectively. The first reset switch is triggered to turn on by the first level signal and transmits the first reset signal to control the driving transistor to turn on, and is triggered to turn off by the second level signal. A switching circuit is connected to the anode voltage terminal, the first and second terminals of the storage capacitor, and the control and output terminals of the driving transistor, respectively. The switching circuit is triggered by the first level signal to form a first path and triggered by the row-off signal to form a second path. The first path consists of the anode voltage terminal, the second terminal of the storage capacitor, the first terminal of the storage capacitor, and the output terminal of the driving transistor. The second path consists of the anode voltage terminal, the first terminal of the storage capacitor, the second terminal of the storage capacitor, and the control terminal of the driving transistor.

2. The display panel as described in claim 1, characterized in that, The switching circuit includes: The first switching circuit is connected to the first terminal of the storage capacitor, the second terminal of the storage capacitor, the anode voltage terminal, the scan line and the logic circuit respectively. The first switching circuit is used to connect the anode voltage terminal and the first terminal of the storage capacitor when a row close signal is received, or to connect the anode voltage terminal and the second terminal of the storage capacitor when the first level signal is received, or to turn off when the row open signal and the second level signal are received. The second switching circuit is connected to the first terminal of the storage capacitor, the second terminal of the storage capacitor, the control terminal of the driving transistor, the output terminal of the driving transistor, the scan line, and the logic circuit, respectively. The second switching circuit is used to connect the output terminal of the driving transistor and the first terminal of the storage capacitor when the first level signal is received, or to connect the second terminal of the storage capacitor and the control terminal of the driving transistor when the row close signal is received, or to turn off when the second level signal and the row open signal are received.

3. The display panel as described in claim 2, characterized in that, The first switching circuit includes a first transistor and a second transistor; The first terminal of the first transistor, the first terminal of the second transistor, and the anode voltage terminal are connected. The second terminal of the first transistor is connected to the first terminal of the storage capacitor. The second terminal of the second transistor is connected to the second terminal of the storage capacitor. The control terminal of the first transistor is connected to the scan line. The control terminal of the second transistor is connected to the output terminal of the logic circuit. The second switching circuit includes a third transistor and a fourth transistor; The first terminal of the third transistor is connected to the first terminal of the storage capacitor, the first terminal of the fourth transistor is connected to the second terminal of the storage capacitor, the second terminal of the third transistor is connected to the output terminal of the driving transistor, the second terminal of the fourth transistor is connected to the control terminal of the driving transistor, the control terminal of the third transistor is connected to the output terminal of the logic circuit, and the control terminal of the fourth transistor is connected to the scan line.

4. The display panel as described in claim 1, characterized in that, The logic circuit includes a NOR gate and an OR gate. The first input terminal of the NOR gate is connected to the data line. The second input terminal of the NOR gate, the first input terminal of the OR gate, and the scan line are connected. The output terminal of the NOR gate is connected to the second input terminal of the OR gate. The output terminal of the OR gate constitutes the output terminal of the logic circuit.

5. The display panel as described in any one of claims 1 to 4, characterized in that, The pixel circuit also includes: The second reset switch has a first terminal for inputting a second reset signal, a second terminal connected to the light-emitting unit, and a control terminal connected to the scan line. The second reset switch is triggered to turn on by the row enable signal and triggered to turn off by the row disable signal.

6. A driving method for a display panel, used to drive the display panel as described in any one of claims 1 to 5, characterized in that, The driving method for the display panel includes: Determine whether the content of the next frame of the target partial image on the display panel has changed; When the content of the next frame of the target partial image remains unchanged, switch to the maintenance mode, and when the next frame is scanned, output the corresponding row enable signal and do not output data signal to the target pixel circuit corresponding to the target partial image, and control the control terminal of the driving transistor of the target pixel circuit to maintain the data signal of the previous frame. When the content of the next frame of the target partial image changes, the system switches to the working mode. During the scanning drive of the next frame, the system outputs the corresponding data signal and the line opening signal to the target pixel circuit corresponding to the target partial image, and controls the control terminal of the driving transistor of the target pixel circuit to input the data signal of the current frame.

7. The driving method for a display panel as described in claim 6, characterized in that, When the content of the next frame of the target partial image remains unchanged, the mode is switched to a maintenance mode, and during the scanning drive of the next frame, a corresponding row enable signal is output and no data signal is output to the target pixel circuit corresponding to the target partial image, including: During the sampling period of the sustain mode, a row enable signal is output to the scan line, and no data signal is output to the data line; During the light emission period of the maintenance mode, a row turn-off signal is output to the scan line, and a data signal corresponding to the next row pixel circuit is output to the data line or no data signal is output to the data line.

8. The driving method for a display panel as described in claim 6, characterized in that, When the content of the next frame of the target partial image changes, the system switches to a working mode, and during the scanning drive of the next frame, outputs the corresponding data signal and the line opening signal to the target pixel circuit corresponding to the target partial image, including: During the sampling period of the operating mode, a row enable signal is output to the scan line and a data signal is output to the data line; During the light emission period of the operating mode, no line activation signal is output to the scan line, and no data signal is output to the data line corresponding to the next row pixel circuit.

9. A driving circuit for a display panel, characterized in that, It includes a source driving circuit, a gate driving circuit, and a timing controller. The source driving circuit is connected to multiple data lines of the display panel, and the gate driving circuit is connected to multiple scan lines of the display panel. The timing controller is connected to the source driving circuit and the gate driving circuit respectively. The timing controller is used to output control signals to the source driving circuit and the gate driving circuit to implement the driving method of the display panel as described in any one of claims 6 to 8.

10. A display device, characterized in that, The display panel includes any one of claims 1 to 5 and the driving circuit of the display panel as described in claim 9, wherein the driving circuit of the display panel is connected to the display panel.

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