A semiconductor capacitor structure and a manufacturing method thereof, a memory, and an electronic device

Abstract

The present disclosure provides a semiconductor capacitor structure and a manufacturing method thereof, a memory, and an electronic device. The structure includes a semiconductor substrate and a plurality of pads distributed thereon, and a lower electrode on the pad. At least two layers of lower support members are arranged between the sidewalls of adjacent lower electrodes. A dynamic random access memory includes the capacitor structure of the present disclosure. The device includes the dynamic random access memory of the present disclosure. The method includes forming a pad on a semiconductor substrate and forming a first stack and a second stack. The first stack includes a lower molding layer, two lower support layers, and a treatment layer between the two lower support layers, and the second stack includes an upper molding layer and an upper support layer. The second stack and the first bottom layer are etched to form at least two layers of lower support members and upper support members. The present disclosure has a plurality of lower support members between two adjacent electrodes in a direction perpendicular to the substrate, thereby solving the problem of the upper limit of the capacitor height due to insufficient tilt margin.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor device technology, and more specifically, to a semiconductor capacitor structure and its manufacturing method, a memory, and an electronic device. Background Technology

[0002] The capacitor manufacturing process for Dynamic Random Access Memory (DRAM) involves contact processes with high aspect ratios. In this process, it is crucial to avoid electrode tilting issues. After separating the lower electrode nodes, a photolithography or etching process is required to remove the underlying oxide film. It is evident that increasing the number of support layers often leads to an increase in etching steps; therefore, conventional techniques often only use two support layers to support the electrodes due to process complexity. However, as the integration density of semiconductor devices increases, the aspect ratio of the capacitor also increases. Conventional techniques result in insufficient learning margin; therefore, the support layers in semiconductor capacitor structures fabricated using conventional techniques are no longer sufficient for many practical applications. Summary of the Invention

[0003] To address the problem that the support layer in existing semiconductor capacitor structures can no longer meet the needs of practical applications, this disclosure innovatively provides a semiconductor capacitor structure, its manufacturing method, memory, and electronic device.

[0004] To achieve the above-mentioned technical objectives, this disclosure provides a semiconductor capacitor structure, which includes, but is not limited to, a semiconductor substrate, bonding pads, a lower electrode, multiple layers of lower supports, and an upper support. A plurality of bonding pads are formed on the semiconductor substrate at intervals, and the bottom of the lower electrode is located on the bonding pads. The lower supports consist of at least two layers, each disposed between the sidewalls of adjacent lower electrodes, and the upper support consists of at least one layer, disposed between the sidewalls of adjacent lower electrodes. The upper support is positioned above the lower supports.

[0005] To achieve the above-mentioned technical objectives, this disclosure provides a dynamic random access memory, which includes the semiconductor capacitor structure in any embodiment of this disclosure.

[0006] To achieve the above-mentioned technical objectives, this disclosure provides an electronic device, which includes a dynamic random access memory in any embodiment of this disclosure.

[0007] To achieve the above-mentioned technical objectives, this disclosure also provides a method for manufacturing a semiconductor capacitor structure, the method including but not limited to the following steps: A semiconductor substrate is provided, and a plurality of spaced-apart pads are formed on the semiconductor substrate. At least one first stack and at least one second stack are sequentially formed over the semiconductor substrate. The first stack includes a lower molding layer, two lower support layers, and a treatment layer between the two lower support layers; the second stack includes an upper molding layer and an upper support layer. The second stack and the first stack are etched to form capacitor vias, thereby exposing the pads. A lower electrode is deposited and formed within each capacitor via. The remaining second stack and the first stack are etched to form at least two lower support layers and at least one upper support layer between the sidewalls of adjacent lower electrodes.

[0008] The beneficial effects of this disclosure are as follows:

[0009] This disclosure features multiple lower support layers between adjacent electrodes along a direction perpendicular to the substrate, resolving the issue of insufficient tilt margin limiting capacitor height. This disclosure provides greater etching margin, meeting the height requirements of semiconductor capacitors and effectively addressing existing problems. Based on the product structure and implementation process provided by this disclosure, semiconductor capacitor structures with greater height can be achieved. This significantly increases the capacitance of semiconductor capacitors while meeting the miniaturization requirements of semiconductor devices, ensuring the stability and reliability of the capacitor structure, and making it suitable for more applications. Attached Figure Description

[0010] Figure 1 A schematic diagram of the longitudinal cross-sectional structure of the device after forming the first and second stacks on a semiconductor substrate is shown.

[0011] Figure 2 A schematic diagram of the longitudinal cross-sectional structure of the device after forming a capacitor hole by etching the first and second stacks is shown.

[0012] Figure 3 A schematic diagram of the longitudinal cross-sectional structure of the device is shown after a hard mask layer and a photoresist layer are formed on top of the device.

[0013] Figure 4 A schematic diagram of the longitudinal cross-sectional structure of the device after etching the second stack based on the remaining hard mask and the support mask is shown.

[0014] Figure 5 A schematic diagram of the longitudinal cross-sectional structure of the device after removing the upper molding layer using a BOE-type solution is shown.

[0015] Figure 6 A schematic diagram of the longitudinal cross-sectional structure of the device after etching the first stack based on the remaining hard mask and the support mask is shown.

[0016] Figure 7 A schematic diagram of the longitudinal cross-sectional structure of the device after removing the treatment layer and the lower molding layer using a BOE-type solution is shown.

[0017] Figure 8 A schematic diagram of the longitudinal cross-sectional structure of a conventional semiconductor capacitor is shown.

[0018] In the picture,

[0019] 100. Semiconductor substrate.

[0020] 200. Solder pad.

[0021] 300, lower electrode.

[0022] 400. Lower support component; 401. Lower molding layer; 402. Treatment layer;

[0023] 500. Upper support component.

[0024] 600. Upper molding layer.

[0025] 700, high dielectric insulation layer.

[0026] 800, upper electrode.

[0027] 900, Hard mask layer; 901, Photoresist layer; 902, Support hole. Detailed Implementation

[0028] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0029] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0030] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0031] One or more embodiments of this disclosure can provide a method for manufacturing a semiconductor capacitor structure, which may include, but is not limited to, the following steps.

[0032] like Figure 1 and Figure 2 As shown, a semiconductor substrate 100 is provided, on which a plurality of spaced-apart pads 200 are formed. In some embodiments of this disclosure, at least one first stack and at least one second stack are sequentially formed over the semiconductor substrate 100. The first stack includes a lower molding layer 401, two lower support layers, and a disposal layer 402 between the two lower support layers. The second stack includes an upper molding layer 600 and an upper support layer. In subsequent semiconductor processes, the lower support layer is used to form a lower support member, and the upper support layer is used to form an upper support member. More specifically, in some embodiments of this disclosure, a lower molding layer 401, a lower support layer, a disposal layer 402, a lower support layer, an upper molding layer 600, and an upper support layer may be formed sequentially. The first stack is formed by sequentially depositing a lower molding layer 401, a lower support layer, a treatment layer 402, and another lower support layer. The second stack is formed by sequentially depositing an upper molding layer 600 and an upper support layer. These structures can be arranged sequentially in a vertical direction to form a stacked structure. One or more of these structures may be removed during the formation of the capacitor structure.

[0033] In some embodiments of this disclosure, the treatment layer 402 may be silicon nitride, and both the lower molding layer 401 and the upper molding layer 600 may be mold oxide layers. Mold oxide layers may be, for example, one of flowable oxide (FOX), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate-phosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PE-TEOS), fluorinated silicate glass (FSG), plasma-enhanced oxide (PEOX), or high-density plasma CVD (HDP-CVD) oxide. Some embodiments of this disclosure use silicon nitride, which is more soluble in BOE-type chemicals, as the treatment layer 402, which helps maintain a better profile during etching stacking, keeps the structure of the two underlying support layers stable, and thus ensures the stability of the capacitor structure at higher positions.

[0034] like Figure 2As shown, the second and first stacked layers can be etched sequentially to form capacitor nodeholes, thereby exposing each pad 200. In other embodiments of this disclosure, capacitor nodeholes are formed by sequentially etching the second and first stacked layers. The capacitor nodeholes are spaced apart and arranged in a honeycomb pattern, for example, they can be repeatedly arranged. Then, a lower electrode 300 is deposited within each capacitor nodehole. In this disclosure, the lower electrode 300 can be formed within each capacitor nodehole by depositing lower electrode 300 material. Next, the remaining second and first stacked layers can be etched. The process of etching the remaining second and first stacked layers is as follows.

[0035] like Figure 3 As shown, in some embodiments of this disclosure, a hard mask layer 900 and a photoresist layer 901 are sequentially formed on the upper support layer. A photoresist mask can be disposed above the photoresist layer 901. The photoresist layer 901 is patterned according to the support pattern to be formed. The hard mask layer 900 is then etched using the patterned photoresist layer 901 as a mask to form the support mask. Next, the remaining second and first stacked layers can be etched based on the remaining hard mask and the support mask. The process of etching the remaining second and first stacked layers based on the remaining hard mask and the support mask in some embodiments of this disclosure is as follows.

[0036] like Figure 4 As shown, the second stack can be etched based on the remaining hard mask and the support mask to form a support hole 902 between the lower electrodes 300 deposited in the capacitor hole. The etching method for the second stack can be, for example, dry etching.

[0037] like Figure 5 As shown, a BOE-based solution is filled into the support hole 902 to remove the upper molding layer 600. In some embodiments of this disclosure, using a BOE-based solution to remove the upper molding layer 600 can reduce the possibility of profile degradation during memory node etching, thereby avoiding problems such as bowing of the support film surface and the molding layer film surface. The BOE-based solution is a buffered oxide etching solution, which can be a mixture of hydrofluoric acid, water, and ammonium fluoride.

[0038] like Figure 6 As shown, etching continues downwards along the support hole 902 formed above. In some embodiments of this disclosure, the first stack is etched based on the remaining hard mask and the support mask, thereby deepening the support hole 902. The etching of the first stack can, for example, be done using dry etching.

[0039] like Figure 7As shown, a BOE-based solution is filled into the deepened support hole 902 to remove the treatment layer 402 and the lower molding layer 401. At this time, some embodiments of this disclosure can complete the etching of the remaining second and first stacks to form at least two lower support members 400 (lower support layers) and at least one upper support member 500 (upper support layer) between the sidewalls of adjacent lower electrodes 300. Some embodiments of this disclosure utilize BOE to remove the lower molding layer 401, which can reduce the possibility of profile degradation during memory node etching, thereby avoiding problems such as bowing of the support film surface and the molding layer film surface. The BOE-based solution is a buffered oxide etching solution, which can be composed of hydrofluoric acid, water, and ammonium fluoride.

[0040] It should be noted that other embodiments of this disclosure can also employ other methods to etch the remaining second and first layers, such as replacing the aforementioned layers. Figures 4 to 7 The steps described above are as follows. Other methods include, but are not limited to, the following steps: dry etching the second and first stacks based on the remaining hard mask and the support mask to form a support hole 902 between the lower electrode 300 deposited in the capacitor hole. The support hole 902 passes through the second stack and into the first stack, i.e., the support hole 902 extends directly into the first stack (e.g., into the upper support layer, which is different from the above method). Then, a BOE-based solution is filled into the support hole 902, and the upper molding layer 600 is removed using the BOE-based solution. The first stack is then dry etched again based on the remaining hard mask and the support mask, thereby deepening the support hole 902. The deepened support hole 902 is filled with a BOE-based solution, and the treatment layer 402 and the lower molding layer 401 are removed using the BOE-based solution. For the various embodiments of this disclosure, multiple etching operations more than those described above can also be used to achieve the final structure of the support. For example, this disclosure may also consider removing the upper molding layer 600 and the treatment layer 402 simultaneously, and then removing the lower molding layer 401, etc.

[0041] like Figure 7 As shown, after forming at least two layers of lower support members 400 and at least one layer of upper support member 500 between the sidewalls of adjacent lower electrodes 300, some embodiments of this disclosure may further include the following steps: A high-dielectric insulating layer 700 and an upper electrode 800 are sequentially deposited into the capacitor hole. The high-dielectric insulating layer 700 is deposited on the bottom and inner sidewall of the lower electrode 300, and then the upper electrode 800 is deposited on top of the high-dielectric insulating layer 700. Thus, this disclosure can also form a complete electrode structure in the capacitor hole.

[0042] like Figure 7As shown, based on the same inventive concept as the manufacturing method described above, one or more embodiments of this disclosure may also provide a semiconductor capacitor structure. Figure 8 Unlike conventional semiconductor capacitor structures, this semiconductor capacitor structure includes, but is not limited to, a semiconductor substrate 100, a bonding pad 200, a lower electrode 300, a multilayer lower support 400, an upper support 500, a high-dielectric insulating layer 700, and an upper electrode 800.

[0043] A plurality of spaced-apart pads 200 are formed on a semiconductor substrate 100, and each of the pads 200 can be disposed in a nitride layer. The nitride layer can be formed on the semiconductor substrate 100 and can be used for insulation between different pads 200. The semiconductor substrate 100 can be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, a III-V compound semiconductor substrate, or an epitaxial thin film substrate obtained by selective epitaxial growth (SEG). In some embodiments of this disclosure, the semiconductor substrate 100 may have structures such as active regions, bit lines, bit line node contacts, word lines, memory node contacts, pads, and sidewalls. The bit line material is at least one of a doped semiconductor material (e.g., doped silicon or doped germanium), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), a metal (e.g., tungsten, titanium, or tantalum), and / or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, or titanium silicide), and the bit line node contacts may be made of the same material as the bit lines. The structures disposed on the active region and the positions and connections between these structures can be wisely chosen from existing designs, and will not be elaborated further in this disclosure.

[0044] The solder pad 200 is conductive and is therefore disposed within an insulating nitride layer. The material of the solder pad 200 may be tungsten or cobalt, or at least one of a doped semiconductor material (e.g., doped silicon or doped germanium), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), a metal (e.g., tungsten, titanium, or tantalum), and / or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, or titanium silicide).

[0045] The bottom of the lower electrode 300 is located on the bonding pad 200. The material of the lower electrode 300 can be at least one of the following: metal, conductive metal oxide, doped polycrystalline silicon, such as high-melting-point metals (e.g., cobalt, titanium, nickel, tungsten, or molybdenum), metal nitrides (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), and / or tungsten nitride (WN)), noble metals (e.g., platinum (Pt), ruthenium (Ru), or iridium (Ir)), conductive noble metal oxides (e.g., PtO, RuO2, or IrO2), and / or conductive oxides (e.g., SrRuO3, RuO3, CaRuO3).

[0046] like Figure 7 As shown in some embodiments of this disclosure, at least two lower support members 400 are disposed between the sidewalls of adjacent lower electrodes 300. The material of the lower support member 400 can be a relatively hard nitride to achieve the function and role of supporting the electrode.

[0047] At least one upper support member 500 can also be disposed between the sidewalls of adjacent lower electrodes 300. The upper support member 500 is located above the lower support member 400. The upper support member 500 can be made of a relatively hard nitride material, thereby realizing the function and role of supporting the upper part of the electrode structure.

[0048] A high-dielectric insulating layer 700 is formed along the inner wall of the lower electrode 300. It is formed on the inner sidewall of the lower electrode by depositing high-dielectric insulating layer material, so the high-dielectric insulating layer 700 can be deposited on the bottom and inner sidewall of the lower electrode 300.

[0049] The upper electrode 800 is deposited above the high-dielectric insulating layer 700. The upper electrode is formed within the high-dielectric insulating layer by depositing upper electrode material, so the high-dielectric insulating layer 700 is located between the upper electrode 800 and the lower electrode 300. The material of the upper electrode 800 can be at least one of the following: metal, conductive metal oxide, and doped polycrystalline silicon, such as high-melting-point metals (e.g., cobalt, titanium, nickel, tungsten, or molybdenum), metal nitrides (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), and / or tungsten nitride (WN)), noble metals (e.g., platinum (Pt), ruthenium (Ru), or iridium (Ir)), conductive noble metal oxides (e.g., PtO, RuO2, or IrO2), and / or conductive oxides (e.g., SrRuO3, RuO3, CaRuO3).

[0050] One or more embodiments of this disclosure can provide a semiconductor capacitor structure with three or more supports, including at least two lower supports. The multiple supports can be positioned at different heights, effectively supporting the longitudinally distributed electrodes of the capacitor and preventing problems such as electrode misalignment due to increased height. The technical solution provided by this disclosure ensures a stable structure for capacitors with higher capacitance, guaranteeing the reliability and dependability of capacitor operation.

[0051] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, comprising multiple memory cells arranged in a matrix structure. Each memory cell mainly consists of a transistor and a capacitor controlled by the transistor. The memory cells are electrically connected through word lines and bit lines. Data is input from the bit line and then transmitted to the capacitor through the transistor, or data stored in the capacitor is output through the transistor and bit line. The capacitance of the capacitor is one of the most important factors determining the characteristics of DRAM, so maximizing the capacitance is crucial in its development. However, with the miniaturization of semiconductor devices, the cross-sectional size of DRAM products is becoming increasingly smaller, and the cross-sectional area of ​​the capacitor is also decreasing, making it very difficult to increase the capacitance. Some embodiments of this disclosure also provide DRAM, including a semiconductor capacitor structure according to one or more embodiments of this disclosure. This structure is suitable for three-dimensional capacitors, increasing the effective surface area of ​​the electrodes within a limited cross-section, thereby improving the capacitance while meeting the requirements of small-size devices. The memory may be, for example, DRAM. The electronic devices involved in this disclosure may include dynamic random access memory (DRAM) according to one or more embodiments of this disclosure. Electronic devices may include, for example, smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, power banks, etc.

[0052] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0053] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor capacitor structure, characterized in that, include: A semiconductor substrate is provided, on which a plurality of spaced-apart pads are formed; At least one first stack and at least one second stack are sequentially formed over the semiconductor substrate; the first stack includes a lower molding layer, two lower support layers and a treatment layer between the two lower support layers, and the second stack includes an upper molding layer and an upper support layer; The second stack and the first stack are etched to form capacitor holes, thereby exposing each solder pad; A lower electrode is deposited within each of the capacitor holes; The remaining second stack and the first stack are etched to form at least two lower supports and at least one upper support between the sidewalls of the adjacent lower electrodes; A high-dielectric insulating layer and an upper electrode are sequentially deposited into the capacitor hole. The high-dielectric insulating layer is deposited on the bottom and inner sidewall of the lower electrode, and the upper electrode is deposited on top of the high-dielectric insulating layer. The process of etching the remaining second and first layers includes: A hard mask layer and a photoresist layer are formed sequentially; The photoresist layer is patterned according to the support pattern to be formed; The hard mask layer is etched using the patterned photoresist layer as a mask to form the support mask; The remaining second stack and the first stack are etched based on the remaining hard mask and the support mask; The process of etching the remaining second and first stacked layers based on the remaining hard mask and the support mask includes: Based on the remaining hard mask and the support mask, the second stack and the first stack are etched to form a support hole between the lower electrodes deposited in the capacitor hole; the support hole passes through the second stack and into the first stack; The support hole is filled with a BOE-based solution, and the upper molding layer is removed using the BOE-based solution. The first stack is etched based on the remaining hard mask and the support mask, thereby deepening the support hole; The deepened support hole is filled with a BOE-based solution, and the treatment layer and the lower molding layer are removed using the BOE-based solution; the treatment layer is made of silicon nitride; the lower molding layer is made of molding oxide.

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