Low-refractive layer and display device

Abstract

The present application relates to a low-refractive layer and a display device. The display device includes a plurality of light emitting elements, a color conversion layer on the light emitting elements, and a low-refractive layer on the color conversion layer, wherein the low-refractive layer contains a monomer represented by Formula 1. In Formula 1, R1 and R3 can each independently be a substituted or unsubstituted alkyl group or hydrogen, R2 can be a substituted or unsubstituted alkylene group having two or more carbon atoms, X a , X b , and X c may each independently be a curable functional group, and n and m can each independently be a natural number of 1 to 5. Formula 1

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0095354, filed with the Korean Intellectual Property Office on July 30, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure relate to low-refractive layers and display devices. Background Technology

[0004] In recent years, interest in information display has increased. Therefore, research and development of display devices are ongoing. Summary of the Invention

[0005] Exemplary embodiments of this disclosure provide a low-refractive layer capable of improving display quality and light efficiency, as well as a display device.

[0006] The purposes of embodiments of this disclosure are not limited to those described above, and other purposes not described above will be apparent to those skilled in the art from the following description.

[0007] A display device according to an exemplary embodiment of the present disclosure includes: a plurality of light-emitting elements, a color conversion layer on the light-emitting elements, and a low-refractive-index layer on the color conversion layer, wherein the low-refractive-index layer comprises the following monomers represented by Formula 1:

[0008] Formula 1

[0009]

[0010] In Formula 1, R1 and R3 can each be independently a substituted or unsubstituted alkyl group or hydrogen, R2 can be a substituted or unsubstituted alkylene group having two or more carbon atoms, and X a X b and X c Each can be a solidifiable functional group independently, and n and m can each be a natural number from 1 to 5 independently.

[0011] The monomer may be included in an amount of 3 wt% to 10 wt% relative to the solid content of the low-refractive layer of 100 wt%.

[0012] The low-refractive layer may further contain hollow particles.

[0013] The hollow particles may be included in a content of 10 wt% to 80 wt% relative to the 100 wt% solid content of the low-refractive layer.

[0014] The curable functional group may include at least one selected from methacrylate groups, acrylate groups, vinyl groups, and epoxy groups.

[0015] The display device may further include an inorganic layer between the color conversion layer and the low-refractive layer.

[0016] The display device may further include a color filter layer overlapping the color conversion layer, and the low refractive layer may be located between the color conversion layer and the color filter layer.

[0017] The display device may further include an inorganic layer between the color filter layer and the low-refractive layer.

[0018] The inorganic layer may contain components selected from silicon oxide (SiO2). x (where x is a real number from 0.5 to 4), silicon nitride (SiN) x (where x is a real number from 0.5 to 4), silicon nitride (SiO2) x N y Where x is a real number from 0.5 to 4 and y is a real number from 0.1 to 2), aluminum oxide (AlO) x (where x is a real number from 0.5 to 4) and titanium oxide (TiO2) x , where x is at least one of the real numbers from 0.5 to 4.

[0019] The color conversion layer may comprise a matrix resin and quantum dots dispersed in the matrix resin.

[0020] Each of the light-emitting elements may include a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer.

[0021] An exemplary embodiment of the present disclosure comprises a low-refractive layer containing the following monomers represented by Formula 1:

[0022] Formula 1

[0023]

[0024] In Formula 1, R1 and R3 can each be independently a substituted or unsubstituted alkyl group or hydrogen, R2 can be a substituted or unsubstituted alkylene group having two or more carbon atoms, and X a X b and X c Each can be a solidifiable functional group independently, and n and m can each be a natural number from 1 to 5 independently.

[0025] The monomer may be included in an amount of 3 wt% to 10 wt% relative to the solid content of the low-refractive layer of 100 wt%.

[0026] The low-refractive layer may further contain hollow particles.

[0027] The hollow particles may be included in a content of 10 wt% to 80 wt% relative to the 100 wt% solid content of the low-refractive layer.

[0028] The hollow particles may have a diameter of 10 nm to 200 nm, and the shell of the hollow particles may have a thickness of 5 nm to 50 nm.

[0029] The hollow particles may include hollow silica particles.

[0030] The hollow particles may contain at least one selected from acrylic polymers, polyimide polymers, urethane polymers, styrene polymers, siloxane polymers, and epoxy polymers on their surface.

[0031] The low-refractive layer may further comprise at least one selected from curing agents, photopolymerization initiators, and ultraviolet absorbers.

[0032] The curable functional group may include at least one selected from methacrylate groups, acrylate groups, vinyl groups, and epoxy groups.

[0033] Other features of the exemplary embodiments are included in the detailed description and accompanying drawings. Attached Figure Description

[0034] The accompanying drawings, together with the description, illustrate embodiments of the subject matter of this disclosure and, together with the description, serve to explain the principles of embodiments of the subject matter of this disclosure.

[0035] Figure 1 and Figure 2 These are perspective and cross-sectional views illustrating a light-emitting element according to an exemplary embodiment.

[0036] Figure 3 This is a plan view illustrating a display device according to an exemplary embodiment.

[0037] Figures 4 to 6 This is a circuit diagram illustrating a pixel according to an exemplary embodiment.

[0038] Figure 7 This is a cross-sectional view illustrating a display device according to an exemplary embodiment.

[0039] Figure 8 and Figure 9 This is an example. Figure 7 A cross-sectional view of pixels.

[0040] Figure 10 This is a cross-sectional view illustrating a display device according to another exemplary embodiment.

[0041] Figure 11 This is a cross-sectional view illustrating a display device according to yet another exemplary embodiment. Detailed Implementation

[0042] The features of this disclosure and methods for implementing said features will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of this disclosure are illustrated. However, this disclosure is not limited to the exemplary embodiments set forth herein and can be implemented in various forms. Exemplary embodiments are provided only to complete the disclosure and to enable those skilled in the art to fully understand the scope of this disclosure. The scope of this disclosure is defined only by the appended claims and their equivalents.

[0043] The terminology used in this specification is intended to explain exemplary embodiments and not to limit the scope of this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. It should be further understood that the terms “comprises,” “comprising,” “includes,” and / or “including,” if used herein, specify the presence of the stated components, steps, operations, and / or elements, but do not preclude the presence or addition of one or more other components, steps, operations, and / or elements.

[0044] Furthermore, the term "connection" or "linkage" can refer to a physical and / or electrical connection or link. Additionally, the term can refer to a direct or indirect connection or link, as well as an integral or non-integral connection or link.

[0045] It should be understood that when an element or layer is referred to as "on" or "above" another element or layer, it can be directly on or above the other element or layer, or there can be an intermediate element or layer. Throughout the specification, the same reference numerals refer to the same element.

[0046] It should be understood that although terms such as “first” and “second” may be used herein to describe various components, these components are not limited by these terms. These terms are used only to distinguish one element or component from another. Therefore, without departing from the scope and spirit of this disclosure, the first component described below may be referred to as the second component.

[0047] Exemplary embodiments of this disclosure will be described in more detail below with reference to the accompanying drawings.

[0048] Figure 1 and Figure 2 These are perspective and cross-sectional views illustrating a light-emitting element according to an exemplary embodiment. Figure 1 and Figure 2 The example shown is a rod-shaped light-emitting element (LD) with a circular columnar shape, but the type (or kind) and / or shape of the light-emitting element (LD) is not limited to this.

[0049] refer to Figure 1 and Figure 2 The light-emitting element (LD) may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. As an example, when the extension direction of the light-emitting element (LD) is considered as the direction of length L, the light-emitting element (LD) may include a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13 stacked sequentially in the direction of length L.

[0050] The light-emitting element (LD) can be provided in the shape of a rod extending in one direction. The light-emitting element LD may include a first end EP1 and a second end EP2. One of the first semiconductor layer 11 and the second semiconductor layer 13 may be located at the first end EP1 of the light-emitting element LD. The other of the first semiconductor layer 11 and the second semiconductor layer 13 may be located at the second end EP2 of the light-emitting element LD.

[0051] According to an exemplary embodiment, the light-emitting element LD can be a rod-shaped light-emitting element (also known as a "bar-shaped light-emitting diode") manufactured by etching methods or the like. In this specification, the term "bar-shaped" includes all rod-shaped and bar-shaped forms, such as circular and polygonal cylinders, which are long in the direction of length L (e.g., having an aspect ratio greater than 1). The shape of the cross-section of the rod shape is not particularly limited. For example, the length L of the light-emitting element LD can be greater than its diameter D (or the width of the cross-section).

[0052] Light-emitting elements (LDs) can have small dimensions ranging from nanometers to micrometers. For example, an LD can have a diameter D (or width) and / or a length L, each ranging from nanometers to micrometers. However, the size of an LD is not limited to this. The size of an LD can vary depending on the design requirements of various devices (e.g., display devices using light-emitting devices that include LDs as a light source).

[0053] The first semiconductor layer 11 may be a first conductivity type semiconductor layer. For example, the first semiconductor layer 11 may include an N-type semiconductor layer. As an example, the first semiconductor layer 11 may include an N-type semiconductor layer containing any one of the semiconductor materials selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a first conductivity type dopant such as silicon (Si), germanium (Ge), or tin (Sn). However, the materials constituting the first semiconductor layer 11 are not limited to these, and the first semiconductor layer 11 may be made of various materials.

[0054] The active layer 12 can be on the first semiconductor layer 11 and can be formed as a single quantum well structure or a multi-quantum well structure. The position of the active layer 12 can be varied depending on the type (or kind) of the light-emitting element LD.

[0055] A cladding layer doped with conductive dopant may be formed on and / or beneath the active layer 12. As an example, the cladding layer may be formed as an AlGaN layer and / or an InAlGaN layer. According to an exemplary embodiment, materials such as AlGaN and / or InAlGaN may be used to form the active layer 12, and furthermore, various materials may constitute the active layer 12.

[0056] The second semiconductor layer 13 may be on the active layer 12 and may include a semiconductor layer of a different type than the first semiconductor layer 11. For example, the second semiconductor layer 13 may include a P-type semiconductor layer. As an example, the second semiconductor layer 13 may include a P-type semiconductor layer containing any semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a second conductivity type dopant such as magnesium (Mg). However, the materials constituting the second semiconductor layer 13 are not limited to this, and the second semiconductor layer 13 may be made of various materials.

[0057] In one exemplary embodiment, the first semiconductor layer 11 and the second semiconductor layer 13 may have different lengths (or thicknesses) in the direction of the length L of the light-emitting element LD. As an example, the first semiconductor layer 11 may have a relatively larger length (or thickness) than the second semiconductor layer 13 in the direction of the length L of the light-emitting element LD. Therefore, when the second semiconductor layer 13 is at the first end EP1 and the first semiconductor layer 11 is at the second end EP2, the active layer 12 of the light-emitting element LD may be positioned closer to the first end EP1 than the second end EP2.

[0058] When a voltage greater than or equal to the threshold voltage is applied to both ends of the light-emitting element (LD), electrons and holes combine with each other in the active layer 12, and thus, the LD emits light. By controlling the light emission of the LD using this principle, the LD can be used as a light source for various light-emitting devices, such as the light source for pixels in a display device.

[0059] The light-emitting element LD may further include an insulating film INF provided on its surface. The insulating film INF may be formed on the surface of the light-emitting element LD to surround at least the outer peripheral (e.g., circumferential) surface of the active layer 12. Furthermore, the insulating film INF may further surround a region of each of the first semiconductor layer 11 and the second semiconductor layer 13.

[0060] According to an exemplary embodiment, the insulating film INF can expose two ends of the light-emitting element LD with different polarities. For example, the insulating film INF can expose one end of each of the second semiconductor layer 13 and the first semiconductor layer 11 located at the first end EP1 and the second end EP2 of the light-emitting element LD. In another exemplary embodiment, the insulating film INF can expose the sides of the first semiconductor layer 11 and the second semiconductor layer 13 adjacent to the second end EP2 and the first end EP1 of the light-emitting element LD with different polarities.

[0061] According to an exemplary embodiment, the insulating film INF can be formed to contain materials selected from silicon oxide (SiO2). x ), silicon nitride (SiN) x ), aluminum oxide (AlO) x ) and titanium oxide (TiO) x At least one single layer or multiple layers of insulating material (e.g., aluminum oxide (AlO)) x ) and silicon oxide (SiO) x (The double layer is made of [insulation material]), but this disclosure is not limited thereto. According to an exemplary embodiment, the insulating film INF can be removed or omitted.

[0062] When an insulating film INF is provided to cover the surface of the light-emitting element LD, such as the outer periphery (e.g., circumferential) surface of the active layer 12, short circuits between the active layer 12 and the first pixel electrode or the second pixel electrode, which will be further described below, can be prevented or reduced. Therefore, the electrical stability of the light-emitting element LD can be ensured.

[0063] Furthermore, when the insulating film INF is provided on the surface of the light-emitting element (LD), surface defects of the LD can be minimized or reduced, thereby improving the lifespan and efficiency of the LD. Additionally, even when multiple LDs are close to each other, unwanted short circuits between the LDs can be prevented or reduced.

[0064] In one exemplary embodiment, the light-emitting element (LD) may further include additional components besides the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and / or the insulating film INF surrounding the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13. For example, the LD may additionally include at least one phosphor layer, an active layer, a semiconductor layer, and / or an electrode layer at one end of the first semiconductor layer 11, the active layer 12, and / or the second semiconductor layer 13. As an example, the electrode layer may be located at a first end EP1 and a second end EP2 of the LD. The electrode layer may be an ohmic contact electrode, but this disclosure is not limited to this. The electrode layer may be a Schottky contact electrode (e.g., an electrode at a metal-semiconductor junction). In some embodiments, in Figure 1 and Figure 2 The example shown is a rod-shaped light-emitting element (LD), but the type (or variety), structure, and / or shape of the light-emitting element (LD) can vary in various ways. For example, the light-emitting element (LD) can be formed as a core-shell structure with a polygonal pyramidal shape.

[0065] Light-emitting devices including the light-emitting elements (LDs) described above can be used in various types (or kinds) of devices that require a light source, such as display devices. For example, multiple light-emitting elements (LDs) can be present in each pixel of a display panel, and the light-emitting elements (LDs) can serve as the light source for each pixel. However, the application areas of light-emitting elements (LDs) are not limited to the examples described above. For example, light-emitting elements (LDs) can be used in other types (or kinds) of devices that require a light source, such as lighting devices.

[0066] Figure 3 This is a plan view illustrating a display device according to an exemplary embodiment.

[0067] As can be used in Figure 1 and Figure 2 The exemplary implementation described herein is an example of an electronic device with a light-emitting element (LD) as a light source. Figure 3 The illustrations depict display devices, such as display panels (PNLs) included in display equipment. However, this disclosure is not limited to this, and display panels (PNLs) may use various light-emitting elements, such as organic light-emitting diodes (OLEDs) including organic light-emitting layers, as light sources.

[0068] Each pixel unit PXU of the display panel PNL and each pixel constituting the pixel unit PXU may include one or more light-emitting elements (LDs). For convenience, in Figure 3 The structure of the display panel PNL is briefly illustrated based on the display area DA. However, according to an exemplary embodiment, at least one driving circuit unit (e.g., at least one selected from scan driver and data driver), lines, and pads may further be included in the display panel PNL.

[0069] refer to Figure 3 The display panel PNL may include a substrate SUB and pixel units PXU on the substrate SUB. Pixel unit PXU may include a first pixel PXL1, a second pixel PXL2, and / or a third pixel PXL3. In the following, when any one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 is arbitrarily described, the pixel will be referred to as "pixel PXL", or when at least two of the pixels are arbitrarily described, the pixel will be referred to as "pixel PXL".

[0070] The substrate SUB can form the base component of the display panel PNL and can be a rigid and / or flexible substrate and / or film. As an example, the substrate SUB can be a rigid substrate made of glass and / or tempered glass, a flexible substrate (or film) made of plastic and / or metal, or at least one insulating layer. The material and / or physical properties of the substrate SUB are not particularly limited.

[0071] In one exemplary embodiment, the substrate SUB may be substantially transparent. Here, the term "substantially transparent" may mean that light can be transmitted at a set or predetermined transmittance or at a transmittance higher than the set or predetermined transmittance. In another exemplary embodiment, the substrate SUB may be translucent or opaque. Furthermore, the substrate SUB may contain a reflective material according to the exemplary embodiment.

[0072] The display panel PNL and the substrate SUB used to form the display panel PNL may include a display area DA for displaying images and a non-display area NDA other than the display area DA.

[0073] Pixel PXL can be located in the display area DA. Various lines, pads, and / or embedded circuit units of pixel PXL connected to the display area DA can be located in the non-display area NDA. Pixel PXL can be configured as stripes and / or... Layout structure ( (This is a registered trademark of Samsung Display Co., Ltd.) The pixels PXL are arranged in a regular pattern. However, the arrangement structure of the pixels PXL is not limited to this, and the pixels PXL can be arranged in various structures and / or methods within the display area DA.

[0074] According to an exemplary embodiment, pixels PXL of two or more types (or varieties) emitting light of different colors can be located in the display area DA. As an example, a first pixel PXL1 emitting a first color of light, a second pixel PXL2 emitting a second color of light, and a third pixel PXL3 emitting a third color of light can be arranged in the display area DA. At least one first pixel PXL1, at least one second pixel PXL2, and at least one third pixel PXL3 adjacent to each other can constitute a pixel unit PXU capable of emitting light of various colors. For example, the first to third pixels (PXL1, PXL2, and PXL3) can each be a sub-pixel emitting light of a set or predetermined color. According to an exemplary embodiment, the first pixel PXL1 can be a red pixel emitting red light, the second pixel PXL2 can be a green pixel emitting green light, and the third pixel PXL3 can be a blue pixel emitting blue light, but this disclosure is not limited thereto.

[0075] In one exemplary embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may each include an element emitting a first color light, an element emitting a second color light, and an element emitting a third color light as light sources to emit the first color light, the second color light, and the third color light, respectively. In another exemplary embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include light-emitting elements emitting the same (e.g., substantially the same) color light. Furthermore, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include color conversion layers and / or color filters of different colors on the light-emitting elements to emit the first color light, the second color light, and the third color light. However, the color, type (or variety), and / or number of pixels PXL constituting each pixel unit PXU are not particularly limited. For example, the color of the light emitted by each pixel PXL can be varied.

[0076] Pixel PXL may include at least one light source driven by a set or predetermined control signal (e.g., scan signal and data signal) and / or a set or predetermined power supply (e.g., a first power supply and a second power supply). In one exemplary embodiment, the light source may include one or more according to... Figure 1 and Figure 2 The exemplary embodiments of the light-emitting element LD are, for example, micro light-emitting element LDs with small dimensions ranging from nanometers to micrometers. However, the present disclosure is not limited to this, and furthermore, various types (or kinds) of light-emitting element LDs can be used as the light source for the pixel PXL.

[0077] In one exemplary embodiment, each pixel PXL can be formed as an active pixel. However, the type (or variety), structure, and / or driving method of the pixel PXL suitable for a display device are not particularly limited. For example, each pixel PXL having various structures and / or driving methods can be formed as a pixel of a passive light-emitting display device or an active light-emitting display device.

[0078] Figures 4 to 6 This is a circuit diagram illustrating a pixel according to an exemplary embodiment. For example, Figures 4 to 6 An example of an implementation of a pixel PXL suitable for an active display device is shown. However, the type (or type) of pixel PXL and display device is not limited to this.

[0079] According to an exemplary implementation, Figures 4 to 6 The pixel PXL shown in the example can be selected from... Figure 3 The display panel PNL provides any one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may have substantially the same or similar structures.

[0080] refer to Figure 4 The pixel PXL may include a light source unit LSU for generating light at a brightness corresponding to the data signal and a pixel circuit PXC for driving the light source unit LSU.

[0081] A light source unit (LSU) may include one or more light-emitting elements (LDs) connected between a first power supply (VDD) and a second power supply (VSS). For example, the LSU may include a first electrode ELT1 (or also referred to as a "first pixel electrode" or "first alignment electrode") connected to the first power supply (VDD) via a pixel circuit (PXC) and a first power line PL1; a second electrode ELT2 (or also referred to as a "second pixel electrode" or "second alignment electrode") connected to the second power supply (VSS) via a second power line PL2; and a plurality of light-emitting elements (LDs) connected between the first electrode ELT1 and the second electrode ELT2 in the same (e.g., substantially the same) direction. In one exemplary embodiment, the first electrode ELT1 may be an anode, and the second electrode ELT2 may be a cathode.

[0082] Each of the light-emitting elements (LDs) may include a first end (e.g., a P-type end) connected to a first power supply VDD via a first electrode ELT1 and / or a pixel circuit PXC, and a second end (e.g., an N-type end) connected to a second power supply VSS via a second electrode ELT2. For example, the light-emitting elements (LDs) may be connected in parallel in the forward direction between the first electrode ELT1 and the second electrode ELT2. Each of the light-emitting elements (LDs) connected in the forward direction between the first power supply VDD and the second power supply VSS constitutes each effective light source, and the effective light sources may be aggregated to form a light source unit (LSU) for a pixel PXL.

[0083] The first power supply VDD and the second power supply VSS can have different potentials, causing the light-emitting element LD to emit light. As an example, the first power supply VDD can be set to a high potential power supply, and the second power supply VSS can be set to a low potential power supply. In this case, the potential difference between the first power supply VDD and the second power supply VSS can be set to be greater than or equal to the threshold voltage of the light-emitting element LD during the emission period of pixel PXL.

[0084] One end (e.g., the P-type end) of the light-emitting element LD constituting each light source unit LSU can be connected to the pixel circuit PXC via an electrode of the light source unit LSU (e.g., the first electrode ELT1 of each pixel PXL), and can be connected to the first power supply VDD via the pixel circuit PXC and the first power line PL1. The other end (e.g., the N-type end) of the light-emitting element LD can be connected to the second power supply VSS via another electrode of the light source unit LSU (e.g., the second electrode ELT2 of each pixel PXL) and the second power line PL2.

[0085] The light-emitting elements (LDs) can emit light with a brightness corresponding to the drive current supplied by the corresponding pixel circuits (PXCs). For example, during each frame period, the pixel circuits (PXCs) can supply a drive current to the light source units (LSUs) corresponding to the grayscale value expressed in the corresponding frame. The drive current supplied to the light source units (LSUs) can be split to flow to the light-emitting elements (LDs) connected in the forward direction. Therefore, when each light-emitting element (LD) emits light with a brightness corresponding to the current flowing to it, the light source unit (LSU) can emit light with a brightness corresponding to the drive current.

[0086] The pixel circuit PXC can be connected between the first power supply VDD and the first electrode ELT1. The pixel circuit PXC can be connected to the scan line Si and data line Dj of the corresponding pixel PXL. As an example, when pixel PXL is in the i-th horizontal line (row) and j-th vertical line (column) of display area DA (where i and j are natural numbers), the pixel circuit PXC of pixel PXL can be connected to the i-th scan line Si and the j-th data line Dj in display area DA.

[0087] According to an exemplary embodiment, a pixel circuit PXC may include a plurality of transistors and at least one capacitor. For example, a pixel circuit PXC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0088] The first transistor T1 is connected between the first power supply VDD and the light source unit LSU. For example, the first electrode (e.g., the source electrode) of the first transistor T1 can be connected to the first power supply VDD, and the second electrode (e.g., the drain electrode) of the first transistor T1 can be connected to the first electrode ELT1. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 controls the drive current supplied to the light source unit LSU in response to the voltage of the first node N1. For example, the first transistor T1 can be a drive transistor that controls the drive current of pixel PXL.

[0089] A second transistor T2 is connected between the data line Dj and the first node N1. For example, the first electrode (e.g., the source electrode) of the second transistor T2 can be connected to the data line Dj, and the second electrode (e.g., the drain electrode) of the second transistor T2 can be connected to the first node N1. The gate electrode of the second transistor T2 is connected to the scan line Si. When a scan signal SSi with a gate on-state voltage (e.g., a low voltage) is supplied from the scan line Si, the second transistor T2 is turned on to electrically connect the data line Dj and the first node N1.

[0090] During each frame period, a data signal DSj for the corresponding frame is supplied to the data line Dj, and the data signal DSj is transmitted to the first node N1 via a second transistor T2 that is turned on during the period in which a scan signal SSi with a gate on voltage is supplied. For example, the second transistor T2 may be a switching transistor for transmitting each data signal DSj to pixel PXL.

[0091] One electrode of the storage capacitor Cst is connected to the first power supply VDD, and the other electrode is connected to the first node N1. During each frame period, the storage capacitor Cst is charged with a voltage corresponding to the data signal DSj supplied to the first node N1.

[0092] exist Figure 4In this disclosure, the transistors included in the pixel circuit PXC (e.g., all of the first transistor T1 and the second transistor T2) are exemplified as P-type transistors, but the present disclosure is not limited thereto. At least one selected from the first transistor T1 and the second transistor T2 may be changed to an N-type transistor. Furthermore, the pixel circuit PXC may be provided with pixel circuits having various structures and / or driving methods.

[0093] refer to Figure 5 The pixel circuit PXC can be further connected to the sensing control line SCLi and the sensing line SLj. As an example, the pixel circuit PXC of pixel PXL in the i-th horizontal line and j-th vertical line of display area DA can be connected to the i-th sensing control line SCLi and the j-th sensing line SLj of display area DA. The pixel circuit PXC can further include a third transistor T3. In another exemplary embodiment, the sensing line SLj can be removed or omitted, and the characteristics of pixel PXL can also be detected by detecting the sensing signal SENj passing through the data line Dj of pixel PXL (or adjacent pixels).

[0094] The third transistor T3 is connected between the first transistor T1 and the sensing line SLj. For example, one electrode of the third transistor T3 can be connected to the first electrode (e.g., the source electrode) of the first transistor T1, which is connected to the first electrode ELT1, and the other electrode of the third transistor T3 can be connected to the sensing line SLj. In some embodiments, when the sensing line SLj is removed or omitted, the other electrode of the third transistor T3 can be connected to the data line Dj.

[0095] The gate electrode of the third transistor T3 is connected to the sensing control line SCLi. When the sensing control line SCLi is removed or omitted, the gate electrode of the third transistor T3 can be connected to the scan line Si. The third transistor T3 is turned on by a sensing control signal SCSi with a gate on-state voltage (e.g., high flat voltage) supplied to the sensing control line SCLi during a set or predetermined sensing period, thereby electrically connecting the sensing line SLj and the first transistor T1.

[0096] According to an exemplary embodiment, the sensing period can be the period during which characteristics (e.g., the threshold voltage of the first transistor T1) of each pixel PXL in the display area DA are extracted. During the sensing period described above, a set or predetermined reference voltage that can turn on the first transistor T1 can be supplied to the first node N1 via the data line Dj and the second transistor T2, or each pixel PXL can be connected to a current source, etc., to turn on the first transistor T1. Furthermore, a sensing control signal SCSi with a gate turn-on voltage can be supplied to the third transistor T3 to turn on the third transistor T3, thereby connecting the first transistor T1 to the sensing line SLj. Thereafter, a sensing signal SENj is obtained via the sensing line SLj, and the characteristics of each pixel PXL (including the threshold voltage of the first transistor T1) can be detected using the sensing signal SENj. The characteristic information of each pixel PXL can be used to convert image data so that characteristic differences between pixels PXL in the display area DA can be compensated.

[0097] exist Figure 5 In this embodiment, all of the first transistors T1 to the third transistors T3 are exemplified as N-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistors T1 to the third transistors T3 may be changed to a P-type transistor.

[0098] In addition, Figure 4 and Figure 5 In this context, the effective light sources constituting each light source unit (LSU), i.e., the light-emitting elements (LDs), are all connected in parallel, but this disclosure is not limited to this. For example, such as Figure 6 As illustrated, the light source unit (LSU) of each pixel PXL can be formed as a series structure comprising at least two stages. In the description... Figure 6 When referring to exemplary implementations, the details will not be repeated. Figure 4 and Figure 5 Detailed description of components that are the same as or similar to those in the exemplary embodiments (e.g., pixel circuits PXC).

[0099] refer to Figure 6 A light source unit (LSU) may include at least two light-emitting elements connected in series with each other. As an example, the LSU may include a first light-emitting element LD1, a second light-emitting element LD2, and a third light-emitting element LD3 connected in series between a first power supply VDD and a second power supply VSS. The first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can constitute an effective light source.

[0100] In the following text, when describing a specific or designated light-emitting element among the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3, the corresponding light-emitting element will be referred to as "first light-emitting element LD1", "second light-emitting element LD2", or "third light-emitting element LD3". When any one of the first light-emitting elements LD1, the second light-emitting element LD2, and the third light-emitting element LD3 is described, that light-emitting element will be referred to as "light-emitting element LD", or when the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 are described together, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 will all be referred to as "light-emitting element LD".

[0101] The first end (e.g., P-type end) of the first light-emitting element LD1 is connected to the first power supply VDD via the first electrode ELT1 (e.g., the first pixel electrode) of the light source unit LSU. The second end (e.g., N-type end) of the first light-emitting element LD1 is connected to the first end (e.g., P-type end) of the second light-emitting element LD2 via the first intermediate electrode IET1.

[0102] The first end of the second light-emitting element LD2 is connected to the second end of the first light-emitting element LD1. The second end of the second light-emitting element LD2 (e.g., the N-type end) is connected to the first end of the third light-emitting element LD3 (e.g., the P-type end) through the second intermediate electrode IET2.

[0103] The first end of the third light-emitting element LD3 is connected to the second end of the second light-emitting element LD2. The second end of the third light-emitting element LD3 (e.g., an N-type end) can be connected to the second power supply VSS via the second electrode ELT2 (e.g., the second pixel electrode) of the light source unit LSU. In the manner described above, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be connected in series between the first electrode ELT1 and the second electrode ELT2 of the light source unit LSU.

[0104] Figure 6 An exemplary embodiment in which the light-emitting elements (LDs) are connected in a three-stage series structure is illustrated, but the present disclosure is not limited thereto. Two light-emitting elements (LDs) may be connected in a two-stage series structure, or four or more light-emitting elements (LDs) may be connected in a four-stage series structure.

[0105] Assuming that the same brightness is expressed using light-emitting elements (LDs) under the same conditions (e.g., the same size and / or number), compared to a light source unit (LSU) having a structure in which the LDs are connected in parallel, the voltage applied between the first electrode ELT1 and the second electrode ELT2 can be increased in a light source unit (LSU) having a structure in which the LDs are connected in series, and the magnitude of the drive current flowing in the light source unit (LSU) can be reduced. Therefore, when the light source unit (LSU) for each pixel PXL is formed by applying a series structure, the panel current flowing in the display panel (PNL) can be reduced.

[0106] As described in the exemplary embodiments above, each light source unit (LSU) may include multiple light-emitting elements (LDs) connected in the forward direction between a first power supply (VDD) and a second power supply (VSS) to form an effective light source. Furthermore, the connection structure between the light-emitting elements (LDs) can be varied according to the exemplary embodiments. For example, the light-emitting elements (LDs) may be connected only in series or in parallel, or they may be connected in a hybrid series-parallel structure.

[0107] Figure 7 This is a cross-sectional view illustrating a display device according to an exemplary embodiment. Figure 8 and Figure 9 This is an example. Figure 7 A cross-sectional view of pixels.

[0108] exist Figure 7 In this context, a cross-section of a display device is illustrated based on a region in which a pixel unit PXU, comprising a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3 that are adjacent to each other. For example, a cross-section of a display panel PNL in a display device is provided.

[0109] also, Figure 8 and Figure 9 The structure of each pixel PXL is schematically illustrated based on a light-emitting element LD. To illustrate the various circuit elements constituting the pixel circuit PXC, a transistor T (e.g., connected to the first electrode ELT1) is shown. Figure 4 The first transistor T1 (etc.) and the storage capacitor Cst. In the following text, when it is not necessary to distinguish and specify the first transistor T1, the first transistor T1 will also be referred to as "transistor T".

[0110] In some implementations, the structure and / or location on each layer of the transistor T and the storage capacitor Cst are not limited to... Figure 8 and Figure 9The exemplary embodiments illustrated herein are subject to various modifications. Furthermore, in one exemplary embodiment, the transistors T constituting each pixel circuit PXC may have substantially the same or similar structures, but this disclosure is not limited thereto. For example, in another exemplary embodiment, at least one of the transistors T constituting each pixel circuit PXC may have a different cross-sectional structure than the other transistors T and / or may be located on a different layer than the other transistors T.

[0111] refer to Figures 7 to 9 The pixel PXL and the display device including the pixel PXL may include a substrate SUB, a circuit layer PCL on one surface of the substrate SUB, a display layer DPL, a color conversion layer CCL, a low refractive index layer LRL and / or a color filter layer CFL.

[0112] The circuit layer PCL may include circuit elements of the pixel circuit PXC constituting each pixel PXL and various lines connected to the circuit elements. The display layer DPL may include electrodes (e.g., first electrode ELT1 and second electrode ELT2 and / or first contact electrode CNE1 and second contact electrode CNE2) and light-emitting elements LD constituting the light source unit LSU constituting each pixel PXL.

[0113] The circuit layer PCL may include at least one circuit element electrically connected to the light-emitting element LD of each pixel PXL. For example, the circuit layer PCL may include a plurality of transistors T and storage capacitors Cst, which are located in each pixel region PXA and constitute the pixel circuit PXC of the corresponding pixel PXL. Furthermore, the circuit layer PCL may further include at least one power line and / or signal line connected to each pixel circuit PXC and / or light source unit LSU. For example, the circuit layer PCL may include a first power line PL1, a second power line PL2, and scan lines Si and data lines Dj for each pixel PXL. In some embodiments, the circuit layer PCL may be removed or omitted when the pixel circuit PXC is removed or omitted and the light source unit LSU of each pixel PXL is directly connected to the first power line PL1 and the second power line PL2 (or a set or predetermined signal line).

[0114] Furthermore, the circuit layer PCL may include multiple insulating layers. For example, the circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, a first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2, and / or a passivation layer PSV, sequentially stacked on one surface of the substrate SUB. Additionally, the circuit layer PCL may optionally further include at least one light-blocking pattern beneath at least some transistors T.

[0115] A buffer layer (BFL) prevents or reduces the diffusion of impurities into each circuit element. The buffer layer (BFL) can be formed as a single layer, but it can also be formed as a multilayer comprising at least two layers. When the buffer layer (BFL) is provided as a multilayer, the individual layers can be made of the same (e.g., substantially the same) material or can be made of different materials. Various circuit elements, such as transistors (T) and storage capacitors (Cst), as well as various lines connected to the circuit elements, can be on the buffer layer (BFL). In some embodiments, the buffer layer (BFL) can be removed or omitted according to exemplary embodiments. In this case, at least one circuit element and / or line can be directly on one surface of the substrate (SUB).

[0116] Each transistor T includes a semiconductor pattern SCP (also known as a “semiconductor layer” or “active layer”), a gate electrode GE, and a first transistor electrode TE1 and a second transistor electrode TE2. Figure 8 and Figure 9 An exemplary embodiment is illustrated in which each transistor T includes a first transistor electrode TE1 and a second transistor electrode TE2 formed separately from the semiconductor pattern SCP, but the present disclosure is not limited thereto. For example, in another exemplary embodiment, the first transistor electrode TE1 and / or the second transistor electrode TE2 provided in at least one transistor T may be integrated with each semiconductor pattern SCP.

[0117] The semiconductor pattern SCP can be on the buffer layer BFL. As an example, the semiconductor pattern SCP can be between the gate insulating layer GI and the substrate SUB on which the buffer layer BFL is formed. The semiconductor pattern SCP may include a first region contacting (e.g., physically contacting) each first transistor electrode TE1, a second region contacting (e.g., physically contacting) each second transistor electrode TE2, and a channel region positioned between the first and second regions. According to an exemplary embodiment, one of the first and second regions may be a source region, and the other may be a drain region.

[0118] According to an exemplary embodiment, the semiconductor pattern SCP can be a semiconductor pattern made of polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. Furthermore, the channel region of the semiconductor pattern SCP can be an undoped semiconductor pattern, such as an intrinsic semiconductor, and the first and second regions of the semiconductor pattern SCP can each be semiconductor patterns doped with a specified or predetermined impurity.

[0119] In one exemplary embodiment, the semiconductor pattern SCP of the transistor T constituting each pixel circuit PXC can be made of substantially the same or similar materials. For example, the semiconductor pattern SCP of the transistor T can be made of the same (e.g., substantially the same) material selected from polycrystalline silicon, amorphous silicon, and oxide semiconductors.

[0120] In another exemplary embodiment, some transistors T and the remaining transistors T may include semiconductor patterns SCP made of different materials. For example, the semiconductor patterns SCP of some transistors T may be made of polycrystalline silicon and / or amorphous silicon, and the semiconductor patterns SCP of the remaining transistors T may be made of oxide semiconductor.

[0121] The gate insulating layer GI can be on the semiconductor pattern SCP. As an example, the gate insulating layer GI can be between the semiconductor pattern SCP and the gate electrode GE. The gate insulating layer GI can be formed as a single layer or multiple layers and can contain various types (or kinds) of organic / inorganic insulating materials, including silicon nitride (SiN). x ) and / or silicon oxide (SiO) x ).

[0122] The gate electrode GE can be on the gate insulating layer GI. For example, the gate electrode GE can overlap with the semiconductor pattern SCP, and the gate insulating layer GI can be interposed therebetween. Figure 8 and Figure 9 The example shown depicts a transistor T with a top gate structure, but in another exemplary embodiment, the transistor T may have a bottom gate structure. In this case, the gate electrode GE may be superimposed on the semiconductor pattern SCP.

[0123] The first interlayer insulating layer ILD1 may be on the gate electrode GE. As an example, the first interlayer insulating layer ILD1 may be between the gate electrode GE and the first transistor electrode TE1 and the second transistor electrode TE2. The first interlayer insulating layer ILD1 may be formed as a single layer or multiple layers and may contain at least one inorganic insulating material and / or an organic insulating material. For example, the first interlayer insulating layer ILD1 may contain various types (or kinds) of organic / inorganic insulating materials, including silicon nitride (SiN). x ), silicon oxide (SiO) x ) and / or silicon nitride oxide (SiO) x N y Furthermore, the structural material of the first interlayer insulation layer ILD1 is not specifically restricted.

[0124] A first transistor electrode TE1 and a second transistor electrode TE2 may be located on each semiconductor pattern SCP, with at least one first interlayer insulating layer ILD1 interposed therebetween. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be located at different ends of the semiconductor pattern SCP, with a gate insulating layer GI and the first interlayer insulating layer ILD1 interposed therebetween. The first transistor electrode TE1 and the second transistor electrode TE2 may be electrically connected to each semiconductor pattern SCP. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be connected to a first region and a second region of the semiconductor pattern SCP via respective contact holes passing through the gate insulating layer GI and the first interlayer insulating layer ILD1. According to an exemplary embodiment, one of the first transistor electrode TE1 and the second transistor electrode TE2 may be a source electrode, and the other may be a drain electrode.

[0125] At least one transistor T provided in the pixel circuit PXC can be connected to at least one pixel electrode. As an example, the transistor T can be electrically connected to the first electrode ELT1 of the corresponding pixel PXL through a contact hole (e.g., the first contact hole CH1) passing through the passivation layer PSV and / or the bridging pattern BRP.

[0126] The storage capacitor Cst includes a first capacitor electrode CE1 and a second capacitor electrode CE2 that overlap each other. Each of the first capacitor electrode CE1 and the second capacitor electrode CE2 can be formed as a single layer or multiple layers. Furthermore, at least one of the first capacitor electrode CE1 and the second capacitor electrode CE2 can be on the same layer as at least one electrode or semiconductor pattern SCP constituting the first transistor T1.

[0127] For example, the first capacitor electrode CE1 can be formed as a multilayer electrode, including a lower electrode LE on the same layer as the semiconductor pattern SCP of the first transistor T1, and an upper electrode UE on the same layer as the first electrode TE1 and the second electrode TE2 of the first transistor T1 and electrically connected to the lower electrode LE. The second capacitor electrode CE2 can be formed as a single-layer electrode on the same layer as the gate electrode of the first transistor T1 and between the lower electrode LE and the upper electrode UE of the first capacitor electrode CE1. However, the structure and / or position of each of the first capacitor electrode CE1 and the second capacitor electrode CE2 can be varied. For example, one of the first capacitor electrode CE1 and the second capacitor electrode CE2 can include a conductive pattern on a layer different from the electrodes constituting the first transistor T1 (e.g., the gate electrode GE and the first transistor electrode TE1 and the second transistor electrode TE2) and the semiconductor pattern SCP. As an example, the first capacitor electrode CE1 and / or the second capacitor electrode CE2 can have a single-layer structure or a multilayer structure including a conductive pattern on the second interlayer insulating layer ILD2.

[0128] In one exemplary embodiment, at least one signal line and / or power line connected to each pixel PXL may be on the same layer as an electrode of the circuit element constituting the pixel circuit PXC. As an example, the scan line Si of each pixel PXL may be on the same layer as the gate electrode GE of the transistor T, and the data line Dj of each pixel PXL may be on the same layer as the first transistor electrode TE1 and the second transistor electrode TE2 of the transistor T.

[0129] The first power line PL1 and / or the second power line PL2 can be on the same layer as the gate electrode GE of transistor T or the first transistor electrode TE1 and the second transistor electrode TE2, or on a different layer. As an example, the second power line PL2, used to supply power to the second power supply VSS, can be on the second interlayer insulating layer ILD2, and therefore, at least a portion of it can be covered by the passivation layer PSV. The second power line PL2 can be electrically connected to the second electrode ELT2 of the light source unit LSU on the passivation layer PSV through a second contact hole CH2 passing through the passivation layer PSV. However, the location and / or structure of the first power line PL1 and / or the second power line PL2 can be varied. For example, the second power line PL2 can be on the same layer as the gate electrode GE of transistor T or the first transistor electrode TE1 and the second transistor electrode TE2, and therefore electrically connected to the second electrode ELT2 through at least one bridging pattern and / or the second contact hole CH2.

[0130] The second interlayer insulating layer ILD2 may be on the first interlayer insulating layer ILD1 and may cover the first transistor electrode TE1 and the second transistor electrode TE2 and / or the storage capacitor Cst positioned on the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may be formed as a single layer or multiple layers and may contain at least one inorganic insulating material and / or an organic insulating material. For example, the second interlayer insulating layer ILD2 may contain various types (or kinds) of organic / inorganic insulating materials, including silicon nitride (SiN). x ), silicon oxide (SiO) x ) and / or silicon nitride oxide (SiO) x N y However, this disclosure is not limited to this.

[0131] The bridging pattern BRP for connecting at least one circuit element (e.g., a first transistor T1) provided in the pixel circuit PXC to the first electrode ELT1, the first power line PL1, and / or the second power line PL2 can be on the second interlayer insulating layer ILD2. However, the second interlayer insulating layer ILD2 can be removed or omitted according to exemplary embodiments. In this case, it can be removed or omitted. Figure 8 and Figure 9 The bridging pattern BRP, etc., and the second power line PL2 can be positioned on a layer in which one electrode of the transistor T is located.

[0132] The passivation layer PSV can be applied to circuit elements such as transistor T and storage capacitor Cst, and / or lines such as first power line PL1 and second power line PL2. The passivation layer PSV can be formed as a single layer or multiple layers and can contain at least one inorganic insulating material and / or an organic insulating material. As an example, the passivation layer PSV can include at least an organic insulating layer and can be used to substantially planarize the surface of the circuit layer PCL.

[0133] The display layer DPL can be on the passivation layer PSV of the circuit layer PCL. The display layer DPL can include at least one pair of first electrodes ELT1 and second electrodes ELT2 constituting at least one pair in the emission region EMA of each pixel PXL and forming each light source unit LSU, and one or more light-emitting elements LD connected between the first electrodes ELT1 and the second electrodes ELT2. Figures 7 to 9 In the example, one light-emitting element LD is shown in each pixel PXL, but as in Figure 4 In exemplary embodiments such as those described above, each pixel PXL may include a plurality of light-emitting elements (LDs) connected between a first electrode ELT1 and a second electrode ELT2. Therefore, each exemplary embodiment will be described below assuming that the pixel PXL includes a plurality of light-emitting elements (LDs).

[0134] Furthermore, the display layer DPL may further include a first contact electrode CNE1 and a second contact electrode CNE2 for more stably connecting the light-emitting element LD between the first electrode ELT1 and the second electrode ELT2, a first embankment BNK1 for causing a region of each of the first electrode ELT1 and the second electrode ELT2 and / or the first contact electrode CNE1 and the second contact electrode CNE2 to protrude upwards, and a second embankment BNK2 surrounding each emitting region EMA. Furthermore, the display layer DPL may further include at least one conductive layer and / or an insulating layer.

[0135] The first dam BNK1 can be on the circuit layer PCL. The first dam BNK1 can be formed as a discrete or integral pattern. The first dam BNK1 can protrude in the height direction of the substrate SUB.

[0136] The first dike BNK1 can have various shapes according to exemplary embodiments. In an exemplary embodiment, the first dike BNK1 can be a dike structure with a positive reduction structure. For example, as Figures 7 to 9As illustrated, the first dam BNK1 can be formed with an inclined surface that is tilted relative to the substrate SUB at a set or predetermined angle. However, the present disclosure is not limited to this, and the first dam BNK1 can have sidewalls with a curved or stepped shape. As an example, the first dam BNK1 can have a cross-section with a semi-circular or semi-elliptical shape.

[0137] The electrodes and insulating layers on the first dam BNK1 can have shapes corresponding to the first dam BNK1. For example, the first electrode ELT1 and the second electrode ELT2, as well as the first contact electrode CNE1 and the second contact electrode CNE2, can be on a region of the first dam BNK1 and can have inclined or curved surfaces with shapes corresponding to the shape of the first dam BNK1. Similarly, the first insulating layer INS1, the third insulating layer INS3, and / or the fourth insulating layer INS4 can be on the first dam BNK1 and can have inclined or curved surfaces with shapes corresponding to the shape of the first dam BNK1.

[0138] The first dam BNK1 may comprise an insulating material, said insulating material comprising at least one inorganic and / or organic material. As an example, the first dam BNK1 may comprise at least one inorganic film, said inorganic film comprising, for example, silicon nitride (SiN). x ) and / or silicon oxide (SiO) x Various inorganic insulating materials. In some embodiments, the first dike BNK1 may include at least one layer of organic film and / or photoresist film comprising various types (or kinds) of organic insulating material, and / or may include a single-layer or multi-layer insulator comprising a combination of organic and inorganic materials. For example, the structural materials and / or pattern shape of the first dike BNK1 may vary in various ways.

[0139] In an exemplary embodiment, the first dam BNK1 can be used as a reflective member. As an example, the first dam BNK1 can be used as a reflective member that improves the light efficiency of pixel PXL by guiding the light emitted from each light-emitting element LD in a suitable or desired direction (e.g., the upward direction of pixel PXL) through the first electrode ELT1 and the second electrode ELT2 provided thereon.

[0140] The first electrode ELT1 and the second electrode ELT2 constituting the pixel electrodes of each pixel PXL can be on the first embankment BNK1. The first electrode ELT1 and the second electrode ELT2 can be provided therein and / or formed in each pixel region PXA of each pixel PXL. For example, the first electrode ELT1 and the second electrode ELT2 can be in the emission region EMA of each pixel PXL. The first electrode ELT1 and the second electrode ELT2 can be spaced apart from each other. For example, the first electrode ELT1 and the second electrode ELT2 can be spaced apart from each other by a set or predetermined interval in each emission region EMA, and can be side by side.

[0141] According to exemplary embodiments, the first electrode ELT1 and / or the second electrode ELT2 may have separate patterns for each pixel PXL, or they may have patterns that are commonly connected to multiple pixels PXL. In some embodiments, before the formation of pixels PXL, for example, after the alignment of the light-emitting element LD is completed, the first electrodes ELT1 of pixels PXL in the display area DA may be connected to each other, and the second electrodes ELT2 of pixels PXL may be connected to each other. For example, before the alignment of the light-emitting element LD is completed, the first electrodes ELT1 of pixels PXL may be formed integrally or non-integrally with each other and may be electrically connected to each other, and the second electrodes ELT2 of pixels PXL may be formed integrally or non-integrally with each other and may be electrically connected to each other. When the first electrodes ELT1 or the second electrodes ELT2 of pixels PXL are not integrally connected to each other, the first electrodes ELT1 or the second electrodes ELT2 may be electrically connected to each other through at least one contact hole and / or bridging pattern.

[0142] In the alignment operation of the light-emitting element (LD), the first electrode ELT1 and the second electrode ELT2 can each receive a first alignment signal (or a first alignment voltage) and / or a second alignment signal (or a second alignment voltage). As an example, one of the first electrode ELT1 and the second electrode ELT2 can receive an alternating current (AC) alignment signal, and the other of the first electrode ELT1 and the second electrode ELT2 can receive an alignment voltage with a constant voltage level (e.g., ground voltage). In some embodiments, during the alignment operation of the LD, a set or predetermined alignment signal can be applied to the first electrode ELT1 and the second electrode ELT2. Therefore, an electric field can be formed between the first electrode ELT1 and the second electrode ELT2. The LD provided in each pixel region (e.g., the emission region EMA of each pixel PXL) can self-align between the first electrode ELT1 and the second electrode ELT2 via the electric field. After the alignment of the LD is completed, at least the first electrode ELT1 can be disconnected between pixels PXL, and therefore, pixels PXL can be configured to be driven individually.

[0143] The first electrode ELT1 can be electrically connected via the first contact hole CH1 to a set or predetermined circuit element (e.g., at least one transistor constituting the pixel circuit PXC), a power line (e.g., the first power line PL1), and / or a signal line (e.g., a scan line Si, a data line Dj, or a set or predetermined control line). In an exemplary embodiment, the first electrode ELT1 can be electrically connected via the first contact hole CH1 to the bridging pattern BRP and via the bridging pattern BRP to the transistor T. However, this disclosure is not limited to this, and the first electrode ELT1 can be directly connected to a set or predetermined power line or signal line.

[0144] The second electrode ELT2 can be electrically connected via the second contact hole CH2 to a set or predetermined circuit element (e.g., at least one transistor constituting the pixel circuit PXC), a power line (e.g., the second power line PL2), and / or a signal line (e.g., a scan line Si, a data line Dj, or a set or predetermined control line). In one exemplary embodiment, the second electrode ELT2 can be electrically connected to the second power line PL2 via the second contact hole CH2. However, this disclosure is not limited to this, and the second electrode ELT2 can be directly connected to a set or predetermined power line or signal line.

[0145] Each of the first electrode ELT1 and the second electrode ELT2 may contain at least one conductive material (e.g., a conductive material). As an example, each of the first electrode ELT1 and the second electrode ELT2 may contain at least one metal selected from various metallic materials (including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), and copper (Cu)), or an alloy containing said at least one metal, or may contain at least one conductive material (e.g., a conductive material) selected from conductive oxides (e.g., indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), and / or fluorine tin oxide (FTO)) and conductive polymers (e.g., poly(3,4-ethylenedioxythiophene) (PEDOT)), but this disclosure is not limited thereto. For example, each of the first electrode ELT1 and the second electrode ELT2 may contain other conductive materials (e.g., conductive materials), such as carbon nanotubes and / or graphene. Furthermore, each of the first electrode ELT1 and the second electrode ELT2 may be formed as a single layer or multiple layers. As an example, each of the first electrode ELT1 and the second electrode ELT2 may include a reflective electrode layer containing a reflective conductive material (e.g., a reflective conductive material). Additionally, each of the first electrode ELT1 and the second electrode ELT2 may optionally further include at least one transparent electrode layer on and / or below the reflective electrode layer and at least one conductive capping layer covering the upper portion of the reflective electrode layer and / or the transparent electrode layer.

[0146] The first insulating layer INS1 may be on a region of each of the first electrode ELT1 and the second electrode ELT2. For example, the first insulating layer INS1 may be formed to cover a region of each of the first electrode ELT1 and the second electrode ELT2, and may include openings exposing other regions of each of the first electrode ELT1 and the second electrode ELT2. As an example, the first insulating layer INS1 may include openings formed on the upper surface of the first dam BNK1. The first electrode ELT1 and the second electrode ELT2 may be electrically connected to the first contact electrode CNE1 and the second contact electrode CNE2, respectively, in the regions where the first insulating layer INS1 is opened. In some embodiments, the first insulating layer INS1 may be removed or omitted according to exemplary embodiments. In this case, the light-emitting element LD may be directly on the passivation layer PSV and / or one end of the first electrode ELT1 and the second electrode ELT2.

[0147] In one exemplary embodiment, a first insulating layer INS1 can be formed to primarily and completely cover the first electrode ELT1 and the second electrode ELT2. After the first insulating layer INS1 is provided and aligned with the light-emitting element LD, the first insulating layer INS1 can be partially opened to expose a region of the first electrode ELT1 and the second electrode ELT2. For example, the first insulating layer INS1 may have an opening on the upper surface of the first embankment BNK1 that exposes a region of the first electrode ELT1 and the second electrode ELT2, and may at least cover portions of the sloping and / or curved surfaces of the first electrode ELT1 and the second electrode ELT2. In another exemplary embodiment, after the light-emitting element LD is provided and aligned, the first insulating layer INS1 may be patterned as a separate pattern, which is only partially below the light-emitting element LD. After the first electrode ELT1 and the second electrode ELT2 are formed, the first insulating layer INS1 can be formed to cover the first electrode ELT1 and the second electrode ELT2. Therefore, damage to the first electrode ELT1 and the second electrode ELT2 can be prevented or reduced in subsequent processes.

[0148] The first interlayer insulation layer ILD1 can be formed as a single layer or multiple layers, and can contain at least one inorganic insulating material and / or an organic insulating material. For example, the first interlayer insulation layer ILD1 can contain various types (or kinds) of organic / inorganic insulating materials, including silicon nitrides (SiN). x ), silicon oxide (SiO) x ) and / or aluminum oxide (AlO) x ).

[0149] The light-emitting element LD can be provided and aligned on the first electrode ELT1, the second electrode ELT2, and the first insulating layer INS1. In some embodiments, a second dam BNK2 can be formed around the emitting region EMA before the light-emitting element LD is provided. For example, the second dam BNK2 can be formed in the display region DA to surround each emitting region EMA.

[0150] The second dam BNK2 can be a structure defining an emission region EMA for each pixel PXL, and can be, for example, a pixel defining layer. For example, the second dam BNK2 can be provided in the boundary region of each pixel region PXA of each pixel PXL and / or in the region between adjacent pixels PXL, so as to surround the emission region EMA of each pixel region PXA. Hereinafter, when any one of the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 is arbitrarily described, the pixel region will be referred to as "pixel region PXA", or when at least two of the pixel regions are jointly described, the pixel region will be referred to as "pixel region PXA".

[0151] The second barrier BNK2 may contain at least one light-blocking and / or reflective material to prevent or reduce light leakage between adjacent pixels PXL. For example, the second barrier BNK2 may contain at least one black substrate material selected from various types (or varieties) of black substrate materials (e.g., at least one suitable light-blocking material commonly used in the art) and / or a color filter material having a set or specific color. For example, the second barrier BNK2 may be formed as a black opaque pattern to block or reduce light transmission. In an exemplary embodiment, a reflective layer may be formed on the surface (e.g., sidewall) of the second barrier BNK2 to further increase the light efficiency of the pixel PXL.

[0152] Furthermore, in the operation of supplying light-emitting element LD to each pixel PXL, the second dike BNK2 can be used as a dam structure defining each emission region EMA to which the light-emitting element LD should be supplied. For example, because each emission region EMA is divided by the second dike BNK2, the desired type (or variety) and / or amount of light-emitting element ink can be supplied to the emission region EMA.

[0153] In one exemplary embodiment, during the formation of the first barrier BNK1 of pixel PXL, the second barrier BNK2 may be formed in parallel (e.g., simultaneously) on the same layer as the first barrier BNK1. In another exemplary embodiment, the second barrier BNK2 may be formed on the same layer or a different layer than the first barrier BNK1 through a process separate from the formation of the first barrier BNK1. As an example, the second barrier BNK2 may be formed on the first barrier BNK1. For instance, the second barrier BNK2 may be formed on the first insulating layer INS1, but this disclosure is not limited thereto.

[0154] A light-emitting element (LD) can be provided to each pixel region PXA in which a first barrier BNK1, a first electrode ELT1, a second electrode ELT2, a first insulating layer INS1, and a second barrier BNK2 are formed, and can be aligned between the first electrode ELT1 and the second electrode ELT2. As an example, multiple light-emitting elements (LDs) can be provided to the emission region EMA of each pixel PXL via inkjet printing, narrow coating, and / or various other methods. The light-emitting elements (LDs) can be aligned to have directionality between the first electrode ELT1 and the second electrode ELT2 by applying a set or predetermined alignment signal (or alignment voltage) to each of the first electrode ELT1 and the second electrode ELT2.

[0155] In one exemplary embodiment, at least some light-emitting elements (LDs) may be positioned between a pair of first electrodes ELT1 and second electrodes ELT2, such that their two ends (e.g., first end EP1 and second end EP2) overlap the pair of first electrodes ELT1 and second electrodes ELT2. In another exemplary embodiment, at least some light-emitting elements (LDs) may be positioned between a pair of adjacent first electrodes ELT1 and second electrodes ELT2, such that the first electrodes ELT1 and / or the second electrodes ELT2 do not overlap, and may be electrically connected to the pair of first electrodes ELT1 and second electrodes ELT2 via first contact electrodes CNE1 and second contact electrodes CNE2. Each light-emitting element (LD) electrically connected between the first electrodes ELT1 and the second electrodes ELT2 may constitute an effective light source for the corresponding pixel PXL. The effective light source may constitute the light source unit (LSU) for the corresponding pixel PXL.

[0156] The second insulating layer INS2 may be applied to a region of the light-emitting element LD. For example, the second insulating layer INS2 may be applied to a region of each light-emitting element LD to expose the first end EP1 and the second end EP2 of each light-emitting element LD. As an example, the second insulating layer INS2 may be applied locally to a region including the central region of each light-emitting element LD. When the second insulating layer INS2 is formed on the light-emitting element LD after alignment of the light-emitting element LD is completed, separation of the light-emitting element LD from its alignment position can be prevented or reduced.

[0157] The second insulating layer INS2 can be formed as a separate pattern in the emission region EMA of each pixel PXL, but this disclosure is not limited thereto. The second insulating layer INS2 can be removed or omitted according to exemplary embodiments, and in this case, one end of each of the first contact electrode CNE1 and the second contact electrode CNE2 can be directly positioned (e.g., in physical contact) on the upper surface of the light-emitting element LD.

[0158] The second insulating layer INS2 can be formed as a single layer or multiple layers and can contain at least one inorganic insulating material and / or an organic insulating material. For example, the second insulating layer INS2 can contain various types (or kinds) of organic / inorganic insulating materials, including silicon nitrides (SiN). x ), silicon oxide (SiO) x ), aluminum oxide (AlO) x ) and / or photoresist (PR) materials.

[0159] The two ends of the light-emitting element LD that are not covered by the second insulating layer INS2, namely the first end EP1 and the second end EP2, can be covered by the first contact electrode CNE1 and the second contact electrode CNE2, respectively. The first contact electrode CNE1 and the second contact electrode CNE2 are formed to be spaced apart from each other. For example, the first contact electrode CNE1 and the second contact electrode CNE2 that are adjacent to each other can be spaced apart from each other on at least one of the first ends EP1 and the second ends EP2 of the adjacent light-emitting element LD, and the second insulating layer INS2 is inserted therebetween.

[0160] Furthermore, the first contact electrode CNE1 and the second contact electrode CNE2 can be on the first electrode ELT1 and the second electrode ELT2 to cover the exposed areas of the first electrode ELT1 and the second electrode ELT2. For example, the first contact electrode CNE1 and the second contact electrode CNE2 can be on a region of each of the first electrode ELT1 and the second electrode ELT2 to make direct or indirect contact with the first electrode ELT1 and the second electrode ELT2 on or around the first embankment BNK1, respectively. Therefore, the first contact electrode CNE1 and the second contact electrode CNE2 can be electrically connected to the first electrode ELT1 and the second electrode ELT2, respectively. For example, the first electrode ELT1 and the second electrode ELT2 can be electrically connected to the first end EP1 and the second end EP2 of at least one adjacent light-emitting element LD, respectively, through the first contact electrode CNE1 and the second contact electrode CNE2.

[0161] In one exemplary implementation, such as Figure 8 As illustrated, the first contact electrode CNE1 and the second contact electrode CNE2 can be sequentially formed on different layers on one surface of the substrate SUB. In this case, the third insulating layer INS3 can be between the first contact electrode CNE1 and the second contact electrode CNE2. In some embodiments, the order in which the first contact electrode CNE1 and the second contact electrode CNE2 are formed can be changed. For example, in another exemplary embodiment, the second contact electrode CNE2 can be formed first before the first contact electrode CNE1 is formed, and the first contact electrode CNE1 can be formed on one end of the third insulating layer INS3 after the third insulating layer INS3 is formed to cover the second contact electrode CNE2 and the second insulating layer INS2. However, the present disclosure is not limited thereto, and as such... Figure 9As illustrated, the first contact electrode CNE1 and the second contact electrode CNE2 can be on the same layer. For example, the first contact electrode CNE1 and the second contact electrode CNE2 can be formed as the same conductive layer on one surface of the substrate SUB. In this case, because the first contact electrode CNE1 and the second contact electrode CNE2 can be formed in the same (e.g., substantially the same) process and at the same (e.g., substantially the same) time, the manufacturing process of the pixel PXL and the display device including the pixel PXL can be simplified. However, the present disclosure is not limited to this, and the first contact electrode CNE1 and the second contact electrode CNE2 can be formed sequentially.

[0162] The first contact electrode CNE1 and the second contact electrode CNE2 can be made of various transparent conductive materials. As an example, the first contact electrode CNE1 and the second contact electrode CNE2 can contain at least one selected from various transparent conductive materials (e.g., transparent conductive materials) (e.g., indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), and / or fluorine tin oxide (FTO)), and can be substantially transparent or translucent to meet suitable or desired transmittance. Therefore, light emitted from the light-emitting element LD through its first end EP1 and second end EP2 can pass through the first contact electrode CNE1 and the second contact electrode CNE2 to be emitted to the outside of the display panel PNL.

[0163] A third insulating layer INS3 may be applied to the first contact electrode CNE1 to cover it. Alternatively, the third insulating layer INS3 may be applied to both the second insulating layer INS2 and the first contact electrode CNE1, such that one end of the third insulating layer INS3 is inserted between the first contact electrode CNE1 and the second contact electrode CNE2. One end of the second contact electrode CNE2 may be applied to one end of the third insulating layer INS3.

[0164] As described above, when the second insulating layer INS2 and the third insulating layer INS3 are formed on the light-emitting element LD, electrical stability can be ensured between the first end EP1 and the second end EP2 of the light-emitting element LD. For example, the first contact electrode CNE1 and the second contact electrode CNE2 can be stably separated by the second insulating layer INS2 and the third insulating layer INS3. Therefore, short-circuit defects between the first end EP1 and the second end EP2 of the light-emitting element LD can be effectively prevented or reduced.

[0165] The third insulating layer INS3 can be formed as a single layer or multiple layers and can contain at least one inorganic insulating material and / or an organic insulating material. For example, the third insulating layer INS3 can contain various types (or kinds) of organic / inorganic insulating materials, including silicon nitrides (SiN). x ), silicon oxide (SiO) x ), aluminum oxide (AlO) x ) and / or PR materials.

[0166] The fourth insulating layer INS4 may be on the first contact electrode CNE1, the second contact electrode CNE2, and / or the third insulating layer INS3. For example, the fourth insulating layer INS4 may cover the first dam BNK1 and the second dam BNK2, the first electrode ELT1 and the second electrode ELT2, and the first insulating layer INS1, the second insulating layer INS2, and / or the third insulating layer INS3, the light-emitting element LD, and the first contact electrode CNE1 and the second contact electrode CNE2. The fourth insulating layer INS4 may include at least one layer of inorganic film and / or organic film.

[0167] The fourth insulating layer INS4 can be formed as a single layer or multiple layers and can contain at least one inorganic insulating material and / or an organic insulating material. For example, the fourth insulating layer INS4 can contain various types (or kinds) of organic / inorganic insulating materials, including silicon nitrides (SiN). x ), silicon oxide (SiO) x ) and / or aluminum oxide (AlO) x ).

[0168] In one exemplary embodiment, the fourth insulating layer INS4 may include a thin-film encapsulation layer with a multilayer structure. For example, the fourth insulating layer INS4 may include a thin-film encapsulation layer with a multilayer structure comprising at least two inorganic insulating layers and at least one organic insulating layer interposed between the at least two inorganic insulating layers. However, this disclosure is not limited thereto, and the structural materials and / or structure of the fourth insulating layer INS4 may be varied.

[0169] The color conversion layer (CCL) can be on the display layer (DPL). The color conversion layer (CCL) can be in the area divided by the second embankment (BNK2).

[0170] The color conversion layer (CCL) may include a first color conversion layer (CCL1) on the first pixel PXL1, a second color conversion layer (CCL2) on the second pixel PXL2, and a light scattering layer (LSL) on the third pixel PXL3.

[0171] In one exemplary embodiment, the first to third pixels (PXL1, PXL2, and PXL3) may include light-emitting elements (LDs) that emit light having the same (e.g., substantially the same) color. For example, the first to third pixels (PXL1, PXL2, and PXL3) may include light-emitting elements (LDs) that emit a third color of light (e.g., a color in a wavelength band of about 400 nm to about 500 nm). A color conversion layer (CCL) containing color conversion particles is placed on at least some of the pixels PXL in the first to third pixels (PXL1, PXL2, and PXL3) to display a full-color image. However, this disclosure is not limited to this, and the first to third pixels (PXL1, PXL2, and PXL3) may include light-emitting elements (LDs) that emit light of different colors. For example, the first pixel PXL1 may include an element LD that emits a first color (e.g., red) of light, and the second pixel PXL2 may include an element LD that emits a second color (e.g., green) of light, and the third pixel PXL3 may include an element LD that emits a third color (e.g., blue) of light.

[0172] The first color conversion layer CCL1 may contain first color conversion particles that convert third-color light emitted from the light-emitting element LD into first-color light. For example, when the light-emitting element LD is a blue-emitting element that emits blue light and the first pixel PXL1 is a red pixel, the first color conversion layer CCL1 may contain first quantum dots QDr that convert blue light emitted from the blue-emitting element into red light. For example, the first color conversion layer CCL1 may contain a plurality of first quantum dots QDr dispersed in a set or predetermined matrix material (e.g., a matrix resin). The first quantum dots QDr can absorb blue light and change wavelength according to energy conversion to emit red light in a wavelength band of about 620 nm to about 780 nm. In some embodiments, when the first pixel PXL1 is a different-color pixel, the first color conversion layer CCL1 may contain first quantum dots corresponding to the color of the first pixel PXL1.

[0173] The second color conversion layer CCL2 may contain second color conversion particles that convert third-color light emitted from the light-emitting element LD into second-color light. For example, when the light-emitting element LD is a blue-light emitting element and the second pixel PXL2 is a green pixel, the second color conversion layer CCL2 may contain second quantum dots QDg that convert blue light emitted from the blue-light emitting element into green light. For instance, the second color conversion layer CCL2 may contain a plurality of second quantum dots QDg dispersed in a set or predetermined matrix material (e.g., a matrix resin). The second quantum dots QDg can absorb blue light and change wavelength according to energy conversion to emit green light in a wavelength band of about 500 nm to about 570 nm. In some embodiments, when the second pixel PXL2 is a different-color pixel, the second color conversion layer CCL2 may contain second quantum dots corresponding to the color of the second pixel PXL2.

[0174] Each of the first quantum dot QDr and the second quantum dot QDg may be selected from group II-IV compounds, group IV-VI compounds, group IV elements, group VI compounds and combinations thereof, but this disclosure is not limited thereto.

[0175] The first quantum dot QDr and the second quantum dot QDg can have a full width at half maximum (FWHM) of an emission wavelength spectrum of about 45 nm or less, and the light emitted by the first quantum dot QDr and the second quantum dot QDg can be emitted in all directions (e.g., in substantially every direction). Therefore, the viewing angle of the display device can be improved.

[0176] In some embodiments, the first quantum dot QDr and the second quantum dot QDg can be spherical, pyramidal, multi-armed, and / or cubic nanoparticles, nanotubes, nanowires, nanofibers, and / or nanoplate particles, but this disclosure is not limited to these. The shapes of the first quantum dot QDr and the second quantum dot QDg can be varied.

[0177] In one exemplary embodiment, when blue light with a relatively short wavelength in the visible light region is incident on each of the first quantum dot QDr and the second quantum dot QDg, the absorption coefficients of the first quantum dot QDr and the second quantum dot QDg can be increased. Therefore, the efficiency of light emitted from the first pixel PXL1 and the second pixel PXL2 can ultimately be increased, and excellent color reproduction can also be ensured. Furthermore, when the light source unit LSU of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 is formed using an element LD that emits light of the same (e.g., substantially the same) color (e.g., an element LD that emits blue light), the manufacturing efficiency of the display device can be increased.

[0178] A light scattering layer (LSL) may be optionally provided to effectively utilize the third color light emitted from the light-emitting element (LD). As an example, when the light-emitting element (LD) is a blue light-emitting element and the third pixel PXL3 is a blue pixel, the light scattering layer (LSL) may contain at least one type (or kind) of light scattering particles (SCT) to effectively utilize the light emitted from the light-emitting element (LD).

[0179] For example, the light scattering layer LSL may contain multiple light scattering particles SCT dispersed in a predetermined or set matrix material (e.g., matrix resin). As an example, the light scattering layer LSL may contain light scattering particles SCT of titanium dioxide (TiO2) and / or silicon dioxide, but the structural material of the light scattering particles SCT is not limited to these. In some embodiments, the light scattering particles SCT need not be formed only in the third pixel region PXA3 where the third pixel PXL3 is formed. As an example, the light scattering particles SCT may optionally be contained in the first color conversion layer CCL1 and / or the second color conversion layer CCL2.

[0180] The low-refractive-index (LRL) layer can be placed on top of the color conversion layer (CCL). The LRL layer can be positioned above the first through third pixels (PXL1, PXL2, and PXL3). Compared to the CCL, the LRL layer can have a relatively low refractive index. For example, the difference between the refractive index of the LRL layer and the CCL layer can be 0.3 or greater, but is not limited to this.

[0181] In some embodiments, during the formation of the color conversion layer CCL as described above, the thickness distribution of the color conversion layer CCL may increase due to the polarity difference between the inks of the second diaphragm BNK2 and the color conversion layer CCL. When a step difference is formed due to the color conversion layer CCL, display quality such as chromatic aberration may be reduced due to the volume difference of the color filter layer CFL thereon, as will be further described below. Therefore, in a display device according to an exemplary embodiment, the spreadability of the low refractive index layer LRL can be ensured to minimize or reduce the step difference caused by the color conversion layer CCL, etc.

[0182] In some implementations, the low-refractive layer (LRL) may contain a monomer represented by the following formula 1.

[0183] Formula 1

[0184]

[0185] In Formula 1, R1 and R3 can each be independently a substituted or unsubstituted alkyl group or hydrogen, R2 can be a substituted or unsubstituted alkylene group having two or more carbon atoms, and X a X band X c Each can be a curable functional group independently, and n and m can each be a natural number from 1 to 5 independently. In one exemplary embodiment, the curable functional group may include at least one selected from methacrylate groups, acrylate groups, vinyl groups, and epoxy groups, but this disclosure is not limited thereto.

[0186] When the low-refractive-index (LRL) layer contains a monomer represented by Formula 1, silicon (Si) atoms with low surface tension can be linearly arranged to improve spreadability on its surface, and the T-branching can ensure compatibility with matrix materials such as resins in parallel. The monomer can be included in amounts from 3 wt% to 10 wt% (e.g., amount or weight) relative to 100 wt% of the LRL layer's solids content. When the monomer is included in amounts less than 3 wt% (e.g., amount or weight), the effect of reducing step difference due to the LRL layer may not be significant. Furthermore, when the monomer is included in amounts exceeding 10 wt% (e.g., amount or weight), the hardness of the LRL layer and its adhesion to the underlying components may decrease.

[0187] The effects of the comparative examples and embodiments on reducing the step difference will be described below with reference to Table 1. The comparative examples correspond to the case where the low-refractive layer (LRL) does not contain monomers, and Examples 1 to 4 correspond to the case where the low-refractive layer (LRL) contains monomers. In this case, Example 1 corresponds to the case where monomers can be contained at a content (e.g., amount or weight) of 1 wt% relative to the solid content of the low-refractive layer (LRL). Example 2 corresponds to the case where monomers can be contained at a content (e.g., amount or weight) of 3 wt% relative to the solid content of the low-refractive layer (LRL). Example 3 corresponds to the case where monomers can be contained at a content (e.g., amount or weight) of 5 wt% relative to the solid content of the low-refractive layer (LRL). Example 4 corresponds to the case where monomers can be contained at a content (e.g., amount or weight) of 7 wt% relative to the solid content of the low-refractive layer (LRL).

[0188] Table 1

[0189] Monomer content (wt%) Step difference (μm) Effect of reducing step difference (%) Comparative example 0 2.604 - Example 1 1 2.218 14.8 Example 2 3 0.950 63.5 Example 3 5 0.672 74.2 Example 4 7 0.626 76.0

[0190] The step difference is measured based on the upper surface LRLs of the low-refractive-index layer (LRL). As used herein, "the upper surface LRLs of the low-refractive-index layer" can refer to a surface opposite to one of the surfaces covering the color conversion layer (CCL). In some embodiments, the step difference is measured by comparing the heights from the substrate SUB to the upper surface LRLs of the low-refractive-index layer in a third direction (Z-axis direction).

[0191] As can be seen from Table 1, the step difference of the low-refractive-index (LRL) layer in Example 1 is 2.218 μm, which is an improvement of approximately 14.8% compared to the comparative example; the step difference in Example 2 is 0.950 μm, which is an improvement of approximately 63.5% compared to the comparative example; the step difference in Example 3 is 0.672 μm, which is an improvement of approximately 74.2%; and the step difference in Example 4 is 0.626 μm, which is an improvement of approximately 76.0%. For example, according to Examples 2 to 4, when the low-refractive-index (LRL) layer contains a set or predetermined amount (e.g., amount or weight) of monomer, the spreadability of the low-refractive-index (LRL) layer can be ensured to reduce the step difference thereunder.

[0192] According to an exemplary embodiment, the low refractive index layer (LRL) may comprise a matrix resin and hollow particles (HP) dispersed in the matrix resin. The hollow particles (HP) may comprise hollow silica particles. According to an exemplary embodiment, the hollow particles (HP) may contain at least one selected from acrylic polymers, polyimide polymers, urethane polymers, styrene polymers, siloxane polymers, and epoxy polymers on their surface. Furthermore, the low refractive index layer (LRL) may comprise at least one selected from zinc oxide (ZnO) particles, titanium dioxide (TiO2) particles, nano-silicate particles, and porogen particles, but this disclosure is not limited to these.

[0193] In one exemplary embodiment, hollow particles HP may be included in an amount (e.g., by weight) of 10 wt% to 80 wt% relative to the solid content of the low-refractive-index layer (LRL). The hollow particles HP may have a diameter of 10 nm to 200 nm, and the shell of the hollow particles HP may have a thickness of 5 nm to 50 nm, but this disclosure is not necessarily limited thereto. According to an exemplary embodiment, the low-refractive-index layer (LRL) may further comprise at least one selected from a curing agent, a photopolymerization initiator, and an ultraviolet absorber.

[0194] As described above, when the low-refractive-index (LRL) layer contains a set or predetermined amount (e.g., quantity or weight) of monomers represented by Equation 1, the spreadability of the LRL layer can be ensured to minimize or reduce step differences caused by the components beneath it. For example, color differences caused by the thickness distribution of the color conversion layer (CCL) and / or the color filter layer (CFL) can be improved, thereby improving the display quality of the display panel PNL. Furthermore, a separate planarization layer for reducing step differences can be removed or omitted, thereby minimizing or reducing the thickness of the display panel PNL to improve light efficiency.

[0195] A color filter layer (CFL) may be located on a low-refractive-index layer (LRL). The CFL may include color filters corresponding to the color of each pixel (PXL). For example, the CFL may include a first color filter (CF1) on a first pixel (PXL1) to selectively transmit light generated in the first pixel (PXL1), a second color filter (CF2) on a second pixel (PXL2) to selectively transmit light generated in the second pixel (PXL2), and a third color filter (CF3) on a third pixel (PXL3) to selectively transmit light generated in the third pixel (PXL3). In one exemplary embodiment, the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) may be a red color filter, a green color filter, and a blue color filter, respectively, but are not limited thereto. Hereinafter, when any one of the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) is described, the color filter will be referred to as "color filter CF," or when at least two of the color filters are described together, the color filter will be referred to as "color filter CF."

[0196] The first color filter CF1 may overlap with the emission region EMA of the first pixel PXL1 and may contain a color filter material that selectively transmits light of a first color. For example, when the first pixel PXL1 is a red pixel, the first color filter CF1 may contain red color filter material.

[0197] The second color filter CF2 may overlap the emission region EMA of the second pixel PXL2 and may contain a color filter material that selectively transmits a second color of light. For example, when the second pixel PXL2 is a green pixel, the second color filter CF2 may contain green color filter material.

[0198] The third color filter CF3 may overlap with the emission region EMA of the third pixel PXL3 and may contain a color filter material that selectively transmits a third color of light. For example, when the third pixel PXL3 is a blue pixel, the third color filter CF3 may contain a blue color filter material.

[0199] The black substrate BM can be between color filters CF. The black substrate BM can be in the boundary region between pixel regions PXA so as not to overlap each emission region EMA. For example, the black substrate BM can overlap with the second embankment BNK2.

[0200] The black substrate BM may comprise at least one black substrate material selected from various types (or varieties) of black substrate materials (e.g., at least one suitable light-blocking material commonly used in the art) and / or a color filter material having a set or specific color. Furthermore, the black substrate BM may be made of the same (e.g., substantially the same) material as the second dam BNK2, but this disclosure is not limited thereto. For example, the black substrate BM and the second dam BNK2 may comprise the same (e.g., substantially the same) material or different materials. In some embodiments, the black substrate BM may be removed or omitted according to exemplary embodiments. In this case, the first to third color filters (CF1, CF2, and CF3) may overlap each other at the boundaries between pixel regions PXA.

[0201] The encapsulation layer ENC can be on the color filter layer CFL. The encapsulation layer ENC can cover the underlying color filter layer CFL, color conversion layer CCL, display layer DPL, and circuit layer PCL. The encapsulation layer ENC can prevent or reduce the penetration of moisture and / or air into the underlying components described above. For this purpose, the encapsulation layer ENC can include at least one inorganic layer. For example, the inorganic layer can contain materials selected from silicon nitride (SiN). x ), aluminum nitride (AlN) x ), titanium nitride (TiN) x ), silicon oxide (SiO) x ), aluminum oxide (AlO) x ), titanium oxide (TiO) x ) and silicon nitride oxide (SiO) x N y The present disclosure may include at least one of the following: (e.g., ), but is not limited thereto. Furthermore, the encapsulation layer ENC can protect the components described above beneath it from foreign substances such as dust. For this purpose, the encapsulation layer ENC may include at least one organic layer. For example, the organic layer may be made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin, but is not limited thereto. As described above, when the encapsulation layer ENC is on the color filter layer CFL, the thickness of the display panel PNL can be minimized or reduced to improve light efficiency because the separate upper substrate can be removed or omitted.

[0202] According to an exemplary embodiment, the capping layers (CP1 and CP2) may further be respectively located on one surface and another surface of the low-refractive-index layer LRL. The capping layers (CP1 and CP2) may include a first capping layer CP1 and a second capping layer CP2 respectively located on one surface and another surface of the low-refractive-index layer LRL.

[0203] The first capping layer CP1 can be located between the color conversion layer CCL and the low-refractive layer LRL. The first capping layer CP1 can be located above the first to third pixels (PXL1, PXL2, and PXL3). The first capping layer CP1 can seal the color conversion layer CCL. Therefore, it can prevent or reduce the penetration of impurities such as external moisture and / or air into the color conversion layer CCL, thus preventing damage or contamination of the color conversion layer CCL. The first capping layer CP1 can be an inorganic layer and can be made of materials selected from silicon nitride (SiN). x ), aluminum nitride (AlN) x ), titanium nitride (TiN) x ), silicon oxide (SiO) x ), aluminum oxide (AlO) x ), titanium oxide (TiO) x ) and silicon nitride oxide (SiO) x N y It is made from at least one of the following:

[0204] The second capping layer CP2 may be located between the low-refractive layer LRL and the color filter layer CFL. The second capping layer CP2 may be located above the first to third pixels (PXL1, PXL2, and PXL3). The second capping layer CP2 may prevent or reduce the penetration of impurities such as external moisture and / or air into the color filter layer CFL and / or the color conversion layer CCL, thereby preventing damage or contamination of the color filter layer CFL and / or the color conversion layer CCL. Furthermore, the second capping layer CP2 may prevent or reduce the diffusion of colorants contained in the color filter layer CFL into other components. The second capping layer CP2 may be an inorganic layer and may be made of the same (e.g., substantially the same) material as the first capping layer CP1, or may contain at least one material selected from those exemplified as the structural material of the first capping layer CP1.

[0205] According to the display device based on the exemplary embodiments described above, because the low-refractive-index layer (LRL) contains monomers represented by Formula 1 in a set or predetermined amount (e.g., quantity or weight), the spreadability of the LRL can be ensured to minimize or reduce step differences caused by the components beneath it. For example, color differences caused by the thickness distribution of the color conversion layer (CCL) and / or the color filter layer (CFL) can be improved, thereby improving the display quality of the display panel PNL. Furthermore, a separate planarization layer for reducing step differences can be removed or omitted, thereby minimizing or reducing the thickness of the display panel PNL to improve light efficiency.

[0206] Other exemplary embodiments will be described below. In the following exemplary embodiments, the same components as those described above will be represented by the same reference numerals, and their repetitive descriptions will not be repeated here or will be simplified.

[0207] Figure 10 This is a cross-sectional view illustrating a display device according to another exemplary embodiment.

[0208] refer to Figure 10 The display device according to this exemplary embodiment and Figures 1 to 9 The exemplary implementation differs in that the low-refractive layer LRL is in the region divided by the second embankment BNK2.

[0209] In some implementations, the low-refractive-index layer LRL may be inside the second dam BNK2 and may be partially located in each of the first to third pixel regions (PXA1, PXA2 and PXA3).

[0210] In this configuration, because the color conversion layer CCL is formed with a height lower than that of the second dam BNK2, even when a predetermined or set step difference is formed between the color conversion layer CCL and the second dam BNK2, the low refractive index layer LRL can minimize or reduce the step difference caused by the color conversion layer CCL within the area divided by the second dam BNK2. Therefore, color difference caused by the thickness distribution of the color conversion layer CCL and / or the color filter layer CFL can be improved, thereby improving the display quality of the display panel PNL. Furthermore, the separate planarization layer used to reduce step difference can be removed or omitted, thereby minimizing or reducing the thickness of the display panel PNL to improve light efficiency, as described above.

[0211] Furthermore, because the low refractive index layer (LRL), color conversion layer (CCL), and color filter layer (CFL) have already been referenced... Figure 7 Therefore, its repetitive description will not be repeated here.

[0212] Figure 11 This is a cross-sectional view illustrating a display device according to yet another exemplary embodiment.

[0213] refer to Figure 11 The display device according to this exemplary embodiment and Figures 1 to 9 The exemplary implementation differs in that the upper substrate UPL is positioned on a substrate SUB with pixel units PXU.

[0214] In some implementations, the upper substrate UPL (also known as the “encapsulation substrate” or “color filter substrate”) configured to encapsulate the first to third pixels (PXL1, PXL2 and PXL3) can be on one surface of the substrate SUB.

[0215] The upper substrate UPL can be on the color filter layer CFL, low refractive index layer LRL and color conversion layer CCL that overlap the first to third pixels (PXL1, PXL2 and PXL3).

[0216] In one exemplary embodiment, the space between the lower plate of the display panel PNL, including the substrate SUB and the display layer DPL, and the upper plate of the display panel PNL, including the upper substrate UPL, the color filter layer CFL, the low refractive index layer LRL, and the color conversion layer CCL, can be filled with an outer coating OC and / or an air layer having a relatively low refractive index of about 1 to about 1.6. According to an exemplary embodiment, an inorganic layer may further be present between the color conversion layer CCL and the outer coating OC. The inorganic layer can prevent or reduce the penetration of impurities such as moisture and / or air into the color conversion layer CCL. The inorganic layer may be made of materials selected from silicon nitride (SiN). x ), aluminum nitride (AlN) x ), titanium nitride (TiN) x ), silicon oxide (SiO) x ), aluminum oxide (AlO) x ), titanium oxide (TiO) x ) and silicon nitride oxide (SiO) x N y It may be made from at least one of the following, but this disclosure is not necessarily limited thereto.

[0217] The color filter layer (CFL), low-refractive-index layer (LRL), and color conversion layer (CCL) can be located on one surface of the upper substrate (UPL). For example, the color filter layer (CFL) can be formed on the upper substrate (UPL), the low-refractive-index layer (LRL) can be formed on the color filter layer (CFL), and the color conversion layer (CCL) can be formed on both the color filter layer (CFL) and the low-refractive-index layer (LRL). However, this disclosure is not limited thereto, and the order in which the color filter layer (CFL), the low-refractive-index layer (LRL), and the color conversion layer (CCL) are formed and / or the shapes thereof can be varied.

[0218] According to an exemplary embodiment, the black substrate BM can be located between the first color filter CF1, the second color filter CF2, and the third color filter CF3. The black substrate BM can be located at the boundaries between pixel regions PXA so as not to cover each emission region EMA. For example, the black substrate BM can overlap with the second embankment BNK2. Figure 11 The illustration shows a case where the black substrate BM is on the upper substrate UPL and each of the first to third color filters (CF1, CF2, and CF3) is located in an area divided by the black substrate BM, but the present disclosure is not limited thereto. In some embodiments, the first to third color filters (CF1, CF2, and CF3) may be formed on the upper substrate UPL, and the black substrate BM may be formed at the boundaries between pixel regions PXA. For example, the order in which the color filter layers CFL are formed and / or the position and / or shape according to the order may vary according to various exemplary embodiments.

[0219] According to an exemplary embodiment, the black substrate BM can be further positioned between the first color conversion layer CCL1, the second color conversion layer CCL2, and the light scattering layer LSL. Figure 11 The illustration shows a case where a black substrate BM is on a low-refractive layer LRL (or a first capping layer CP1) and each of the first color conversion layer CCL1, the second color conversion layer CCL2, and the light scattering layer LSL is located in an area divided by the black substrate BM, but the present disclosure is not limited thereto. For example, when it is not necessary to form the black substrate BM first according to the processing method and / or the performance of the printing equipment, the first color conversion layer CCL1, the second color conversion layer CCL2, and the light scattering layer LSL may be formed first, and then the black substrate BM may be formed. In some embodiments, the order in which the color conversion layers CCL are formed and / or the position and / or shape according to the order may be varied.

[0220] Furthermore, because the color filter layer CFL, the low refractive index layer LRL, and the color conversion layer CCL have already been referenced Figure 7 Therefore, its repetitive description will not be repeated here.

[0221] According to exemplary embodiments of this disclosure, the spreadability of the low-refractive layer can be ensured to minimize or reduce step differences caused by the components beneath it. For example, color differences caused by the thickness distribution of the color conversion layer and / or color filter layer can be improved, thereby improving the display quality of the display panel. Furthermore, a separate planarization layer for reducing step differences can be removed or omitted, thereby minimizing or reducing the thickness of the display panel to improve light efficiency.

[0222] The effects of implementing the embodiments of this disclosure are not limited to the exemplary embodiments described herein, and further additional effects and implementations are included in this specification.

[0223] It will be apparent to those skilled in the art to which the exemplary embodiments of this disclosure pertain, that various modifications are possible without departing from the essential characteristics of this disclosure. Therefore, the embodiments described above should be interpreted as illustrative rather than restrictive. It should be understood that the scope of this disclosure is defined by the appended claims, and all their equivalents fall within the scope of this disclosure.

Claims

1. A display device, comprising: Multiple light-emitting elements; Color conversion layer on the light-emitting element; as well as The low-refractive layer on the color conversion layer, The low-refractive layer comprises the following monomers represented by Formula 1: Formula 1 ， In Formula 1, R1 and R3 are each independently a substituted or unsubstituted alkyl group or hydrogen, R2 is a substituted or unsubstituted alkylene group having two or more carbon atoms, and X a X b and X c Each of them is an independently solidifiable functional group, and n and m are each independently natural numbers from 1 to 5. The monomer is contained in an amount of 3 wt% to 10 wt% relative to the solid content of the low-refractive layer of 100 wt%.

2. The display device of claim 1, wherein the low-refractive layer further comprises hollow particles.

3. The display device of claim 2, wherein the hollow particles are contained in an amount of 10 wt% to 80 wt% relative to the solid content of the low-refractive layer of 100 wt%.

4. The display device of claim 1, wherein the curable functional group comprises at least one selected from methacrylate groups, acrylate groups, vinyl groups, and epoxy groups.

5. The display device of claim 1, further comprising an inorganic layer between the color conversion layer and the low refractive layer.

6. The display device of claim 1, further comprising a color filter layer overlapping the color conversion layer. The low-refractive layer is located between the color conversion layer and the color filter layer.

7. The display device of claim 6, further comprising an inorganic layer between the color filter layer and the low refractive layer.

8. The display device of claim 7, wherein the inorganic layer comprises at least one selected from silicon oxide, silicon nitride, silicon nitride, aluminum oxide, and titanium oxide.

9. The display device of claim 1, wherein the color conversion layer comprises a matrix resin and quantum dots dispersed in the matrix resin.

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