A pixel and a display device including the pixel

Abstract

A pixel and a display device including the pixel are disclosed. The pixel is disposed in a pixel region defined by a gate line, a data line, and a pixel power supply line, and includes a light-emitting portion and a pixel circuit. The pixel circuit may include: a protruding electrode protruding from the gate line along the length direction of the data line; and a first switching thin-film transistor and a second switching thin-film transistor, which are arranged in parallel between the light-emitting portion and the gate line and use the protruding electrode as a gate electrode.

Description

Technical Field

[0001] The present disclosure relates to a pixel and a display device including the pixel. Background Art

[0002] With the progress of the information age, the demand for display devices for displaying images has increased in various forms. Therefore, various types of display devices have been used recently, such as liquid crystal display (LCD) devices, plasma display panel (PDP) devices, and organic light emitting display (OLED) devices.

[0003] Among these display devices, an organic light emitting display device is a self-luminous display device using an organic light emitting diode, which injects holes from an anode and electrons from a cathode into a light emitting layer, and emits light when excitons generated by the combination of the injected holes and electrons change their state from an excited state to a ground state.

[0004] According to the light emission direction, the organic light emitting display device can be classified into a top emission type, a bottom emission type, and a dual emission type, and according to the driving method, the organic light emitting display device can be classified into a passive matrix type and an active matrix type.

[0005] Different from a liquid crystal display (LCD) device, an organic light emitting display device does not require a separate light source, and thus can be manufactured in a thin and light form. In addition, since the organic light emitting display device is driven at a low voltage, it is advantageous in terms of power consumption. In addition, the organic light emitting display device has excellent color expression ability, high response speed, wide viewing angle, and high contrast ratio (CR). Therefore, the organic light emitting display device has been studied as a next-generation display device.

[0006] The organic light emitting display device has been developed in terms of a large area and / or an ultra-high resolution structure, thereby reducing the size of pixels. In this regard, a high aperture ratio structure for increasing the aperture area ratio in pixels is required. As the aperture area increases, the probability of pixel defects occurring in ultra-high resolution increases. When a defect occurs in a pixel, the pixel is connected to another pixel having the same color as the above pixel and adjacent to it, so that the pixel having the defect may not be recognized by a user. Considering these different situations, it will be necessary to develop a display device that can ensure a high aperture ratio in a large area and / or an ultra-high resolution and has a repair structure for defective pixels.

[0007] The disclosure of the above background art is owned by the inventors of the present disclosure to design the present disclosure, or is technical information obtained through the process of designing the present disclosure, but cannot be regarded as known art publicly available to the public before the present disclosure is disclosed. Summary of the Invention

[0008] The present disclosure is made in view of the above problems, and an object of the present disclosure is to provide a pixel and a display device including the pixel, in which the aperture ratio can be increased in a limited space of a sub-pixel, the structure can be simplified, and an improved repair structure can be obtained.

[0009] In addition to the object of the present disclosure described above, those skilled in the art will clearly understand additional objects and features of the present disclosure from the following description of the present disclosure.

[0010] According to one aspect of the present disclosure, the above and other objects can be achieved by providing a pixel disposed in a pixel region defined by a gate line, a data line, and a pixel power supply line, and including a light-emitting portion and a pixel circuit, wherein the pixel circuit may include: a protruding electrode protruding from the gate line along the length direction of the data line; and a first switching thin-film transistor and a second switching thin-film transistor disposed in parallel between the light-emitting portion and the gate line and using the protruding electrode as a gate electrode.

[0011] According to another aspect of the present disclosure, the above and other objects can be achieved by providing a display device including the above pixel.

[0012] According to another aspect of the present disclosure, the above and other objects can be achieved by providing a display device including a plurality of sub-pixels disposed in a pixel region defined by a gate line, a data line, and a pixel power supply line, the sub-pixel having a light-emitting portion and a pixel circuit, wherein the pixel circuit may include: a driving thin-film transistor connected to a first node, a second node, and the pixel power supply line; a first switching thin-film transistor connected to the gate line, the data line, and the first node between the light-emitting portion and the gate line; a second switching thin-film transistor disposed in parallel with the first switching thin-film transistor between the light-emitting portion and the gate line and connected to a reference line and the second node; a capacitor located between the first node and the second node; and a protruding electrode protruding from the gate line to overlap each of the first switching thin-film transistor and the second switching thin-film transistor, and the protruding electrode may be a gate electrode of each of the first switching thin-film transistor and the second switching thin-film transistor.

[0013] In the display device according to the present disclosure, the sensing thin-film transistor and the switching thin-film transistor may be disposed at a lower portion based on the opening area of each sub-pixel. The sensing thin-film transistor and the switching thin-film transistor share a gate electrode, and the data line and the sensing line may be simultaneously repaired and cut. As a result, the aperture ratio can be increased within the limited space of the sub-pixel, and an improved repair structure can be achieved. Consequently, the display performance can be improved by increasing the brightness based on the increased aperture ratio, and the lifespan of the light-emitting diode can be enhanced.

[0014] In addition to the effects of the present disclosure described above, those skilled in the art will clearly understand other objects and features of the present disclosure from the following description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other objects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0016] Figure 1 is a schematic block diagram showing a display device according to various embodiments of the present disclosure;

[0017] Figure 2 shows Figure 1 a schematic circuit driving diagram of a sub-pixel of the display device;

[0018] Figure 3 shows Figure 1 an equivalent circuit diagram of an example of a sub-pixel of the display device shown;

[0019] Figure 4 is a schematic plan view showing a unit pixel of a display device according to various embodiments of the present disclosure;

[0020] Figure 5 is a plan view showing a unit pixel of a display device according to various embodiments of the present disclosure;

[0021] Figure 6 is Figure 5 an enlarged view of part A of;

[0022] Figure 7 is a cross-sectional view taken along line I-I' of Figure 6 ;

[0023] Figure 8 is a view showing a repair process of a display device according to various embodiments of the present disclosure;

[0024] Figure 9 is Figure 8 an enlarged view of part B of;

[0025] Figure 10is a plan view showing a unit pixel of a display device according to various embodiments of the present disclosure;

[0026] Figure 11 is a cross-sectional view taken along the Figure 10 line II-II';

[0027] Figure 12 is a cross-sectional view taken along the Figure 10 line III-III';

[0028] Figure 13 is a cross-sectional view taken along the Figure 10 line IV-IV';

[0029] Figure 14 shows the Figure 10 equivalent circuit diagram of the storage capacitor of the sub-pixel of part C; and

[0030] Figures 15 to 19 is a plan view showing a single-layer structure of a part of a unit pixel of a display device according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0031] Advantages and features of the present disclosure and methods for implementing the same will be clarified by the following embodiments described with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is only defined by the scope of the claims.

[0032] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings used to describe the embodiments of the present disclosure are merely examples, and thus, the present disclosure is not limited to the details shown. Throughout the specification, the same reference numerals denote the same elements. In the following description, when a detailed description of a related known function or configuration is determined to unnecessarily obscure the gist of the present disclosure, the detailed description will be omitted.

[0033] When using "comprising", "having", and "including" described in this specification, another component may be added unless "only ~" is used. A term in the singular form may include the plural form unless otherwise stated.

[0034] When interpreting an element, the element is also interpreted to include a range of errors even though not explicitly described.

[0035] When describing a positional relationship, for example, when the positional relationship is described as "above", "over", "under", and "next to", one or more parts may be arranged between two other parts, unless "exactly" or "directly" is used.

[0036] When describing a temporal relationship, for example, when the time sequence is described as "after", "subsequently", "then", and "before", discontinuous cases may be included, unless "exactly" or "directly" is used.

[0037] It should be understood that although terms such as "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to separate one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present invention.

[0038] The terms "first horizontal axis direction", "second horizontal axis direction", and "vertical axis direction" should not be interpreted only based on the geometric relationship that each direction is perpendicular to each other, but may be expressed as directions with a wider directivity within the range where the components of the present disclosure can perform functional operations.

[0039] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of the first item, the second item, and the third item" represents all combinations of two or more of the first item, the second item, and the third item, as well as the first item, the second item, or the third item.

[0040] As can be fully understood by those skilled in the art, the features of various embodiments of the present disclosure may be combined or combined partially or wholly with each other, and may operate with each other in various ways and be technically driven. The embodiments of the present disclosure may be executed independently of each other, or may be executed together in a mutually dependent relationship.

[0041] Hereinafter, preferred embodiments of a display device according to the present disclosure will be described in detail with reference to the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to represent the same or similar components. Since, for ease of description, the scale of each element shown in the drawings is different from the actual scale, the present disclosure is not limited to the shown scale.

[0042] Figure 1 is a schematic block diagram showing a display device according to various embodiments of the present disclosure. Figure 2 is a schematic circuit driving diagram showing Figure 1 the sub-pixels of the display device. Figure 3 is a schematic circuit driving diagram showing Figure 1An equivalent circuit diagram of an example of sub-pixels of the display device shown.

[0043] Referring Figures 1 to 3 , according to various embodiments of the present disclosure, the display device 100 may include a display panel 110, an image processor 120, a timing controller 130, a data driver 140, and a scan driver 150.

[0044] The display panel 110 may display an image in response to a data signal DATA and a scan signal provided from the data driver 140 and the scan driver 150, respectively. The display panel 100 may include sub-pixels SP that operate to display an image.

[0045] According to the structure, the sub-pixels may be formed as a top-emission type, a bottom-emission type, or a dual-emission type. The sub-pixels SP may include red sub-pixels, green sub-pixels, and blue sub-pixels, or may include red sub-pixels, blue sub-pixels, white sub-pixels, and green sub-pixels. According to the light-emitting characteristics, the sub-pixels SP may have one or more different light-emitting regions.

[0046] The image processor 120 may output a data enable signal DE together with a data signal DATA provided from the outside. In addition to the data enable signal DE, the image processor 120 may also output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, but for the sake of convenience of description, these signals will be omitted and not shown.

[0047] The data signal DATA together with a driving signal including the data enable signal DE or a vertical synchronization signal, a horizontal synchronization signal, and a clock signal may be provided to the timing controller 130 from the image processor 120. The timing controller 130 may output a data timing control signal DDC for controlling the operation timing of the data driver 140 and a gate timing control signal GDC for controlling the operation timing of the scan driver 150 based on the driving signal.

[0048] The data driver 140 may sample and latch the data signal DATA provided from the timing controller 130 in response to the data timing control signal DDC provided from the timing controller 130, convert the latched data signal into a gamma reference voltage, and output the converted gamma reference voltage. The data driver 140 may output the data signal DATA through data lines DL1 to DLn. The data driver 140 may be implemented in the form of an integrated circuit (IC).

[0049] The scan driver 150 may output a scan signal in response to a gate timing control signal GDC provided from the timing controller 130. The scan driver 150 may output the scan signal through gate lines GL1 to GLm. The scan driver 150 may be implemented in the form of an integrated circuit (IC) or may be implemented in the display panel 110 in the type of gate-in-panel (GIP).

[0050] As Figure 2 shown, one sub-pixel SP constituting a unit pixel may include a switching thin film transistor SW, a driving thin film transistor DR, a storage capacitor Cst, a compensation circuit CC, and a light emitting diode EL.

[0051] In response to the scan signal provided through the first gate line GL1, the switching thin film transistor SW may perform a switching operation to store the data signal provided through the first data line DL1 in the storage capacitor Cst as a data voltage. The driving thin film transistor DR may operate according to the data voltage stored in the storage capacitor Cst to cause a driving current to flow between a first power supply line EVDD (e.g., a high potential voltage) and a second power supply line EVSS (e.g., a low potential voltage). The light emitting diode EL may operate according to the driving current formed by the driving thin film transistor DR to emit light.

[0052] The compensation circuit CC is a circuit added within the sub-pixel to compensate for the threshold voltage of the driving thin film transistor DR. The compensation circuit CC may include one or more thin film transistors. The compensation circuit CC may have various configurations according to the compensation method, and thus examples thereof will be described below.

[0053] As Figure 3 shown, the compensation circuit CC may include a sensing thin film transistor ST and a sensing line VREF.

[0054] The sensing thin film transistor ST may be connected between the drain electrode of the driving thin film transistor DR and the anode electrode of the light emitting diode EL (hereinafter referred to as the sensing node). The sensing thin film transistor ST may operate to provide an initialization voltage (or a sensing voltage) transmitted through the sensing line VREF to the sensing node of the driving thin film transistor DR, or sense the voltage or current of the sensing node or the sensing line VREF of the driving thin film transistor DR.

[0055] The first electrode (e.g., the source electrode) of the switching thin film transistor SW may be connected to the first data line DL1, and the second electrode (e.g., the drain electrode) of the switching thin film transistor SW may be connected to the gate electrode of the driving thin film transistor DR.

[0056] The first electrode (e.g., source electrode) of the driving thin film transistor DR can be connected to the first power supply line EVDD, and the second electrode (e.g., drain electrode) of the driving thin film transistor DR can be connected to the anode electrode of the light emitting diode EL.

[0057] The storage capacitor Cst can include a first electrode connected to the gate electrode of the driving thin film transistor DR and a second electrode connected to the anode electrode of the light emitting diode EL. In the display device according to various embodiments of the present disclosure, the storage capacitor Cst can include a first electrode pattern DTG connected to the gate electrode of the driving thin film transistor DR and a second electrode pattern DTS connected to the source electrode of the driving thin film transistor DR. The first electrode pattern DTG and the second electrode pattern DTS can be formed by conductorizing the active layer. In addition, according to various variations of the first electrode pattern DTG and the second electrode pattern DTS, the storage capacitor Cst can include a first capacitor formed in the horizontal direction and a second capacitor formed in the vertical direction. For example, each of the first electrode pattern DTG and the second electrode pattern DTS can include a finger pattern structure in which the first electrode pattern and the second electrode pattern are arranged in parallel on the same plane. The horizontal capacitor can be formed by a structure spaced apart from each other in the horizontal direction. The storage capacitor Cst will be described in more detail later.

[0058] The anode electrode of the light emitting diode EL can be connected to the second electrode of the driving thin film transistor DR, and its cathode electrode can be connected to the second power supply line EVSS. For example, the light emitting diode EL can be an organic light emitting diode (OLED).

[0059] The first electrode (e.g., source electrode) of the sensing thin film transistor ST can be connected to the sensing line VREF, and its second electrode (e.g., drain electrode) can be connected to the anode electrode of the light emitting diode EL and the second electrode of the driving thin film transistor DR, which serve as a sensing node.

[0060] According to the compensation algorithm (or the configuration of the compensation circuit), the operation time of the sensing thin film transistor ST can be similar to, the same as, or different from the operation time of the switching thin film transistor SW. For example, the gate electrode of the switching thin film transistor SW can be connected to the first gate line GL1, and the gate electrode of the sensing thin film transistor ST can be connected to the second gate line GL2. In this case, the scan signal Scan can be transmitted to the first gate line GL1, and the sense signal Sense can be transmitted to the second gate line GL2. Again, the first gate line GL1 connected to the gate electrode of the switching thin film transistor SW and the second gate line GL2 connected to the gate electrode of the sensing thin film transistor ST can be connected to each other.

[0061] The sensing line VREF can be connected to the data driver 140. In this case, the data driver 140 can sense the sensing nodes of the sub-pixels in real time (e.g., during the non-display period of an image or during the non-display period in an N-frame period (N is an integer greater than or equal to 1)), and can generate sensing results. At the same time, the switching thin film transistor SW and the sensing thin film transistor ST can be turned on simultaneously. In this case, the sensing operation through the sensing line VREF and the data output operation for outputting data signals can be separated (resolved) from each other by the time division method of the data driver 140.

[0062] In addition, the compensation target based on the sensing result can be a digital data signal, an analog data signal, or gamma. The compensation circuit for generating a compensation signal (or compensation voltage) based on the sensing result can be implemented as an internal circuit of the data driver 140, an internal circuit of the timing controller 130, or a separate circuit.

[0063] In addition, in Figure 3 's example, although the sub-pixel of the 3T (transistor) 1C (capacitor) structure including the switching thin film transistor SW, the driving thin film transistor DR, the storage capacitor Cst, the light emitting diode EL, and the sensing thin film transistor ST has been described as an example, when the compensation circuit CC is added thereto, each sub-pixel can have a structure such as 3T2C, 4T2C, 5T1C, 6T2C, etc.

[0064] Figure 4 is a schematic plan view showing a unit pixel of a display device according to various embodiments of the present disclosure. Figure 4 Briefly shown is Figure 3 the unit pixel composed of the sub-pixels of

[0065] Referring to Figure 4 , the unit pixel of the display device according to various embodiments of the present disclosure can be composed of first to fourth sub-pixels R, B, W, G including a red sub-pixel R, a blue sub-pixel B, a white sub-pixel W, and a green sub-pixel G. However, the present disclosure is not limited to Figure 4 this example of

[0066] Each of the first to fourth sub-pixels R, B, W, and G may be arranged in an opening area LE of a light-emitting area, and a first circuit area C1 and a second circuit area C2 may be respectively provided on both sides of the opening area (or light-emitting area) LE (i.e., the upper side and the lower side of the figure). That is, in a display device according to various embodiments of the present disclosure, the first circuit area C1 and the second circuit area C2 in each of the sub-pixels R, B, W, and G may be separated from each other based on the opening area LE.

[0067] In a display device according to various embodiments of the present disclosure, driving thin-film transistors DR included in the first to fourth sub-pixels R, B, W, and G may be respectively provided in the first circuit areas RC1, BC1, WC1, and GC1, and switching thin-film transistors SW and sensing thin-film transistors ST may be respectively provided in the second circuit areas RC2, BC2, WC2, and GC2, and storage capacitors Cst may respectively overlap with the opening areas RLE, BLE, WLE, and GLE and be provided between the first circuit areas RC1, BC1, WC1, and GC1 and the second circuit areas RC2, BC2, WC2, and GC2.

[0068] Since a display device according to various embodiments of the present disclosure includes a first circuit area C1 and a second circuit area C2 based on the opening areas LE of the sub-pixels R, B, W, and G located on the upper side and the lower side, different rows of sub-pixels R, B, W, and G adjacent to each other may be set in a mirror shape to share a common line therebetween, thereby obtaining an effect of increasing the aperture ratio.

[0069] Figure 5 is a plan view showing a unit pixel of a display device according to various embodiments of the present disclosure. Figure 5 More specifically shown is Figure 4 the unit pixel of the display device.

[0070] Referring to Figure 5 , a display device according to various embodiments of the present disclosure may include first to fourth sub-pixels R, B, W, and G constituting one unit pixel.

[0071] Each of the sub-pixels R, B, W, and G may be defined by an intersection between a gate line GL and a data line DL, and may include a light-emitting diode PXL, a driving thin-film transistor DR, a sensing thin-film transistor ST, a switching thin-film transistor SW, a first storage capacitor Cst1, and a second storage capacitor Cst2.

[0072] A first electrode ANO of the light-emitting diode PXL and the first storage capacitor Cst1 may be provided in the opening area (or light-emitting area).

[0073] The driving thin film transistor DR can be disposed in a first circuit region provided on one side of the opening region (e.g., the upper side of the opening region), and the sensing thin film transistor ST, the switching thin film transistor SW, and the second storage capacitor Cs2 can be disposed in a second circuit region provided on the other side of the opening region (e.g., the lower side of the opening region).

[0074] Each of the sub-pixels R, B, W, G may include an opening region (or a light-emitting region) provided with a first storage capacitor Cs1, a color filter CF, and a light-emitting diode PXL, a first circuit region including a driving thin film transistor DR provided on one side of the opening region (e.g., the upper side of the opening region), and a second circuit region including a sensing thin film transistor ST, a switching thin film transistor SW, and a second storage capacitor Cs2 provided on the other side of the opening region (e.g., the lower side of the opening region).

[0075] By using a plurality of pixel power supply lines EVDD1 and EVDD2 as boundaries, four sub-pixels (first sub-pixel to fourth sub-pixels R, B, W, G) constituting one unit pixel can be separated from an adjacent unit pixel. For example, the plurality of power supply lines EVDD1 and EVDD2 may be respectively provided on the left side of the first sub-pixel R and the right side of the fourth sub-pixel G arranged along the second direction (e.g., the vertical direction). A pixel power supply sharing line EVDD_H extending in the first direction and electrically connected to the pixel power supply lines EVDD1 and EVDD2 on the left and right sides may be included between the plurality of pixel power supply lines EVDD1 and EVDD2. The plurality of pixel power supply lines EVDD1 and EVDD2 may be connected to the driving thin film transistor DR provided in the first circuit region of the first sub-pixel to the fourth sub-pixels R, B, W, G through the pixel power supply sharing line EVDD_H.

[0076] The data lines DL1 to DL4 may be arranged in parallel between the first sub-pixel R and the second sub-pixel B arranged along the second direction and between the third sub-pixel W and the fourth sub-pixel G. Each of the data lines DL1 to DL4 may supply a data signal to the switching thin film transistor SW provided in the second circuit region of the adjacent sub-pixels R, B, W, G.

[0077] A gate line GL arranged to extend along the first direction may be included at a position corresponding to the second circuit region of the respective sub-pixels R, B, W, G.

[0078] The reference line VREF can be set parallel to a plurality of pixel power supply lines EVDD1 and EVDD2 between a second sub-pixel B and a third sub-pixel W arranged along a second direction. The reference line VREF can include a second power sharing line VREF_H extending left and right in a horizontal direction. The second power sharing line VREF_H can be formed to extend to the left and right based on a center connected to the reference line. The reference line VREF can be connected to a sensing thin film transistor ST provided in a second circuit region of the first sub-pixel to the fourth sub-pixels R, B, W, G through the second power sharing line VREF_H.

[0079] Figure 6 is Figure 5 an enlarged view of part A of. Figure 7 is a cross-sectional view taken along line I-I’ of Figure 6 . These drawings are intended to specifically describe the sensing thin film transistor and the switching thin film transistor in a display device according to various embodiments of the present disclosure.

[0080] Combined with Figure 5 and with reference to Figure 6 and Figure 7 , in a second circuit region of each of the sub-pixels R, B, W, G in a display device according to various embodiments of the present disclosure, a protruding electrode ST_SW_GAT protruding from a gate line GL can be formed along the length direction of a data line DL. The protruding electrode ST_SW_GAT can be a gate electrode commonly used in the sensing thin film transistor ST and the switching thin film transistor SW.

[0081] The sensing thin film transistor ST and the switching thin film transistor SW can be arranged in parallel in a horizontal direction intersecting the protruding electrode ST_SW_GAT.

[0082] The sensing thin film transistor ST can be connected to the gate line GL, the reference line VREF, and a source electrode of a driving thin film transistor DR. The sensing thin film transistor ST can include a reference line connection pattern VREF_H_b that extends in a horizontal direction intersecting the protruding electrode ST_SW_GAT and is connected to the reference sharing line VREF_H. The reference line connection pattern VREF_H_b can be formed as an active layer ST_ACT extending from the sensing thin film transistor ST. For example, the active layer can be made conductive to serve as the reference line connection pattern VREF_H_b.

[0083] The switching thin-film transistor SW can be connected to the gate line GL, the data line DL, and the gate electrode of the driving thin-film transistor DR. The switching thin-film transistor SW can include a data line connection pattern DL_b that extends in a horizontal direction intersecting the protruding electrode ST_SW_GAT and is connected to the data line DL. The data line connection pattern DL_b can be formed as an active layer SW_ACT extending from the switching thin-film transistor SW. For example, the active layer can be made conductive to serve as the data line connection pattern DL_b. Meanwhile, although Figure 5 and Figure 6 show the sensing thin-film transistor ST disposed on the upper portion and the switching thin-film transistor SW disposed on the lower portion, various embodiments of the present disclosure are not limited to Figure 5 and Figure 6 the example, the switching thin-film transistor SW can be disposed on the upper portion and the sensing thin-film transistor ST can be disposed on the lower portion.

[0084] An auxiliary capacitor Cst2 can be formed in the second circuit region of each of the sub-pixels R, B, W, G. The auxiliary capacitor Cst2 can be formed between the gate electrode of the driving thin-film transistor DR and the source electrode of any one of the sensing thin-film transistor ST and the switching thin-film transistor SW.

[0085] Referring to Figure 7 , a buffer layer BUF, an active layer ST_ACT of the sensing thin-film transistor ST, an active layer SW_ACT of the switching thin-film transistor SW, a protruding electrode ST_SW_GAT, an interlayer dielectric film ILD, and source / drain electrodes SD can be disposed on the substrate SUB.

[0086] The active layer ST_ACT of the sensing thin-film transistor ST can be formed parallel to the gate line GL and connected to the reference shared line VREF_H, while the active layer SW_ACT of the switching thin-film transistor SW can be formed parallel to the active layer ST_ACT of the sensing thin-film transistor ST and connected to the data line DL. In a cross-sectional view, the active layer ST_ACT and the active layer SW_ACT can be spaced apart from each other on the buffer layer BUF and arranged parallel to each other.

[0087] The protruding electrode ST_SW_GAT can be formed to protrude from the gate line GL along the length direction of the data line DL. The protruding electrode ST_SW_GAT can be formed to overlap the active layer ST_ACT of the sensing thin-film transistor ST and the active layer SW_ACT of the switching thin-film transistor SW, and can be connected to the gate line GL through a contact hole ST_SW_GAT_CNT.

[0088] The protruding electrode ST_SW_GAT can be commonly connected to the active layer ST_ACT of the sensing thin film transistor ST and the active layer SW_ACT of the switching thin film transistor SW, and thus can be used as a gate electrode that can commonly transmit the signal of the gate line GL to the sensing thin film transistor ST and the switching thin film transistor SW.

[0089] In a display device according to various embodiments of the present disclosure, a protruding electrode ST_SW_GAT extending from a gate line GL can be used as a gate electrode to form a sensing thin film transistor ST and a switching thin film transistor SW, thereby simplifying the structures of the sensing thin film transistor ST and the switching thin film transistor SW. A reference line connection pattern VREF_H_b between the sensing thin film transistor ST and a reference line VREF and a data line connection pattern DL_b between the switching thin film transistor SW and a data line DL can be set to be parallel to each other, and when a dark defect occurs, repair cutting can be performed simultaneously in the length direction of the protruding electrode ST_SW_GAT, thereby implementing an improved repair structure.

[0090] Figure 8 is a view showing a repair process of a display device according to various embodiments of the present disclosure. Figure 9 is Figure 8 an enlarged view of part B of

[0091] Referring to Figure 8 and Figure 9 , the display device may include first to fourth sub-pixels R, B, W, G that constitute a unit pixel. For example, when a dark defect occurs in which the red light of the first sub-pixel R among the sub-pixels R, B, W, G is not normally displayed, the first sub-pixel R can be separated from the other sub-pixels B, W, G, thereby repairing the defect. To this end, a repair cut EVDD_CT can be performed between the driving thin film transistor DR of the first sub-pixel R and a pixel power supply line EVDD, and a repair cut EVDD_CT can be performed between the driving transistor DR and a reference line VREF. In addition, a repair cut VREF_CT can be performed between the sensing thin film transistor ST and the reference line VREF and between the switching thin film transistor SW and the data line DL. In addition, a first electrode ANO of a light emitting diode can be welded WC by a laser.

[0092] As Figure 9As shown, during the repair process according to various embodiments of the present disclosure, the reference line connection pattern VREF_H_b between the sensing thin film transistor ST and the reference line VREF and the data line connection pattern DL_b between the switching thin film transistor SW and the data line DL can be simultaneously repaired and cut VREF_DL_CT in the length direction of the protruding electrode ST_SW_GAT, and thus the sensing thin film transistor ST and the reference line VREF and the switching thin film transistor SW and the data line DL can be separated from each other. The reference line connection pattern VREF_H_b and the data line connection pattern DL_b can be cut by only one repair cut VREF_DL_CT. For example, the reference line connection pattern VREF_H_b and the data line connection pattern DL_b can be formed as an active layer. Alternatively, the reference line connection pattern VREF_H_b and the data line connection pattern DL_b can be formed as an active multi-layer structure in which an active layer and a metal material layer are deposited. For example, the active multi-layer structure can be composed of a three-layer of active layer / MoTi / Cu or a two-layer of active layer / MoTi. According to various embodiments, the repair cut VREF_CT between the driving transistor DR and the reference line VREF can also be performed during the repair cut VREF_DL_CT of the sensing thin film transistor ST and the switching thin film transistor SW. For example, a laser cutting device with a wavelength range of 1064 nm can be used for the repair cut.

[0093] Figure 10 is a plan view of a unit pixel of a display device according to various embodiments of the present disclosure. Figure 11 is along Figure 10 the line II-II' taken sectional view. Figure 12 is along Figure 10 the line III-III' taken sectional view. Figure 13 is along Figure 10 the line IV-IV' taken sectional view. Figure 14 is shown Figure 10 the equivalent circuit diagram of the storage capacitor of the sub-pixel of part C of. These drawings are intended to specifically describe the storage capacitor Cst in the display device according to various embodiments of the present disclosure. Therefore, in the following description, the repeated description of other identical elements except for the description of the storage capacitor Cst will be omitted.

[0094] As Figure 10 shown, each sub-pixel R, B, W, G can be defined by the intersection between the gate line G1 and the data line DL, and can include a light emitting diode PXL, a driving thin film transistor DR, a sensing thin film transistor ST, a switching thin film transistor SW, a first storage capacitor Cs1, and a second storage capacitor Cs2.

[0095] The first electrode ANO of the light-emitting diode PXL and the first storage capacitor Cst1 can be disposed in the opening region (or light-emitting region).

[0096] The driving thin-film transistor DR can be disposed in the first circuit region provided on one side (e.g., the upper side) of the opening region, and the second storage capacitor Cs2 can be disposed in the second circuit region provided on the other side (e.g., the lower side) of the opening region.

[0097] As Figure 11 shown, in the opening region of each of the sub-pixels R, B, W, and G, a buffer layer BUF, an active layer ACT, an interlayer dielectric film ILD, a color filter CF, an overcoat layer OC, and a light-emitting diode PXL can be disposed on the substrate SUB.

[0098] The buffer layer BUF can be formed on the entire surface of the substrate SUB, and the active layer ACT on the buffer layer BUF can be connected to either the gate electrode or the source electrode of the driving thin-film transistor DR. For example, in Figure 11 it, the active layer ACT can be a first electrode pattern DTG that is made conductive by being connected to the gate electrode of the driving thin-film transistor DR. Alternatively, the active layer ACT can be a second electrode pattern DTS that is made conductive by being connected to the source electrode of the driving thin-film transistor DR.

[0099] The interlayer dielectric film ILD, the color filter CF, the overcoat layer OC, and the light-emitting diode PXL can be formed on the active layer ACT.

[0100] The first electrode pattern DTG formed by the conductivity of the active layer ACT and the first electrode ANO of the light-emitting diode PXL can be separated from each other by interposing the interlayer dielectric film ILD, the color filter CF, and the overcoat layer OC, whereby a vertical capacitor Cst_V1 can be formed in the vertical direction. Alternatively, the vertical capacitor Cst_V1 can be formed in the vertical direction between the second electrode pattern DTS formed by the conductivity of the active layer ACT and the first electrode ANO of the light-emitting diode PXL.

[0101] As Figure 12 shown, in the opening region of each of the sub-pixels R, B, W, and G, a buffer layer BUF, an active layer ACT, an interlayer dielectric film ILD, a color filter CF, an overcoat layer OC, and a light-emitting diode PXL can be disposed on the substrate SUB.

[0102] The buffer layer BUF can be formed on the entire surface of the substrate SUB, and the active layer ACT on the buffer layer BUF can be connected to either the gate electrode or the source electrode of the driving thin-film transistor DR. For example, in Figure 12In [the structure], the active layer ACT may be a finger pattern structure, in which each of a plurality of first electrode patterns DTG that are conductified by being connected to the gate electrode of the driving thin-film transistor DR and each of a plurality of second electrode patterns DTS that are conductified by being connected to the source electrode of the driving thin-film transistor DR are arranged in parallel on the same plane. The width h1 of each of the plurality of first electrode patterns DTG and second electrode patterns DTS may be smaller than the width h2 between the first electrode pattern DTG and the second electrode pattern DTS.

[0103] A plurality of first electrode patterns DTG and a plurality of second electrode patterns DTS formed by the conductification of the active layer ACT may be alternately arranged, whereby a horizontal capacitor Cst_H can be formed in the horizontal direction between the first electrode pattern and the second electrode pattern.

[0104] Referring to Figure 11 and Figure 12 , a first storage capacitor Cst1 including Figure 11 the vertical capacitor Cst_V1 shown in Figure 12 and the horizontal capacitor Cst_H shown in

[0105] can be formed in the opening region of each of the sub-pixels R, B, W, G. For example, based on the red sub-pixel R, the first storage capacitor Cst1 in the opening region may be a capacitor in which the vertical capacitor Cst_V1 and the horizontal capacitor Cst_H are combined with each other. Figure 13 As shown in

[0106] , in the second circuit region of each of the sub-pixels R, B, W, G, a light-shielding layer LS, a buffer layer BUF, an active layer ACT, an interlayer dielectric film ILD, and source / drain electrodes SD may be provided on the substrate SUB. Figure 13 The light-shielding layer LS may be provided on the substrate SUB so as to overlap with the active layer ACT and the source / drain electrodes SD. The active layer ACT on the buffer layer BUF may be connected to either the gate electrode or the source electrode of the driving thin-film transistor DR. For example, in

[0107] , the active layer ACT may be a first electrode pattern DTG that is conductified by being connected to the gate electrode of the driving thin-film transistor DR. Alternatively, the active layer ACT may be a second electrode pattern DTS that is conductified by being connected to the source electrode of the driving thin-film transistor DR.

[0108] In a first electrode pattern DTG formed by the conduction of an active layer ACT, by interposing a buffer layer BUF, it is separated from a light-shielding layer LS, and by interposing an interlayer dielectric film ILD, it is separated from a source / drain electrode SD. A dual vertical capacitor Cst_V2 can be formed in the vertical direction for each of the light-shielding layer LS below it and the source / drain electrode SD above it.

[0109] Referring Figure 14 , in a display device according to various embodiments of the present disclosure, a storage capacitor Cst can overlap with the opening regions of sub-pixels R and B and is formed between a driving thin-film transistor DR in a first circuit region and a sensing thin-film transistor ST in a second circuit region. For example, based on the red sub-pixel R, a capacitor in which a vertical storage capacitor Cst_V1 and a horizontal capacitor Cst_H of a first storage capacitor Cst1 corresponding to the opening region are combined with a dual vertical capacitor Cst_V2 in a non-opening region (or a second circuit region) can be combined with each other to form a storage capacitor Cst.

[0110] Figures 15 to 19 is a plan view of a single-layer structure showing a part of a unit pixel of a display device according to various embodiments of the present disclosure.

[0111] Referring Figures 15 to 19 , sub-pixels constituting a unit pixel in a display device according to various embodiments of the present disclosure will be described in more detail.

[0112] As Figure 15 shown, a plurality of pixel power supply lines EVDD1 and EVDD2 are arranged parallel to each other along a first direction (e.g., a horizontal direction) and extend in a second direction (e.g., a vertical direction) intersecting the first direction. First data lines DL1 and DL2, third data lines DL3 and DL4, and a reference line VREF can be formed on the substrate and are arranged adjacent to each other and parallel to the plurality of pixel power supply lines EVDD1 and EVDD2 between the pixel power supply lines EVDD1 and EVDD2, and a reference line VREF is arranged parallel to the second data line DL2 and the third data line DL3 between the second data line DL2 and the third data line DL3. The plurality of pixel power supply lines EVDD1 and EVDD2, data lines DL1 to DL4, and the reference line VREF can be formed through a light-shielding layer LS.

[0113] A light-shielding pattern Cst2_LS can be provided, which corresponds to a sensing thin-film transistor ST and a switching thin-film transistor SW formed in the second circuit regions of the first sub-pixel to the fourth sub-pixel R, B, W, G and forms a second storage capacitor Cs2.

[0114] The buffer layer BUF can be disposed on the substrate on which the Figure 15 components shown are formed to cover the components. The buffer layer BUF can be used to protect the thin film transistors formed by subsequent processes from impurities (such as alkali ions leaking from the light shielding layer LS or the substrate). The buffer layer BUF can be silicon oxide (SiOx), silicon nitride (SiNx), or a multi-layer of SiOx and SiNx.

[0115] As Figure 16 shown, the active layer ACT can be disposed on the buffer layer BUF.

[0116] The active layer ACT can include the active layer DR_ACT of the driving thin film transistor DR disposed in the first circuit regions RC1, BC1, WC1, and GC1 of each of the sub-pixels R, B, W, G, the active layer ST_ACT of the sensing thin film transistor ST disposed in the second circuit regions RC2, BC2, WC2, and GC2, and the active layer SW_ACT of the switching thin film transistor SW. In addition, the active layer ACT can include the active layer constituting the first electrode pattern DTG and the second electrode pattern DTS disposed in the opening regions of each of the sub-pixels R, B, W, G. In the active layer ACT, the portion connected to the gate electrode of the driving thin film transistor DR in the first circuit region, the portion constituting the first electrode pattern DTG in the opening region, and the portion of the switching thin film transistor SW constituting the second circuit region can be formed integrally. In addition, in the active layer ACT, the portion connected to the source electrode of the driving thin film transistor DR in the first circuit region, the portion constituting the second electrode pattern DTS in the opening region, and the portion of the sensing thin film transistor ST constituting the second circuit region can be formed integrally. In addition, the active layer ACT can include a common active layer that is formed to partially overlap with the pixel power supply lines EVDD1 and EVDD2 and at the same time overlap with the pixel power sharing line EVDD_H to be formed between the pixel power supply lines EVDD1 and EVDD2.

[0117] Each of the first electrode pattern DTG and the second electrode pattern DTS in the opening region of the active layer ACT can be formed as a first common pattern, a second common pattern, a plurality of first electrode patterns, and a plurality of second electrode patterns. The plurality of first electrode patterns and the plurality of second electrode patterns are respectively connected to the first common pattern and the second common pattern and are arranged in parallel in a finger-like pattern structure.

[0118] As Figure 17As shown, the gate electrode DR_GAT for constituting the driving thin film transistor DR can be formed in the first circuit regions of the first to fourth sub-pixels R, B, W, G, and the protruding electrode ST_SW_GAT common to the sensing thin film transistor ST and the switching thin film transistor SW can be provided in the second circuit region. The protruding electrode ST_SW_GAT can be formed to extend from the gate line GL in the length direction of the data line DL.

[0119] The interlayer dielectric film ILD can be provided on the substrate on which the Figure 17 shown elements are formed to cover the elements. The interlayer dielectric film ILD can be silicon oxide (SiOx), silicon nitride (SiNx), or a multi-layer of SiOx and SiNx.

[0120] As Figure 18 shown, a plurality of first power supply lines EVDD1 and EVDD2, a pixel power sharing line EVDD_H, a second power sharing line VREF_H, and a gate line GL can be formed on the interlayer dielectric film ILD. In addition, the source / drain electrodes SD of the driving thin film transistor DR formed in the first circuit regions of the first to fourth sub-pixels R, B, W, G, and the source / drain electrodes SD of the sensing thin film transistor ST and the switching thin film transistor SW formed in the second circuit region can be formed.

[0121] Figure 18 The shown elements can be formed of the same material and can be a multi-layer made of any one selected from Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or their alloys. For example, the elements can be made of a double layer of Cu / MoTi.

[0122] In addition, a passivation film PAS can be provided to cover Figure 18 all the shown elements. The passivation film PAS is an insulating film for protecting the elements thereunder and can be silicon oxide (SiOx), silicon nitride (SiNx), or a multi-layer of SiOx and SiNx.

[0123] Red, blue, white, and green color filters CF can be provided on the passivation film PAS to correspond to the opening regions of the respective sub-pixels R, B, W, G. The color filters CF can emit red, blue, white, and green light by filtering the white light emitted from the light emitting diode PXL.

[0124] An overcoat layer OC can be provided on the color filters CF to cover the color filters CF. The overcoat layer OC can be a planarization film for reducing the step difference of the underlying structure.

[0125] As Figure 19As shown, the light-emitting diode PXL may be disposed on the overcoat layer OC to correspond to the opening regions of each of the sub-pixels R, B, W, and G. The light-emitting diode PXL may include a first electrode (e.g., an anode electrode ANO), a light-emitting layer, and a second electrode (e.g., a cathode electrode). For example, the light-emitting diode PXL may be an organic light-emitting diode (OLED).

[0126] Pixels according to various embodiments of the present disclosure and a display device including the same may be described as follows.

[0127] Pixels according to various embodiments of the present disclosure are disposed in a pixel region defined by a gate line, a data line, and a pixel power supply line, and include: a light-emitting unit and a pixel circuit, where the pixel circuit may include a protruding electrode protruding from the gate line along the length direction of the data line; and a first thin-film transistor and a second thin-film transistor parallelly disposed between the light-emitting unit and the gate line using the protruding electrode as a gate electrode.

[0128] In the pixel according to various embodiments of the present disclosure, the first thin-film transistor and the second thin-film transistor may be disposed in a horizontal direction intersecting with the protruding electrode.

[0129] In the pixel according to various embodiments of the present disclosure, the pixel circuit may further include a driving thin-film transistor connected to a first node, a second node, and a pixel power supply line, and a first storage capacitor located between the first node and the second node.

[0130] In the pixel according to various embodiments of the present disclosure, the pixel circuit may include a first circuit region and a second circuit region disposed with the light-emitting unit interposed therebetween, the driving thin-film transistor may be disposed in the first circuit region, the first and second thin-film transistors may be disposed in the second circuit region, and the first storage capacitor may overlap with the light-emitting unit and be disposed between the first circuit region and the second circuit region.

[0131] In the pixel according to various embodiments of the present disclosure, the pixel may further include an active layer and a light-emitting diode in the light-emitting unit, the active layer is connected to any one of the first node and the second node of the driving thin-film transistor, a first electrode pattern of the active layer that is made conductive by connecting to the second node of the driving thin-film transistor and a second electrode pattern of the active layer that is made conductive by connecting to the first node of the driving thin-film transistor may be spaced apart from the first electrode of the light-emitting diode by interposing at least one of an interlayer dielectric film, a color filter, and an overcoat layer, whereby a vertical capacitor of the first storage capacitor may be formed in a vertical direction.

[0132] In the pixels according to various embodiments of the present disclosure, a plurality of first electrode patterns and a plurality of second electrode patterns may be alternately disposed in parallel on the same plane, whereby a horizontal capacitor of the first storage capacitor may be formed in a horizontal direction between the first electrode pattern and the second electrode pattern.

[0133] In the pixels according to various embodiments of the present disclosure, in the active layer, a portion connected to the second node of the driving thin film transistor in the first circuit region, a portion constituting the first electrode pattern in the light emitting portion, and a portion constituting the data line connection pattern of the second thin film transistor in the second circuit region may be formed integrally, and a portion connected to the first node of the driving thin film transistor in the first circuit region, a portion constituting the second electrode pattern in the light emitting portion, and a portion constituting the reference line connection pattern of the first thin film transistor in the second circuit region may be formed integrally.

[0134] In the pixels according to various embodiments of the present disclosure, the second circuit region may further include a second storage capacitor formed between the gate electrode of the driving thin film transistor and the source electrode of any one of the first thin film transistor and the second thin film transistor.

[0135] The pixels according to various embodiments of the present disclosure may further include a reference line to which a reference voltage is applied, wherein the first thin film transistor may be connected to the gate line, the reference line, and the source electrode of the driving thin film transistor as the first node, and the second thin film transistor may be connected to the gate line, the data line, and the gate electrode of the driving thin film transistor as the second node.

[0136] In the pixels according to various embodiments of the present disclosure, the first thin film transistor may be configured to provide an initialization voltage transmitted through the reference line to the first node of the driving thin film transistor, or sense the first node of the driving thin film transistor, and the second thin film transistor may be configured to provide a data voltage transmitted through the data line to the second node of the driving thin film transistor.

[0137] In the pixels according to various embodiments of the present disclosure, the first thin film transistor may include a reference line connection pattern that intersects the protruding electrode and is connected to the reference line, and the second thin film transistor may include a data line connection pattern that extends parallel to the reference line connection pattern and is connected to the data line.

[0138] In the pixels according to various embodiments of the present disclosure, the reference line connection pattern and the data line connection pattern may be formed as a part of the active layer.

[0139] In a pixel according to various embodiments of the present disclosure, a reference line connection pattern and a data line connection pattern may be formed of an active multi-layer structure in which an active layer and at least one metal material layer are deposited.

[0140] In a pixel according to various embodiments of the present disclosure, when a dark defect occurs, the reference line connection pattern and the data line connection pattern may be cut off by simultaneously performing a repair cut in the length direction of the protruding electrode.

[0141] In a pixel according to various embodiments of the present disclosure, the repair cut may also be performed between the driving thin film transistor and the pixel power line and between the driving thin film transistor and the reference line so that the pixel can be separated from adjacent pixels.

[0142] A display device according to various embodiments of the present disclosure may include a plurality of sub-pixels respectively disposed in a pixel region defined by a gate line, a data line, and a pixel power line, the plurality of sub-pixels respectively having a light emitting portion and a pixel circuit, wherein the pixel circuit may include: a driving thin film transistor connected to a first node, a second node, and a pixel power line; a first switching thin film transistor connected to the gate line, the data line, and the first node between the light emitting portion and the gate line; a second switching thin film transistor disposed in parallel with the first switching thin film transistor between the light emitting portion and the gate line and connected to the gate line, a reference line, and the second node; a capacitor located between the first node and the second node; and a protruding electrode protruding from the gate line to overlap with each of the first switching thin film transistor and the second switching thin film transistor, and the protruding electrode may be a gate electrode of each of the first switching thin film transistor and the second switching thin film transistor.

[0143] In a display device according to various embodiments of the present disclosure, the protruding electrode may protrude from the gate line along the length direction of the data line, and the first switching thin film transistor and the second switching thin film transistor may be disposed in parallel in a horizontal direction intersecting the protruding electrode.

[0144] In a display device according to various embodiments of the present disclosure, the pixel circuit may include a first circuit region and a second circuit region provided by interposing the light emitting portion, the driving thin film transistor may be disposed in the first circuit region, the first switching thin film transistor and the second switching thin film transistor may be disposed in the second circuit region, and the capacitor may overlap with the light emitting portion and be disposed between the first circuit region and the second circuit region.

[0145] In a display device according to various embodiments of the present disclosure, the second circuit region may further include an auxiliary capacitor formed between a gate electrode of the driving thin film transistor and a source electrode of any one of the first switching thin film transistor and the second switching thin film transistor.

[0146] In a display device according to various embodiments of the present disclosure, a second switching thin film transistor may be connected to a gate line, a reference line, and a source electrode of a driving thin film transistor, and a first switching thin film transistor may be connected to the gate line, a data line, and a gate electrode of the driving thin film transistor.

[0147] In a display device according to various embodiments of the present disclosure, the second switching thin film transistor may include a reference line connection pattern extending in a horizontal direction intersecting with a protruding electrode and connected to the reference line, while the first switching thin film transistor may include a data line connection pattern extending parallel to the reference line connection pattern and connected to the data line.

[0148] In a display device according to various embodiments of the present disclosure, the reference line connection pattern and the data line connection pattern may be formed as part of an active layer.

[0149] In a display device according to various embodiments of the present disclosure, the reference line connection pattern and the data line connection pattern may be formed of an active multi-layer structure in which an active layer and at least one metal material layer are deposited.

[0150] In a display device according to various embodiments of the present disclosure, when a dark defect occurs, the reference line connection pattern and the data line connection pattern may be cut off by simultaneously performing repair cutting in the longitudinal direction of the protruding electrode.

[0151] It will be apparent to those skilled in the art that the present disclosure described above is not limited by the above embodiments and drawings, and various substitutions, modifications, and changes can be made to the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the scope of the present disclosure is defined by the appended claims, and all changes or modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of the present disclosure.

Claims

1. A pixel, the pixel being disposed in a pixel region defined by a gate line, a data line, and a pixel power supply line, the pixel including a light-emitting portion and a pixel circuit, Among them, The pixel circuit includes: A protruding electrode that protrudes from the gate line along the length direction of the data line; and A first thin-film transistor and a second thin-film transistor, the first thin-film transistor and the second thin-film transistor being disposed in parallel between the light-emitting portion and the gate line, and using the protruding electrode as a gate electrode.

2. The pixel according to claim 1, wherein, The first thin-film transistor and the second thin-film transistor are disposed in a horizontal direction intersecting with the protruding electrode.

3. The pixel according to claim 1, wherein, The pixel circuit further includes: A driving thin-film transistor connected to a first node, a second node, and the pixel power supply line; and A first storage capacitor located between the first node and the second node.

4. The pixel according to claim 3, wherein, The pixel circuit includes a first circuit region and a second circuit region provided by interposing the light-emitting portion, the driving thin-film transistor being disposed in the first circuit region, the first thin-film transistor and the second thin-film transistor being disposed in the second circuit region, and the first storage capacitor overlapping with the light-emitting portion and being disposed between the first circuit region and the second circuit region.

5. The pixel according to claim 4, the pixel further including a light-emitting diode and an active layer in the light-emitting portion, the active layer being connected to any one of the first node and the second node of the driving thin-film transistor, Among them, A first electrode pattern of the active layer that is made conductive by being connected to the second node of the driving thin-film transistor and a second electrode pattern of the active layer that is made conductive by being connected to the first node of the driving thin-film transistor are spaced apart from a first electrode of the light-emitting diode by interposing at least one of an interlayer dielectric film, a color filter, and an overcoat layer, thereby forming a vertical capacitor of the first storage capacitor in a vertical direction.

6. The pixel according to claim 5, wherein, A plurality of first electrode patterns and a plurality of second electrode patterns are alternately disposed in parallel on the same plane, thereby forming a horizontal capacitor of the first storage capacitor in a horizontal direction between the first electrode pattern and the second electrode pattern.

7. The pixel according to claim 6, wherein, In the active layer, a portion connected to the second node of the driving thin-film transistor in the first circuit region, a portion constituting the first electrode pattern in the light-emitting portion, and a portion constituting a data line connection pattern of the second thin-film transistor in the second circuit region are formed integrally, and A portion connected to the first node of the driving thin-film transistor in the first circuit region, a portion constituting the second electrode pattern in the light-emitting portion, and a portion constituting a reference line connection pattern of the first thin-film transistor in the second circuit region are formed integrally.

8. The pixel according to claim 4, wherein The second circuit region further includes a second storage capacitor formed between a gate electrode of the driving thin-film transistor and a source electrode of any one of the first thin-film transistor and the second thin-film transistor.

9. The pixel according to claim 4, wherein the pixel further includes a reference line to which a reference voltage is applied. Among them, The first thin film transistor is connected to the gate line, the reference line, and a source electrode of the driving thin film transistor serving as the first node, and The second thin film transistor is connected to the gate line, the data line, and a gate electrode of the driving thin film transistor serving as the second node.

10. The pixel according to claim 9, wherein, The first thin film transistor is configured to provide an initialization voltage transmitted through the reference line to the first node of the driving thin film transistor, or sense the first node of the driving thin film transistor, and the second thin film transistor is configured to provide a data voltage transmitted through the data line to the second node of the driving thin film transistor.

11. The pixel according to claim 9, wherein The first thin film transistor includes a reference line connection pattern that intersects the protruding electrode and is connected to the reference line, and the second thin film transistor includes a data line connection pattern that extends parallel to the reference line connection pattern and is connected to the data line.

12. The pixel according to claim 11, wherein, The reference line connection pattern and the data line connection pattern are formed as part of the active layer.

13. The pixel according to claim 11, wherein, The reference line connection pattern and the data line connection pattern are formed of an active multi-layer structure in which an active layer and at least one metal material layer are deposited.

14. The pixel according to claim 11, wherein, When a dark defect occurs, the reference line connection pattern and the data line connection pattern are cut off by simultaneously performing repair cutting in the length direction of the protruding electrode.

15. The pixel according to claim 14, wherein, The repair cutting is also performed between the driving thin film transistor and the pixel power supply line and between the driving thin film transistor and the reference line so that the pixel is separated from adjacent pixels.

16. A display device, the display device including the pixel according to any one of claims 1 to 15.

17. A display device, the display device including a plurality of sub-pixels each disposed in a pixel region defined by a gate line, a data line, and a pixel power supply line, the plurality of sub-pixels each having a light emitting portion and a pixel circuit, Among them, The pixel circuit includes: A driving thin film transistor connected to a first node, a second node, and the pixel power supply line; A first switching thin film transistor between the light emitting portion and the gate line and connected to the gate line, the data line, and the first node; A second switching thin film transistor disposed parallel to the first switching thin film transistor between the light emitting portion and the gate line and connected to the gate line, a reference line, and the second node; A capacitor located between the first node and the second node; and A protruding electrode protruding from the gate line to overlap each of the first switching thin film transistor and the second switching thin film transistor, wherein the protruding electrode is a gate electrode of each of the first switching thin film transistor and the second switching thin film transistor.

18. The display device according to claim 17, wherein, The protruding electrode protrudes from the gate line along the length direction of the data line, and the first switching thin film transistor and the second switching thin film transistor are arranged in parallel in a horizontal direction intersecting with the protruding electrode.

19. The display device according to claim 17, wherein, The pixel circuit includes a first circuit region and a second circuit region provided by interposing the light emitting portion. The driving thin film transistor is provided in the first circuit region, the first switching thin film transistor and the second switching thin film transistor are provided in the second circuit region, and the capacitor overlaps with the light emitting portion and is provided between the first circuit region and the second circuit region.

20. The display device according to claim 19, wherein The second circuit region further includes an auxiliary capacitor formed between the gate electrode of the driving thin film transistor and the source electrode of any one of the first switching thin film transistor and the second switching thin film transistor.

21. The display device according to claim 19, wherein, The second switching thin film transistor is connected to the gate line, the reference line, and the source electrode of the driving thin film transistor, and the first switching thin film transistor is connected to the gate line, the data line, and the gate electrode of the driving thin film transistor.

22. The display device according to claim 21, wherein, The second switching thin film transistor includes a reference line connection pattern extending in a horizontal direction intersecting with the protruding electrode and connected to the reference line, and the first switching thin film transistor includes a data line connection pattern extending parallel to the reference line connection pattern and connected to the data line.

23. The display device according to claim 22, wherein, The reference line connection pattern and the data line connection pattern are formed as part of the active layer.

24. The display device according to claim 22, wherein The reference line connection pattern and the data line connection pattern are formed by an active multi-layer structure in which an active layer and at least one metal material layer are deposited.

25. The display device according to claim 22, wherein, When a dark defect occurs, the reference line connection pattern and the data line connection pattern are cut off by simultaneously performing repair cutting in the length direction of the protruding electrode.

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